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DS90LV028AH High Temperature 3V LVDS Dual Differential Line Receiver
Check for Samples: DS90LV028AH
1FEATURES DESCRIPTION
The DS90LV028AH is a dual CMOS differential line
2• -40°C to +125°C Operating Temperature Range receiver designed for applications requiring ultra low
• >400 Mbps (200 MHz) Switching Rates power dissipation, low noise and high data rates. The
• 50 ps Differential Skew (Typical) device is designed to support data rates in excess of
400 Mbps (200 MHz) utilizing Low Voltage Differential
• 0.1 ns Channel-to-Channel Skew (Typical) Signaling (LVDS) technology.
• 2.5 ns Maximum Propagation Delay The DS90LV028AH accepts low voltage (350 mV
• 3.3V Power Supply Design typical) differential input signals and translates them
• Flow-Through Pinout to 3V CMOS output levels. The DS90LV028AH has a
• Power Down High Impedance on LVDS Inputs flow-through design for easy PCB layout.
• Low Power Design (18mW @ 3.3V Static) The DS90LV028AH and companion LVDS line driver
• LVDS Inputs Accept LVDS/CML/LVPECL DS90LV027AH provide a new alternative to high
power PECL/ECL devices for high speed point-to-
Signals point interface applications.
• Conforms to ANSI/TIA/EIA-644 Standard
• Available in SOIC Package Connection Diagram
Figure 1. SOIC
See Package Number D(R-PDSO-G8)
Functional Diagram
Truth Table
INPUTS OUTPUT
[RIN+] −[RIN−] ROUT
VID ≥0.1V H
VID ≤ −0.1V L
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC)−0.3V to +4V
Input Voltage (RIN+, RIN−)−0.3V to +3.9V
Output Voltage (ROUT)−0.3V to VCC + 0.3V
Maximum Package Power Dissipation @ +25°C
D Package 1025 mW
Derate D Package 8.2 mW/°C above +25°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range Soldering
(4 sec.) +260°C
Maximum Junction Temperature +150°C
ESD Rating(3)
(HBM 1.5 kΩ, 100 pF) ≥7 kV
(EIAJ 0Ω, 200 pF) ≥500 V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply
that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) ESD Rating:
HBM (1.5 kΩ, 100 pF) ≥7 kV
EIAJ (0Ω, 200 pF) ≥500V
Recommended Operating Conditions Min Typ Max Units
Supply Voltage (VCC) +3.0 +3.3 +3.6 V
Receiver Input Voltage GND 3.0 V
Operating Free Air
Temperature (TA)−40 25 +125 °C
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Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.(1)(2)
Symbol Parameter Conditions Pin Min Typ Max Units
VTH Differential Input High Threshold VCM = +1.2V, 0V, 3V(3) RIN+, +100 mV
RIN−
VTL Differential Input Low Threshold −100 mV
IIN Input Current VIN = +2.8V VCC = 3.6V or 0V −10 ±1 +10 μA
VIN = 0V −10 ±1 +10 μA
VIN = +3.6V VCC = 0V -20 +20 μA
VOH Output High Voltage IOH =−0.4 mA, VID = +200 mV ROUT 2.7 3.1 V
IOH =−0.4 mA, Inputs terminated 2.7 3.1 V
IOH =−0.4 mA, Inputs shorted 2.7 3.1 V
VOL Output Low Voltage IOL = 2 mA, VID =−200 mV 0.3 0.5 V
IOS Output Short Circuit Current VOUT = 0V(4) −15 −50 −100 mA
VCL Input Clamp Voltage ICL =−18 mA −1.5 −0.8 V
ICC No Load Supply Current Inputs Open VCC 5.4 9 mA
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified (such as VID).
(2) All typicals are given for: VCC = +3.3V and TA= +25°C.
(3) VCC is always higher than RIN+ and RIN−voltage. RIN+ and RIN−are allowed to have voltage range −0.05V to +3.05V. VID is not allowed
to be greater than 100 mV when VCM = 0V or 3V.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted
at a time, do not exceed maximum junction temperature specification.
Switching Characteristics
VCC = +3.3V ± 10%, TA=−40°C to +125°C(1)(2)
Symbol Parameter Conditions Min Typ Max Units
tPHLD Differential Propagation Delay High to Low CL= 15 pF 1.0 1.6 2.5 ns
VID = 200 mV
tPLHD Differential Propagation Delay Low to High 1.0 1.7 2.5 ns
(Figure 2 and Figure 3)
tSKD1 Differential Pulse Skew |tPHLD −tPLHD|(3) 0 50 650 ps
tSKD2 Differential Channel-to-Channel Skew-same device(4) 0 0.1 0.5 ns
tSKD3 Differential Part to Part Skew(5) 0 1.0 ns
tSKD4 Differential Part to Part Skew(6) 0 1.5 ns
tTLH Rise Time 325 800 ps
tTHL Fall Time 225 800 ps
fMAX Maximum Operating Frequency(7) 200 250 MHz
(1) CLincludes probe and jig capacitance.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50Ω, trand tf(0% to 100%) ≤3 ns for RIN.
(3) tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of
the same channel.
(4) tSKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple
receivers within the integrated circuit.
(5) tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VCC and within 5°C of each other within the operating temperature range.
(6) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over the recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max −Min|
differential propagation delay.
(7) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria:
60%/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), load = 15 pF (stray plus probes).
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PARAMETER MEASUREMENT INFORMATION
Figure 2. Receiver Propagation Delay and Transition Time Test Circuit
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
TYPICAL APPLICATION
Balanced System
Figure 4. Point-to-Point Application
APPLICATION INFORMATION
General application guidelines and hints for LVDS drivers and receivers may be found in the following application
notes: LVDS Owner's Manual (lit #550062-003), AN-808 (SNLA028), AN-977 (SNLA166), AN-971 (SNLA165),
AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034).
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 4. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ωshould be selected to match the media, and is located as close to
the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a
voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination loading must be taken into account.
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The DS90LV028AH differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V
common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V.
The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting
may be the result of a ground potential difference between the driver's ground reference and the receiver's
ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters
of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V
(measured from each pin to ground). The device will operate for receiver input voltages up to VCC, but exceeding
VCC will turn on the ESD protection circuitry which will clamp the bus voltages.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1μF and 0.01μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple
vias should be used to connect the decoupling capacitors to the power planes. A 10μF (35V) or greater solid
tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply
and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to
put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable)
and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave
the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as
common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than
traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise
induced on the differential lines is much more likely to appear as common-mode which is rejected by the
receiver.
Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result! (Note that the velocity of propagation, v = c/E rwhere c (the speed of light) = 0.2997mm/ps or 0.0118
in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number of vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
TERMINATION
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
should be between 90Ωand 130Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS will not work correctly without resistor termination. Typically, connecting a
single resistor across the pair at the receiver end will suffice.
Surface mount 1% - 2% resistors are the best. PCB stubs, component lead, and the distance from the
termination to the receiver inputs should be minimized. The distance between the termination resistor and the
receiver should be < 10mm (12mm MAX).
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INPUT FAILSAFE BIASING
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor
and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors
should be in the 5kΩto 15kΩrange to minimize loading and waveform distortion to the driver. The common-
mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal
circuitry. Please refer to application note AN-1194 (SNLA051), “Failsafe Biasing of LVDS Interfaces” for more
information.
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100Ω. They should not introduce major impedance discontinuities.
Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for
noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and
also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by
the receiver.
For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤d≤10M, CAT 3
(category 3) twisted pair cable works well, is readily available and relatively inexpensive.
Pin Descriptions
Pin No. Name Description
1, 4 RIN- Inverting receiver input pin
2, 3 RIN+ Non-inverting receiver input pin
6, 7 ROUT Receiver output pin
8 VCC Power supply pin, +3.3V ± 0.3V
5 GND Ground pin
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TYPICAL PERFORMANCE CURVES
Output High Voltage vs Output Low Voltage vs
Power Supply Voltage Power Supply Voltage
Output Short Circuit Current vs Differential Transition Voltage vs
Power Supply Voltage Power Supply Voltage
Power Supply Current Differential Propagation Delay vs
vs Frequency Power Supply Voltage
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TYPICAL PERFORMANCE CURVES (continued)
Differential Propagation Delay vs Differential Propagation Delay vs
Differential Input Voltage Common-Mode Voltage
Transition Time vs Differential Skew vs
Power Supply Voltage Power Supply Voltage
Differential Propagation Delay Differential Propagation Delay
vs Load vs Load
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REVISION HISTORY
Changes from Original (April 2013) to Revision A Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 8
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS90LV028AHM/NOPB NRND SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 90LV0
28AHM
DS90LV028AHMX/NOPB NRND SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 90LV0
28AHM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 30-Oct-2013
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS90LV028AHMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90LV028AHMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 2
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