LM3S2016 Microcontroller
DATA SHEET
Copyright ©2007 Luminary Micro, Inc.DS-LM3S2016-1972
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November 30, 20072
Preliminary
Table of Contents
About This Document .................................................................................................................... 18
Audience .............................................................................................................................................. 18
About This Manual ................................................................................................................................ 18
Related Documents ............................................................................................................................... 18
Documentation Conventions .................................................................................................................. 18
1 Architectural Overview ...................................................................................................... 20
1.1 Product Features ...................................................................................................................... 20
1.2 Target Applications .................................................................................................................... 25
1.3 High-Level Block Diagram ......................................................................................................... 25
1.4 Functional Overview .................................................................................................................. 26
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 27
1.4.2 Motor Control Peripherals .......................................................................................................... 27
1.4.3 Analog Peripherals .................................................................................................................... 28
1.4.4 Serial Communications Peripherals ............................................................................................ 28
1.4.5 System Peripherals ................................................................................................................... 30
1.4.6 Memory Peripherals .................................................................................................................. 30
1.4.7 Additional Features ................................................................................................................... 31
1.4.8 Hardware Details ...................................................................................................................... 31
2 ARM Cortex-M3 Processor Core ...................................................................................... 33
2.1 Block Diagram .......................................................................................................................... 34
2.2 Functional Description ............................................................................................................... 34
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 34
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 35
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 35
2.2.4 ROM Table ............................................................................................................................... 35
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 35
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 35
3 Memory Map ....................................................................................................................... 39
4 Interrupts ............................................................................................................................ 41
5 JTAG Interface .................................................................................................................... 43
5.1 Block Diagram .......................................................................................................................... 44
5.2 Functional Description ............................................................................................................... 44
5.2.1 JTAG Interface Pins .................................................................................................................. 45
5.2.2 JTAG TAP Controller ................................................................................................................. 46
5.2.3 Shift Registers .......................................................................................................................... 47
5.2.4 Operational Considerations ........................................................................................................ 47
5.3 Initialization and Configuration ................................................................................................... 50
5.4 Register Descriptions ................................................................................................................ 50
5.4.1 Instruction Register (IR) ............................................................................................................. 50
5.4.2 Data Registers .......................................................................................................................... 52
6 System Control ................................................................................................................... 54
6.1 Functional Description ............................................................................................................... 54
6.1.1 Device Identification .................................................................................................................. 54
6.1.2 Reset Control ............................................................................................................................ 54
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6.1.3 Power Control ........................................................................................................................... 57
6.1.4 Clock Control ............................................................................................................................ 57
6.1.5 System Control ......................................................................................................................... 59
6.2 Initialization and Configuration ................................................................................................... 59
6.3 Register Map ............................................................................................................................ 60
6.4 Register Descriptions ................................................................................................................ 61
7 Internal Memory ............................................................................................................... 109
7.1 Block Diagram ........................................................................................................................ 109
7.2 Functional Description ............................................................................................................. 109
7.2.1 SRAM Memory ........................................................................................................................ 109
7.2.2 Flash Memory ......................................................................................................................... 110
7.3 Flash Memory Initialization and Configuration ........................................................................... 111
7.3.1 Flash Programming ................................................................................................................. 111
7.3.2 Nonvolatile Register Programming ........................................................................................... 112
7.4 Register Map .......................................................................................................................... 112
7.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 113
7.6 Flash Register Descriptions (System Control Offset) .................................................................. 120
8 General-Purpose Input/Outputs (GPIOs) ....................................................................... 133
8.1 Functional Description ............................................................................................................. 133
8.1.1 Data Control ........................................................................................................................... 134
8.1.2 Interrupt Control ...................................................................................................................... 135
8.1.3 Mode Control .......................................................................................................................... 136
8.1.4 Commit Control ....................................................................................................................... 136
8.1.5 Pad Control ............................................................................................................................. 136
8.1.6 Identification ........................................................................................................................... 136
8.2 Initialization and Configuration ................................................................................................. 136
8.3 Register Map .......................................................................................................................... 137
8.4 Register Descriptions .............................................................................................................. 139
9 General-Purpose Timers ................................................................................................. 174
9.1 Block Diagram ........................................................................................................................ 174
9.2 Functional Description ............................................................................................................. 175
9.2.1 GPTM Reset Conditions .......................................................................................................... 175
9.2.2 32-Bit Timer Operating Modes .................................................................................................. 176
9.2.3 16-Bit Timer Operating Modes .................................................................................................. 177
9.3 Initialization and Configuration ................................................................................................. 181
9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 181
9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 182
9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 182
9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 183
9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 183
9.3.6 16-Bit PWM Mode ................................................................................................................... 184
9.4 Register Map .......................................................................................................................... 184
9.5 Register Descriptions .............................................................................................................. 185
10 Watchdog Timer ............................................................................................................... 210
10.1 Block Diagram ........................................................................................................................ 210
10.2 Functional Description ............................................................................................................. 210
10.3 Initialization and Configuration ................................................................................................. 211
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10.4 Register Map .......................................................................................................................... 211
10.5 Register Descriptions .............................................................................................................. 212
11 Analog-to-Digital Converter (ADC) ................................................................................. 233
11.1 Block Diagram ........................................................................................................................ 234
11.2 Functional Description ............................................................................................................. 234
11.2.1 Sample Sequencers ................................................................................................................ 234
11.2.2 Module Control ........................................................................................................................ 235
11.2.3 Hardware Sample Averaging Circuit ......................................................................................... 236
11.2.4 Analog-to-Digital Converter ...................................................................................................... 236
11.2.5 Test Modes ............................................................................................................................. 236
11.3 Initialization and Configuration ................................................................................................. 236
11.3.1 Module Initialization ................................................................................................................. 236
11.3.2 Sample Sequencer Configuration ............................................................................................. 236
11.4 Register Map .......................................................................................................................... 237
11.5 Register Descriptions .............................................................................................................. 238
12 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 265
12.1 Block Diagram ........................................................................................................................ 266
12.2 Functional Description ............................................................................................................. 266
12.2.1 Transmit/Receive Logic ........................................................................................................... 266
12.2.2 Baud-Rate Generation ............................................................................................................. 267
12.2.3 Data Transmission .................................................................................................................. 268
12.2.4 Serial IR (SIR) ......................................................................................................................... 268
12.2.5 FIFO Operation ....................................................................................................................... 269
12.2.6 Interrupts ................................................................................................................................ 269
12.2.7 Loopback Operation ................................................................................................................ 270
12.2.8 IrDA SIR block ........................................................................................................................ 270
12.3 Initialization and Configuration ................................................................................................. 270
12.4 Register Map .......................................................................................................................... 271
12.5 Register Descriptions .............................................................................................................. 272
13 Synchronous Serial Interface (SSI) ................................................................................ 306
13.1 Block Diagram ........................................................................................................................ 306
13.2 Functional Description ............................................................................................................. 306
13.2.1 Bit Rate Generation ................................................................................................................. 307
13.2.2 FIFO Operation ....................................................................................................................... 307
13.2.3 Interrupts ................................................................................................................................ 307
13.2.4 Frame Formats ....................................................................................................................... 308
13.3 Initialization and Configuration ................................................................................................. 315
13.4 Register Map .......................................................................................................................... 316
13.5 Register Descriptions .............................................................................................................. 317
14 Inter-Integrated Circuit (I2C) Interface ............................................................................ 343
14.1 Block Diagram ........................................................................................................................ 343
14.2 Functional Description ............................................................................................................. 343
14.2.1 I2C Bus Functional Overview .................................................................................................... 344
14.2.2 Available Speed Modes ........................................................................................................... 346
14.2.3 Interrupts ................................................................................................................................ 347
14.2.4 Loopback Operation ................................................................................................................ 347
14.2.5 Command Sequence Flow Charts ............................................................................................ 348
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14.3 Initialization and Configuration ................................................................................................. 354
14.4 I2C Register Map ..................................................................................................................... 355
14.5 Register Descriptions (I2C Master) ........................................................................................... 356
14.6 Register Descriptions (I2C Slave) ............................................................................................. 369
15 Controller Area Network (CAN) Module ......................................................................... 378
15.1 Controller Area Network Overview ............................................................................................ 378
15.2 Controller Area Network Features ............................................................................................ 378
15.3 Controller Area Network Block Diagram .................................................................................... 379
15.4 Controller Area Network Functional Description ......................................................................... 380
15.4.1 Initialization ............................................................................................................................. 380
15.4.2 Operation ............................................................................................................................... 381
15.4.3 Transmitting Message Objects ................................................................................................. 381
15.4.4 Configuring a Transmit Message Object .................................................................................... 381
15.4.5 Updating a Transmit Message Object ....................................................................................... 382
15.4.6 Accepting Received Message Objects ...................................................................................... 382
15.4.7 Receiving a Data Frame .......................................................................................................... 383
15.4.8 Receiving a Remote Frame ...................................................................................................... 383
15.4.9 Receive/Transmit Priority ......................................................................................................... 383
15.4.10 Configuring a Receive Message Object .................................................................................... 383
15.4.11 Handling of Received Message Objects .................................................................................... 384
15.4.12 Handling of Interrupts .............................................................................................................. 384
15.4.13 Bit Timing Configuration Error Considerations ........................................................................... 385
15.4.14 Bit Time and Bit Rate ............................................................................................................... 385
15.4.15 Calculating the Bit Timing Parameters ...................................................................................... 387
15.5 Controller Area Network Register Map ...................................................................................... 389
15.6 Register Descriptions .............................................................................................................. 391
16 Pin Diagram ...................................................................................................................... 419
17 Signal Tables .................................................................................................................... 420
18 Operating Characteristics ............................................................................................... 432
19 Electrical Characteristics ................................................................................................ 433
19.1 DC Characteristics .................................................................................................................. 433
19.1.1 Maximum Ratings ................................................................................................................... 433
19.1.2 Recommended DC Operating Conditions .................................................................................. 433
19.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 434
19.1.4 Power Specifications ............................................................................................................... 434
19.1.5 Flash Memory Characteristics .................................................................................................. 435
19.2 AC Characteristics ................................................................................................................... 436
19.2.1 Load Conditions ...................................................................................................................... 436
19.2.2 Clocks .................................................................................................................................... 436
19.2.3 Analog-to-Digital Converter ...................................................................................................... 437
19.2.4 I2C ......................................................................................................................................... 437
19.2.5 Synchronous Serial Interface (SSI) ........................................................................................... 438
19.2.6 JTAG and Boundary Scan ........................................................................................................ 439
19.2.7 General-Purpose I/O ............................................................................................................... 441
19.2.8 Reset ..................................................................................................................................... 441
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Table of Contents
20 Package Information ........................................................................................................ 444
A Serial Flash Loader .......................................................................................................... 446
A.1 Serial Flash Loader ................................................................................................................. 446
A.2 Interfaces ............................................................................................................................... 446
A.2.1 UART ..................................................................................................................................... 446
A.2.2 SSI ......................................................................................................................................... 446
A.3 Packet Handling ...................................................................................................................... 447
A.3.1 Packet Format ........................................................................................................................ 447
A.3.2 Sending Packets ..................................................................................................................... 447
A.3.3 Receiving Packets ................................................................................................................... 447
A.4 Commands ............................................................................................................................. 448
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 448
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 448
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 448
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 449
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 449
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 449
B Register Quick Reference ............................................................................................... 451
C Ordering and Contact Information ................................................................................. 467
C.1 Ordering Information ................................................................................................................ 467
C.2 Kits ......................................................................................................................................... 467
C.3 Company Information .............................................................................................................. 467
C.4 Support Information ................................................................................................................. 468
7November 30, 2007
Preliminary
LM3S2016 Microcontroller
List of Figures
Figure 1-1. Stellaris®2000 Series High-Level Block Diagram ............................................................... 26
Figure 2-1. CPU Block Diagram ......................................................................................................... 34
Figure 2-2. TPIU Block Diagram ........................................................................................................ 35
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 44
Figure 5-2. Test Access Port State Machine ....................................................................................... 47
Figure 5-3. IDCODE Register Format ................................................................................................. 52
Figure 5-4. BYPASS Register Format ................................................................................................ 53
Figure 5-5. Boundary Scan Register Format ....................................................................................... 53
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 55
Figure 7-1. Flash Block Diagram ...................................................................................................... 109
Figure 8-1. GPIO Port Block Diagram ............................................................................................... 134
Figure 8-2. GPIODATA Write Example ............................................................................................. 135
Figure 8-3. GPIODATA Read Example ............................................................................................. 135
Figure 9-1. GPTM Module Block Diagram ........................................................................................ 175
Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 179
Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 180
Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 181
Figure 10-1. WDT Module Block Diagram .......................................................................................... 210
Figure 11-1. ADC Module Block Diagram ........................................................................................... 234
Figure 12-1. UART Module Block Diagram ......................................................................................... 266
Figure 12-2. UART Character Frame ................................................................................................. 267
Figure 12-3. IrDA Data Modulation ..................................................................................................... 269
Figure 13-1. SSI Module Block Diagram ............................................................................................. 306
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 308
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 309
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 310
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 310
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 311
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 312
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 312
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 313
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 314
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 315
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 315
Figure 14-1. I2C Block Diagram ......................................................................................................... 343
Figure 14-2. I2C Bus Configuration .................................................................................................... 344
Figure 14-3. START and STOP Conditions ......................................................................................... 344
Figure 14-4. Complete Data Transfer with a 7-Bit Address ................................................................... 345
Figure 14-5. R/S Bit in First Byte ........................................................................................................ 345
Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 345
Figure 14-7. Master Single SEND ...................................................................................................... 348
Figure 14-8. Master Single RECEIVE ................................................................................................. 349
Figure 14-9. Master Burst SEND ....................................................................................................... 350
Figure 14-10. Master Burst RECEIVE .................................................................................................. 351
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 352
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Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 353
Figure 14-13. Slave Command Sequence ............................................................................................ 354
Figure 15-1. CAN Module Block Diagram ........................................................................................... 379
Figure 15-2. CAN Bit Time ................................................................................................................ 386
Figure 16-1. Pin Connection Diagram ................................................................................................ 419
Figure 19-1. Load Conditions ............................................................................................................ 436
Figure 19-2. I2C Timing ..................................................................................................................... 438
Figure 19-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 438
Figure 19-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 439
Figure 19-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 439
Figure 19-6. JTAG Test Clock Input Timing ......................................................................................... 440
Figure 19-7. JTAG Test Access Port (TAP) Timing .............................................................................. 441
Figure 19-8. JTAG TRST Timing ........................................................................................................ 441
Figure 19-9. External Reset Timing (RST) .......................................................................................... 442
Figure 19-10. Power-On Reset Timing ................................................................................................. 442
Figure 19-11. Brown-Out Reset Timing ................................................................................................ 442
Figure 19-12. Software Reset Timing ................................................................................................... 443
Figure 19-13. Watchdog Reset Timing ................................................................................................. 443
Figure 20-1. 100-Pin LQFP Package .................................................................................................. 444
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LM3S2016 Microcontroller
List of Tables
Table 1. Documentation Conventions ............................................................................................ 18
Table 3-1. Memory Map ................................................................................................................... 39
Table 4-1. Exception Types .............................................................................................................. 41
Table 4-2. Interrupts ........................................................................................................................ 42
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 45
Table 5-2. JTAG Instruction Register Commands ............................................................................... 50
Table 6-1. System Control Register Map ........................................................................................... 60
Table 7-1. Flash Protection Policy Combinations ............................................................................. 111
Table 7-2. Flash Resident Registers ............................................................................................... 112
Table 7-3. Flash Register Map ........................................................................................................ 112
Table 8-1. GPIO Pad Configuration Examples ................................................................................. 137
Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 137
Table 8-3. GPIO Register Map ....................................................................................................... 138
Table 9-1. Available CCP Pins ........................................................................................................ 175
Table 9-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 178
Table 9-3. Timers Register Map ...................................................................................................... 184
Table 10-1. Watchdog Timer Register Map ........................................................................................ 211
Table 11-1. Samples and FIFO Depth of Sequencers ........................................................................ 234
Table 11-2. ADC Register Map ......................................................................................................... 237
Table 12-1. UART Register Map ....................................................................................................... 271
Table 13-1. SSI Register Map .......................................................................................................... 316
Table 14-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 346
Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 355
Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 360
Table 15-1. Transmit Message Object Bit Settings ............................................................................. 382
Table 15-2. Receive Message Object Bit Settings .............................................................................. 384
Table 15-3. CAN Protocol Ranges .................................................................................................... 386
Table 15-4. CAN Register Map ......................................................................................................... 389
Table 17-1. Signals by Pin Number ................................................................................................... 420
Table 17-2. Signals by Signal Name ................................................................................................. 423
Table 17-3. Signals by Function, Except for GPIO ............................................................................. 427
Table 17-4. GPIO Pins and Alternate Functions ................................................................................. 430
Table 18-1. Temperature Characteristics ........................................................................................... 432
Table 18-2. Thermal Characteristics ................................................................................................. 432
Table 19-1. Maximum Ratings .......................................................................................................... 433
Table 19-2. Recommended DC Operating Conditions ........................................................................ 433
Table 19-3. LDO Regulator Characteristics ....................................................................................... 434
Table 19-4. Detailed Power Specifications ........................................................................................ 435
Table 19-5. Flash Memory Characteristics ........................................................................................ 435
Table 19-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 436
Table 19-7. Clock Characteristics ..................................................................................................... 436
Table 19-8. Crystal Characteristics ................................................................................................... 436
Table 19-9. ADC Characteristics ....................................................................................................... 437
Table 19-10. I2C Characteristics ......................................................................................................... 437
Table 19-11. SSI Characteristics ........................................................................................................ 438
Table 19-12. JTAG Characteristics ..................................................................................................... 439
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Table 19-13. GPIO Characteristics ..................................................................................................... 441
Table 19-14. Reset Characteristics ..................................................................................................... 441
Table C-1. Part Ordering Information ............................................................................................... 467
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LM3S2016 Microcontroller
List of Registers
System Control .............................................................................................................................. 54
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 62
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 64
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 65
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 66
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 67
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 68
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 69
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 70
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 74
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 75
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 77
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 78
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 80
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 81
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 83
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 85
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 87
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 88
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 90
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 92
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 94
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 96
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 98
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 100
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 102
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 104
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 106
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 107
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 108
Internal Memory ........................................................................................................................... 109
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 114
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 115
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 116
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 118
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 119
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 120
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 121
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 122
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 123
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 124
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 125
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 126
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 127
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 128
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Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 129
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 130
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 131
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 132
General-Purpose Input/Outputs (GPIOs) ................................................................................... 133
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 140
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 141
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 142
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 143
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 144
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 145
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 146
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 147
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 148
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 149
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 151
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 152
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 153
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 154
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 155
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 156
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 157
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 158
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 159
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 160
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 162
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 163
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 164
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 165
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 166
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 167
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 168
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 169
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 170
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 171
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 172
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 173
General-Purpose Timers ............................................................................................................. 174
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 186
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 187
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 189
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 191
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 194
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 196
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 197
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 198
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 200
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 201
13November 30, 2007
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LM3S2016 Microcontroller
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 202
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 203
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 204
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 205
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 206
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 207
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 208
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 209
Watchdog Timer ........................................................................................................................... 210
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 213
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 214
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 215
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 216
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 217
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 218
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 219
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 220
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 221
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 222
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 223
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 224
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 225
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 226
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 227
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 228
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 229
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 230
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 231
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 232
Analog-to-Digital Converter (ADC) ............................................................................................. 233
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 239
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 240
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 241
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 242
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 243
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 244
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 247
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 248
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 249
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 250
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 251
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 253
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 256
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 256
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 256
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 256
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 257
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 257
November 30, 200714
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Table of Contents
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 257
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 257
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 258
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 258
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 259
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 259
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 261
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 262
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 263
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 265
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 273
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 275
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 277
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 279
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 280
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 281
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 282
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 284
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 286
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 288
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 290
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 291
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 292
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 294
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 295
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 296
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 297
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 298
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 299
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 300
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 301
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 302
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 303
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 304
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 305
Synchronous Serial Interface (SSI) ............................................................................................ 306
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 318
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 320
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 322
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 323
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 325
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 326
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 328
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 329
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 330
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 331
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 332
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 333
15November 30, 2007
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LM3S2016 Microcontroller
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 334
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 335
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 336
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 337
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 338
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 339
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 340
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 341
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 342
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 343
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 357
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 358
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 362
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 363
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 364
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 365
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 366
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 367
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 368
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 370
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 371
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 373
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 374
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 375
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 376
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 377
Controller Area Network (CAN) Module ..................................................................................... 378
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 392
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 394
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 397
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 398
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 400
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 401
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 403
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 404
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 404
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 405
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 405
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 408
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 408
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 409
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 409
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 410
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 410
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 411
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 411
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 412
November 30, 200716
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Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 412
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 414
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 414
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 414
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 414
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 414
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 414
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 414
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 414
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 415
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 415
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 416
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 416
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 417
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 417
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 418
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 418
17November 30, 2007
Preliminary
LM3S2016 Microcontroller
About This Document
This data sheet provides reference information for the LM3S2016 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■ARM® Cortex™-M3 Technical Reference Manual
■ARM® CoreSight Technical Reference Manual
■ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 18.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
REGISTER
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 39.
offset 0xnnn
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register N
November 30, 200718
Preliminary
About This Document
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
reserved
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
yy:xx
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Register Bit/Field
Types
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
W1C
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Reset Value
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin/Signal Notation
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
assert a signal
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
SIGNAL
Numbers
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
X
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
0x
19November 30, 2007
Preliminary
LM3S2016 Microcontroller
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris®
LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris
family with Bosch CAN networking technology, the golden standard in short-haul industrial networks.
The Stellaris®LM3S2000 series also marks the first integration of CAN capabilities with the
revolutionary Cortex-M3 core. The Stellaris®LM3S6000 series combines both a 10/100 Ethernet
Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated
connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC
and PHY available in an ARM architecture MCU. The Stellaris®LM3S8000 series combines Bosch
Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and
Physical (PHY) layer.
The LM3S2016 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
In addition, the LM3S2016 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S2016 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S2016 microcontroller includes the following product features:
■32-Bit RISC Performance
–32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
–System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
–Thumb®-compatible Thumb-2-only instruction set processor core for high code density
–50-MHz operation
–Hardware-division and single-cycle-multiplication
November 30, 200720
Preliminary
Architectural Overview
–Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
–24 interrupts with eight priority levels
–Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
–Unaligned data access, enabling data to be efficiently packed into memory
–Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■Internal Memory
–64 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
–8 KB single-cycle SRAM
■General-Purpose Timers
–Two General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
–32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
–16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
21November 30, 2007
Preliminary
LM3S2016 Microcontroller
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
–16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
–16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ARM FiRM-compliant Watchdog Timer
–32-bit down counter with a programmable load register
–Separate watchdog clock with an enable
–Programmable interrupt generation logic with interrupt masking
–Lock register protection from runaway software
–Reset generation logic with an enable/disable
–User-enabled stalling when the controller asserts the CPU Halt flag during debug
■Controller Area Network (CAN)
–Supports CAN protocol version 2.0 part A/B
–Bit rates up to 1Mb/s
–32 message objects, each with its own identifier mask
–Maskable interrupt
–Disable automatic retransmission mode for TTCAN
–Programmable loop-back mode for self-test operation
■Synchronous Serial Interface (SSI)
–Master or slave operation
–Programmable clock bit rate and prescale
–Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
–Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
–Programmable data frame size from 4 to 16 bits
November 30, 200722
Preliminary
Architectural Overview
–Internal loopback test mode for diagnostic/debug testing
■UART
–Two fully programmable 16C550-type UARTs with IrDA support
–Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
–Programmable baud-rate generator with fractional divider
–Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
–FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
–Standard asynchronous communication bits for start, stop, and parity
–False-start-bit detection
–Line-break generation and detection
■ADC
–Single- and differential-input configurations
–Four 10-bit channels (inputs) when used as single-ended inputs
–Sample rate of 500 thousand samples/second
–Flexible, configurable analog-to-digital conversion
–Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
–Each sequence triggered by software or internal event (timers, or GPIO)
■I2C
–Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
–Interrupt generation
–Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■GPIOs
–18-39 GPIOs, depending on configuration
–5-V-tolerant input/outputs
–Programmable interrupt generation as either edge-triggered or level-sensitive
–Bit masking in both read and write operations through address lines
23November 30, 2007
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–Can initiate an ADC sample sequence
–Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■Power
–On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
–Low-power options on controller: Sleep and Deep-sleep modes
–Low-power options for peripherals: software controls shutdown of individual peripherals
–User-enabled LDO unregulated voltage detection and automatic reset
–3.3-V supply brown-out detection and reporting via interrupt or reset
■Flexible Reset Sources
–Power-on reset (POR)
–Reset pin assertion
–Brown-out (BOR) detector alerts to system power drops
–Software reset
–Watchdog timer reset
–Internal low drop-out (LDO) regulator output goes unregulated
■Additional Features
–Six reset sources
–Programmable clock source control
–Clock gating to individual peripherals for power savings
–IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
–Debug access via JTAG and Serial Wire interfaces
–Full JTAG boundary scan
■Industrial-range 100-pin RoHS-compliant LQFP package
November 30, 200724
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Architectural Overview
1.2 Target Applications
■Remote monitoring
■Electronic point-of-sale (POS) machines
■Test and measurement equipment
■Network appliances and switches
■Factory automation
■HVAC and building control
■Gaming equipment
■Motion control
■Medical instrumentation
■Fire and security
■Power and energy
■Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 26 represents the full set of features in the Stellaris®2000 series of devices;
not all features may be available on the LM3S2016 microcontroller.
25November 30, 2007
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LM3S2016 Microcontroller
Figure 1-1. Stellaris®2000 Series High-Level Block Diagram
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S2016 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 467.
November 30, 200726
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Architectural Overview
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 33)
All members of the Stellaris®product family, including the LM3S2016 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 33 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■A high-speed alarm timer using the system clock.
■A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■A simple counter. Software can use this to measure time to completion and time used.
■An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S2016 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 24 interrupts.
“Interrupts” on page 41 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S2016 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
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On the LM3S2016, PWM motion control functionality can be achieved through:
■The motion control features of the general-purpose timers using the CCP pins
CCP Pins (see page 180)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Analog Peripherals
To handle analog signals, the LM3S2016 microcontroller offers an Analog-to-Digital Converter
(ADC).
1.4.3.1 ADC (see page 233)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S2016 ADC module features 10-bit conversion resolution and supports four input channels.
Four buffered sample sequences allow rapid sampling of up to eight analog input sources without
controller intervention. Each sample sequence provides flexible programming with fully configurable
input source, trigger events, interrupt generation, and sequence priority.
1.4.4 Serial Communications Peripherals
The LM3S2016 controller supports both asynchronous and synchronous serial communications
with:
■Two fully programmable 16C550-type UARTs
■One SSI module
■One I2C module
■One CAN unit
1.4.4.1 UART (see page 265)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S2016 controller includes two fully programmable 16C550-type UARTs that support data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 306)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S2016 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
November 30, 200728
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Architectural Overview
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.4.3 I2C (see page 343)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking
devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and
diagnostic purposes in product development and manufacture.
The LM3S2016 controller includes one I2C module that provides the ability to communicate to other
IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write
and read) data.
Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive,
Slave Transmit, and Slave Receive.
A Stellaris®I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I2C slave generates
interrupts when data has been sent or requested by a master.
1.4.4.4 Controller Area Network (see page 378)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, now it is used in many embedded control
applications (for example, industrial or medical). Bit rates up to 1Mb/s are possible at network lengths
below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kb/s at
500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information. The LM3S2016 includes one CAN units.
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1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 133)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris®GPIO module is composed of eight physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 18-39 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
420 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.5.2 Two Programmable Timers (see page 174)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris®General-Purpose Timer Module (GPTM) contains two GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Timers can also be used to trigger analog-to-digital (ADC) conversions.
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 210)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris®Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S2016 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 109)
The LM3S2016 static random access memory (SRAM) controller supports 8 KB SRAM. The internal
SRAM of the Stellaris®devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
November 30, 200730
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1.4.6.2 Flash (see page 110)
The LM3S2016 Flash controller supports 64 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.7 Additional Features
1.4.7.1 Memory Map (see page 39)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S2016 controller can be found in “Memory Map” on page 39. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.7.2 JTAG TAP Controller (see page 43)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
The JTAG port is comprised of the standard five pins: TRST,TCK,TMS,TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.7.3 System Control and Clocks (see page 54)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
■“Pin Diagram” on page 419
■“Signal Tables” on page 420
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2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power consumption,
while delivering outstanding computational performance and exceptional system response to
interrupts. Features include:
■Compact core.
■Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■Migration from the ARM7™ processor family for better performance and power efficiency.
■Full-featured debug solution with a:
–Serial Wire JTAG Debug Port (SWJ-DP)
–Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
–Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
–Instrumentation Trace Macrocell (ITM) for support of printf style debugging
–Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
The Stellaris®family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
33November 30, 2007
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2.1 Block Diagram
Figure 2-1. CPU Block Diagram
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Adv. High-
Perf. Bus
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
2.2 Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris®implementation.
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 34. As
noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are
flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1 Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris®devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
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ARM Cortex-M3 Processor Core
2.2.2 Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris®devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris®devices have implemented TPIU as shown in Figure 2-2 on page 35.
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ATB
Interface Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
2.2.4 ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
2.2.5 Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S2016 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
2.2.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■Facilitates low-latency exception and interrupt handling
■Controls power management
■Implements system control registers
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The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge
of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
All NVIC registers and system debug registers are little endian regardless of the endianness state
of the processor.
2.2.6.1 Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S2016 microcontroller supports 24 interrupts with eight priority
levels.
2.2.6.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■A high-speed alarm timer using the system clock.
■A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■A simple counter. Software can use this to measure time to completion and time used.
■An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
Functional Description
The timer consists of three registers:
■A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
■The reload value for the counter, used to provide the counter's wrap value.
■The current value of the counter.
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris®devices.
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
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Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write
does not trigger the SysTick exception logic. On a read, the current value is the value of the register
at the time the register is accessed.
If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect
to a reference clock. The reference clock can be the core clock or an external clock source.
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
0ROreserved31:17
Returns 1 if timer counted to 0 since last time this was read. Clears on read by
application. If read by the debugger using the DAP, this bit is cleared on read-only
if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
0R/WCOUNTFLAG16
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
0ROreserved15:3
0 = external reference clock. (Not implemented for Stellaris microcontrollers.)
1 = core clock.
If no reference clock is provided, it is held at 1 and so gives the same time as the
core clock. The core clock must be at least 2.5 times faster than the reference clock.
If it is not, the count values are unpredictable.
0R/WCLKSOURCE2
1 = counting down to 0 pends the SysTick handler.
0 = counting down to 0 does not pend the SysTick handler. Software can use the
COUNTFLAG to determine if ever counted to 0.
0R/WTICKINT1
1 = counter operates in a multi-shot way. That is, counter loads with the Reload
value and then begins counting down. On reaching 0, it sets the COUNTFLAG to
1 and optionally pends the SysTick handler, based on TICKINT. It then loads the
Reload value again, and begins counting.
0 = counter disabled.
0R/WENABLE0
SysTick Reload Value Register
Use the SysTick Reload Value Register to specify the start value to load into the current value
register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value
of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is
any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99
must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single
shot, then the actual count down must be written. For example, if a tick is next required after 400
clock pulses, 400 must be written into the RELOAD.
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a read-modify-write
operation.
0ROreserved31:24
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DescriptionResetTypeNameBit/Field
Value to load into the SysTick Current Value Register when the counter reaches 0.-W1CRELOAD23:0
SysTick Current Value Register
Use the SysTick Current Value Register to find the current value in the register.
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
0ROreserved31:24
Current value at the time the register is accessed. No read-modify-write protection is
provided, so change with care.
This register is write-clear. Writing to it with any value clears the register to 0. Clearing
this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
-W1CCURRENT23:0
SysTick Calibration Value Register
The SysTick Calibration Value register is not implemented.
November 30, 200738
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3 Memory Map
The memory map for the LM3S2016 controller is provided in Table 3-1 on page 39.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 39, addresses not listed are reserved.
Table 3-1. Memory Mapa
For details on
registers, see
page ...
DescriptionEndStart
Memory
113On-chip flash b
0x0000.FFFF0x0000.0000
113Bit-banded on-chip SRAMc
0x2000.1FFF0x2000.0000
-Reserved non-bit-banded SRAM space0x21FF.FFFF0x2010.0000
109Bit-band alias of 0x2000.0000 through 0x200F.FFFF0x23FF.FFFF0x2200.0000
-Reserved non-bit-banded SRAM space0x3FFF.FFFF0x2400.0000
FiRM Peripherals
212Watchdog timer0x4000.0FFF0x4000.0000
139GPIO Port A0x4000.4FFF0x4000.4000
139GPIO Port B0x4000.5FFF0x4000.5000
139GPIO Port C0x4000.6FFF0x4000.6000
139GPIO Port D0x4000.7FFF0x4000.7000
317SSI00x4000.8FFF0x4000.8000
272UART00x4000.CFFF0x4000.C000
272UART10x4000.DFFF0x4000.D000
Peripherals
356I2C Master 00x4002.07FF0x4002.0000
369I2C Slave 00x4002.0FFF0x4002.0800
139GPIO Port E0x4002.4FFF0x4002.4000
139GPIO Port F0x4002.5FFF0x4002.5000
139GPIO Port G0x4002.6FFF0x4002.6000
139GPIO Port H0x4002.7FFF0x4002.7000
185Timer00x4003.0FFF0x4003.0000
185Timer10x4003.1FFF0x4003.1000
238ADC0x4003.8FFF0x4003.8000
391CAN0 Controller0x4004.0FFF0x4004.0000
113Flash control0x400F.DFFF0x400F.D000
61System control0x400F.EFFF0x400F.E000
-Bit-banded alias of 0x4000.0000 through 0x400F.FFFF0x43FF.FFFF0x4200.0000
Private Peripheral Bus
39November 30, 2007
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For details on
registers, see
page ...
DescriptionEndStart
ARM®
Cortex™-M3
Technical
Reference
Manual
Instrumentation Trace Macrocell (ITM)0xE000.0FFF0xE000.0000
Data Watchpoint and Trace (DWT)0xE000.1FFF0xE000.1000
Flash Patch and Breakpoint (FPB)0xE000.2FFF0xE000.2000
Reserved0xE000.DFFF0xE000.3000
Nested Vectored Interrupt Controller (NVIC)0xE000.EFFF0xE000.E000
Reserved0xE003.FFFF0xE000.F000
Trace Port Interface Unit (TPIU)0xE004.0FFF0xE004.0000
-Reserved0xE004.1FFF0xE004.1000
-Reserved0xE00F.FFFF0xE004.2000
-Reserved for vendor peripherals0xFFFF.FFFF0xE010.0000
a. All reserved space returns a bus fault when read or written.
b. The unavailable flash will bus fault throughout this range.
c. The unavailable SRAM will bus fault throughout this range.
November 30, 200740
Preliminary
Memory Map
4 Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which
enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back
interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 on page 41 lists all the exceptions. Software can set eight priority levels on seven of these
exceptions (system handlers) as well as on 24 interrupts (listed in Table 4-2 on page 42).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. You can also group priorities by splitting priority levels into pre-emption priorities
and subpriorities. All the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower the
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Note: In Table 4-2 on page 42 interrupts not listed are reserved.
Table 4-1. Exception Types
DescriptionPrioritya
PositionException Type
Stack top is loaded from first entry of vector table on reset.-0-
Invoked on power up and warm reset. On first instruction, drops to lowest
priority (and then is called the base level of activation). This is
asynchronous.
-3 (highest)1Reset
Cannot be stopped or preempted by any exception but reset. This is
asynchronous.
An NMI is only producible by software, using the NVIC Interrupt Control
State register.
-22Non-Maskable
Interrupt (NMI)
All classes of Fault, when the fault cannot activate due to priority or the
configurable fault handler has been disabled. This is synchronous.
-13Hard Fault
MPU mismatch, including access violation and no match. This is
synchronous.
The priority of this exception can be changed.
settable4Memory Management
Pre-fetch fault, memory access fault, and other address/memory related
faults. This is synchronous when precise and asynchronous when
imprecise.
You can enable or disable this fault.
settable5Bus Fault
Usage fault, such as undefined instruction executed or illegal state
transition attempt. This is synchronous.
settable6Usage Fault
Reserved.-7-10-
System service call with SVC instruction. This is synchronous.settable11SVCall
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DescriptionPrioritya
PositionException Type
Debug monitor (when not halting). This is synchronous, but only active
when enabled. It does not activate if lower priority than the current
activation.
settable12Debug Monitor
Reserved.-13-
Pendable request for system service. This is asynchronous and only
pended by software.
settable14PendSV
System tick timer has fired. This is asynchronous.settable15SysTick
Asserted from outside the ARM Cortex-M3 core and fed through the NVIC
(prioritized). These are all asynchronous. Table 4-2 on page 42 lists the
interrupts on the LM3S2016 controller.
settable16 and
above
Interrupts
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
DescriptionInterrupt (Bit in Interrupt Registers)
GPIO Port A0
GPIO Port B1
GPIO Port C2
GPIO Port D3
GPIO Port E4
UART05
UART16
SSI07
I2C08
ADC Sequence 014
ADC Sequence 115
ADC Sequence 216
ADC Sequence 317
Watchdog timer18
Timer0 A19
Timer0 B20
Timer1 A21
Timer1 B22
System Control28
Flash Control29
GPIO Port F30
GPIO Port G31
GPIO Port H32
CAN039
November 30, 200742
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Interrupts
5 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of the standard five pins: TRST,TCK,TMS,TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
The JTAG module has the following features:
■IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■Four-bit Instruction Register (IR) chain for storing JTAG instructions
■IEEE standard instructions:
–BYPASS instruction
–IDCODE instruction
–SAMPLE/PRELOAD instruction
–EXTEST instruction
–INTEST instruction
■ARM additional instructions:
–APACC instruction
–DPACC instruction
–ABORT instruction
■Integrated ARM Serial Wire Debug (SWD)
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
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5.1 Block Diagram
Figure 5-1. JTAG Module Block Diagram
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TRST
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
5.2 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 44. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST,TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 50 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 439 for JTAG timing diagrams.
November 30, 200744
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JTAG Interface
5.2.1 JTAG Interface Pins
The JTAG interface consists of five standard pins: TRST,TCK,TMS,TDI, and TDO. These pins and
their associated reset state are given in Table 5-1 on page 45. Detailed information on each pin
follows.
Table 5-1. JTAG Port Pins Reset State
Drive ValueDrive StrengthInternal Pull-DownInternal Pull-UpData DirectionPin Name
N/AN/ADisabledEnabledInputTRST
N/AN/ADisabledEnabledInputTCK
N/AN/ADisabledEnabledInputTMS
N/AN/ADisabledEnabledInputTDI
High-Z2-mA driverDisabledEnabledOutputTDO
5.2.1.1 Test Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP
controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the
Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters
the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction,
IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled
on PB7/TRST; otherwise JTAG communication could be lost.
5.2.1.2 Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers
that are daisy-chained together can synchronously communicate serial test data between
components. During normal operation, TCK is driven by a free-running clock with a nominal 50%
duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK
is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction
and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
5.2.1.3 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered.
Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine
can be seen in its entirety in Figure 5-2 on page 47.
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By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost.
5.2.1.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling
edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost.
5.2.1.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states.
5.2.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 47. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state, please
refer to IEEE Standard 1149.1.
November 30, 200746
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JTAG Interface
Figure 5-2. Test Access Port State Machine
Test Logic Reset
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
1 11
1 1
1
1 1
1 1
1 1
1 1
1 10 0
00
00
0 0
0 0
0 0
00
0
0
5.2.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 50.
5.2.4 Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG pins
can be programmed to be GPIOs, board configuration and reset conditions on these pins must be
considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the
method for switching between these two operational modes is described below.
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5.2.4.1 GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting
GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate
hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging
or board-level testing, this provides five more GPIOs for use in the design.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris®microcontroller. If the program code loaded into ash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 149) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 159) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 160) have been set to 1.
Recovering a "Locked" Device
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the device. Performing
a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset
mass erases the flash memory. The sequence to recover the device is:
1. Assert and hold the RST signal.
2. Perform the JTAG-to-SWD switch sequence.
3. Perform the SWD-to-JTAG switch sequence.
4. Perform the JTAG-to-SWD switch sequence.
5. Perform the SWD-to-JTAG switch sequence.
6. Perform the JTAG-to-SWD switch sequence.
7. Perform the SWD-to-JTAG switch sequence.
8. Perform the JTAG-to-SWD switch sequence.
9. Perform the SWD-to-JTAG switch sequence.
10. Perform the JTAG-to-SWD switch sequence.
11. Perform the SWD-to-JTAG switch sequence.
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12. Release the RST signal.
The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug
(SWD)” on page 49. When performing switch sequences for the purpose of recovering the debug
capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed.
5.2.4.2 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller
in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the
following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test
Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run
Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequences of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occurring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in SWD mode, before sending the switch sequence, the SWD goes into the line reset
state.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch sequence to the device. The 16-bit switch sequence
for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also
be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should
consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and
SWD are in their reset/idle states.
49November 30, 2007
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LM3S2016 Microcontroller
2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C.
3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was
already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic
Reset state.
5.3 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. This is done by enabling the five JTAG
pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register.
5.4 Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The registers
can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register
connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2 on page 50. A detailed explanation of each instruction, along
with its associated Data Register, follows.
Table 5-2. JTAG Instruction Register Commands
DescriptionInstructionIR[3:0]
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction onto the pads.
EXTEST0000
Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD
instruction into the controller.
INTEST0001
Captures the current I/O values and shifts the sampled values out of the Boundary Scan
Chain while new preload data is shifted in.
SAMPLE / PRELOAD0010
Shifts data into the ARM Debug Port Abort Register.ABORT1000
Shifts data into and out of the ARM DP Access Register.DPACC1010
Shifts data into and out of the ARM AC Access Register.APACC1011
Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE
chain and shifts it out.
IDCODE1110
Connects TDI to TDO through a single Shift Register chain.BYPASS1111
Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO.ReservedAll Others
5.4.1.1 EXTEST Instruction
The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. This allows
November 30, 200750
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JTAG Interface
tests to be developed that drive known values out of the controller, which can be used to verify
connectivity.
5.4.1.2 INTEST Instruction
The INTEST instruction does not have an associated Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows tests
to be developed that drive known values into the controller, which can be used for testing. It is
important to note that although the RST input pin is on the Boundary Scan Data Register chain, it
is only observable.
5.4.1.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data
Register” on page 53 for more information.
5.4.1.4 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. Please see the “ABORT Data Register” on page 53 for more
information.
5.4.1.5 DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 53 for more information.
5.4.1.6 APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please see “APACC Data Register” on page 53 for more information.
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5.4.1.7 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 52 for more
information.
5.4.1.8 BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 52 for
more information.
5.4.2 Data Registers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan,
APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed
in the following sections.
5.4.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3 on page 52. The standard requires that every JTAG-compliant device implement either
the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1
processor. This allows the debuggers to automatically configure themselves to work correctly with
the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
5.4.2.2 BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4 on page 53. The standard requires that every JTAG-compliant device implement either
the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default instruction.
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Figure 5-4. BYPASS Register Format
5.4.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 53. Each GPIO
pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because
the reset pin is always an input, only the input signal is included in the Data Register chain.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 5-5. Boundary Scan Register Format
OTDOTDI O
I
N E
U
T
O
O
I
N E
U
TO
O
I
N E
U
TO
O
I
N E
U
T
I
N
... ...
RSTGPIO PB6 GPIOm GPIO m+1 GPIO n
For detailed information on the order of the input, output, and output enable bits for each of the
GPIO ports, please refer to the Stellaris®Family Boundary Scan Description Language (BSDL) files,
downloadable from www.luminarymicro.com.
5.4.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
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6 System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking to the core and individual peripherals, and handles reset detection and
reporting.
6.1 Functional Description
The System Control module provides the following capabilities:
■Device identification, see “Device Identification” on page 54
■Local control, such as reset (see “Reset Control” on page 54), power (see “Power
Control” on page 57) and clock control (see “Clock Control” on page 57)
■System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 59
6.1.1 Device Identification
Seven read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0,DID1, and DC0-DC4 registers.
6.1.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
6.1.2.2 Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 54.
2. Power-on reset (POR), see “Power-On Reset (POR)” on page 55.
3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 55.
4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 56.
5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 56.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator.
6.1.2.3 RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals except
the JTAG TAP controller (see “JTAG Interface” on page 43). The external reset sequence is as
follows:
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1. The external reset pin (RST) is asserted and then de-asserted.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for
synchronization.
The external reset timing is shown in Figure 19-9 on page 442.
6.1.2.4 Power-On Reset (POR)
The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit
generates a reset signal to the internal logic when the power supply ramp reaches a threshold value
(VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power
supply (VDD) through a pull-up resistor (1K to 10K Ω).
The device must be operating within the specified operating parameters at the point when the on-chip
power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within
10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of
an external reset to hold the device in reset longer than the internal POR, the RST input may be
used with the circuit as shown in Figure 6-1 on page 55.
Figure 6-1. External Circuitry to Extend Reset
R1
C1
R2
RST
Stellaris
D1
The R1and C1components define the power-on delay. The R2resistor mitigates any leakage from
the RST input. The diode (D1) discharges C1rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST) or internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, the first instruction designated by the program counter, and begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing
is shown in Figure 19-10 on page 442.
Note: The power-on reset also resets the JTAG controller. An external reset does not.
6.1.2.5 Brown-Out Reset (BOR)
A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops
below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may
generate a controller interrupt or a system reset.
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Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger
a reset.
The brown-out reset is equivelent to an assertion of the external RST input and the reset is held
active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt
handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to
determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 19-11 on page 442.
6.1.2.6 Software Reset
Software can reset a specific peripheral or generate a reset to the entire system .
Peripherals can be individually reset by software via three registers that control reset signals to each
peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and
subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with
the encoding of the clock gating control for peripherals and on-chip functions (see “System
Control” on page 59). Note that all reset signals for all clocks of the specified unit are asserted as
a result of a software-initiated reset.
The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the controller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
The software-initiated system reset timing is shown in Figure 19-12 on page 443.
6.1.2.7 Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts
down to its zero state again before the first time-out interrupt is cleared, and the reset signal has
been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset
sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the controller loads from memory the initial stack pointer, the
initial program counter, the first instruction designated by the program counter, and begins
execution.
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The watchdog reset timing is shown in Figure 19-13 on page 443.
6.1.3 Power Control
The Stellaris®microcontroller provides an integrated LDO regulator that may be used to provide
power to the majority of the controller's internal logic. The LDO regulator provides software a
mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V
to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ
field in the LDO Power Control (LDOPCTL) register.
Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or
by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25
pins on the printed circuit board. The LDO requires decoupling capacitors on the printed
circuit board. If an external regulator is used, it is strongly recommended that the external
regulator supply the controller only and not be shared with other devices on the printed
circuit board.
6.1.4 Clock Control
System control determines the control of clocks in this part.
6.1.4.1 Fundamental Clock Sources
There are four clock sources for use in the device:
■Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
■Main Oscillator: The main oscillator provides a frequency-accurate clock source by one of two
means: an external single-ended clock source is connected to the OSC0 input pin, or an external
crystal is connected across the OSC0 input and OSC1 output pins. The crystal value allowed
depends on whether the main oscillator is used as the clock reference source to the PLL. If so,
the crystal must be one of the supported frequencies between 3.579545 MHz through 8.192
MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit in
the RCC register (see page 70).
■Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
The internal system clock (sysclk), is derived from any of the four sources plus two others: the output
of the internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the
PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
57November 30, 2007
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used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options.
6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 70) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
6.1.4.3 PLL Frequency Configuration
The PLL is disabled by default during power-on reset and is enabled later by software if required.
Software configures the PLL input reference clock source, specifies the output divisor to set the
system clock frequency, and enables the PLL to drive the output.
If the main oscillator provides the clock reference to the PLL, the translation provided by hardware
and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG)
register (see page 74). The internal translation provides a translation within ± 1% of the targeted
PLL VCO frequency.
The Crystal Value field (XTAL) on page 70 describes the available crystal choices and default
programming of the PLLCFG register. The crystal number is written into the XTAL field of the
Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings
are translated and the internal PLL settings are updated.
6.1.4.4 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■Normal: The PLL multiplies the input clock reference and drives the output.
■Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 70 and page 75).
6.1.4.5 PLL Operation
If the PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
19-6 on page 436). During this time, the PLL is not usable as a clock reference.
The PLL is changed by one of the following:
■Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to
keep the PLL from being used as a system clock until the TREADY condition is met after one of the
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two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC/RCC2 register is switched to use the PLL.
6.1.5 System Control
For power-savings purposes, the RCGCn ,SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active
peripherals is unchanged, but the processor is not clocked and therefore no longer executes code.
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code. Each mode is described in more detail below.
There are four levels of operation for the device defined as:
■Run Mode. Run mode provides normal operation of the processor and all of the peripherals that
are currently enabled by the RCGCn registers. The system clock can be any of the available
clock sources including the PLL.
■Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for
Interrupt) instruction. Any properly configured interrupt event in the system will bring the
processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3
Technical Reference Manual for more details.
In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in
the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any
properly configured interrupt event in the system will bring the processor back into Run mode.
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up,
if necessary, and the main oscillator is powered down. If the PLL is running at the time of the
WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active
RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration.
6.2 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
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1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
6.3 Register Map
Table 6-1 on page 60 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Table 6-1. System Control Register Map
See
page
DescriptionResetTypeNameOffset
62Device Identification 0-RODID00x000
78Device Identification 1-RODID10x004
80Device Capabilities 00x001F.001FRODC00x008
81Device Capabilities 10x0101.329FRODC10x010
83Device Capabilities 20x0003.1013RODC20x014
85Device Capabilities 30x0F0F.0000RODC30x018
87Device Capabilities 40x0000.00FFRODC40x01C
64Brown-Out Reset Control0x0000.7FFDR/WPBORCTL0x030
65LDO Power Control0x0000.0000R/WLDOPCTL0x034
106Software Reset Control 00x00000000R/WSRCR00x040
107Software Reset Control 10x00000000R/WSRCR10x044
108Software Reset Control 20x00000000R/WSRCR20x048
66Raw Interrupt Status0x0000.0000RORIS0x050
67Interrupt Mask Control0x0000.0000R/WIMC0x054
68Masked Interrupt Status and Clear0x0000.0000R/W1CMISC0x058
69Reset Cause-R/WRESC0x05C
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See
page
DescriptionResetTypeNameOffset
70Run-Mode Clock Configuration0x07A0.3AD1R/WRCC0x060
74XTAL to PLL Translation-ROPLLCFG0x064
75Run-Mode Clock Configuration 20x0780.2800R/WRCC20x070
88Run Mode Clock Gating Control Register 00x00000040R/WRCGC00x100
94Run Mode Clock Gating Control Register 10x00000000R/WRCGC10x104
100Run Mode Clock Gating Control Register 20x00000000R/WRCGC20x108
90Sleep Mode Clock Gating Control Register 00x00000040R/WSCGC00x110
96Sleep Mode Clock Gating Control Register 10x00000000R/WSCGC10x114
102Sleep Mode Clock Gating Control Register 20x00000000R/WSCGC20x118
92Deep Sleep Mode Clock Gating Control Register 00x00000040R/WDCGC00x120
98Deep Sleep Mode Clock Gating Control Register 10x00000000R/WDCGC10x124
104Deep Sleep Mode Clock Gating Control Register 20x00000000R/WDCGC20x128
77Deep Sleep Clock Configuration0x0780.0000R/WDSLPCLKCFG0x144
6.4 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
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Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the device.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
16171819202122232425262728293031
CLASSreservedVERreserved
ROROROROROROROROROROROROROROROROType
1000000000001000Reset
0123456789101112131415
MINORMAJOR
ROROROROROROROROROROROROROROROROType
----------------Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows:
DescriptionValue
First revision of the DID0 register format, for Stellaris®
Fury-class devices .
0x1
0x1ROVER30:28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved27:24
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all devices in a particular product line. The CLASS
field value is changed for new product lines, for changes in fab process
(for example, a remap or shrink), or any case where the MAJOR or MINOR
fields require differentiation from prior devices. The value of the CLASS
field is encoded as follows (all other encodings are reserved):
DescriptionValue
Stellaris® Sandstorm-class devices.0x0
Stellaris® Fury-class devices.0x1
0x1ROCLASS23:16
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DescriptionResetTypeNameBit/Field
Major Revision
This field specifies the major revision number of the device. The major
revision reflects changes to base layers of the design. The major revision
number is indicated in the part number as a letter (A for first revision, B
for second, and so on). This field is encoded as follows:
DescriptionValue
Revision A (initial device)0x0
Revision B (first base layer revision)0x1
Revision C (second base layer revision)0x2
and so on.
-ROMAJOR15:8
Minor Revision
This field specifies the minor revision number of the device. The minor
revision reflects changes to the metal layers of the design. The MINOR
field value is reset when the MAJOR field is changed. This field is numeric
and is encoded as follows:
DescriptionValue
Initial device, or a major revision update.0x0
First metal layer change.0x1
Second metal layer change.0x2
and so on.
-ROMINOR7:0
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Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedBORIORreserved
ROR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:2
BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the controller. If set, a
reset is signaled. Otherwise, an interrupt is signaled.
0R/WBORIOR1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
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Register 3: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
LDO Power Control (LDOPCTL)
Base 0x400F.E000
Offset 0x034
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
VADJreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:6
LDO Output Voltage
This field sets the on-chip output voltage. The programming values for
the VADJ field are provided below.
VOUT (V)Value
2.500x00
2.450x01
2.400x02
2.350x03
2.300x04
2.250x05
Reserved0x06-0x3F
2.750x1B
2.700x1C
2.650x1D
2.600x1E
2.550x1F
0x0R/WVADJ5:0
65November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedBORRISreservedPLLLRISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts.
0ROPLLLRIS6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:2
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
0ROBORRIS1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
November 30, 200766
Preliminary
System Control
Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedBORIMreservedPLLLIMreserved
ROR/WROROROROR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS
is set; otherwise, an interrupt is not generated.
0R/WPLLLIM6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:2
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
0R/WBORIM1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
67November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
register (see page 66).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedBORMISreservedPLLLMISreserved
ROR/W1CROROROROR/W1CROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
0R/W1CPLLLMIS6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:2
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
0R/W1CBORMIS1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
November 30, 200768
Preliminary
System Control
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an external reset is the cause, and then
all the other bits in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
EXTPORBORWDTSWLDOreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
------0000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:6
LDO Reset
When set, indicates the LDO circuit has lost regulation and has
generated a reset event.
-R/WLDO5
Software Reset
When set, indicates a software reset is the cause of the reset event.
-R/WSW4
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
-R/WWDT3
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
-R/WBOR2
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
-R/WPOR1
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
-R/WEXT0
69November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x07A0.3AD1
16171819202122232425262728293031
reserved
USESYSDIV
SYSDIVACGreserved
ROROROROROROR/WR/WR/WR/WR/WR/WROROROROType
0000000111100000Reset
0123456789101112131415
MOSCDISIOSCDISreservedOSCSRCXTALreservedBYPASSreservedPWRDNreserved
R/WR/WROROR/WR/WR/WR/WR/WR/WROR/WROR/WROROType
1000101101011100Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:28
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers
are used to control the clocks distributed to the peripherals when the
controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating
Control (RCGCn) registers are used when the controller enters a sleep
mode.
The RCGCn registers are always used to control the clocks in Run
mode.
This allows peripherals to consume less power when the controller is
in a sleep mode and the peripheral is unused.
0R/WACG27
November 30, 200770
Preliminary
System Control
DescriptionResetTypeNameBit/Field
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
Frequency (BYPASS=0)Divisor (BYPASS=1)Value
reservedreserved0x0
reserved/20x1
reserved/30x2
50 MHz/40x3
40 MHz/50x4
33.33 MHz/60x5
28.57 MHz/70x6
25 MHz/80x7
22.22 MHz/90x8
20 MHz/100x9
18.18 MHz/110xA
16.67 MHz/120xB
15.38 MHz/130xC
14.29 MHz/140xD
13.33 MHz/150xE
12.5 MHz (default)/160xF
When reading the Run-Mode Clock Configuration (RCC) register (see
page 70), the SYSDIV value is MINSYSDIV if a lower divider was
requested and the PLL is being used. This lower value is allowed to
divide a non-PLL source.
0xFR/WSYSDIV26:23
Enable System Clock Divider
Use the system clock divider as the source for the system clock. The
system clock divider is forced to be used when the PLL is selected as
the source.
0R/WUSESYSDIV22
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved21:14
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
1R/WPWRDN13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1ROreserved12
71November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
Note: The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.
1R/WBYPASS11
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved10
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below.
Crystal Frequency (MHz)
Using the PLL
Crystal Frequency (MHz)
Not Using the PLL
Value
reserved1.0000x0
reserved1.84320x1
reserved2.0000x2
reserved2.45760x3
3.579545 MHz0x4
3.6864 MHz0x5
4 MHz0x6
4.096 MHz0x7
4.9152 MHz0x8
5 MHz0x9
5.12 MHz0xA
6 MHz (reset value)0xB
6.144 MHz0xC
7.3728 MHz0xD
8 MHz0xE
8.192 MHz0xF
0xBR/WXTAL9:6
Oscillator Source
Picks among the four input sources for the OSC. The values are:
Input SourceValue
Main oscillator (default)0x0
Internal oscillator (default)0x1
Internal oscillator / 4 (this is necessary if used as input to PLL)0x2
reserved0x3
0x1R/WOSCSRC5:4
November 30, 200772
Preliminary
System Control
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:2
Internal Oscillator Disable
0: Internal oscillator (IOSC) is enabled.
1: Internal oscillator is disabled.
0R/WIOSCDIS1
Main Oscillator Disable
0: Main oscillator is enabled.
1: Main oscillator is disabled (default).
1R/WMOSCDIS0
73November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 70).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RFreserved
ROROROROROROROROROROROROROROROROType
--------------00Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:14
PLL F Value
This field specifies the value supplied to the PLL’s F input.
-ROF13:5
PLL R Value
This field specifies the value supplied to the PLL’s R input.
-ROR4:0
November 30, 200774
Preliminary
System Control
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows
RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible
to previous parts. The fields within the RCC2 register occupy the same bit positions as they do
within the RCC register as LSB-justified.
The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system
clock frequency for improved Deep Sleep power consumption.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2800
16171819202122232425262728293031
reservedSYSDIV2reservedUSERCC2
ROROROROROROROR/WR/WR/WR/WR/WR/WROROR/WType
0000000111100000Reset
0123456789101112131415
reservedOSCSRC2reservedBYPASS2reservedPWRDN2reserved
ROROROROR/WR/WR/WROROROROR/WROR/WROROType
0000000000010100Reset
DescriptionResetTypeNameBit/Field
Use RCC2
When set, overrides the RCC register fields.
0R/WUSERCC231
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved30:29
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
This field is wider than the RCC register SYSDIV field in order to provide
additional divisor values. This permits the system clock to be run at
much lower frequencies during Deep Sleep mode. For example, where
the RCC register SYSDIV encoding of 1111 provides /16, the RCC2
register SYSDIV2 encoding of 111111 provides /64.
0x0FR/WSYSDIV228:23
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved22:14
Power-Down PLL
When set, powers down the PLL.
1R/WPWRDN213
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved12
Bypass PLL
When set, bypasses the PLL for the clock source.
1R/WBYPASS211
75November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved10:7
System Clock Source
DescriptionValue
Main oscillator (MOSC)0x0
Internal oscillator (IOSC)0x1
Internal oscillator / 40x2
30 kHz internal oscillator0x3
32 kHz external oscillator0x7
0x0R/WOSCSRC26:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:0
November 30, 200776
Preliminary
System Control
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
16171819202122232425262728293031
reservedDSDIVORIDEreserved
ROROROROROROROR/WR/WR/WR/WR/WR/WROROROType
0000000111100000Reset
0123456789101112131415
reservedDSOSCSRCreserved
ROROROROR/WR/WR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:29
Divider Field Override
6-bit system divider field to override when Deep-Sleep occurs with PLL
running.
0x0FR/WDSDIVORIDE28:23
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved22:7
Clock Source
When set, forces IOSC to be clock source during Deep Sleep mode.
DescriptionNameValue
No override to the oscillator clock source is doneNOORIDE0x0
Use internal 12 MHz oscillator as sourceIOSC0x1
Use 30 kHz internal oscillator30kHz0x3
Use 32 kHz external oscillator32kHz0x7
0x0R/WDSOSCSRC6:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:0
77November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 12: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset -
16171819202122232425262728293031
PARTNOFAMVER
ROROROROROROROROROROROROROROROROType
0010101100001000Reset
0123456789101112131415
QUALROHSPKGTEMPreservedPINCOUNT
ROROROROROROROROROROROROROROROROType
--11010000000010Reset
DescriptionResetTypeNameBit/Field
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
DescriptionValue
First revision of the DID1 register format, indicating a Stellaris
Fury-class device.
0x1
0x1ROVER31:28
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
DescriptionValue
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
0x0
0x0ROFAM27:24
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
DescriptionValue
LM3S20160xD4
0xD4ROPARTNO23:16
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
DescriptionValue
100-pin package0x2
0x2ROPINCOUNT15:13
November 30, 200778
Preliminary
System Control
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved12:8
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
DescriptionValue
Industrial temperature range (-40°C to 85°C)0x1
0x1ROTEMP7:5
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
DescriptionValue
LQFP package0x1
0x1ROPKG4:3
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
1ROROHS2
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
DescriptionValue
Engineering Sample (unqualified)0x0
Pilot Production (unqualified)0x1
Fully Qualified0x2
-ROQUAL1:0
79November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 13: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x001F.001F
16171819202122232425262728293031
SRAMSZ
ROROROROROROROROROROROROROROROROType
1111100000000000Reset
0123456789101112131415
FLASHSZ
ROROROROROROROROROROROROROROROROType
1111100000000000Reset
DescriptionResetTypeNameBit/Field
SRAM Size
Indicates the size of the on-chip SRAM memory.
DescriptionValue
8 KB of SRAM0x001F
0x001FROSRAMSZ31:16
Flash Size
Indicates the size of the on-chip flash memory.
DescriptionValue
64 KB of Flash0x001F
0x001FROFLASHSZ15:0
November 30, 200780
Preliminary
System Control
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0,SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0101.329F
16171819202122232425262728293031
ADCreservedCAN0reserved
ROROROROROROROROROROROROROROROROType
1000000010000000Reset
0123456789101112131415
JTAGSWDSWOWDTPLLreservedMPUMAXADCSPDMINSYSDIV
ROROROROROROROROROROROROROROROROType
1111100101001100Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:25
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
1ROCAN024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:17
ADC Module Present
When set, indicates that the ADC module is present.
1ROADC16
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
DescriptionValue
Specifies a 50-MHz CPU clock with a PLL divider of 4.0x3
0x3ROMINSYSDIV15:12
Max ADC Speed
Indicates the maximum rate at which the ADC samples data.
DescriptionValue
500K samples/second0x2
0x2ROMAXADCSPD11:8
81November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
1ROMPU7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved6:5
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
1ROPLL4
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
1ROWDT3
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
1ROSWO2
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
1ROSWD1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
1ROJTAG0
November 30, 200782
Preliminary
System Control
Register 15: Device Capabilities 2 (DC2), offset 0x014
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register
is consistent with the RCGC1,SCGC1, and DCGC1 clock control registers and the SRCR1 software
reset control register.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x0003.1013
16171819202122232425262728293031
TIMER0TIMER1reserved
ROROROROROROROROROROROROROROROROType
1100000000000000Reset
0123456789101112131415
UART0UART1reservedSSI0reservedI2C0reserved
ROROROROROROROROROROROROROROROROType
1100100000001000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:18
Timer 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
1ROTIMER117
Timer 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
1ROTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
1ROI2C012
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:5
SSI0 Present
When set, indicates that SSI module 0 is present.
1ROSSI04
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:2
UART1 Present
When set, indicates that UART module 1 is present.
1ROUART11
83November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
UART0 Present
When set, indicates that UART module 0 is present.
1ROUART00
November 30, 200784
Preliminary
System Control
Register 16: Device Capabilities 3 (DC3), offset 0x018
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Analog
Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0x0F0F.0000
16171819202122232425262728293031
ADC0ADC1ADC2ADC3reservedCCP0CCP1CCP2CCP3reserved
ROROROROROROROROROROROROROROROROType
1111000011110000Reset
0123456789101112131415
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:28
CCP3 Pin Present
When set, indicates that Capture/Compare/PWM pin 3 is present.
1ROCCP327
CCP2 Pin Present
When set, indicates that Capture/Compare/PWM pin 2 is present.
1ROCCP226
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
1ROCCP125
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
1ROCCP024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:20
ADC3 Pin Present
When set, indicates that ADC pin 3 is present.
1ROADC319
ADC2 Pin Present
When set, indicates that ADC pin 2 is present.
1ROADC218
ADC1 Pin Present
When set, indicates that ADC pin 1 is present.
1ROADC117
ADC0 Pin Present
When set, indicates that ADC pin 0 is present.
1ROADC016
85November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:0
November 30, 200786
Preliminary
System Control
Register 17: Device Capabilities 4 (DC4), offset 0x01C
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: Ethernet MAC
and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2,SCGC2,
and DCGC2 clock control registers and the SRCR2 software reset control register.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x0000.00FF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHreserved
ROROROROROROROROROROROROROROROROType
1111111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
GPIO Port H Present
When set, indicates that GPIO Port H is present.
1ROGPIOH7
GPIO Port G Present
When set, indicates that GPIO Port G is present.
1ROGPIOG6
GPIO Port F Present
When set, indicates that GPIO Port F is present.
1ROGPIOF5
GPIO Port E Present
When set, indicates that GPIO Port E is present.
1ROGPIOE4
GPIO Port D Present
When set, indicates that GPIO Port D is present.
1ROGPIOD3
GPIO Port C Present
When set, indicates that GPIO Port C is present.
1ROGPIOC2
GPIO Port B Present
When set, indicates that GPIO Port B is present.
1ROGPIOB1
GPIO Port A Present
When set, indicates that GPIO Port A is present.
1ROGPIOA0
87November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
16171819202122232425262728293031
ADCreservedCAN0reserved
R/WROROROROROROROR/WROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedWDTreservedMAXADCSPDreserved
ROROROR/WROROROROR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:25
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
0R/WCAN024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:17
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WADC16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:12
November 30, 200788
Preliminary
System Control
DescriptionResetTypeNameBit/Field
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
DescriptionValue
500K samples/second0x2
250K samples/second0x1
125K samples/second0x0
0R/WMAXADCSPD11:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:4
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WWDT3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
89November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
16171819202122232425262728293031
ADCreservedCAN0reserved
R/WROROROROROROROR/WROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedWDTreservedMAXADCSPDreserved
ROROROR/WROROROROR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:25
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
0R/WCAN024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:17
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WADC16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:12
November 30, 200790
Preliminary
System Control
DescriptionResetTypeNameBit/Field
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
DescriptionValue
500K samples/second0x2
250K samples/second0x1
125K samples/second0x0
0R/WMAXADCSPD11:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:4
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WWDT3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
91November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
16171819202122232425262728293031
ADCreservedCAN0reserved
R/WROROROROROROROR/WROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedWDTreservedMAXADCSPDreserved
ROROROR/WROROROROR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:25
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
0R/WCAN024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:17
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WADC16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:12
November 30, 200792
Preliminary
System Control
DescriptionResetTypeNameBit/Field
ADC Sample Speed
This field sets the rate at which the ADC samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADCSPD bit as follows:
DescriptionValue
500K samples/second0x2
250K samples/second0x1
125K samples/second0x0
0R/WMAXADCSPD11:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:4
WDT Clock Gating Control
This bit controls the clock gating for the WDT module. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
0R/WWDT3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
93November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
16171819202122232425262728293031
TIMER0TIMER1reserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
UART0UART1reservedSSI0reservedI2C0reserved
R/WR/WROROR/WROROROROROROROR/WROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:18
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER117
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WI2C012
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:5
November 30, 200794
Preliminary
System Control
DescriptionResetTypeNameBit/Field
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WSSI04
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:2
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART11
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART00
95November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
16171819202122232425262728293031
TIMER0TIMER1reserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
UART0UART1reservedSSI0reservedI2C0reserved
R/WR/WROROR/WROROROROROROROR/WROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:18
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER117
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WI2C012
November 30, 200796
Preliminary
System Control
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:5
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WSSI04
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:2
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART11
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART00
97November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the
clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
16171819202122232425262728293031
TIMER0TIMER1reserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
UART0UART1reservedSSI0reservedI2C0reserved
R/WR/WROROR/WROROROROROROROR/WROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:18
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER117
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled. If the unit is unclocked, reads or writes to the
unit will generate a bus fault.
0R/WTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WI2C012
November 30, 200798
Preliminary
System Control
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:5
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WSSI04
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:2
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART11
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, reads or writes to the unit will generate
a bus fault.
0R/WUART00
99November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOH7
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOG6
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOF5
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOE4
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DescriptionResetTypeNameBit/Field
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOD3
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOC2
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOB1
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOA0
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Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOH7
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOG6
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOF5
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOE4
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DescriptionResetTypeNameBit/Field
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOD3
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOC2
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOB1
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOA0
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Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the
clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOH7
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOG6
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOF5
Port E Clock Gating Control
This bit controls the clock gating for Port E. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOE4
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System Control
DescriptionResetTypeNameBit/Field
Port D Clock Gating Control
This bit controls the clock gating for Port D. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOD3
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOC2
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOB1
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the unit receives a
clock and functions. Otherwise, the unit is unclocked and disabled. If
the unit is unclocked, reads or writes to the unit will generate a bus fault.
0R/WGPIOA0
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Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
16171819202122232425262728293031
ADCreservedCAN0reserved
R/WROROROROROROROR/WROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedWDTreserved
ROROROR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:25
CAN0 Reset Control
Reset control for CAN unit 0.
0R/WCAN024
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:17
ADC0 Reset Control
Reset control for SAR ADC module 0.
0R/WADC16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:4
WDT Reset Control
Reset control for Watchdog unit.
0R/WWDT3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
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System Control
Register 28: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
16171819202122232425262728293031
TIMER0TIMER1reserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
UART0UART1reservedSSI0reservedI2C0reserved
R/WR/WROROR/WROROROROROROROR/WROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:18
Timer 1 Reset Control
Reset control for General-Purpose Timer module 1.
0R/WTIMER117
Timer 0 Reset Control
Reset control for General-Purpose Timer module 0.
0R/WTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
I2C0 Reset Control
Reset control for I2C unit 0.
0R/WI2C012
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:5
SSI0 Reset Control
Reset control for SSI unit 0.
0R/WSSI04
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:2
UART1 Reset Control
Reset control for UART unit 1.
0R/WUART11
UART0 Reset Control
Reset control for UART unit 0.
0R/WUART00
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Register 29: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOHreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
Port H Reset Control
Reset control for GPIO Port H.
0R/WGPIOH7
Port G Reset Control
Reset control for GPIO Port G.
0R/WGPIOG6
Port F Reset Control
Reset control for GPIO Port F.
0R/WGPIOF5
Port E Reset Control
Reset control for GPIO Port E.
0R/WGPIOE4
Port D Reset Control
Reset control for GPIO Port D.
0R/WGPIOD3
Port C Reset Control
Reset control for GPIO Port C.
0R/WGPIOC2
Port B Reset Control
Reset control for GPIO Port B.
0R/WGPIOB1
Port A Reset Control
Reset control for GPIO Port A.
0R/WGPIOA0
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7 Internal Memory
The LM3S2016 microcontroller comes with 8 KB of bit-banded SRAM and 64 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
7.1 Block Diagram
Figure 7-1. Flash Block Diagram
Flash Control
FMA
FCMISC
FCIM
FCRIS
FMC
FMD
Flash Timing
USECRL
Flash Protection
FMPREn
FMPPEn
Flash Array
SRAM Array
Bridge
Cortex-M3
ICode
DCode
System Bus
APB
User Registers
USER_REG0
USER_REG1
USER_DBG
7.2 Functional Description
This section describes the functionality of both the flash and SRAM memories.
7.2.1 SRAM Memory
The internal SRAM of the Stellaris®devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
The bit-band alias is calculated by using the formula:
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bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3
Technical Reference Manual.
7.2.2 Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be
programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB
blocks that can be individually protected. The protection allows blocks to be marked as read-only
or execute-only, providing different levels of code protection. Read-only blocks cannot be erased
or programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
See also “Serial Flash Loader” on page 446 for a preprogrammed flash-resident utility used to
download code to the flash memory of a device without the use of a debug interface.
7.2.2.1 Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via the
USec Reload (USECRL) register.
On reset, the USECRL register is loaded with a value that configures the flash timing so that it works
with the maximum clock rate of the part. If software changes the system operating frequency, the
new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash
modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value
of 0x13 (20-1) must be written to the USECRL register.
7.2.2.2 Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in one pair of 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block)
in the FMPPEn and FMPREn registers.
■Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
■Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read
by software or debuggers. If cleared, the block may only be executed. The contents of the memory
block are prohibited from being accessed as data and traversing the DCode bus.
The policies may be combined as shown in Table 7-1 on page 111.
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Internal Memory
Table 7-1. Flash Protection Policy Combinations
ProtectionFMPREnFMPPEn
Execute-only protection. The block may only be executed and may not be written or erased. This mode
is used to protect code.
00
The block may be written, erased or executed, but not read. This combination is unlikely to be used.01
Read-only protection. The block may be read or executed but may not be written or erased. This mode
is used to lock the block from further modification while allowing any read or execute access.
10
No protection. The block may be written, erased, executed or read.11
An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt
may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers
of poorly behaving software during the development and debug phases.
An access that attempts to read an RE-protected block is prohibited. Such accesses return data
filled with all 0s. A controller interrupt may be optionally generated to alert software developers of
poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. Details on
programming these bits are discussed in “Nonvolatile Register Programming” on page 112.
7.3 Flash Memory Initialization and Configuration
7.3.1 Flash Programming
The Stellaris®devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA,FMD, and FMC.
7.3.1.1 To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register.
4. Poll the FMC register until the WRITE bit is cleared.
7.3.1.2 To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register.
3. Poll the FMC register until the ERASE bit is cleared.
7.3.1.3 To perform a mass erase of the flash
1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
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7.3.2 Nonvolatile Register Programming
This section discusses how to update registers that are resident within the flash memory itself.
These registers exist in a separate space from the main flash array and are not affected by an
ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit
in the FMC register to activate a write operation. For the USER_DBG register, the data to be written
must be loaded into the FMD register before it is "committed". All other registers are R/W and can
have their operation tried before committing them to nonvolatile memory.
Important: These registers can only have bits changed from 1 to 0 by the user and there is no
mechanism for the user to erase them back to a 1 value.
In addition, the USER_REG0,USER_REG1, and USER_DBG use bit 31 (NW) of their respective
registers to indicate that they are available for user write. These three registers can only be written
once whereas the flash protection registers may be written multiple times. Table 7-2 on page 112
provides the FMA address required for commitment of each of the registers and the source of the
data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008.
After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to
complete.
Table 7-2. Flash Resident Registersa
Data SourceFMA ValueRegister to be Committed
FMPRE00x0000.0000FMPRE0
FMPRE10x0000.0002FMPRE1
FMPRE20x0000.0004FMPRE2
FMPRE30x0000.0008FMPRE3
FMPPE00x0000.0001FMPPE0
FMPPE10x0000.0003FMPPE1
FMPPE20x0000.0005FMPPE2
FMPPE30x0000.0007FMPPE3
USER_REG00x8000.0000USER_REG0
USER_REG10x8000.0001USER_REG1
FMD0x7510.0000USER_DBG
a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris®device.
7.4 Register Map
Table 7-3 on page 112 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register's address. The FMA,FMD,FMC,FCRIS,FCIM, and FCMISC registers
are relative to the Flash control base address of 0x400F.D000. The FMPREn,FMPPEn,USECRL,
USER_DBG, and USER_REGn registers are relative to the System Control base address of
0x400F.E000.
Table 7-3. Flash Register Map
See
page
DescriptionResetTypeNameOffset
Flash Control Offset
114Flash Memory Address0x0000.0000R/WFMA0x000
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See
page
DescriptionResetTypeNameOffset
115Flash Memory Data0x0000.0000R/WFMD0x004
116Flash Memory Control0x0000.0000R/WFMC0x008
118Flash Controller Raw Interrupt Status0x0000.0000ROFCRIS0x00C
119Flash Controller Interrupt Mask0x0000.0000R/WFCIM0x010
120Flash Controller Masked Interrupt Status and Clear0x0000.0000R/W1CFCMISC0x014
System Control Offset
122Flash Memory Protection Read Enable 00xFFFF.FFFFR/WFMPRE00x130
122Flash Memory Protection Read Enable 00xFFFF.FFFFR/WFMPRE00x200
123Flash Memory Protection Program Enable 00xFFFF.FFFFR/WFMPPE00x134
123Flash Memory Protection Program Enable 00xFFFF.FFFFR/WFMPPE00x400
121USec Reload0x31R/WUSECRL0x140
124User Debug0xFFFF.FFFER/WUSER_DBG0x1D0
125User Register 00xFFFF.FFFFR/WUSER_REG00x1E0
126User Register 10xFFFF.FFFFR/WUSER_REG10x1E4
127Flash Memory Protection Read Enable 10x0000.0000R/WFMPRE10x204
128Flash Memory Protection Read Enable 20x0000.0000R/WFMPRE20x208
129Flash Memory Protection Read Enable 30x0000.0000R/WFMPRE30x20C
130Flash Memory Protection Program Enable 10x0000.0000R/WFMPPE10x404
131Flash Memory Protection Program Enable 20x0000.0000R/WFMPPE20x408
132Flash Memory Protection Program Enable 30x0000.0000R/WFMPPE30x40C
7.5 Flash Register Descriptions (Flash Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
OFFSET
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved31:16
Address Offset
Address offset in flash where operation is performed, except for
nonvolatile registers (see “Nonvolatile Register Programming” on page
112 for details on values for this field).
0x0R/WOFFSET15:0
November 30, 2007114
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Internal Memory
Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Data Value
Data value for write operation.
0x0R/WDATA31:0
115November 30, 2007
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LM3S2016 Microcontroller
Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the location
specified by the Flash Memory Address (FMA) register (see page 114). If the access is a write
access, the data contained in the Flash Memory Data (FMD) register (see page 115) is written.
This is the final register written and initiates the memory operation. There are four control bits in the
lower byte of this register that, when set, initiate the memory operation. The most used of these
register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
WRKEY
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
0123456789101112131415
WRITEERASEMERASECOMTreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Flash Write Key
This field contains a write key, which is used to minimize the incidence
of accidental flash writes. The value 0xA442 must be written into this
field for a write to occur. Writes to the FMC register without this WRKEY
value are ignored. A read of this field returns the value 0.
0x0WOWRKEY31:16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved15:4
Commit Register Value
Commit (write) of register value to nonvolatile storage. A write of 0 has
no effect on the state of this bit.
If read, the state of the previous commit access is provided. If the
previous commit access is complete, a 0 is returned; otherwise, if the
commit access is not complete, a 1 is returned.
This can take up to 50 μs.
0R/WCOMT3
Mass Erase Flash Memory
If this bit is set, the flash main memory of the device is all erased. A
write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is provided. If the
previous mass erase access is complete, a 0 is returned; otherwise, if
the previous mass erase access is not complete, a 1 is returned.
This can take up to 250 ms.
0R/WMERASE2
November 30, 2007116
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Internal Memory
DescriptionResetTypeNameBit/Field
Erase a Page of Flash Memory
If this bit is set, the page of flash main memory as specified by the
contents of FMA is erased. A write of 0 has no effect on the state of this
bit.
If read, the state of the previous erase access is provided. If the previous
erase access is complete, a 0 is returned; otherwise, if the previous
erase access is not complete, a 1 is returned.
This can take up to 25 ms.
0R/WERASE1
Write a Word into Flash Memory
If this bit is set, the data stored in FMD is written into the location as
specified by the contents of FMA. A write of 0 has no effect on the state
of this bit.
If read, the state of the previous write update is provided. If the previous
write access is complete, a 0 is returned; otherwise, if the write access
is not complete, a 1 is returned.
This can take up to 50 µs.
0R/WWRITE0
117November 30, 2007
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LM3S2016 Microcontroller
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled
if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ARISPRISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
Programming Raw Interrupt Status
This bit indicates the current state of the programming cycle. If set, the
programming cycle completed; if cleared, the programming cycle has
not completed. Programming cycles are either write or erase actions
generated through the Flash Memory Control (FMC) register bits (see
page 116).
0ROPRIS1
Access Raw Interrupt Status
This bit indicates if the flash was improperly accessed. If set, the program
tried to access the flash counter to the policy as set in the Flash Memory
Protection Read Enable (FMPREn) and Flash Memory Protection
Program Enable (FMPPEn) registers. Otherwise, no access has tried
to improperly access the flash.
0ROARIS0
November 30, 2007118
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Internal Memory
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
AMASKPMASKreserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the controller. If set, a programming-generated interrupt is promoted
to the controller. Otherwise, interrupts are recorded but suppressed from
the controller.
0R/WPMASK1
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
controller. If set, an access-generated interrupt is promoted to the
controller. Otherwise, interrupts are recorded but suppressed from the
controller.
0R/WAMASK0
119November 30, 2007
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LM3S2016 Microcontroller
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
AMISCPMISCreserved
R/W1CR/W1CROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because a
programming cycle completed and was not masked. This bit is cleared
by writing a 1. The PRIS bit in the FCRIS register (see page 118) is also
cleared when the PMISC bit is cleared.
0R/W1CPMISC1
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because an improper
access was attempted and was not masked. This bit is cleared by writing
a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC
bit is cleared.
0R/W1CAMISC0
7.6 Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
November 30, 2007120
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Internal Memory
Register 7: USec Reload (USECRL), offset 0x140
Note: Offset is relative to System Control base address of 0x400F.E000
This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller.
The internal flash has specific minimum and maximum requirements on the length of time the high
voltage write pulse can be applied. It is required that this register contain the operating frequency
(in MHz -1) whenever the flash is being erased or programmed. The user is required to change this
value if the clocking conditions are changed for a flash erase/program operation.
USec Reload (USECRL)
Base 0x400F.E000
Offset 0x140
Type R/W, reset 0x31
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
USECreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
1000110000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Microsecond Reload Value
MHz -1 of the controller clock when the flash is being erased or
programmed.
USEC should be set to 0x31 (50 MHz) whenever the flash is being erased
or programmed.
0x31R/WUSEC7:0
121November 30, 2007
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LM3S2016 Microcontroller
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.D000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 64 KB of flash.0xFFFFFFFF
0xFFFFFFFFR/WREAD_ENABLE31:0
November 30, 2007122
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Internal Memory
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note: This register is aliased for backwards compatability.
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.D000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 64 KB of flash.0xFFFFFFFF
0xFFFFFFFFR/WPROG_ENABLE31:0
123November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 10: User Debug (USER_DBG), offset 0x1D0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0
disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written
and is controlled through hardware to ensure that the register is only written once.
User Debug (USER_DBG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
16171819202122232425262728293031
DATANW
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
DBG0DBG1DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0111111111111111Reset
DescriptionResetTypeNameBit/Field
User Debug Not Written
Specifies that this 32-bit dword has not been written.
1R/WNW31
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
0x1FFFFFFFR/WDATA30:2
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
1R/WDBG11
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
0R/WDBG00
November 30, 2007124
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Internal Memory
Register 11: User Register 0 (USER_REG0), offset 0x1E0
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
DATANW
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Not Written
Specifies that this 32-bit dword has not been written.
1R/WNW31
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
0x7FFFFFFFR/WDATA30:0
125November 30, 2007
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LM3S2016 Microcontroller
Register 12: User Register 1 (USER_REG1), offset 0x1E4
Note: Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
DATANW
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Not Written
Specifies that this 32-bit dword has not been written.
1R/WNW31
User Data
Contains the user data value. This field is initialized to all 1s and can
only be written once.
0x7FFFFFFFR/WDATA30:0
November 30, 2007126
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Internal Memory
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 64 KB of flash.0x00000000
0x00000000R/WREAD_ENABLE31:0
127November 30, 2007
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LM3S2016 Microcontroller
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 64 KB of flash.0x00000000
0x00000000R/WREAD_ENABLE31:0
November 30, 2007128
Preliminary
Internal Memory
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
READ_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 64 KB of flash.0x00000000
0x00000000R/WREAD_ENABLE31:0
129November 30, 2007
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LM3S2016 Microcontroller
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 64 KB of flash.0x00000000
0x00000000R/WPROG_ENABLE31:0
November 30, 2007130
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Internal Memory
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 64 KB of flash.0x00000000
0x00000000R/WPROG_ENABLE31:0
131November 30, 2007
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LM3S2016 Microcontroller
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note: Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
PROG_ENABLE
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
DescriptionValue
Enables 64 KB of flash.0x00000000
0x00000000R/WPROG_ENABLE31:0
November 30, 2007132
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Internal Memory
8 General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of eight physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, and Port H). The GPIO module is
FiRM-compliant and supports 18-39 programmable input/output pins, depending on the peripherals
being used.
The GPIO module has the following features:
■Programmable control for GPIO interrupts
–Interrupt generation masking
–Edge-triggered on rising, falling, or both
–Level-sensitive on High or Low values
■5-V-tolerant input/outputs
■Bit masking in both read and write operations through address lines
■Programmable control for GPIO pad configuration
–Weak pull-up or pull-down resistors
–2-mA, 4-mA, and 8-mA pad drive
–Slew rate control for the 8-mA drive
–Open drain enables
–Digital input enables
8.1 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
8-1 on page 134). The LM3S2016 microcontroller contains eight ports and thus eight of these physical
GPIO blocks.
133November 30, 2007
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LM3S2016 Microcontroller
Figure 8-1. GPIO Port Block Diagram
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIO Input
GPIO Output
GPIO Output Enable
Pad Output
Pad Output Enable
Package I/O Pin
GPIODATA
GPIODIR
Data
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Interrupt
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Pad
Control
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
Identification Registers
GPIOAFSEL
Mode
Control
MUXMUXDEMUX
Digital
I/O Pad
Pad Input
GPIOLOCK
Commit
Control
GPIOCR
8.1.1 Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
8.1.1.1 Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 141) is used to configure each individual pin as
an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and
the corresponding data register bit will capture and store the value on the GPIO port. When the data
direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit
will be driven out on the GPIO port.
8.1.1.2 Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 140) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA
register is altered. If it is cleared to 0, it is left unchanged.
November 30, 2007134
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General-Purpose Input/Outputs (GPIOs)
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 8-2 on page 135, where uis data unchanged by the write.
Figure 8-2. GPIODATA Write Example
0 10 0 1 10 0 1 0
u 1u u 0 1u u
9876543210
1 11 0 0 11 1
76543210
GPIODATA
0xEB
0x098
ADDR[9:2]
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value.
For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 135.
Figure 8-3. GPIODATA Read Example
0 10 1 0 00 1 0 0
0 10 1 0 00 0
9876543210
0 11 1 1 11 0
76543210
Returned Value
GPIODATA
0x0C4
ADDR[9:2]
8.1.2 Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source
holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
■GPIO Interrupt Sense (GPIOIS) register (see page 142)
■GPIO Interrupt Both Edges (GPIOIBE) register (see page 143)
■GPIO Interrupt Event (GPIOIEV) register (see page 144)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 145).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 146 and page 147). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
135November 30, 2007
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LM3S2016 Microcontroller
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for
PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer
Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see page 148).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS,GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
8.1.3 Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 149), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
8.1.4 Commit Control
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 149) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 159) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 160) have been set to 1.
8.1.5 Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R,GPIODR4R,GPIODR8R,GPIOODR,
GPIOPUR,GPIOPDR,GPIOSLR, and GPIODEN registers.
8.1.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
8.2 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-1 on page 137
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 8-2 on page 137 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
November 30, 2007136
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General-Purpose Input/Outputs (GPIOs)
Table 8-1. GPIO Pad Configuration Examples
GPIO Register Bit Valuea
Configuration
SLRDR8RDR4RDR2RPDRPURDENODRDIRAFSEL
XXXX??1000Digital Input (GPIO)
??????1010Digital Output (GPIO)
XXXXXX1100Open Drain Input
(GPIO)
????XX1110Open Drain Output
(GPIO)
????XX11X1Open Drain
Input/Output (I2C)
XXXX??10X1Digital Input (Timer
CCP)
??????10X1Digital Output (Timer
PWM)
??????10X1Digital Input/Output
(SSI)
??????10X1Digital Input/Output
(UART)
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 8-2. GPIO Interrupt Configuration Example
Pin 2 Bit Valuea
Desired
Interrupt
Event
Trigger
Register
01234567
XX0XXXXX0=edge
1=level
GPIOIS
XX0XXXXX0=single
edge
1=both
edges
GPIOIBE
XX1XXXXX0=Low level,
or negative
edge
1=High level,
or positive
edge
GPIOIEV
001000000=masked
1=not
masked
GPIOIM
a. X=Ignored (don’t care bit)
8.3 Register Map
Table 8-3 on page 138 lists the GPIO registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that GPIO port’s base address:
■GPIO Port A: 0x4000.4000
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LM3S2016 Microcontroller
■GPIO Port B: 0x4000.5000
■GPIO Port C: 0x4000.6000
■GPIO Port D: 0x4000.7000
■GPIO Port E: 0x4002.4000
■GPIO Port F: 0x4002.5000
■GPIO Port G: 0x4002.6000
■GPIO Port H: 0x4002.7000
Important: The GPIO registers in this chapter are duplicated in each GPIO block, however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
cases, writing to those unconnected bits has no effect and reading those unconnected
bits returns no meaningful data.
Note: The default reset value for the GPIOAFSEL,GPIOPUR, and GPIODEN registers are
0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and
PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default
reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
The default register type for the GPIOCR register is RO for all GPIO pins, with the exception
of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because of this, the register type for
GPIO Port B7 and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port
is not accidentally programmed as a GPIO, these five pins default to non-commitable.
Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while
the default reset value of GPIOCR for Port C is 0x0000.00F0.
Table 8-3. GPIO Register Map
See
page
DescriptionResetTypeNameOffset
140GPIO Data0x0000.0000R/WGPIODATA0x000
141GPIO Direction0x0000.0000R/WGPIODIR0x400
142GPIO Interrupt Sense0x0000.0000R/WGPIOIS0x404
143GPIO Interrupt Both Edges0x0000.0000R/WGPIOIBE0x408
144GPIO Interrupt Event0x0000.0000R/WGPIOIEV0x40C
145GPIO Interrupt Mask0x0000.0000R/WGPIOIM0x410
146GPIO Raw Interrupt Status0x0000.0000ROGPIORIS0x414
147GPIO Masked Interrupt Status0x0000.0000ROGPIOMIS0x418
148GPIO Interrupt Clear0x0000.0000W1CGPIOICR0x41C
November 30, 2007138
Preliminary
General-Purpose Input/Outputs (GPIOs)
See
page
DescriptionResetTypeNameOffset
149GPIO Alternate Function Select-R/WGPIOAFSEL0x420
151GPIO 2-mA Drive Select0x0000.00FFR/WGPIODR2R0x500
152GPIO 4-mA Drive Select0x0000.0000R/WGPIODR4R0x504
153GPIO 8-mA Drive Select0x0000.0000R/WGPIODR8R0x508
154GPIO Open Drain Select0x0000.0000R/WGPIOODR0x50C
155GPIO Pull-Up Select-R/WGPIOPUR0x510
156GPIO Pull-Down Select0x0000.0000R/WGPIOPDR0x514
157GPIO Slew Rate Control Select0x0000.0000R/WGPIOSLR0x518
158GPIO Digital Enable-R/WGPIODEN0x51C
159GPIO Lock0x0000.0001R/WGPIOLOCK0x520
160GPIO Commit--GPIOCR0x524
162GPIO Peripheral Identification 40x0000.0000ROGPIOPeriphID40xFD0
163GPIO Peripheral Identification 50x0000.0000ROGPIOPeriphID50xFD4
164GPIO Peripheral Identification 60x0000.0000ROGPIOPeriphID60xFD8
165GPIO Peripheral Identification 70x0000.0000ROGPIOPeriphID70xFDC
166GPIO Peripheral Identification 00x0000.0061ROGPIOPeriphID00xFE0
167GPIO Peripheral Identification 10x0000.0000ROGPIOPeriphID10xFE4
168GPIO Peripheral Identification 20x0000.0018ROGPIOPeriphID20xFE8
169GPIO Peripheral Identification 30x0000.0001ROGPIOPeriphID30xFEC
170GPIO PrimeCell Identification 00x0000.000DROGPIOPCellID00xFF0
171GPIO PrimeCell Identification 10x0000.00F0ROGPIOPCellID10xFF4
172GPIO PrimeCell Identification 20x0000.0005ROGPIOPCellID20xFF8
173GPIO PrimeCell Identification 30x0000.00B1ROGPIOPCellID30xFFC
8.4 Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
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Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 141).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and the data written to the
registers are masked by the eight address lines ipaddr[9:2]. Reads
from this register return its current state. Writes to this register only affect
bits that are not masked by ipaddr[9:2] and are configured as
outputs. See “Data Register Operation” on page 134 for examples of
reads and writes.
0x00R/WDATA7:0
November 30, 2007140
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General-Purpose Input/Outputs (GPIOs)
Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x400
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DIRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Data Direction
The DIR values are defined as follows:
DescriptionValue
Pins are inputs.0
Pins are outputs.1
0x00R/WDIR7:0
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x404
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ISreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Sense
The IS values are defined as follows:
DescriptionValue
Edge on corresponding pin is detected (edge-sensitive).0
Level on corresponding pin is detected (level-sensitive).1
0x00R/WIS7:0
November 30, 2007142
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General-Purpose Input/Outputs (GPIOs)
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 142) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 144). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x408
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IBEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Both Edges
The IBE values are defined as follows:
DescriptionValue
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 144).
0
Both edges on the corresponding pin trigger an interrupt.1
Note: Single edge is determined by the corresponding bit
in GPIOIEV.
0x00R/WIBE7:0
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Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 142). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x40C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IEVreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Event
The IEV values are defined as follows:
DescriptionValue
Falling edge or Low levels on corresponding pins trigger
interrupts.
0
Rising edge or High levels on corresponding pins trigger
interrupts.
1
0x00R/WIEV7:0
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General-Purpose Input/Outputs (GPIOs)
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding
pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables
interrupt triggering on that pin. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x410
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IMEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Mask Enable
The IME values are defined as follows:
DescriptionValue
Corresponding pin interrupt is masked.0
Corresponding pin interrupt is not masked.1
0x00R/WIME7:0
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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask
(GPIOIM) register (see page 145). Bits read as zero indicate that corresponding input pins have not
initiated an interrupt. All bits are cleared by a reset.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x414
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Raw Status
Reflects the status of interrupt trigger condition detection on pins (raw,
prior to masking).
The RIS values are defined as follows:
DescriptionValue
Corresponding pin interrupt requirements not met.0
Corresponding pin interrupt has met requirements.1
0x00RORIS7:0
November 30, 2007146
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for
PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer
Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x418
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
DescriptionValue
Corresponding GPIO line interrupt not active.0
Corresponding GPIO line asserting interrupt.1
0x00ROMIS7:0
147November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x41C
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ICreserved
W1CW1CW1CW1CW1CW1CW1CW1CROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Clear
The IC values are defined as follows:
DescriptionValue
Corresponding interrupt is unaffected.0
Corresponding interrupt is cleared.1
0x00W1CIC7:0
November 30, 2007148
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 149) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 159) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 160) have been set to 1.
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris®microcontroller. If the program code loaded into ash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x420
Type R/W, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
AFSELreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
--------00000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
149November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
GPIO Alternate Function Select
The AFSEL values are defined as follows:
DescriptionValue
Software control of corresponding GPIO line (GPIO mode).0
Hardware control of corresponding GPIO line (alternate
hardware function).
1
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
-R/WAFSEL7:0
November 30, 2007150
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x500
Type R/W, reset 0x0000.00FF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DRV2reserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
1111111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.
0xFFR/WDRV27:0
151November 30, 2007
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LM3S2016 Microcontroller
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x504
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DRV4reserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the second
clock cycle after the write.
0x00R/WDRV47:0
November 30, 2007152
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO
signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R
register are automatically cleared by hardware.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x508
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DRV8reserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the second
clock cycle after the write.
0x00R/WDRV87:0
153November 30, 2007
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LM3S2016 Microcontroller
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 158). Corresponding bits in the drive strength registers (GPIODR2R,GPIODR4R,GPIODR8R,
and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open
drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output
when set to 1.
When using the I2C module, the GPIO Alternate Function Select (GPIOAFSEL) register bit for
PB2 and PB3 should be set to 1 (see examples in “Initialization and Configuration” on page 136).
GPIO Open Drain Select (GPIOODR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x50C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ODEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Output Pad Open Drain Enable
The ODE values are defined as follows:
DescriptionValue
Open drain configuration is disabled.0
Open drain configuration is enabled.1
0x00R/WODE7:0
November 30, 2007154
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 156).
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x510
Type R/W, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PUEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
--------00000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Pad Weak Pull-Up Enable
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
Note: The default reset value for the GPIOAFSEL,GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
These five pins default to JTAG/SWD functionality. Because
of this, the default reset value of these registers for GPIO Port
B is 0x0000.0080 while the default reset value for Port C is
0x0000.000F.
-R/WPUE7:0
155November 30, 2007
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LM3S2016 Microcontroller
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears
the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 155).
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x514
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PDEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Pad Weak Pull-Down Enable
A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n]
enables. The change is effective on the second clock cycle after the
write.
0x00R/WPDE7:0
November 30, 2007156
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 153).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x518
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
SRLreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Slew Rate Limit Enable (8-mA drive only)
The SRL values are defined as follows:
DescriptionValue
Slew rate control disabled.0
Slew rate control enabled.1
0x00R/WSRL7:0
157November 30, 2007
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LM3S2016 Microcontroller
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
GPIO Digital Enable (GPIODEN)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x51C
Type R/W, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DENreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
--------00000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Digital Enable
The DEN values are defined as follows:
DescriptionValue
Digital functions disabled.0
Digital functions enabled.1
Note: The default reset value for the GPIOAFSEL,
GPIOPUR, and GPIODEN registers are 0x0000.0000
for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). These five pins
default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for GPIO
Port B is 0x0000.0080 while the default reset value
for Port C is 0x0000.000F.
-R/WDEN7:0
November 30, 2007158
Preliminary
General-Purpose Input/Outputs (GPIOs)
Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 160). Writing
0x1ACCE551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value
to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns
the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000.
GPIO Lock (GPIOLOCK)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x520
Type R/W, reset 0x0000.0001
16171819202122232425262728293031
LOCK
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
LOCK
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
GPIO Lock
A write of the value 0x1ACCE551 unlocks the GPIO Commit (GPIOCR)
register for write access. A write of any other value reapplies the lock,
preventing any register updates. A read of this register returns the
following values:
DescriptionValue
locked0x0000.0001
unlocked0x0000.0000
0x0000.0001R/WLOCK31:0
159November 30, 2007
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LM3S2016 Microcontroller
Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL register will be committed when a write to the GPIOAFSEL register is
performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit
in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the
GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register
will be committed to the register and will reflect the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register will be ignored if the GPIOLOCK register is locked.
Important: This register is designed to prevent accidental programming of the GPIOAFSEL registers
that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of
the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only
be converted to GPIOs through a deliberate set of writes to the GPIOLOCK,GPIOCR,
and GPIOAFSEL registers.
Because this protection is currently only implemented on the JTAG/SWD pins on PB7
and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0.
These bits are hardwired to 0x1, ensuring that it is always possible to commit new
values to the GPIOAFSEL register bits of these other pins.
GPIO Commit (GPIOCR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x524
Type -, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CRreserved
--------ROROROROROROROROType
--------00000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
November 30, 2007160
Preliminary
General-Purpose Input/Outputs (GPIOs)
DescriptionResetTypeNameBit/Field
GPIO Commit
On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL
bit to be set to its alternate function.
Note: The default register type for the GPIOCR register is RO for
all GPIO pins, with the exception of the five JTAG/SWD pins
(PB7 and PC[3:0]). These five pins are currently the only
GPIOs that are protected by the GPIOCR register. Because
of this, the register type for GPIO Port B7 and GPIO Port
C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the five
JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the
JTAG port is not accidentally programmed as a GPIO, these
five pins default to non-commitable. Because of this, the
default reset value of GPIOCR for GPIO Port B is
0x0000.007F while the default reset value of GPIOCR for Port
C is 0x0000.00F0.
--CR7:0
161November 30, 2007
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LM3S2016 Microcontroller
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4,GPIOPeriphID5,GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFD0
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID4reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[7:0]0x00ROPID47:0
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General-Purpose Input/Outputs (GPIOs)
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4,GPIOPeriphID5,GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFD4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID5reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[15:8]0x00ROPID57:0
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Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4,GPIOPeriphID5,GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFD8
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID6reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[23:16]0x00ROPID67:0
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General-Purpose Input/Outputs (GPIOs)
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4,GPIOPeriphID5,GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFDC
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID7reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[31:24]0x00ROPID77:0
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Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0,GPIOPeriphID1,GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFE0
Type RO, reset 0x0000.0061
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID0reserved
ROROROROROROROROROROROROROROROROType
1000011000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
0x61ROPID07:0
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General-Purpose Input/Outputs (GPIOs)
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0,GPIOPeriphID1,GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFE4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID1reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
0x00ROPID17:0
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Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0,GPIOPeriphID1,GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFE8
Type RO, reset 0x0000.0018
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID2reserved
ROROROROROROROROROROROROROROROROType
0001100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
0x18ROPID27:0
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General-Purpose Input/Outputs (GPIOs)
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0,GPIOPeriphID1,GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFEC
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID3reserved
ROROROROROROROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
0x01ROPID37:0
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Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0,GPIOPCellID1,GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFF0
Type RO, reset 0x0000.000D
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID0reserved
ROROROROROROROROROROROROROROROROType
1011000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
0x0DROCID07:0
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General-Purpose Input/Outputs (GPIOs)
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0,GPIOPCellID1,GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFF4
Type RO, reset 0x0000.00F0
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID1reserved
ROROROROROROROROROROROROROROROROType
0000111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
0xF0ROCID17:0
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Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0,GPIOPCellID1,GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFF8
Type RO, reset 0x0000.0005
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID2reserved
ROROROROROROROROROROROROROROROROType
1010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
0x05ROCID27:0
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General-Purpose Input/Outputs (GPIOs)
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0,GPIOPCellID1,GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0xFFC
Type RO, reset 0x0000.00B1
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID3reserved
ROROROROROROROROROROROROROROROROType
1000110100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
0xB1ROCID37:0
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9 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris®General-Purpose Timer Module (GPTM) contains two GPTM blocks (Timer0 and
Timer1). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB)
that can be configured to operate independently as timers or event counters, or configured to operate
as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger
analog-to-digital (ADC) conversions. The trigger signals from all of the general-purpose timers are
ORed together before reaching the ADC module, so only one timer should be used to trigger ADC
events.
The General-Purpose Timer Module is one timing resource available on the Stellaris®microcontrollers.
Other timer resources include the System Timer (SysTick) (see “System Timer
(SysTick)” on page 36).
The following modes are supported:
■32-bit Timer modes
–Programmable one-shot timer
–Programmable periodic timer
–Real-Time Clock using 32.768-KHz input clock
–Software-controlled event stalling (excluding RTC mode)
■16-bit Timer modes
–General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)
–Programmable one-shot timer
–Programmable periodic timer
–Software-controlled event stalling
■16-bit Input Capture modes
–Input edge count capture
–Input edge time capture
■16-bit PWM mode
–Simple PWM mode with software-programmable output inversion of the PWM signal
9.1 Block Diagram
Note: In Figure 9-1 on page 175, the specific CCP pins available depend on the Stellaris®device.
See Table 9-1 on page 175 for the available CCPs.
November 30, 2007174
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General-Purpose Timers
Figure 9-1. GPTM Module Block Diagram
TA Comparator
TB Comparator
GPTMTBR
GPTMAR
Clock / Edge
Detect
RTC Divider
Clock / Edge
Detect
TimerA
Interrupt
TimerB
Interrupt
System
Clock
0x0000 (Down Counter Modes)
0x0000 (Down Counter Modes)
32 KHz or
Even CCP Pin
Odd CCP Pin
En
En
TimerA Control
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
TimerB Control
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
Table 9-1. Available CCP Pins
Odd CCP PinEven CCP Pin16-Bit Up/Down CounterTimer
-CCP0TimerATimer 0
CCP1-TimerB
-CCP2TimerATimer 1
CCP3-TimerB
9.2 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit
load/initialization registers and their associated control functions. The exact functionality of each
GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 186),
the GPTM TimerA Mode (GPTMTAMR) register (see page 187), and the GPTM TimerB Mode
(GPTMTBMR) register (see page 189). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
9.2.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters TimerA and TimerB are initialized to
0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 200) and the GPTM TimerB Interval Load (GPTMTBILR) register
(see page 201). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale
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LM3S2016 Microcontroller
(GPTMTAPR) register (see page 204) and the GPTM TimerB Prescale (GPTMTBPR) register (see
page 205).
9.2.2 32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM
registers are concatenated to form pseudo 32-bit registers. These registers include:
■GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 200
■GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 201
■GPTM TimerA (GPTMTAR) register [15:0], see page 208
■GPTM TimerB (GPTMTBR) register [15:0], see page 209
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
9.2.2.1 32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 187), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 191), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and output triggers when
it reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 196), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 198). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTIMR) register (see page 194), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 197).
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000.0000
state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE bit in GPTMCTL,
and can trigger SoC-level events such as ADC conversions.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal
is deasserted.
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General-Purpose Timers
9.2.2.2 32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 202) by the controller.
The input clock on the CCP0,CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The
clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the
GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
9.2.3 16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 186). This section describes each of the GPTM 16-bit modes of
operation. TimerA and TimerB have identical modes, so a single description is given using an nto
reference both.
9.2.3.1 16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR)
register.
When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting.
In addition to reloading the count value, the timer generates interrupts and output triggers when it
reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it
until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR,
the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt.
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state,
and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the GPTMCTL
register, and can trigger SoC-level events such as ADC conversions.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal
is deasserted.
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The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period).
Table 9-2. 16-Bit Timer With Prescaler Configurations
UnitsMax Time#Clock (T c)a
Prescale
mS1.3107100000000
mS2.6214200000001
mS3.9321300000010
------------------
mS332.922925411111100
mS334.233625511111110
mS335.544325611111111
a. Tc is the clock period.
9.2.3.2 16-Bit Input Edge Count Mode
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded
using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in
the GPTMCTL register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software.
Figure 9-2 on page 179 shows how input edge count mode works. In this case, the timer start value
is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four
edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMnMR register.
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Figure 9-2. 16-Bit Input Edge Count Mode Example
0x000A
0x0006
0x0007
0x0008
0x0009
Input Signal
Timer stops,
flags
asserted
Timer reload
on next cycle Ignored Ignored
Count
9.2.3.3 16-Bit Input Edge Time Mode
Note: The prescaler is not available in 16-Bit Input Edge Time mode.
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of both
rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in the
GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT
fields of the GPTMCnTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and
the CnEMIS bit, if the interrupt is not masked).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMnILR register.
Figure 9-3 on page 180 shows how input edge timing mode works. In the diagram, it is assumed that
the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
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Figure 9-3. 16-Bit Input Edge Time Mode Example
GPTMTnR=Y
Input Signal
Time
Count GPTMTnR=X GPTMTnR=Z
Z
X
Y
0xFFFF
9.2.3.4 16-Bit PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled
with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR
field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by software
clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM
mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern Match
Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 9-4 on page 181 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is
GPTMnMR=0x411A.
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Figure 9-4. 16-Bit PWM Mode Example
Output
Signal
Time
Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
0xC350
0x411A
TnPWML = 0
TnPWML = 1
TnEN set
9.3 Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0
and TIMER1 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported timer
modes.
9.3.1 32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR).
5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
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7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 7 on page 182. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.2 32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0,CCP2, or CCP4
pins. To enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
9.3.3 16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM
Interrupt Clear Register (GPTMICR).
November 30, 2007182
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In One-Shot mode, the timer stops counting after step 8 on page 182. To re-enable the timer, repeat
the sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.4 16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 183
through step 9 on page 183.
9.3.5 16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
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Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
9.3.6 16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR) register
and the GPTM Timern Prescale Match (GPTMTnPMR) register.
8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
9.4 Register Map
Table 9-3 on page 184 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■Timer0: 0x4003.0000
■Timer1: 0x4003.1000
Table 9-3. Timers Register Map
See
page
DescriptionResetTypeNameOffset
186GPTM Configuration0x0000.0000R/WGPTMCFG0x000
187GPTM TimerA Mode0x0000.0000R/WGPTMTAMR0x004
189GPTM TimerB Mode0x0000.0000R/WGPTMTBMR0x008
191GPTM Control0x0000.0000R/WGPTMCTL0x00C
194GPTM Interrupt Mask0x0000.0000R/WGPTMIMR0x018
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See
page
DescriptionResetTypeNameOffset
196GPTM Raw Interrupt Status0x0000.0000ROGPTMRIS0x01C
197GPTM Masked Interrupt Status0x0000.0000ROGPTMMIS0x020
198GPTM Interrupt Clear0x0000.0000W1CGPTMICR0x024
200GPTM TimerA Interval Load
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
R/WGPTMTAILR0x028
201GPTM TimerB Interval Load0x0000.FFFFR/WGPTMTBILR0x02C
202GPTM TimerA Match
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
R/WGPTMTAMATCHR0x030
203GPTM TimerB Match0x0000.FFFFR/WGPTMTBMATCHR0x034
204GPTM TimerA Prescale0x0000.0000R/WGPTMTAPR0x038
205GPTM TimerB Prescale0x0000.0000R/WGPTMTBPR0x03C
206GPTM TimerA Prescale Match0x0000.0000R/WGPTMTAPMR0x040
207GPTM TimerB Prescale Match0x0000.0000R/WGPTMTBPMR0x044
208GPTM TimerA
0x0000.FFFF
(16-bit mode)
0xFFFF.FFFF
(32-bit mode)
ROGPTMTAR0x048
209GPTM TimerB0x0000.FFFFROGPTMTBR0x04C
9.5 Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
GPTMCFGreserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
GPTM Configuration
The GPTMCFG values are defined as follows:
DescriptionValue
32-bit timer configuration.0x0
32-bit real-time clock (RTC) counter configuration.0x1
Reserved.0x2
Reserved.0x3
16-bit timer configuration, function is controlled by bits 1:0 of
GPTMTAMR and GPTMTBMR.
0x4-0x7
0x0R/WGPTMCFG2:0
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Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x004
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TAMRTACMRTAAMSreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
DescriptionValue
Capture mode is enabled.0
PWM mode is enabled.1
Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
0R/WTAAMS3
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
DescriptionValue
Edge-Count mode.0
Edge-Time mode.1
0R/WTACMR2
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DescriptionResetTypeNameBit/Field
GPTM TimerA Mode
The TAMR values are defined as follows:
DescriptionValue
Reserved.0x0
One-Shot Timer mode.0x1
Periodic Timer mode.0x2
Capture mode.0x3
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for
TimerA.
In 32-bit timer configuration, this register controls the mode and the
contents of GPTMTBMR are ignored.
0x0R/WTAMR1:0
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Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
GPTM TimerB Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBMRTBCMRTBAMSreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
GPTM TimerB Alternate Mode Select
The TBAMS values are defined as follows:
DescriptionValue
Capture mode is enabled.0
PWM mode is enabled.1
Note: To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
0R/WTBAMS3
GPTM TimerB Capture Mode
The TBCMR values are defined as follows:
DescriptionValue
Edge-Count mode.0
Edge-Time mode.1
0R/WTBCMR2
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DescriptionResetTypeNameBit/Field
GPTM TimerB Mode
The TBMR values are defined as follows:
DescriptionValue
Reserved.0x0
One-Shot Timer mode.0x1
Periodic Timer mode.0x2
Capture mode.0x3
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer modes
for TimerB.
In 32-bit timer configuration, this register’s contents are ignored and
GPTMTAMR is used.
0x0R/WTBMR1:0
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Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x00C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TAENTASTALLTAEVENTRTCENTAOTETAPWMLreservedTBENTBSTALLTBEVENTreservedTBOTETBPWMLreserved
R/WR/WR/WR/WR/WR/WR/WROR/WR/WR/WR/WROR/WR/WROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:15
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
DescriptionValue
Output is unaffected.0
Output is inverted.1
0R/WTBPWML14
GPTM TimerB Output Trigger Enable
The TBOTE values are defined as follows:
DescriptionValue
The output TimerB trigger is disabled.0
The output TimerB trigger is enabled.1
0R/WTBOTE13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved12
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
DescriptionValue
Positive edge.0x0
Negative edge.0x1
Reserved0x2
Both edges.0x3
0x0R/WTBEVENT11:10
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DescriptionResetTypeNameBit/Field
GPTM TimerB Stall Enable
The TBSTALL values are defined as follows:
DescriptionValue
TimerB stalling is disabled.0
TimerB stalling is enabled.1
0R/WTBSTALL9
GPTM TimerB Enable
The TBEN values are defined as follows:
DescriptionValue
TimerB is disabled.0
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0R/WTBEN8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
DescriptionValue
Output is unaffected.0
Output is inverted.1
0R/WTAPWML6
GPTM TimerA Output Trigger Enable
The TAOTE values are defined as follows:
DescriptionValue
The output TimerA trigger is disabled.0
The output TimerA trigger is enabled.1
0R/WTAOTE5
GPTM RTC Enable
The RTCEN values are defined as follows:
DescriptionValue
RTC counting is disabled.0
RTC counting is enabled.1
0R/WRTCEN4
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DescriptionResetTypeNameBit/Field
GPTM TimerA Event Mode
The TAEVENT values are defined as follows:
DescriptionValue
Positive edge.0x0
Negative edge.0x1
Reserved0x2
Both edges.0x3
0x0R/WTAEVENT3:2
GPTM TimerA Stall Enable
The TASTALL values are defined as follows:
DescriptionValue
TimerA stalling is disabled.0
TimerA stalling is enabled.1
0R/WTASTALL1
GPTM TimerA Enable
The TAEN values are defined as follows:
DescriptionValue
TimerA is disabled.0
TimerA is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
1
0R/WTAEN0
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Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables
the interrupt, while writing a 0 disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x018
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATOIMCAMIMCAEIMRTCIMreservedTBTOIMCBMIMCBEIMreserved
R/WR/WR/WR/WROROROROR/WR/WR/WROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
GPTM CaptureB Event Interrupt Mask
The CBEIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WCBEIM10
GPTM CaptureB Match Interrupt Mask
The CBMIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WCBMIM9
GPTM TimerB Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WTBTOIM8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:4
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DescriptionResetTypeNameBit/Field
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WRTCIM3
GPTM CaptureA Event Interrupt Mask
The CAEIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WCAEIM2
GPTM CaptureA Match Interrupt Mask
The CAMIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WCAMIM1
GPTM TimerA Time-Out Interrupt Mask
The TATOIM values are defined as follows:
DescriptionValue
Interrupt is disabled.0
Interrupt is enabled.1
0R/WTATOIM0
195November 30, 2007
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Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x01C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATORISCAMRISCAERISRTCRISreservedTBTORISCBMRISCBERISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
0ROCBERIS10
GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
0ROCBMRIS9
GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
0ROTBTORIS8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:4
GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
0RORTCRIS3
GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
0ROCAERIS2
GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
0ROCAMRIS1
GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
0ROTATORIS0
November 30, 2007196
Preliminary
General-Purpose Timers
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x020
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATOMISCAMMISCAEMISRTCMISreservedTBTOMISCBMMISCBEMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
0ROCBEMIS10
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
0ROCBMMIS9
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
0ROTBTOMIS8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:4
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
0RORTCMIS3
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
0ROCAEMIS2
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
0ROCAMMIS1
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
0ROTATOMIS0
197November 30, 2007
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Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x024
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TATOCINTCAMCINTCAECINTRTCCINTreservedTBTOCINTCBMCINTCBECINTreserved
W1CW1CW1CW1CROROROROW1CW1CW1CROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
GPTM CaptureB Event Interrupt Clear
The CBECINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CCBECINT10
GPTM CaptureB Match Interrupt Clear
The CBMCINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CCBMCINT9
GPTM TimerB Time-Out Interrupt Clear
The TBTOCINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CTBTOCINT8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:4
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DescriptionResetTypeNameBit/Field
GPTM RTC Interrupt Clear
The RTCCINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CRTCCINT3
GPTM CaptureA Event Interrupt Clear
The CAECINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CCAECINT2
GPTM CaptureA Match Raw Interrupt
This is the CaptureA match interrupt status after masking.
0W1CCAMCINT1
GPTM TimerA Time-Out Raw Interrupt
The TATOCINT values are defined as follows:
DescriptionValue
The interrupt is unaffected.0
The interrupt is cleared.1
0W1CTATOCINT0
199November 30, 2007
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Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
GPTM TimerA Interval Load (GPTMTAILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x028
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
16171819202122232425262728293031
TAILRH
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0111101111010110Reset
0123456789101112131415
TAILRL
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register, the GPTM
TimerB Interval Load (GPTMTBILR) register loads this value on a
write. A read returns the current value of GPTMTBILR.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBILR.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
R/WTAILRH31:16
GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the counter for
TimerA. A read returns the current value of GPTMTAILR.
0xFFFFR/WTAILRL15:0
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Preliminary
General-Purpose Timers
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
GPTM TimerB Interval Load (GPTMTBILR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x02C
Type R/W, reset 0x0000.FFFF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBILRL
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
GPTM TimerB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to this field
updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads
return the current value of GPTMTBILR.
0xFFFFR/WTBILRL15:0
201November 30, 2007
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Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerA Match (GPTMTAMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x030
Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
16171819202122232425262728293031
TAMRH
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0111101111010110Reset
0123456789101112131415
TAMRL
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
GPTM TimerA Match Register High
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the upper half of
GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect on the
state of GPTMTBMATCHR.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
R/WTAMRH31:16
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via the
GPTMCFG register, this value is compared to the lower half of
GPTMTAR, to determine match events.
When configured for PWM mode, this value along with GPTMTAILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTAILR
minus this value.
0xFFFFR/WTAMRL15:0
November 30, 2007202
Preliminary
General-Purpose Timers
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes.
GPTM TimerB Match (GPTMTBMATCHR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x034
Type R/W, reset 0x0000.FFFF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBMRL
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
GPTM TimerB Match Register Low
When configured for PWM mode, this value along with GPTMTBILR,
determines the duty cycle of the output PWM signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines how many edge events are counted. The total
number of edge events counted is equal to the value in GPTMTBILR
minus this value.
0xFFFFR/WTBMRL15:0
203November 30, 2007
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LM3S2016 Microcontroller
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerA Prescale (GPTMTAPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x038
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TAPSRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPTM TimerA Prescale
The register loads this value on a write. A read returns the current value
of the register.
Refer to Table 9-2 on page 178 for more details and an example.
0x00R/WTAPSR7:0
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Preliminary
General-Purpose Timers
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers when operating in one-shot or
periodic mode.
GPTM TimerB Prescale (GPTMTBPR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x03C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBPSRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPTM TimerB Prescale
The register loads this value on a write. A read returns the current value
of this register.
Refer to Table 9-2 on page 178 for more details and an example.
0x00R/WTBPSR7:0
205November 30, 2007
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LM3S2016 Microcontroller
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerA Prescale Match (GPTMTAPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x040
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TAPSMRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPTM TimerA Prescale Match
This value is used alongside GPTMTAMATCHR to detect timer match
events while using a prescaler.
0x00R/WTAPSMR7:0
November 30, 2007206
Preliminary
General-Purpose Timers
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit
one-shot or periodic mode.
GPTM TimerB Prescale Match (GPTMTBPMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x044
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBPSMRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPTM TimerB Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match
events while using a prescaler.
0x00R/WTBPSMR7:0
207November 30, 2007
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LM3S2016 Microcontroller
Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerA (GPTMTAR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x048
Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
16171819202122232425262728293031
TARH
ROROROROROROROROROROROROROROROROType
0111101111010110Reset
0123456789101112131415
TARL
ROROROROROROROROROROROROROROROROType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
GPTM TimerA Register High
If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
0xFFFF
(32-bit mode)
0x0000 (16-bit
mode)
ROTARH31:16
GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
0xFFFFROTARL15:0
November 30, 2007208
Preliminary
General-Purpose Timers
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge Count
mode. When in this mode, this register contains the time at which the last edge event took place.
GPTM TimerB (GPTMTBR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x04C
Type RO, reset 0x0000.FFFF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TBRL
ROROROROROROROROROROROROROROROROType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
GPTM TimerB
A read returns the current value of the GPTM TimerB Count Register,
except in Input Edge Count mode, when it returns the timestamp from
the last edge event.
0xFFFFROTBRL15:0
209November 30, 2007
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LM3S2016 Microcontroller
10 Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris®Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
10.1 Block Diagram
Figure 10-1. WDT Module Block Diagram
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
WDTVALUE
Comparator
32-Bit Down
Counter
0x00000000
Interrupt
System Clock
Identification Registers
WDTPCellID0 WDTPeriphID0 WDTPeriphID4
WDTPCellID1 WDTPeriphID1 WDTPeriphID5
WDTPCellID2 WDTPeriphID2 WDTPeriphID6
WDTPCellID3 WDTPeriphID3 WDTPeriphID7
10.2 Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer
Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the
November 30, 2007210
Preliminary
Watchdog Timer
Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written,
which prevents the timer configuration from being inadvertently altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) register.
The Watchdog module interrupt and reset generation can be enabled or disabled as required. When
the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its
last state.
10.3 Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write
a value of 0x1ACC.E551.
10.4 Register Map
Table 10-1 on page 211 lists the Watchdog registers. The offset listed is a hexadecimal increment
to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000.
Table 10-1. Watchdog Timer Register Map
See
page
DescriptionResetTypeNameOffset
213Watchdog Load0xFFFF.FFFFR/WWDTLOAD0x000
214Watchdog Value0xFFFF.FFFFROWDTVALUE0x004
215Watchdog Control0x0000.0000R/WWDTCTL0x008
216Watchdog Interrupt Clear-WOWDTICR0x00C
217Watchdog Raw Interrupt Status0x0000.0000ROWDTRIS0x010
218Watchdog Masked Interrupt Status0x0000.0000ROWDTMIS0x014
219Watchdog Test0x0000.0000R/WWDTTEST0x418
220Watchdog Lock0x0000.0000R/WWDTLOCK0xC00
211November 30, 2007
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LM3S2016 Microcontroller
See
page
DescriptionResetTypeNameOffset
221Watchdog Peripheral Identification 40x0000.0000ROWDTPeriphID40xFD0
222Watchdog Peripheral Identification 50x0000.0000ROWDTPeriphID50xFD4
223Watchdog Peripheral Identification 60x0000.0000ROWDTPeriphID60xFD8
224Watchdog Peripheral Identification 70x0000.0000ROWDTPeriphID70xFDC
225Watchdog Peripheral Identification 00x0000.0005ROWDTPeriphID00xFE0
226Watchdog Peripheral Identification 10x0000.0018ROWDTPeriphID10xFE4
227Watchdog Peripheral Identification 20x0000.0018ROWDTPeriphID20xFE8
228Watchdog Peripheral Identification 30x0000.0001ROWDTPeriphID30xFEC
229Watchdog PrimeCell Identification 00x0000.000DROWDTPCellID00xFF0
230Watchdog PrimeCell Identification 10x0000.00F0ROWDTPCellID10xFF4
231Watchdog PrimeCell Identification 20x0000.0005ROWDTPCellID20xFF8
232Watchdog PrimeCell Identification 30x0000.00B1ROWDTPCellID30xFFC
10.5 Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
November 30, 2007212
Preliminary
Watchdog Timer
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated.
Watchdog Load (WDTLOAD)
Base 0x4000.0000
Offset 0x000
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
WDTLoad
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
WDTLoad
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Watchdog Load Value0xFFFF.FFFFR/WWDTLoad31:0
213November 30, 2007
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LM3S2016 Microcontroller
Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Watchdog Value (WDTVALUE)
Base 0x4000.0000
Offset 0x004
Type RO, reset 0xFFFF.FFFF
16171819202122232425262728293031
WDTValue
ROROROROROROROROROROROROROROROROType
1111111111111111Reset
0123456789101112131415
WDTValue
ROROROROROROROROROROROROROROROROType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
Watchdog Value
Current value of the 32-bit down counter.
0xFFFF.FFFFROWDTValue31:0
November 30, 2007214
Preliminary
Watchdog Timer
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTENRESENreserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
Watchdog Reset Enable
The RESEN values are defined as follows:
DescriptionValue
Disabled.0
Enable the Watchdog module reset output.1
0R/WRESEN1
Watchdog Interrupt Enable
The INTEN values are defined as follows:
DescriptionValue
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
0
Interrupt event enabled. Once enabled, all writes are ignored.1
0R/WINTEN0
215November 30, 2007
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LM3S2016 Microcontroller
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the Watchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Watchdog Interrupt Clear (WDTICR)
Base 0x4000.0000
Offset 0x00C
Type WO, reset -
16171819202122232425262728293031
WDTIntClr
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
----------------Reset
0123456789101112131415
WDTIntClr
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
----------------Reset
DescriptionResetTypeNameBit/Field
Watchdog Interrupt Clear-WOWDTIntClr31:0
November 30, 2007216
Preliminary
Watchdog Timer
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. Watchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Watchdog Raw Interrupt Status (WDTRIS)
Base 0x4000.0000
Offset 0x010
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
WDTRISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of WDTINTR.
0ROWDTRIS0
217November 30, 2007
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LM3S2016 Microcontroller
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Watchdog Masked Interrupt Status (WDTMIS)
Base 0x4000.0000
Offset 0x014
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
WDTMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the WDTINTR
interrupt.
0ROWDTMIS0
November 30, 2007218
Preliminary
Watchdog Timer
Register 7: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Watchdog Test (WDTTEST)
Base 0x4000.0000
Offset 0x418
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedSTALLreserved
ROROROROROROROROR/WROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:9
Watchdog Stall Enable
When set to 1, if the Stellaris®microcontroller is stopped with a
debugger, the watchdog timer stops counting. Once the microcontroller
is restarted, the watchdog timer resumes counting.
0R/WSTALL8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved7:0
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Preliminary
LM3S2016 Microcontroller
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00
Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value
written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns
0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)).
Watchdog Lock (WDTLOCK)
Base 0x4000.0000
Offset 0xC00
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
WDTLock
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
WDTLock
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Watchdog Lock
A write of the value 0x1ACC.E551 unlocks the watchdog registers for
write access. A write of any other value reapplies the lock, preventing
any register updates.
A read of this register returns the following values:
DescriptionValue
Locked0x0000.0001
Unlocked0x0000.0000
0x0000R/WWDTLock31:0
November 30, 2007220
Preliminary
Watchdog Timer
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Base 0x4000.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID4reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
WDT Peripheral ID Register[7:0]0x00ROPID47:0
221November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset
0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Base 0x4000.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID5reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
WDT Peripheral ID Register[15:8]0x00ROPID57:0
November 30, 2007222
Preliminary
Watchdog Timer
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset
0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Base 0x4000.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID6reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
WDT Peripheral ID Register[23:16]0x00ROPID67:0
223November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset
0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Base 0x4000.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID7reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
WDT Peripheral ID Register[31:24]0x00ROPID77:0
November 30, 2007224
Preliminary
Watchdog Timer
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset
0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Base 0x4000.0000
Offset 0xFE0
Type RO, reset 0x0000.0005
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID0reserved
ROROROROROROROROROROROROROROROROType
1010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog Peripheral ID Register[7:0]0x05ROPID07:0
225November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset
0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Base 0x4000.0000
Offset 0xFE4
Type RO, reset 0x0000.0018
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID1reserved
ROROROROROROROROROROROROROROROROType
0001100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog Peripheral ID Register[15:8]0x18ROPID17:0
November 30, 2007226
Preliminary
Watchdog Timer
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset
0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Base 0x4000.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID2reserved
ROROROROROROROROROROROROROROROROType
0001100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog Peripheral ID Register[23:16]0x18ROPID27:0
227November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset
0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Base 0x4000.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID3reserved
ROROROROROROROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog Peripheral ID Register[31:24]0x01ROPID37:0
November 30, 2007228
Preliminary
Watchdog Timer
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 0 (WDTPCellID0)
Base 0x4000.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID0reserved
ROROROROROROROROROROROROROROROROType
1011000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog PrimeCell ID Register[7:0]0x0DROCID07:0
229November 30, 2007
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LM3S2016 Microcontroller
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 1 (WDTPCellID1)
Base 0x4000.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID1reserved
ROROROROROROROROROROROROROROROROType
0000111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog PrimeCell ID Register[15:8]0xF0ROCID17:0
November 30, 2007230
Preliminary
Watchdog Timer
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 2 (WDTPCellID2)
Base 0x4000.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID2reserved
ROROROROROROROROROROROROROROROROType
1010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog PrimeCell ID Register[23:16]0x05ROCID27:0
231November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Watchdog PrimeCell Identification 3 (WDTPCellID3)
Base 0x4000.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID3reserved
ROROROROROROROROROROROROROROROROType
1000110100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Watchdog PrimeCell ID Register[31:24]0xB1ROCID37:0
November 30, 2007232
Preliminary
Watchdog Timer
11 Analog-to-Digital Converter (ADC)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The Stellaris®ADC module features 10-bit conversion resolution and supports four input channels.
The ADC module contains a programmable sequencer which allows for the sampling of multiple
analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
The Stellaris®ADC provides the following features:
■Four analog input channels
■Single-ended and differential-input configurations
■Sample rate of 500 thousand samples/second
■Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
■Flexible trigger control
–Controller (software)
–Timers
–GPIO
■Hardware averaging of up to 64 samples for improved accuracy
233November 30, 2007
Preliminary
LM3S2016 Microcontroller
11.1 Block Diagram
Figure 11-1. ADC Module Block Diagram
Analog-to-Digital
Converter
ADCSSFSTAT0
ADCSSCTL0
ADCSSMUX0
Sample
Sequencer 0
ADCSSFSTAT1
ADCSSCTL1
ADCSSMUX1
Sample
Sequencer 1
ADCSSFSTAT2
ADCSSCTL2
ADCSSMUX2
Sample
Sequencer 2
ADCSSFSTAT3
ADCSSCTL3
ADCSSMUX3
Sample
Sequencer 3
ADCUSTAT
ADCOSTAT
ADCACTSS
Control/Status
ADCSSPRI
ADCISC
ADCRIS
ADCIM
Interrupt Control
Analog Inputs
SS0 Interrupt
SS1 Interrupt
SS2 Interrupt
SS3 Interrupt
ADCEMUX
ADCPSSI
Trigger Events
SS0
SS1
SS2
SS3
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
Comparator
GPIO (PB4)
Timer
PWM
ADCSSFIFO0
ADCSSFIFO1
ADCSSFIFO2
ADCSSFIFO3
FIFO Block
Hardware Averager
ADCSAC
11.2 Functional Description
The Stellaris®ADC collects sample data by using a programmable sequence-based approach
instead of the traditional single or double-sampling approach found on many ADC modules. Each
sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the
ADC to collect data from multiple input sources without having to be re-configured or serviced by
the controller. The programming of each sample in the sample sequence includes parameters such
as the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence.
11.2.1 Sample Sequencers
The sampling control and data capture is handled by the Sample Sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 11-1 on page 234 shows the maximum number of samples that each Sequencer
can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit
word, with the lower 10 bits containing the conversion result.
Table 11-1. Samples and FIFO Depth of Sequencers
Depth of FIFONumber of SamplesSequencer
11SS3
44SS2
44SS1
88SS0
November 30, 2007234
Preliminary
Analog-to-Digital Converter (ADC)
For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample
Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control
(ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn
nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits
corresponding to parameters such as interrupt enable, end of sequence, and differential input mode.
Sample Sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample
Sequencer (ADCACTSS) register, but can be configured before being enabled.
When configuring a sample sequence, multiple uses of the same input pin within the same sequence
is allowed. In the ADCSSCTLn register, the Interrupt Enable (IE) bits can be set for any
combination of samples, allowing interrupts to be generated after every sample in the sequence if
necessary. Also, the END bit can be set at any point within a sample sequence. For example, if
Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing
Sequencer 0 to complete execution of the sample sequence after the fifth sample.
After a sample sequence completes execution, the result data can be retrieved from the ADC
Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers
that read a single address to "pop" result data. For software debug purposes, the positions of the
FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn)
registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored
using the ADCOSTAT and ADCUSTAT registers.
11.2.2 Module Control
Outside of the Sample Sequencers, the remainder of the control logic is responsible for tasks such
as interrupt generation, sequence prioritization, and trigger configuration.
Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider
is configured automatically by hardware when the system XTAL is selected. The automatic clock
divider configuration targets 16.667 MHz operation for all Stellaris®devices.
11.2.2.1 Interrupts
The Sample Sequencers dictate the events that cause interrupts, but they don't have control over
whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signal
is controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt
status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which
shows the raw status of a Sample Sequencer's interrupt signal, and the ADC Interrupt Status and
Clear (ADCISC) register, which shows the logical AND of the ADCRIS register’s INR bit and the
ADCIM register’s MASK bits. Interrupts are cleared by writing a 1 to the corresponding IN bit in
ADCISC.
11.2.2.2 Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active Sample
Sequencer units with the same priority do not provide consistent results, so software must ensure
that all active Sample Sequencer units have a unique priority value.
11.2.2.3 Sampling Events
Sample triggering for each Sample Sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. The external peripheral triggering sources vary by Stellaris®family member,
but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting
the CH bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
235November 30, 2007
Preliminary
LM3S2016 Microcontroller
When using the "Always" trigger, care must be taken. If a sequence's priority is too high, it is possible
to starve other lower priority sequences.
11.2.3 Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 250). There is a single averaging circuit and all input channels receive the same
amount of averaging whether they are single-ended or differential.
11.2.4 Analog-to-Digital Converter
The converter itself generates a 10-bit output value for selected analog input. Special analog pads
are used to minimize the distortion on the input.
11.2.5 Test Modes
There is a user-available test mode that allows for loopback operation within the digital portion of
the ADC module. This can be useful for debugging software without having to provide actual analog
stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see
page 263).
11.3 Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and using a supported crystal
frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the
ADC module.
11.3.1 Module Initialization
Initialization of the ADC module is a simple process with very few steps. The main steps include
enabling the clock to the ADC and reconfiguring the Sample Sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC1 register (see page 94).
2. If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample
Sequencer 3 as the lowest priority.
11.3.2 Sample Sequencer Configuration
Configuration of the Sample Sequencers is slightly more complex than the module initialization
since each sample sequence is completely programmable.
The configuration for each Sample Sequencer should be as follows:
1. Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in
the ADCACTSS register. Programming of the Sample Sequencers is allowed without having
November 30, 2007236
Preliminary
Analog-to-Digital Converter (ADC)
them enabled. Disabling the Sequencer during programming prevents erroneous execution if
a trigger event were to occur during the configuration process.
2. Configure the trigger event for the Sample Sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the corresponding
nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit
is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the
ADCACTSS register.
11.4 Register Map
Table 11-2 on page 237 lists the ADC registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the ADC base address of 0x4003.8000.
Table 11-2. ADC Register Map
See
page
DescriptionResetTypeNameOffset
239ADC Active Sample Sequencer0x0000.0000R/WADCACTSS0x000
240ADC Raw Interrupt Status0x0000.0000ROADCRIS0x004
241ADC Interrupt Mask0x0000.0000R/WADCIM0x008
242ADC Interrupt Status and Clear0x0000.0000R/W1CADCISC0x00C
243ADC Overflow Status0x0000.0000R/W1CADCOSTAT0x010
244ADC Event Multiplexer Select0x0000.0000R/WADCEMUX0x014
247ADC Underflow Status0x0000.0000R/W1CADCUSTAT0x018
248ADC Sample Sequencer Priority0x0000.3210R/WADCSSPRI0x020
249ADC Processor Sample Sequence Initiate-WOADCPSSI0x028
250ADC Sample Averaging Control0x0000.0000R/WADCSAC0x030
251ADC Sample Sequence Input Multiplexer Select 00x0000.0000R/WADCSSMUX00x040
253ADC Sample Sequence Control 00x0000.0000R/WADCSSCTL00x044
256ADC Sample Sequence Result FIFO 00x0000.0000ROADCSSFIFO00x048
257ADC Sample Sequence FIFO 0 Status0x0000.0100ROADCSSFSTAT00x04C
258ADC Sample Sequence Input Multiplexer Select 10x0000.0000R/WADCSSMUX10x060
259ADC Sample Sequence Control 10x0000.0000R/WADCSSCTL10x064
256ADC Sample Sequence Result FIFO 10x0000.0000ROADCSSFIFO10x068
257ADC Sample Sequence FIFO 1 Status0x0000.0100ROADCSSFSTAT10x06C
237November 30, 2007
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LM3S2016 Microcontroller
See
page
DescriptionResetTypeNameOffset
258ADC Sample Sequence Input Multiplexer Select 20x0000.0000R/WADCSSMUX20x080
259ADC Sample Sequence Control 20x0000.0000R/WADCSSCTL20x084
256ADC Sample Sequence Result FIFO 20x0000.0000ROADCSSFIFO20x088
257ADC Sample Sequence FIFO 2 Status0x0000.0100ROADCSSFSTAT20x08C
261ADC Sample Sequence Input Multiplexer Select 30x0000.0000R/WADCSSMUX30x0A0
262ADC Sample Sequence Control 30x0000.0002R/WADCSSCTL30x0A4
256ADC Sample Sequence Result FIFO 30x0000.0000ROADCSSFIFO30x0A8
257ADC Sample Sequence FIFO 3 Status0x0000.0100ROADCSSFSTAT30x0AC
263ADC Test Mode Loopback0x0000.0000R/WADCTMLB0x100
11.5 Register Descriptions
The remainder of this section lists and describes the ADC registers, in numerical order by address
offset.
November 30, 2007238
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Analog-to-Digital Converter (ADC)
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be
enabled/disabled independently.
ADC Active Sample Sequencer (ADCACTSS)
Base 0x4003.8000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ASEN0ASEN1ASEN2ASEN3reserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
ADC SS3 Enable
Specifies whether Sample Sequencer 3 is enabled. If set, the sample
sequence logic for Sequencer 3 is active. Otherwise, the Sequencer is
inactive.
0R/WASEN33
ADC SS2 Enable
Specifies whether Sample Sequencer 2 is enabled. If set, the sample
sequence logic for Sequencer 2 is active. Otherwise, the Sequencer is
inactive.
0R/WASEN22
ADC SS1 Enable
Specifies whether Sample Sequencer 1 is enabled. If set, the sample
sequence logic for Sequencer 1 is active. Otherwise, the Sequencer is
inactive.
0R/WASEN11
ADC SS0 Enable
Specifies whether Sample Sequencer 0 is enabled. If set, the sample
sequence logic for Sequencer 0 is active. Otherwise, the Sequencer is
inactive.
0R/WASEN00
239November 30, 2007
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LM3S2016 Microcontroller
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits
may be polled by software to look for interrupt conditions without having to generate controller
interrupts.
ADC Raw Interrupt Status (ADCRIS)
Base 0x4003.8000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INR0INR1INR2INR3reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SS3 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL3 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN3 bit.
0ROINR33
SS2 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL2 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN2 bit.
0ROINR22
SS1 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL1 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN1 bit.
0ROINR11
SS0 Raw Interrupt Status
Set by hardware when a sample with its respective ADCSSCTL0 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN0 bit.
0ROINR00
November 30, 2007240
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Analog-to-Digital Converter (ADC)
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the Sample Sequencer raw interrupt signals are promoted to controller
interrupts. The raw interrupt signal for each Sample Sequencer can be masked independently.
ADC Interrupt Mask (ADCIM)
Base 0x4003.8000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MASK0MASK1MASK2MASK3reserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SS3 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 3
(ADCRIS register INR3 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
0R/WMASK33
SS2 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 2
(ADCRIS register INR2 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
0R/WMASK22
SS1 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 1
(ADCRIS register INR1 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
0R/WMASK11
SS0 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 0
(ADCRIS register INR0 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
0R/WMASK00
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Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing interrupt conditions, and shows the status of
controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical
AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the corresponding
bit position. If software is polling the ADCRIS instead of generating interrupts, the INR bits are still
cleared via the ADCISC register, even if the IN bit is not set.
ADC Interrupt Status and Clear (ADCISC)
Base 0x4003.8000
Offset 0x00C
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IN0IN1IN2IN3reserved
R/W1CR/W1CR/W1CR/W1CROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SS3 Interrupt Status and Clear
This bit is set by hardware when the MASK3 and INR3 bits are both 1,
providing a level-based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR3 bit.
0R/W1CIN33
SS2 Interrupt Status and Clear
This bit is set by hardware when the MASK2 and INR2 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR2 bit.
0R/W1CIN22
SS1 Interrupt Status and Clear
This bit is set by hardware when the MASK1 and INR1 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR1 bit.
0R/W1CIN11
SS0 Interrupt Status and Clear
This bit is set by hardware when the MASK0 and INR0 bits are both 1,
providing a level based interrupt to the controller. It is cleared by writing
a 1, and also clears the INR0 bit.
0R/W1CIN00
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Analog-to-Digital Converter (ADC)
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
Base 0x4003.8000
Offset 0x010
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
OV0OV1OV2OV3reserved
R/W1CR/W1CR/W1CR/W1CROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SS3 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
0R/W1COV33
SS2 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
0R/W1COV22
SS1 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
0R/W1COV11
SS0 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
0R/W1COV00
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Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014
The ADCEMUX selects the event (trigger) that initiates sampling for each Sample Sequencer. Each
Sample Sequencer can be configured with a unique trigger source.
ADC Event Multiplexer Select (ADCEMUX)
Base 0x4003.8000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
EM0EM1EM2EM3
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:16
SS3 Trigger Select
This field selects the trigger source for Sample Sequencer 3.
The valid configurations for this field are:
EventValue
Controller (default)0x0
Reserved0x1
Reserved0x2
Reserved0x3
External (GPIO PB4)0x4
Timer0x5
Reserved0x6
Reserved0x7
Reserved0x8
reserved0x9-0xE
Always (continuously sample)0xF
0x00R/WEM315:12
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Analog-to-Digital Converter (ADC)
DescriptionResetTypeNameBit/Field
SS2 Trigger Select
This field selects the trigger source for Sample Sequencer 2.
The valid configurations for this field are:
EventValue
Controller (default)0x0
Reserved0x1
Reserved0x2
Reserved0x3
External (GPIO PB4)0x4
Timer0x5
Reserved0x6
Reserved0x7
Reserved0x8
reserved0x9-0xE
Always (continuously sample)0xF
0x00R/WEM211:8
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
EventValue
Controller (default)0x0
Reserved0x1
Reserved0x2
Reserved0x3
External (GPIO PB4)0x4
Timer0x5
Reserved0x6
Reserved0x7
Reserved0x8
reserved0x9-0xE
Always (continuously sample)0xF
0x00R/WEM17:4
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LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0.
The valid configurations for this field are:
EventValue
Controller (default)0x0
Reserved0x1
Reserved0x2
Reserved0x3
External (GPIO PB4)0x4
Timer0x5
Reserved0x6
Reserved0x7
Reserved0x8
reserved0x9-0xE
Always (continuously sample)0xF
0x00R/WEM03:0
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Analog-to-Digital Converter (ADC)
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the Sample Sequencer FIFOs. The corresponding
underflow condition can be cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
Base 0x4003.8000
Offset 0x018
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
UV0UV1UV2UV3reserved
R/W1CR/W1CR/W1CR/W1CROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SS3 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
0R/W1CUV33
SS2 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
0R/W1CUV22
SS1 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
0R/W1CUV11
SS0 FIFO Underflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
underflow condition where the FIFO is empty and a read was requested.
The problematic read does not move the FIFO pointers, and 0s are
returned. This bit is cleared by writing a 1.
0R/W1CUV00
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Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the Sample Sequencers. Out of reset, Sequencer 0 has
the highest priority, and sample sequence 3 has the lowest priority. When reconfiguring sequence
priorities, each sequence must have a unique priority or the ADC behavior is inconsistent.
ADC Sample Sequencer Priority (ADCSSPRI)
Base 0x4003.8000
Offset 0x020
Type R/W, reset 0x0000.3210
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
SS0reservedSS1reservedSS2reservedSS3reserved
R/WR/WROROR/WR/WROROR/WR/WROROR/WR/WROROType
0000100001001100Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:14
SS3 Priority
The SS3 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 3. A priority encoding of 0 is highest
and 3 is lowest. The priorities assigned to the Sequencers must be
uniquely mapped. ADC behavior is not consistent if two or more fields
are equal.
0x3R/WSS313:12
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved11:10
SS2 Priority
The SS2 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 2.
0x2R/WSS29:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved7:6
SS1 Priority
The SS1 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 1.
0x1R/WSS15:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved3:2
SS0 Priority
The SS0 field contains a binary-encoded value that specifies the priority
encoding of Sample Sequencer 0.
0x0R/WSS01:0
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Analog-to-Digital Converter (ADC)
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the Sample
Sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
ADC Processor Sample Sequence Initiate (ADCPSSI)
Base 0x4003.8000
Offset 0x028
Type WO, reset -
16171819202122232425262728293031
reserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
----------------Reset
0123456789101112131415
SS0SS1SS2SS3reserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
----------------Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
-WOreserved31:4
SS3 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 3, assuming the Sequencer is enabled in the ADCACTSS
register.
-WOSS33
SS2 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 2, assuming the Sequencer is enabled in the ADCACTSS
register.
-WOSS22
SS1 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 1, assuming the Sequencer is enabled in the ADCACTSS
register.
-WOSS11
SS0 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 0, assuming the Sequencer is enabled in the ADCACTSS
register.
-WOSS00
249November 30, 2007
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Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030
This register controls the amount of hardware averaging applied to conversion results. The final
conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified
ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6,
then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An
AVG = 7 provides unpredictable results.
ADC Sample Averaging Control (ADCSAC)
Base 0x4003.8000
Offset 0x030
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
AVGreserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
Hardware Averaging Control
Specifies the amount of hardware averaging that will be applied to ADC
samples. The AVG field can be any value between 0 and 6. Entering a
value of 7 creates unpredictable results.
DescriptionValue
No hardware oversampling0x0
2x hardware oversampling0x1
4x hardware oversampling0x2
8x hardware oversampling0x3
16x hardware oversampling0x4
32x hardware oversampling0x5
64x hardware oversampling0x6
Reserved0x7
0x0R/WAVG2:0
November 30, 2007250
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Analog-to-Digital Converter (ADC)
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0),
offset 0x040
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 0.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0)
Base 0x4003.8000
Offset 0x040
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
MUX4reservedMUX5reservedMUX6reservedMUX7reserved
R/WR/WROROR/WR/WROROR/WR/WROROR/WR/WROROType
0000000000000000Reset
0123456789101112131415
MUX0reservedMUX1reservedMUX2reservedMUX3reserved
R/WR/WROROR/WR/WROROR/WR/WROROR/WR/WROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:30
8th Sample Input Select
The MUX7 field is used during the eighth sample of a sequence executed
with the Sample Sequencer. It specifies which of the analog inputs is
sampled for the analog-to-digital conversion. The value set here indicates
the corresponding pin, for example, a value of 1 indicates the input is
ADC1.
0R/WMUX729:28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27:26
7th Sample Input Select
The MUX6 field is used during the seventh sample of a sequence
executed with the Sample Sequencer and specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
0R/WMUX625:24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23:22
6th Sample Input Select
The MUX5 field is used during the sixth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
0R/WMUX521:20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved19:18
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LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
5th Sample Input Select
The MUX4 field is used during the fifth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
0R/WMUX417:16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:14
4th Sample Input Select
The MUX3 field is used during the fourth sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
0R/WMUX313:12
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:10
3rd Sample Input Select
The MUX2 field is used during the third sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
0R/WMUX29:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:6
2nd Sample Input Select
The MUX1 field is used during the second sample of a sequence
executed with the Sample Sequencer and specifies which of the analog
inputs is sampled for the analog-to-digital conversion.
0R/WMUX15:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:2
1st Sample Input Select
The MUX0 field is used during the first sample of a sequence executed
with the Sample Sequencer and specifies which of the analog inputs is
sampled for the analog-to-digital conversion.
0R/WMUX01:0
November 30, 2007252
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Analog-to-Digital Converter (ADC)
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 0. When configuring a sample sequence, the END bit must be set at some point,
whether it be after the first sample, last sample, or any sample in between.
This register is 32-bits wide and contains information for eight possible samples.
ADC Sample Sequence Control 0 (ADCSSCTL0)
Base 0x4003.8000
Offset 0x044
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
D4END4IE4reservedD5END5IE5reservedD6END6IE6reservedD7END7IE7reserved
R/WR/WR/WROR/WR/WR/WROR/WR/WR/WROR/WR/WR/WROType
0000000000000000Reset
0123456789101112131415
D0END0IE0reservedD1END1IE1reservedD2END2IE2reservedD3END3IE3reserved
R/WR/WR/WROR/WR/WR/WROR/WR/WR/WROR/WR/WR/WROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31
8th Sample Interrupt Enable
The IE7 bit is used during the eighth sample of the sample sequence
and specifies whether the raw interrupt signal (INR0 bit) is asserted at
the end of the sample's conversion. If the MASK0 bit in the ADCIM
register is set, the interrupt is promoted to a controller-level interrupt.
When this bit is set, the raw interrupt is asserted, otherwise it is not. It
is legal to have multiple samples within a sequence generate interrupts.
0R/WIE730
8th Sample is End of Sequence
The END7 bit indicates that this is the last sample of the sequence. It is
possible to end the sequence on any sample position. Samples defined
after the sample containing a set END are not requested for conversion
even though the fields may be non-zero. It is required that software write
the END bit somewhere within the sequence. (Sample Sequencer 3,
which only has a single sample in the sequence, is hardwired to have
the END0 bit set.)
Setting this bit indicates that this sample is the last in the sequence.
0R/WEND729
8th Sample Diff Input Select
The D7 bit indicates that the analog input is to be differentially sampled.
The corresponding ADCSSMUXx nibble must be set to the pair number
"i", where the paired inputs are "2i and 2i+1". When set, the analog
inputs are differentially sampled.
0R/WD728
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved27
253November 30, 2007
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LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
7th Sample Interrupt Enable
Same definition as IE7 but used during the seventh sample.
0R/WIE626
7th Sample is End of Sequence
Same definition as END7 but used during the seventh sample.
0R/WEND625
7th Sample Diff Input Select
Same definition as D7 but used during the seventh sample.
0R/WD624
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved23
6th Sample Interrupt Enable
Same definition as IE7 but used during the sixth sample.
0R/WIE522
6th Sample is End of Sequence
Same definition as END7 but used during the sixth sample.
0R/WEND521
6th Sample Diff Input Select
Same definition as D7 but used during the sixth sample.
0R/WD520
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved19
5th Sample Interrupt Enable
Same definition as IE7 but used during the fifth sample.
0R/WIE418
5th Sample is End of Sequence
Same definition as END7 but used during the fifth sample.
0R/WEND417
5th Sample Diff Input Select
Same definition as D7 but used during the fifth sample.
0R/WD416
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
0R/WIE314
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
0R/WEND313
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
0R/WD312
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11
November 30, 2007254
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Analog-to-Digital Converter (ADC)
DescriptionResetTypeNameBit/Field
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
0R/WIE210
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
0R/WEND29
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
0R/WD28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
0R/WIE16
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
0R/WEND15
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
0R/WD14
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
0R/WIE02
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
0R/WEND01
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0R/WD00
255November 30, 2007
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LM3S2016 Microcontroller
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
This register contains the conversion results for samples collected with the Sample Sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)
Base 0x4003.8000
Offset 0x048
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:10
Conversion Result Data0x00RODATA9:0
November 30, 2007256
Preliminary
Analog-to-Digital Converter (ADC)
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset
0x04C
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset
0x06C
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset
0x08C
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset
0x0AC
This register provides a window into the Sample Sequencer, providing full/empty status information
as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty
FIFO. The ADCSSFSTAT0 register provides status on FIF0, ADCSSFSTAT1 on FIFO1,
ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3.
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0)
Base 0x4003.8000
Offset 0x04C
Type RO, reset 0x0000.0100
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TPTRHPTREMPTYreservedFULLreserved
ROROROROROROROROROROROROROROROROType
0000000010000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:13
FIFO Full
When set, indicates that the FIFO is currently full.
0ROFULL12
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved11:9
FIFO Empty
When set, indicates that the FIFO is currently empty.
1ROEMPTY8
FIFO Head Pointer
This field contains the current "head" pointer index for the FIFO, that is,
the next entry to be written.
0x00ROHPTR7:4
FIFO Tail Pointer
This field contains the current "tail" pointer index for the FIFO, that is,
the next entry to be read.
0x00ROTPTR3:0
257November 30, 2007
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Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),
offset 0x060
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 251 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1)
Base 0x4003.8000
Offset 0x060
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MUX0reservedMUX1reservedMUX2reservedMUX3reserved
R/WR/WROROR/WR/WROROR/WR/WROROR/WR/WROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:14
4th Sample Input Select0R/WMUX313:12
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:10
3rd Sample Input Select0R/WMUX29:8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7:6
2nd Sample Input Select0R/WMUX15:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:2
1st Sample Input Select0R/WMUX01:0
November 30, 2007258
Preliminary
Analog-to-Digital Converter (ADC)
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some
point, whether it be after the first sample, last sample, or any sample in between. This register is
16-bits wide and contains information for four possible samples. See the ADCSSCTL0 register on
page 253 for detailed bit descriptions.
ADC Sample Sequence Control 1 (ADCSSCTL1)
Base 0x4003.8000
Offset 0x064
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
D0END0IE0reservedD1END1IE1reservedD2END2IE2reservedD3END3IE3reserved
R/WR/WR/WROR/WR/WR/WROR/WR/WR/WROR/WR/WR/WROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:15
4th Sample Interrupt Enable
Same definition as IE7 but used during the fourth sample.
0R/WIE314
4th Sample is End of Sequence
Same definition as END7 but used during the fourth sample.
0R/WEND313
4th Sample Diff Input Select
Same definition as D7 but used during the fourth sample.
0R/WD312
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11
3rd Sample Interrupt Enable
Same definition as IE7 but used during the third sample.
0R/WIE210
3rd Sample is End of Sequence
Same definition as END7 but used during the third sample.
0R/WEND29
3rd Sample Diff Input Select
Same definition as D7 but used during the third sample.
0R/WD28
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved7
259November 30, 2007
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LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
2nd Sample Interrupt Enable
Same definition as IE7 but used during the second sample.
0R/WIE16
2nd Sample is End of Sequence
Same definition as END7 but used during the second sample.
0R/WEND15
2nd Sample Diff Input Select
Same definition as D7 but used during the second sample.
0R/WD14
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
0R/WIE02
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
0R/WEND01
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0R/WD00
November 30, 2007260
Preliminary
Analog-to-Digital Converter (ADC)
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3),
offset 0x0A0
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample.
See the ADCSSMUX0 register on page 251 for detailed bit descriptions.
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3)
Base 0x4003.8000
Offset 0x0A0
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MUX0reserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
1st Sample Input Select0R/WMUX01:0
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Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer.
This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0
register on page 253 for detailed bit descriptions.
ADC Sample Sequence Control 3 (ADCSSCTL3)
Base 0x4003.8000
Offset 0x0A4
Type R/W, reset 0x0000.0002
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
D0END0IE0reserved
R/WR/WR/WROROROROROROROROROROROROROType
0100000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
1st Sample Interrupt Enable
Same definition as IE7 but used during the first sample.
0R/WIE02
1st Sample is End of Sequence
Same definition as END7 but used during the first sample.
Since this sequencer has only one entry, this bit must be set.
1R/WEND01
1st Sample Diff Input Select
Same definition as D7 but used during the first sample.
0R/WD00
November 30, 2007262
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Analog-to-Digital Converter (ADC)
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100
This register provides loopback operation within the digital logic of the ADC, which can be useful in
debugging software without having to provide actual analog stimulus. This test mode is entered by
writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode,
the read-only portion of this register is returned.
Read-Only Register
ADC Test Mode Loopback (ADCTMLB)
Base 0x4003.8000
Offset 0x100
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MUXreservedDIFFCONTCNTreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:10
Continuous Sample Counter
Continuous sample counter that is initialized to 0 and counts each
sample as it processed. This helps provide a unique value for the data
received.
0x0ROCNT9:6
Continuation Sample Indicator
When set, indicates that this is a continuation sample. For example, if
two sequencers were to run back-to-back, this indicates that the
controller kept continuously sampling at full rate.
0ROCONT5
Differential Sample Indicator
When set, indicates that this is a differential sample.
0RODIFF4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3
Analog Input Indicator
Indicates which analog input is to be sampled.
0x0ROMUX2:0
263November 30, 2007
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Write-Only Register
ADC Test Mode Loopback (ADCTMLB)
Base 0x4003.8000
Offset 0x100
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
LBreserved
WOROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Loopback Mode Enable
When set, forces a loopback within the digital block to provide information
on input and unique numbering.
The 10-bit loopback data is defined as shown in the read for bits 9:0
above.
0WOLB0
November 30, 2007264
Preliminary
Analog-to-Digital Converter (ADC)
12 Universal Asynchronous Receivers/Transmitters
(UARTs)
The Stellaris®Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable,
16C550-type serial interface characteristics. The LM3S2016 controller is equipped with two UART
modules.
Each UART has the following features:
■Separate transmit and receive FIFOs
■Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■Programmable baud-rate generator allowing rates up to 3.125 Mbps
■Standard asynchronous communication bits for start, stop, and parity
■False start bit detection
■Line-break generation and detection
■Fully programmable serial interface characteristics:
–5, 6, 7, or 8 data bits
–Even, odd, stick, or no-parity bit generation/detection
–1 or 2 stop bit generation
■IrDA serial-IR (SIR) encoder/decoder providing:
–Programmable use of IrDA Serial InfraRed (SIR) or UART input/output
–Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
–Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
–Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
265November 30, 2007
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12.1 Block Diagram
Figure 12-1. UART Module Block Diagram
Receiver
Transmitter
System Clock
Control / Status
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
Baud Rate
Generator
UARTIBRD
UARTFBRD
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UART PeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTDR
TXFIFO
16x8
.
.
.
RXFIFO
16x8
.
.
.
Interrupt
UnTx
UnRx
12.2 Functional Description
Each Stellaris®UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 284). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
12.2.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
November 30, 2007266
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 12-2 on page 267 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 12-2. UART Character Frame
105-8 data bits
LSB MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
12.2.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 280) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 281). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.):
BRD = BRDI + BRDF = SysClk / (16 * Baud Rate)
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register)
can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and
adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error
detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 282), the UARTIBRD
and UARTFBRD registers form an internal 30-bit register. This internal register is only updated
when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must
be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
■UARTIBRD write, UARTFBRD write, and UARTLCRH write
■UARTFBRD write, UARTIBRD write, and UARTLCRH write
■UARTIBRD write and UARTLCRH write
■UARTFBRD write and UARTLCRH write
267November 30, 2007
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LM3S2016 Microcontroller
12.2.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit FIFO.
If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated
in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit
FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 277) is asserted as soon as
data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while
data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the
last character has been transmitted from the shift register, including the stop bits. The UART can
indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 266).
The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is
detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR)
register (see page 275). If the start bit was valid, successive data bits are sampled on every 16th
cycle of Baud16 (that is, one bit period later) according to the programmed length of the data
characters. The parity bit is then checked if parity mode was enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
12.2.4 Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream, and half-duplex
serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to
provide a digital encoded output, and decoded input to the UART. The UART signal pins can be
connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block
has two modes of operation:
■In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the
selected baud rate bit period on the output pin, while logic one levels are transmitted as a static
LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.
■In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register.
Figure 12-3 on page 269 shows the UART transmit and receive signals, with and without IrDA
modulation.
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Figure 12-3. IrDA Data Modulation
1
010 001101
Data bits
1
010 001101
Data bits
Start
bit
Start Stop
Bit period Bit period
3
16
UnTx
UnTx with IrDA
UnRx with IrDA
UnRx
Stop
bit
In both normal and low-power IrDA modes:
■During transmission, the UART data bit is used as the base for encoding
■During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
12.2.5 FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 273). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 282).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 277) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE,TXFF,RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 286). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
12.2.6 Interrupts
The UART can generate interrupts when the following conditions are observed:
■Overrun Error
■Break Error
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■Parity Error
■Framing Error
■Receive Timeout
■Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
■Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 291).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM ) register (see page 288) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS)
register (see page 290).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 292).
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data
is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or when a 1 is
written to the corresponding bit in the UARTICR register.
12.2.7 Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 284). In loopback mode,
data transmitted on UnTx is received on the UnRx input.
12.2.8 IrDA SIR block
The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the
SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR
transceiver.
The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same
time. Transmission must be stopped before data can be received. The IrDA SIR physical layer
specifies a minimum 10-ms delay between transmission and reception.
12.3 Initialization and Configuration
To use the UARTs, the peripheral clock must be enabled by setting the UART0 or UART1 bits in the
RCGC1 register.
This section discusses the steps that are required for using a UART module. For this example, the
system clock is assumed to be 20 MHz and the desired UART configuration is:
■115200 baud rate
■Data length of 8 bits
■One stop bit
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■No parity
■FIFOs disabled
■No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 267, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 280) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 281) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
12.4 Register Map
Table 12-1 on page 271 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■UART0: 0x4000.C000
■UART1: 0x4000.D000
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 284)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 12-1. UART Register Map
See
page
DescriptionResetTypeNameOffset
273UART Data0x0000.0000R/WUARTDR0x000
275UART Receive Status/Error Clear0x0000.0000R/WUARTRSR/UARTECR0x004
277UART Flag0x0000.0090ROUARTFR0x018
279UART IrDA Low-Power Register0x0000.0000R/WUARTILPR0x020
280UART Integer Baud-Rate Divisor0x0000.0000R/WUARTIBRD0x024
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See
page
DescriptionResetTypeNameOffset
281UART Fractional Baud-Rate Divisor0x0000.0000R/WUARTFBRD0x028
282UART Line Control0x0000.0000R/WUARTLCRH0x02C
284UART Control0x0000.0300R/WUARTCTL0x030
286UART Interrupt FIFO Level Select0x0000.0012R/WUARTIFLS0x034
288UART Interrupt Mask0x0000.0000R/WUARTIM0x038
290UART Raw Interrupt Status0x0000.000FROUARTRIS0x03C
291UART Masked Interrupt Status0x0000.0000ROUARTMIS0x040
292UART Interrupt Clear0x0000.0000W1CUARTICR0x044
294UART Peripheral Identification 40x0000.0000ROUARTPeriphID40xFD0
295UART Peripheral Identification 50x0000.0000ROUARTPeriphID50xFD4
296UART Peripheral Identification 60x0000.0000ROUARTPeriphID60xFD8
297UART Peripheral Identification 70x0000.0000ROUARTPeriphID70xFDC
298UART Peripheral Identification 00x0000.0011ROUARTPeriphID00xFE0
299UART Peripheral Identification 10x0000.0000ROUARTPeriphID10xFE4
300UART Peripheral Identification 20x0000.0018ROUARTPeriphID20xFE8
301UART Peripheral Identification 30x0000.0001ROUARTPeriphID30xFEC
302UART PrimeCell Identification 00x0000.000DROUARTPCellID00xFF0
303UART PrimeCell Identification 10x0000.00F0ROUARTPCellID10xFF4
304UART PrimeCell Identification 20x0000.0005ROUARTPCellID20xFF8
305UART PrimeCell Identification 30x0000.00B1ROUARTPCellID30xFFC
12.5 Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by address
offset.
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Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAFEPEBEOEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:12
UART Overrun Error
The OE values are defined as follows:
DescriptionValue
There has been no data loss due to a FIFO overrun.0
New data was received when the FIFO was full, resulting in
data loss.
1
0ROOE11
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
0ROBE10
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DescriptionResetTypeNameBit/Field
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
0ROPE9
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
0ROFE8
Data Transmitted or Received
When written, the data that is to be transmitted via the UART. When
read, the data that was received by the UART.
0R/WDATA7:0
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Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset
0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register.
If the status is read from this register, then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Read-Only Receive Status (UARTRSR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
FEPEBEOEreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:4
UART Overrun Error
When this bit is set to 1, data is received and the FIFO is already full.
This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written when
the FIFO is full, only the contents of the shift register are overwritten.
The CPU must now read the data in order to empty the FIFO.
0ROOE3
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the received data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the receive data input
goes to a 1 (marking state) and the next valid start bit is received.
0ROBE2
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DescriptionResetTypeNameBit/Field
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
0ROPE1
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
0ROFE0
Write-Only Error Clear (UARTECR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x004
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
0123456789101112131415
DATAreserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0WOreserved31:8
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
0WODATA7:0
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Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF,RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
UART Flag (UARTFR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x018
Type RO, reset 0x0000.0090
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedBUSYRXFETXFFRXFFTXFEreserved
ROROROROROROROROROROROROROROROROType
0000100100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding
register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO
is empty.
1ROTXFE7
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is full.
If the FIFO is enabled, this bit is set when the receive FIFO is full.
0RORXFF6
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding register
is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is full.
0ROTXFF5
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DescriptionResetTypeNameBit/Field
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
1RORXFE4
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
0ROBUSY3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved2:0
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Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020
The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor
value used to generate the IrLPBaud16 signal by dividing down the system clock (SysClk). All the
bits are cleared to 0 when reset.
The IrLPBaud16 internal signal is generated by dividing down the UARTCLK signal according to
the low-power divisor value written to UARTILPR. The low-power divisor value is calculated as
follows:
ILPDVSR = SysClk / FIrLPBaud16
where FIrLPBaud16 is nominally 1.8432 MHz.
IrLPBaud16 is an internal signal used for SIR pulse generation when low-power mode is used.
You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power
pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency
of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that
pulses greater than 1.4 μs are accepted as valid pulses.
Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being
generated.
UART IrDA Low-Power Register (UARTILPR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x020
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ILPDVSRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
IrDA Low-Power Divisor
This is an 8-bit low-power divisor value.
0x00R/WILPDVSR7:0
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Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD
register is ignored. When changing the UARTIBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 267
for configuration details.
UART Integer Baud-Rate Divisor (UARTIBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x024
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DIVINT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:16
Integer Baud-Rate Divisor0x0000R/WDIVINT15:0
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Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared
on reset. When changing the UARTFBRD register, the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 267
for configuration details.
UART Fractional Baud-Rate Divisor (UARTFBRD)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x028
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DIVFRACreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
Fractional Baud-Rate Divisor0x000R/WDIVFRAC5:0
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Register 7: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity,
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
UART Line Control (UARTLCRH)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x02C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
BRKPENEPSSTP2FENWLENSPSreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
UART Stick Parity Select
When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the
parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
0R/WSPS7
UART Word Length
The bits indicate the number of data bits transmitted or received in a
frame as follows:
DescriptionValue
8 bits0x3
7 bits0x2
6 bits0x1
5 bits (default)0x0
0R/WWLEN6:5
UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO
mode).
When cleared to 0, FIFOs are disabled (Character mode). The FIFOs
become 1-byte-deep holding registers.
0R/WFEN4
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DescriptionResetTypeNameBit/Field
UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a frame.
The receive logic does not check for two stop bits being received.
0R/WSTP23
UART Even Parity Select
If this bit is set to 1, even parity generation and checking is performed
during transmission and reception, which checks for an even number
of 1s in data and parity bits.
When cleared to 0, then odd parity is performed, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
0R/WEPS2
UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled; otherwise,
parity is disabled and no parity bit is added to the data frame.
0R/WPEN1
UART Send Break
If this bit is set to 1, a Low level is continually output on the UnTX output,
after completing transmission of the current character. For the proper
execution of the break command, the software must set this bit for at
least two frames (character periods). For normal use, this bit must be
cleared to 0.
0R/WBRK0
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Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x030
Type R/W, reset 0x0000.0300
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
UARTENSIRENSIRLPreservedLBETXERXEreserved
R/WR/WR/WROROROROR/WR/WR/WROROROROROROType
0000000011000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:10
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
1R/WRXE9
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled. When
the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note: To enable transmission, the UARTEN bit must also be set.
1R/WTXE8
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
0R/WLBE7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved6:3
November 30, 2007284
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Universal Asynchronous Receivers/Transmitters (UARTs)
DescriptionResetTypeNameBit/Field
UART SIR Low Power Mode
This bit selects the IrDA encoding mode. If this bit is cleared to 0,
low-level bits are transmitted as an active High pulse with a width of
3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted
with a pulse width which is 3 times the period of the IrLPBaud16 input
signal, regardless of the selected bit rate. Setting this bit uses less power,
but might reduce transmission distances. See page 279 for more
information.
0R/WSIRLP2
UART SIR Enable
If this bit is set to 1, the IrDA SIR block is enabled, and the UART will
transmit and receive data using SIR protocol.
0R/WSIREN1
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is disabled
in the middle of transmission or reception, it completes the current
character before stopping.
0R/WUARTEN0
285November 30, 2007
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LM3S2016 Microcontroller
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x034
Type R/W, reset 0x0000.0012
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TXIFLSELRXIFLSELreserved
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
0100100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
DescriptionValue
RX FIFO ≥ 1/8 full0x0
RX FIFO ≥ ¼ full0x1
RX FIFO ≥ ½ full (default)0x2
RX FIFO ≥ ¾ full0x3
RX FIFO ≥ 7/8 full0x4
Reserved0x5-0x7
0x2R/WRXIFLSEL5:3
November 30, 2007286
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Universal Asynchronous Receivers/Transmitters (UARTs)
DescriptionResetTypeNameBit/Field
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
DescriptionValue
TX FIFO ≤ 1/8 full0x0
TX FIFO ≤ ¼ full0x1
TX FIFO ≤ ½ full (default)0x2
TX FIFO ≤ ¾ full0x3
TX FIFO ≤ 7/8 full0x4
Reserved0x5-0x7
0x2R/WTXIFLSEL2:0
287November 30, 2007
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LM3S2016 Microcontroller
Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x038
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedRXIMTXIMRTIMFEIMPEIMBEIMOEIMreserved
ROROROROR/WR/WR/WR/WR/WR/WR/WROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
0R/WOEIM10
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
0R/WBEIM9
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
0R/WPEIM8
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
0R/WFEIM7
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
0R/WRTIM6
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
0R/WTXIM5
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DescriptionResetTypeNameBit/Field
UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller.
0R/WRXIM4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved3:0
289November 30, 2007
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LM3S2016 Microcontroller
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x03C
Type RO, reset 0x0000.000F
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedRXRISTXRISRTRISFERISPERISBERISOERISreserved
ROROROROROROROROROROROROROROROROType
1111000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0ROOERIS10
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0ROBERIS9
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0ROPERIS8
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0ROFERIS7
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0RORTRIS6
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0ROTXRIS5
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
0RORXRIS4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0xFROreserved3:0
November 30, 2007290
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
UART Masked Interrupt Status (UARTMIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x040
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedRXMISTXMISRTMISFEMISPEMISBEMISOEMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0ROOEMIS10
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0ROBEMIS9
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0ROPEMIS8
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0ROFEMIS7
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0RORTMIS6
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0ROTXMIS5
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0RORXMIS4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:0
291November 30, 2007
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LM3S2016 Microcontroller
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x044
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedRXICTXICRTICFEICPEICBEICOEICreserved
ROROROROW1CW1CW1CW1CW1CW1CW1CROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:11
Overrun Error Interrupt Clear
The OEIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1COEIC10
Break Error Interrupt Clear
The BEIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CBEIC9
Parity Error Interrupt Clear
The PEIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CPEIC8
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Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
DescriptionResetTypeNameBit/Field
Framing Error Interrupt Clear
The FEIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CFEIC7
Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CRTIC6
Transmit Interrupt Clear
The TXIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CTXIC5
Receive Interrupt Clear
The RXIC values are defined as follows:
DescriptionValue
No effect on the interrupt.0
Clears interrupt.1
0W1CRXIC4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved3:0
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LM3S2016 Microcontroller
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 4 (UARTPeriphID4)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFD0
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID4reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
0x0000ROPID47:0
November 30, 2007294
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 5 (UARTPeriphID5)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFD4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID5reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
0x0000ROPID57:0
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LM3S2016 Microcontroller
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 6 (UARTPeriphID6)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFD8
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID6reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
0x0000ROPID67:0
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Universal Asynchronous Receivers/Transmitters (UARTs)
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 7 (UARTPeriphID7)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFDC
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID7reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
0x0000ROPID77:0
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LM3S2016 Microcontroller
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 0 (UARTPeriphID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFE0
Type RO, reset 0x0000.0011
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID0reserved
ROROROROROROROROROROROROROROROROType
1000100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
0x11ROPID07:0
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Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 1 (UARTPeriphID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFE4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID1reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
0x00ROPID17:0
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LM3S2016 Microcontroller
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 2 (UARTPeriphID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFE8
Type RO, reset 0x0000.0018
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID2reserved
ROROROROROROROROROROROROROROROROType
0001100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
0x18ROPID27:0
November 30, 2007300
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
UART Peripheral Identification 3 (UARTPeriphID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFEC
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID3reserved
ROROROROROROROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
0x01ROPID37:0
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LM3S2016 Microcontroller
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 0 (UARTPCellID0)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFF0
Type RO, reset 0x0000.000D
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID0reserved
ROROROROROROROROROROROROROROROROType
1011000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification system.
0x0DROCID07:0
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Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 1 (UARTPCellID1)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFF4
Type RO, reset 0x0000.00F0
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID1reserved
ROROROROROROROROROROROROROROROROType
0000111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification system.
0xF0ROCID17:0
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LM3S2016 Microcontroller
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 2 (UARTPCellID2)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFF8
Type RO, reset 0x0000.0005
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID2reserved
ROROROROROROROROROROROROROROROROType
1010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification system.
0x05ROCID27:0
November 30, 2007304
Preliminary
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset
values.
UART PrimeCell Identification 3 (UARTPCellID3)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0xFFC
Type RO, reset 0x0000.00B1
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID3reserved
ROROROROROROROROROROROROROROROROType
1000110100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification system.
0xB1ROCID37:0
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13 Synchronous Serial Interface (SSI)
The Stellaris®Synchronous Serial Interface (SSI) is a master or slave interface for synchronous
serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas
Instruments synchronous serial interfaces.
The Stellaris®SSI module has the following features:
■Master or slave operation
■Programmable clock bit rate and prescale
■Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
■Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■Programmable data frame size from 4 to 16 bits
■Internal loopback test mode for diagnostic/debug testing
13.1 Block Diagram
Figure 13-1. SSI Module Block Diagram
Transmit/
Receive
Logic
Clock
Prescaler
SSICPSR
Control / Status
SSICR0
SSICR1
SSISR
Interrupt Control
SSIIM
SSIMIS
SSIRIS
SSIICR
SSIDR
TxFIFO
8 x 16
.
.
.
RxFIFO
8 x 16
.
.
.
System Clock
SSITx
SSIRx
SSIClk
SSIFss
Interrupt
Identification Registers
SSIPCellID0 SSIPeriphID0 SSIPeriphID4
SSIPCellID1 SSIPeriphID1 SSIPeriphID5
SSIPCellID2 SSIPeriphID2 SSIPeriphID6
SSIPCellID3 SSIPeriphID3 SSIPeriphID7
13.2 Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
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internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
13.2.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the 50-MHz input clock. The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 325). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 318).
The frequency of the output clock SSIClk is defined by:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note that although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be
able to operate at that speed. For master mode, the system clock must be at least two times faster
than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 438 to view SSI timing parameters.
13.2.2 FIFO Operation
13.2.2.1 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 322), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
13.2.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
13.2.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
■Transmit FIFO service
■Receive FIFO service
■Receive FIFO time-out
■Receive FIFO overrun
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
can only generate a single interrupt request to the controller at any given time. You can mask each
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of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask
(SSIIM) register (see page 326). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status
(SSIMIS) registers (see page 328 and page 329, respectively).
13.2.4 Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
■Texas Instruments synchronous serial
■Freescale SPI
■MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame format,
both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and
latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
13.2.4.1 Texas Instruments Synchronous Serial Frame Format
Figure 13-2 on page 308 shows the Texas Instruments synchronous serial frame format for a single
transmitted frame.
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
4 to 16 bits
SSIFss
SSITx/SSIRx MSB LSB
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In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit
FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB
of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data
is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive
FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 13-3 on page 309 shows the Texas Instruments synchronous serial frame format when
back-to-back frames are transmitted.
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer)
MSB
LSB
4 to 16 bits
SSIClk
SSIFss
SSITx/SSIRx
13.2.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk
pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not
being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition
before the first data capture edge. When the SPH phase control bit is Low, data is captured on the
first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition.
13.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 13-4 on page 310 and Figure 13-5 on page 310.
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Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
4 to 16 bits
SSIClk
SSIFss
SSIRx Q
SSITx MSB
MSB
LSB
LSB
Note: Q is undefined.
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
SSIClk
SSIFss
SSIRx LSB
SSITx MSB LSB
4 to 16 bits
LSB MSB
MSB
MSB
LSB
In this configuration, during idle periods:
■SSIClk is forced Low
■SSIFss is forced High
■The transmit data line SSITx is arbitrarily forced Low
■When the SSI is configured as a master, it enables the SSIClk pad
■When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto
the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further half
SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
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13.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure
13-6 on page 311, which covers both single and continuous transfers.
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
QMSB
LSB
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■SSIClk is forced Low
■SSIFss is forced High
■The transmit data line SSITx is arbitrarily forced Low
■When the SSI is configured as a master, it enables the SSIClk pad
■When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After
a further one half SSIClk period, both master and slave valid data is enabled onto their respective
transmission lines. At the same time, the SSIClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned
to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
13.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 13-7 on page 312 and Figure 13-8 on page 312.
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Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
QMSB
MSB LSB
LSB
Note: Q is undefined.
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSITx/SSIRx MSB LSB
4 to 16 bits
LSB MSB
In this configuration, during idle periods:
■SSIClk is forced High
■SSIFss is forced High
■The transmit data line SSITx is arbitrarily forced Low
■When the SSI is configured as a master, it enables the SSIClk pad
■When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be immediately
transferred onto the SSIRx line of the master. The master SSITx output pad is enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer. This is because the slave select pin freezes the data in its
serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore,
the master device must raise the SSIFss pin of the slave device between each data transfer to
enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin
is returned to its idle state one SSIClk period after the last bit has been captured.
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13.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
13-9 on page 313, which covers both single and continuous transfers.
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1
4 to 16 bits
SSIClk
SSIFss
SSIRx
SSITx
Q Q
MSB
MSB
LSB
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■SSIClk is forced High
■SSIFss is forced High
■The transmit data line SSITx is arbitrarily forced Low
■When the SSI is configured as a master, it enables the SSIClk pad
■When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words
and termination is the same as that of the single word transfer.
13.2.4.7 MICROWIRE Frame Format
Figure 13-10 on page 314 shows the MICROWIRE frame format, again for a single frame. Figure
13-11 on page 315 shows the same format when back-to-back frames are transmitted.
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Figure 13-10. MICROWIRE Frame Format (Single Frame)
SSIClk
SSIFss
LSBMSB
SSIRx 4 to 16 bits
output data
0
SSITx MSB LSB
8-bit control
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of
full-duplex, using a master-slave message passing technique. Each serial transmission begins with
an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip
slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has
been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the
total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
■SSIClk is forced Low
■SSIFss is forced High
■The transmit data line SSITx is arbitrarily forced Low
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss
causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial
shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the
SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains
tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven
onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising
edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one
clock period after the last bit has been latched in the receive serial shifter, which causes the data
to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer.
However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs
back-to-back. The control byte of the next frame follows directly after the LSB of the received data
from the current frame. Each of the received values is transferred from the receive shifter on the
falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
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Figure 13-11. MICROWIRE Frame Format (Continuous Transfer)
8-bit control
SSIClk
SSIFss
LSBMSB
SSIRx 4 to 16 bits
output data
0
SSITx MSB LSBLSB
MSB
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk.
Figure 13-12 on page 315 illustrates these setup and hold time requirements. With respect to the
SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss
must have a setup of at least two times the period of SSIClk on which the SSI operates. With
respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one
SSIClk period.
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
tSetup=(2*tSSIClk
)
tHold=tSSIClk
13.3 Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
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4. Write the SSICR0 register with the following configuration:
■Serial clock rate (SCR)
■Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
■Master operation
■Freescale SPI mode (SPO=1, SPH=1)
■1 Mbps bit rate
■8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
13.4 Register Map
Table 13-1 on page 316 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■SSI0: 0x4000.8000
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 13-1. SSI Register Map
See
page
DescriptionResetTypeNameOffset
318SSI Control 00x0000.0000R/WSSICR00x000
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See
page
DescriptionResetTypeNameOffset
320SSI Control 10x0000.0000R/WSSICR10x004
322SSI Data0x0000.0000R/WSSIDR0x008
323SSI Status0x0000.0003ROSSISR0x00C
325SSI Clock Prescale0x0000.0000R/WSSICPSR0x010
326SSI Interrupt Mask0x0000.0000R/WSSIIM0x014
328SSI Raw Interrupt Status0x0000.0008ROSSIRIS0x018
329SSI Masked Interrupt Status0x0000.0000ROSSIMIS0x01C
330SSI Interrupt Clear0x0000.0000W1CSSIICR0x020
331SSI Peripheral Identification 40x0000.0000ROSSIPeriphID40xFD0
332SSI Peripheral Identification 50x0000.0000ROSSIPeriphID50xFD4
333SSI Peripheral Identification 60x0000.0000ROSSIPeriphID60xFD8
334SSI Peripheral Identification 70x0000.0000ROSSIPeriphID70xFDC
335SSI Peripheral Identification 00x0000.0022ROSSIPeriphID00xFE0
336SSI Peripheral Identification 10x0000.0000ROSSIPeriphID10xFE4
337SSI Peripheral Identification 20x0000.0018ROSSIPeriphID20xFE8
338SSI Peripheral Identification 30x0000.0001ROSSIPeriphID30xFEC
339SSI PrimeCell Identification 00x0000.000DROSSIPCellID00xFF0
340SSI PrimeCell Identification 10x0000.00F0ROSSIPCellID10xFF4
341SSI PrimeCell Identification 20x0000.0005ROSSIPCellID20xFF8
342SSI PrimeCell Identification 30x0000.00B1ROSSIPCellID30xFFC
13.5 Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
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Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DSSFRFSPOSPHSCR
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:16
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
0x0000R/WSCR15:8
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
0R/WSPH7
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
0R/WSPO6
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DescriptionResetTypeNameBit/Field
SSI Frame Format Select
The FRF values are defined as follows:
Frame FormatValue
Freescale SPI Frame Format0x0
Texas Intruments Synchronous Serial Frame Format0x1
MICROWIRE Frame Format0x2
Reserved0x3
0x0R/WFRF5:4
SSI Data Size Select
The DSS values are defined as follows:
Data SizeValue
Reserved0x0-0x2
4-bit data0x3
5-bit data0x4
6-bit data0x5
7-bit data0x6
8-bit data0x7
9-bit data0x8
10-bit data0x9
11-bit data0xA
12-bit data0xB
13-bit data0xC
14-bit data0xD
15-bit data0xE
16-bit data0xF
0x00R/WDSS3:0
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Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
Offset 0x004
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
LBMSSEMSSODreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In multiple-slave
systems, it is possible for the SSI master to broadcast a message to all
slaves in the system while ensuring that only one slave drives data onto
the serial output line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD bit can be
configured so that the SSI slave does not drive the SSITx pin.
The SOD values are defined as follows:
DescriptionValue
SSI can drive SSITx output in Slave Output mode.0
SSI must not drive the SSITx output in Slave mode.1
0R/WSOD3
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
SSI is disabled (SSE=0).
The MS values are defined as follows:
DescriptionValue
Device configured as a master.0
Device configured as a slave.1
0R/WMS2
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Synchronous Serial Interface (SSI)
DescriptionResetTypeNameBit/Field
SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
The SSE values are defined as follows:
DescriptionValue
SSI operation disabled.0
SSI operation enabled.1
Note: This bit must be set to 0 before any control registers
are reprogrammed.
0R/WSSE1
SSI Loopback Mode
Setting this bit enables Loopback Test mode.
The LBM values are defined as follows:
DescriptionValue
Normal serial port operation enabled.0
Output of the transmit serial shift register is connected internally
to the input of the receive serial shift register.
1
0R/WLBM0
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Register 3: SSI Data (SSIDR), offset 0x008
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed
to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed
bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer.
The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1
register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI.
SSI Data (SSIDR)
SSI0 base: 0x4000.8000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation writes the
transmit FIFO.
Software must right-justify data when the SSI is programmed for a data
size that is less than 16 bits. Unused bits at the top are ignored by the
transmit logic. The receive logic automatically right-justifies the data.
0x0000R/WDATA15:0
November 30, 2007322
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Synchronous Serial Interface (SSI)
Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
Offset 0x00C
Type RO, reset 0x0000.0003
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TFETNFRNERFFBSYreserved
R0ROROROROROROROROROROROROROROROType
1100000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:5
SSI Busy Bit
The BSY values are defined as follows:
DescriptionValue
SSI is idle.0
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
1
0ROBSY4
SSI Receive FIFO Full
The RFF values are defined as follows:
DescriptionValue
Receive FIFO is not full.0
Receive FIFO is full.1
0RORFF3
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
DescriptionValue
Receive FIFO is empty.0
Receive FIFO is not empty.1
0RORNE2
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
DescriptionValue
Transmit FIFO is full.0
Transmit FIFO is not full.1
1ROTNF1
323November 30, 2007
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LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
SSI Transmit FIFO Empty
The TFE values are defined as follows:
DescriptionValue
Transmit FIFO is not empty.0
Transmit FIFO is empty.1
1R0TFE0
November 30, 2007324
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Synchronous Serial Interface (SSI)
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CPSDVSRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
0x00R/WCPSDVSR7:0
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Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORIMRTIMRXIMTXIMreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
DescriptionValue
TX FIFO half-full or less condition interrupt is masked.0
TX FIFO half-full or less condition interrupt is not masked.1
0R/WTXIM3
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
DescriptionValue
RX FIFO half-full or more condition interrupt is masked.0
RX FIFO half-full or more condition interrupt is not masked.1
0R/WRXIM2
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
DescriptionValue
RX FIFO time-out interrupt is masked.0
RX FIFO time-out interrupt is not masked.1
0R/WRTIM1
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Synchronous Serial Interface (SSI)
DescriptionResetTypeNameBit/Field
SSI Receive Overrun Interrupt Mask
The RORIM values are defined as follows:
DescriptionValue
RX FIFO overrun interrupt is masked.0
RX FIFO overrun interrupt is not masked.1
0R/WRORIM0
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Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
Offset 0x018
Type RO, reset 0x0000.0008
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORRISRTRISRXRISTXRISreserved
ROROROROROROROROROROROROROROROROType
0001000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
1ROTXRIS3
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
0RORXRIS2
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
0RORTRIS1
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0RORORRIS0
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Synchronous Serial Interface (SSI)
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
SSI Masked Interrupt Status (SSIMIS)
SSI0 base: 0x4000.8000
Offset 0x01C
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORMISRTMISRXMISTXMISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:4
SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
0ROTXMIS3
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
0RORXMIS2
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
0RORTMIS1
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
0RORORMIS0
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Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
Offset 0x020
Type W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORICRTICreserved
W1CW1CROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
DescriptionValue
No effect on interrupt.0
Clears interrupt.1
0W1CRTIC1
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
DescriptionValue
No effect on interrupt.0
Clears interrupt.1
0W1CRORIC0
November 30, 2007330
Preliminary
Synchronous Serial Interface (SSI)
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 4 (SSIPeriphID4)
SSI0 base: 0x4000.8000
Offset 0xFD0
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID4reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
0x00ROPID47:0
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Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 5 (SSIPeriphID5)
SSI0 base: 0x4000.8000
Offset 0xFD4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID5reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register[15:8]
Can be used by software to identify the presence of this peripheral.
0x00ROPID57:0
November 30, 2007332
Preliminary
Synchronous Serial Interface (SSI)
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 6 (SSIPeriphID6)
SSI0 base: 0x4000.8000
Offset 0xFD8
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID6reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register[23:16]
Can be used by software to identify the presence of this peripheral.
0x00ROPID67:0
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LM3S2016 Microcontroller
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 7 (SSIPeriphID7)
SSI0 base: 0x4000.8000
Offset 0xFDC
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID7reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register[31:24]
Can be used by software to identify the presence of this peripheral.
0x00ROPID77:0
November 30, 2007334
Preliminary
Synchronous Serial Interface (SSI)
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 0 (SSIPeriphID0)
SSI0 base: 0x4000.8000
Offset 0xFE0
Type RO, reset 0x0000.0022
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID0reserved
ROROROROROROROROROROROROROROROROType
0100010000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:8
SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this peripheral.
0x22ROPID07:0
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LM3S2016 Microcontroller
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 1 (SSIPeriphID1)
SSI0 base: 0x4000.8000
Offset 0xFE4
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID1reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
0x00ROPID17:0
November 30, 2007336
Preliminary
Synchronous Serial Interface (SSI)
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 2 (SSIPeriphID2)
SSI0 base: 0x4000.8000
Offset 0xFE8
Type RO, reset 0x0000.0018
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID2reserved
ROROROROROROROROROROROROROROROROType
0001100000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
0x18ROPID27:0
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LM3S2016 Microcontroller
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI Peripheral Identification 3 (SSIPeriphID3)
SSI0 base: 0x4000.8000
Offset 0xFEC
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PID3reserved
ROROROROROROROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
0x01ROPID37:0
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Preliminary
Synchronous Serial Interface (SSI)
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 0 (SSIPCellID0)
SSI0 base: 0x4000.8000
Offset 0xFF0
Type RO, reset 0x0000.000D
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID0reserved
ROROROROROROROROROROROROROROROROType
1011000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
0x0DROCID07:0
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Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 1 (SSIPCellID1)
SSI0 base: 0x4000.8000
Offset 0xFF4
Type RO, reset 0x0000.00F0
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID1reserved
ROROROROROROROROROROROROROROROROType
0000111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
0xF0ROCID17:0
November 30, 2007340
Preliminary
Synchronous Serial Interface (SSI)
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 2 (SSIPCellID2)
SSI0 base: 0x4000.8000
Offset 0xFF8
Type RO, reset 0x0000.0005
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID2reserved
ROROROROROROROROROROROROROROROROType
1010000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
0x05ROCID27:0
341November 30, 2007
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LM3S2016 Microcontroller
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
SSI PrimeCell Identification 3 (SSIPCellID3)
SSI0 base: 0x4000.8000
Offset 0xFFC
Type RO, reset 0x0000.00B1
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
CID3reserved
ROROROROROROROROROROROROROROROROType
1000110100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SSI PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
0xB1ROCID37:0
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Synchronous Serial Interface (SSI)
14 Inter-Integrated Circuit (I2C) Interface
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as
serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C
bus may also be used for system testing and diagnostic purposes in product development and
manufacture. The LM3S2016 microcontroller includes one I2C module, providing the ability to interact
(both send and receive) with other I2C devices on the bus.
Devices on the I2C bus can be designated as either a master or a slave. The Stellaris®I2C module
supports both sending and receiving data as either a master or a slave, and also supports the
simultaneous operation as both a master and a slave. There are a total of four I2C modes: Master
Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris®I2C module can
operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I2C master and slave can generate interrupts; the I2C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error) and the I2C slave generates
interrupts when data has been sent or requested by a master.
14.1 Block Diagram
Figure 14-1. I2C Block Diagram
I2C I/O Select
I2C Master Core
Interrupt
I2C Slave Core
I2CSCL
I2CSDA
I2CSDA
I2CSCL
I2CSDA
I2CSCL
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CSICRI2CMMIS
I2C Control
14.2 Functional Description
The I2C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I2C bus configuration is shown in Figure 14-2 on page 344.
See “I2C” on page 437 for I2C timing diagrams.
343November 30, 2007
Preliminary
LM3S2016 Microcontroller
Figure 14-2. I2C Bus Configuration
RPUP
StellarisTM
I2CSCL I2CSDA
RPUP
3rd Party Device
with I2C Interface
SCL SDA
I2C Bus
SCL
SDA
3rd Party Device
with I2C Interface
SCL SDA
14.2.1 I2C Bus Functional Overview
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris®
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are high.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 344) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
14.2.1.1 START and STOP Conditions
The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP.
A high-to-low transition on the SDA line while the SCL is high is defined as a START condition, and
a low-to-high transition on the SDA line while SCL is high is defined as a STOP condition. The bus
is considered busy after a START condition and free after a STOP condition. See Figure
14-3 on page 344.
Figure 14-3. START and STOP Conditions
START
condition
SD
A
SCL STOP
condition
SD
A
SCL
14.2.1.2 Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 14-4 on page 345. After the START condition, a
slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction
bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates
a request for data (receive). A data transfer is always terminated by a STOP condition generated
by the master, however, a master can initiate communications with another device on the bus by
generating a repeated START condition and addressing another slave without first generating a
STOP condition. Various combinations of receive/send formats are then possible within a single
transfer.
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Figure 14-4. Complete Data Transfer with a 7-Bit Address
DataSlave address
ACKLSBMSBACKR/SLSBMSB
SD
A
SCL 1 2 7 8 9 1 2 7 8 9
The first seven bits of the first byte make up the slave address (see Figure 14-5 on page 345). The
eighth bit determines the direction of the message. A zero in the R/S position of the first byte means
that the master will write (send) data to the selected slave, and a one in this position means that
the master will receive data from the slave.
Figure 14-5. R/S Bit in First Byte
R/S
LSB
Slave address
MSB
14.2.1.3 Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is low (see Figure 14-6 on page 345).
Figure 14-6. Data Validity During Bit Transfer on the I2C Bus
Change
of data
allowed
Dataline
stable
SDA
SCL
14.2.1.4 Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data
validity requirements described in “Data Validity” on page 345.
When a slave receiver does not acknowledge the slave address, SDA must be left high by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Since the master controls the number of bytes in the transfer, it signals the end
of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave
transmitter must then release SDA to allow the master to generate the STOP or a repeated START
condition.
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14.2.1.5 Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the
competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low)
will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
14.2.2 Available Speed Modes
The I2C clock rate is determined by the parameters: CLK_PRD,TIMER_PRD,SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see
page 363).
The I2C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 14-1 on page 346 gives examples of timer period, system clock, and speed mode (Standard
or Fast).
Table 14-1. Examples of I2C Master Timer Period versus Speed Mode
Fast ModeTimer PeriodStandard ModeTimer PeriodSystem Clock
--100 Kbps0x014 Mhz
--100 Kbps0x026 Mhz
312 Kbps0x0189 Kbps0x0612.5 Mhz
278 Kbps0x0293 Kbps0x0816.7 Mhz
333 Kbps0x02100 Kbps0x0920 Mhz
312 Kbps0x0396.2 Kbps0x0C25 Mhz
330 Kbps0x0497.1 Kbps0x1033Mhz
400 Kbps0x04100 Kbps0x1340Mhz
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Fast ModeTimer PeriodStandard ModeTimer PeriodSystem Clock
357 Kbps0x06100 Kbps0x1850Mhz
14.2.3 Interrupts
The I2C can generate interrupts when the following conditions are observed:
■Master transaction completed
■Master transaction error
■Slave transaction received
■Slave transaction requested
There is a separate interrupt signal for the I2C master and I2C modules. While both modules can
generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
14.2.3.1 I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or
receive), or when an error occurs during a transaction. To enable the I2C master interrupt, software
must write a '1' to the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition
is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to
verify that an error didn't occur during the last transaction. An error condition is asserted if the last
transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of
the bus due to a lost arbitration round with another master. If an error is not detected, the application
can proceed with the transfer. The interrupt is cleared by writing a '1' to the I2C Master Interrupt
Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Master Raw Interrupt Status (I2CMRIS) register.
14.2.3.2 I2C Slave Interrupts
The slave module generates interrupts as it receives requests from an I2C master. To enable the
I2C slave interrupt, write a '1' to the I2C Slave Interrupt Mask (I2CSIMR) register. Software
determines whether the module should write (transmit) or read (receive) data from the I2C Slave
Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status
(I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received,
the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a '1' to the I2C Slave
Interrupt Clear (I2CSICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I2C Slave Raw Interrupt Status (I2CSRIS) register.
14.2.4 Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This
is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
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14.2.5 Command Sequence Flow Charts
This section details the steps required to perform the various I2C transfer types in both master and
slave mode.
14.2.5.1 I2C Master Command Sequences
The figures that follow show the command sequences available for the I2C master.
Figure 14-7. Master Single SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
Sequence
may be
omitted in a
Single Master
system
BUSBSY bit=0?
NO
Write ---0-111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
YES
NO
NO
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Figure 14-8. Master Single RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
Sequence may be
omitted in a Single
Master system
BUSBSY bit=0?
NO
Write ---00111 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
Error Service
Idle
NO
NO
Read data from
I2CMDR
YES
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Figure 14-9. Master Burst SEND
Idle
Write Slave
Address to
I2CMSA
Write data to
I2CMDR
Read I2CMCS
BUSBSY bit=0?
YES
Write ---0-011 to
I2CMCS
NO
Read I2CMCS
BUSY bit=0?
YES
ERROR bit=0?
YES
ARBLST bit=1?
Write data to
I2CMDR
Write ---0-100 to
I2CMCS
Index=n?
NO
Error Service
Idle
YES
Write ---0-001 to
I2CMCS
Write ---0-101 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0?
ERROR bit=0?
YES
NO
Idle
YES
Error Service NO
NO
NO
NO
Sequence
may be
omitted in a
Single Master
system
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Figure 14-10. Master Burst RECEIVE
Idle
Write Slave
Address to
I2CMSA
Read I2CMCS
BUSBSY bit=0?
NO
Write ---01011 to
I2CMCS
YES
Read I2CMCS
BUSY bit=0? NO
ERROR bit=0?
YES
ARBLST bit=1?
Write ---0-100 to
I2CMCS
NO
Error Service
YES
Idle
Read data from
I2CMDR
Index=m-1?
Write ---00101 to
I2CMCS
YES
Idle
Read data from
I2CMDR
Error Service
ERROR bit=0?
YES
Write ---01001 to
I2CMCS
Read I2CMCS
BUSY bit=0? NO
YES
Sequence
may be
omitted in a
Single Master
system
NO
NO
NO
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Figure 14-11. Master Burst RECEIVE after Burst SEND
Idle
Master operates in
Master Transmit mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---01011 to
I2CMCS
Master operates in
Master Receive mode
Idle
Repeated START
condition is generated
with changing data
direction
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Figure 14-12. Master Burst SEND after Burst RECEIVE
Idle
Master operates in
Master Receive mode
STOP condition is not
generated
Write Slave
Address to
I2CMSA
Write ---0-011 to
I2CMCS
Master operates in
Master Transmit mode
Idle
Repeated START
condition is generated
with changing data
direction
14.2.5.2 I2C Slave Command Sequences
Figure 14-13 on page 354 presents the command sequence available for the I2C slave.
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Figure 14-13. Slave Command Sequence
Idle
Write OWN Slave
Address to
I2CSOAR
Write -------1 to
I2CSCSR
Read I2CSCSR
RREQ bit=1?
Read data from
I2CSDR
YES
TREQ bit=1? NO
Write data to
I2CSDR
YES
NO
FBR is
also valid
14.3 Initialization and Configuration
The following example shows how to configure the I2C module to send a single byte as a master.
This assumes the system clock is 20 MHz.
1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System
Control module.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control
module.
3. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation.
4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020.
5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct
value. The value written to the I2CMTPR register represents the number of system clock periods
in one SCL clock period. The TPR value is determined by the following equation:
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TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1;
TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1;
TPR = 9
Write the I2CMTPR register with the value of 0x0000.0009.
6. Specify the slave address of the master and that the next operation will be a Send by writing
the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B.
7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired
data.
8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with
a value of 0x0000.0007 (STOP, START, RUN).
9. Wait until the transmission completes by polling the I2CMCS register’s BUSBSY bit until it has
been cleared.
14.4 I2C Register Map
Table 14-2 on page 355 lists the I2C registers. All addresses given are relative to the I2C base
addresses for the master and slave:
■I2C Master 0: 0x4002.0000
■I2C Slave 0: 0x4002.0800
Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map
See
page
DescriptionResetTypeNameOffset
I2C Master
357I2C Master Slave Address0x0000.0000R/WI2CMSA0x000
358I2C Master Control/Status0x0000.0000R/WI2CMCS0x004
362I2C Master Data0x0000.0000R/WI2CMDR0x008
363I2C Master Timer Period0x0000.0001R/WI2CMTPR0x00C
364I2C Master Interrupt Mask0x0000.0000R/WI2CMIMR0x010
365I2C Master Raw Interrupt Status0x0000.0000ROI2CMRIS0x014
366I2C Master Masked Interrupt Status0x0000.0000ROI2CMMIS0x018
367I2C Master Interrupt Clear0x0000.0000WOI2CMICR0x01C
368I2C Master Configuration0x0000.0000R/WI2CMCR0x020
I2C Slave
370I2C Slave Own Address0x0000.0000R/WI2CSOAR0x000
371I2C Slave Control/Status0x0000.0000ROI2CSCSR0x004
373I2C Slave Data0x0000.0000R/WI2CSDR0x008
374I2C Slave Interrupt Mask0x0000.0000R/WI2CSIMR0x00C
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See
page
DescriptionResetTypeNameOffset
375I2C Slave Raw Interrupt Status0x0000.0000ROI2CSRIS0x010
376I2C Slave Masked Interrupt Status0x0000.0000ROI2CSMIS0x014
377I2C Slave Interrupt Clear0x0000.0000WOI2CSICR0x018
14.5 Register Descriptions (I2C Master)
The remainder of this section lists and describes the I2C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 369.
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Register 1: I2C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
I2C Master Slave Address (I2CMSA)
I2C Master 0 base: 0x4002.0000
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R/SSAreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
I2C Slave Address
This field specifies bits A6 through A0 of the slave address.
0R/WSA7:1
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).
DescriptionValue
Send.0
Receive.1
0R/WR/S0
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Register 2: I2C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I2C bus
controller.
The control register consists of four bits: the RUN,START,STOP, and ACK bits. The START bit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I2C bus controller requires no further data to be sent
from the slave transmitter.
Read-Only Status Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
BUSYERRORADRACKDATACKARBLSTIDLEBUSBSYreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:7
Bus Busy
This bit specifies the state of the I2C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
0ROBUSBSY6
I2C Idle
This bit specifies the I2C controller state. If set, the controller is idle;
otherwise the controller is not idle.
0ROIDLE5
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
0ROARBLST4
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DescriptionResetTypeNameBit/Field
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
0RODATACK3
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
0ROADRACK2
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged, the
transmit data not being acknowledged, or because the controller lost
arbitration.
0ROERROR1
I2C Busy
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
0ROBUSY0
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
0123456789101112131415
RUNSTARTSTOPACKreserved
WOWOWOWOWOWOWOWOWOWOWOWOWOWOWOWOType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00WOreserved31:4
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 14-3 on page 360.
0WOACK3
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 14-3 on page 360.
0WOSTOP2
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DescriptionResetTypeNameBit/Field
Generate START
When set, causes the generation of a START or repeated START
condition. See field decoding in Table 14-3 on page 360.
0WOSTART1
I2C Master Enable
When set, allows the master to send or receive data. See field decoding
in Table 14-3 on page 360.
0WORUN0
Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3)
DescriptionI2CMCS[3:0]I2CMSA[0]Current
State RUNSTARTSTOPACKR/S
START condition followed by SEND (master goes to the
Master Transmit state).
110Xa
0Idle
START condition followed by a SEND and STOP
condition (master remains in Idle state).
111X0
START condition followed by RECEIVE operation with
negative ACK (master goes to the Master Receive state).
11001
START condition followed by RECEIVE and STOP
condition (master remains in Idle state).
11101
START condition followed by RECEIVE (master goes to
the Master Receive state).
11011
Illegal.11111
NOP.All other combinations not listed are non-operations.
SEND operation (master remains in Master Transmit
state).
100XXMaster
Transmit
STOP condition (master goes to Idle state).001XX
SEND followed by STOP condition (master goes to Idle
state).
101XX
Repeated START condition followed by a SEND (master
remains in Master Transmit state).
110X0
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
111X0
Repeated START condition followed by a RECEIVE
operation with a negative ACK (master goes to Master
Receive state).
11001
Repeated START condition followed by a SEND and
STOP condition (master goes to Idle state).
11101
Repeated START condition followed by RECEIVE (master
goes to Master Receive state).
11011
Illegal.11111
NOP.All other combinations not listed are non-operations.
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DescriptionI2CMCS[3:0]I2CMSA[0]Current
State RUNSTARTSTOPACKR/S
RECEIVE operation with negative ACK (master remains
in Master Receive state).
1000XMaster
Receive
STOP condition (master goes to Idle state).b
001XX
RECEIVE followed by STOP condition (master goes to
Idle state).
1010X
RECEIVE operation (master remains in Master Receive
state).
1001X
Illegal.1011X
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
11001
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
11101
Repeated START condition followed by RECEIVE (master
remains in Master Receive state).
11011
Repeated START condition followed by SEND (master
goes to Master Transmit state).
110X0
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
111X0
NOP.All other combinations not listed are non-operations.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
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Register 3: I2C Master Data (I2CMDR), offset 0x008
This register contains the data to be transmitted when in the Master Transmit state, and the data
received when in the Master Receive state.
I2C Master Data (I2CMDR)
I2C Master 0 base: 0x4002.0000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Data Transferred
Data transferred during transaction.
0x00R/WDATA7:0
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Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock.
I2C Master Timer Period (I2CMTPR)
I2C Master 0 base: 0x4002.0000
Offset 0x00C
Type R/W, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TPRreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I2C clock).
TPR is the Timer Period register value (range of 1 to 255).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
0x1R/WTPR7:0
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Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Master Interrupt Mask (I2CMIMR)
I2C Master 0 base: 0x4002.0000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IMreserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
0R/WIM0
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Inter-Integrated Circuit (I2C) Interface
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
This register specifies whether an interrupt is pending.
I2C Master Raw Interrupt Status (I2CMRIS)
I2C Master 0 base: 0x4002.0000
Offset 0x014
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
master block. If set, an interrupt is pending; otherwise, an interrupt is
not pending.
0RORIS0
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Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018
This register specifies whether an interrupt was signaled.
I2C Master Masked Interrupt Status (I2CMMIS)
I2C Master 0 base: 0x4002.0000
Offset 0x018
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C master
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
0ROMIS0
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Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C
This register clears the raw interrupt.
I2C Master Interrupt Clear (I2CMICR)
I2C Master 0 base: 0x4002.0000
Offset 0x01C
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ICreserved
WOROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Interrupt Clear
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise, a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
0WOIC0
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Register 9: I2C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C Master 0 base: 0x4002.0000
Offset 0x020
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
LPBKreservedMFESFEreserved
R/WROROROR/WR/WROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:6
I2C Slave Function Enable
This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.
0R/WSFE5
I2C Master Function Enable
This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.
0R/WMFE4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved3:1
I2C Loopback
This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.
0R/WLPBK0
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Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000
This register consists of seven address bits that identify the Stellaris®I2C device on the I2C bus.
I2C Slave Own Address (I2CSOAR)
I2C Slave 0 base: 0x4002.0800
Offset 0x000
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
OARreserved
R/WR/WR/WR/WR/WR/WR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:7
I2C Slave Own Address
This field specifies bits A6 through A0 of the slave address.
0x00R/WOAR6:0
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Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR,RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris®device detects its own slave address
and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates
that the Stellaris®I2C device has received a data byte from an I2C master. Read one data byte from
the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
indicates that the Stellaris®I2C device is addressed as a Slave Transmitter. Write one data byte
into the I2C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris®I2C slave operation.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RREQTREQFBRreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:3
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
0ROFBR2
Transmit Request
This bit specifies the state of the I2C slave with regards to outstanding
transmit requests. If set, the I2C unit has been addressed as a slave
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
0ROTREQ1
Receive Request
This bit specifies the status of the I2C slave with regards to outstanding
receive requests. If set, the I2C unit has outstanding receive data from
the I2C master and uses clock stretching to delay the master until the
data has been read from the I2CSDR register. Otherwise, no receive
data is outstanding.
0RORREQ0
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Write-Only Control Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
Offset 0x004
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DAreserved
WOROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Device Active
DescriptionValue
Disables the I2C slave operation.0
Enables the I2C slave operation.1
0WODA0
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Register 12: I2C Slave Data (I2CSDR), offset 0x008
This register contains the data to be transmitted when in the Slave Transmit state, and the data
received when in the Slave Receive state.
I2C Slave Data (I2CSDR)
I2C Slave 0 base: 0x4002.0800
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DATAreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
Data for Transfer
This field contains the data for transfer during a slave receive or transmit
operation.
0x0R/WDATA7:0
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Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C
This register controls whether a raw interrupt is promoted to a controller interrupt.
I2C Slave Interrupt Mask (I2CSIMR)
I2C Slave 0 base: 0x4002.0800
Offset 0x00C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IMreserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Interrupt Mask
This bit controls whether a raw interrupt is promoted to a controller
interrupt. If set, the interrupt is not masked and the interrupt is promoted;
otherwise, the interrupt is masked.
0R/WIM0
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Inter-Integrated Circuit (I2C) Interface
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010
This register specifies whether an interrupt is pending.
I2C Slave Raw Interrupt Status (I2CSRIS)
I2C Slave 0 base: 0x4002.0800
Offset 0x010
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Raw Interrupt Status
This bit specifies the raw interrupt state (prior to masking) of the I2C
slave block. If set, an interrupt is pending; otherwise, an interrupt is not
pending.
0RORIS0
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Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C Slave 0 base: 0x4002.0800
Offset 0x014
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MISreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I2C slave
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
0ROMIS0
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Inter-Integrated Circuit (I2C) Interface
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018
This register clears the raw interrupt.
I2C Slave Interrupt Clear (I2CSICR)
I2C Slave 0 base: 0x4002.0800
Offset 0x018
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ICreserved
WOROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:1
Clear Interrupt
This bit controls the clearing of the raw interrupt. A write of 1 clears the
interrupt; otherwise a write of 0 has no affect on the interrupt state. A
read of this register returns no meaningful data.
0WOIC0
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15 Controller Area Network (CAN) Module
15.1 Controller Area Network Overview
Controller Area Network (CAN) is a multicast shared serial bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, it is also used in many embedded control
applications (such as industrial and medical). Bit rates up to 1 Mbps are possible at network lengths
below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at
500 m).
15.2 Controller Area Network Features
The Stellaris®CAN module supports the following features:
■CAN protocol version 2.0 part A/B
■Bit rates up to 1 Mbps
■32 message objects
■Each message object has its own identifier mask
■Maskable interrupt
■Disable Automatic Retransmission mode for Time Triggered CAN (TTCAN) applications
■Programmable Loopback mode for self-test operation
■Programmable FIFO mode
■Gluelessly attach to an external CAN PHY through the CAN0Tx and CAN0Rx pins
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15.3 Controller Area Network Block Diagram
Figure 15-1. CAN Module Block Diagram
CANCTL
CANSTS
CANBIT
CANINT
CANTST
CANBRPE
CAN Control
CANIF1CRQ
CANIF1CMSK
CANIF1MSK1
CANIF1MSK2
CANIF1ARB1
CANIF1ARB2
CANIF1DA1
CANIF1DA2
CANIF1MCTL
APB Interface
APB Pins
CAN Core
Message RAM
32 Message Objects
CANIF1DB1
CANIF1DB2
CANIF2CRQ
CANIF2CMSK
CANIF2MSK1
CANIF2MSK2
CANIF2ARB1
CANIF2ARB2
CANIF2DA1
CANIF2DA2
CANIF2MCTL
CANIF2DB1
CANIF2DB2
CAN TX/RX
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15.4 Controller Area Network Functional Description
The CAN module conforms to the CAN protocol version 2.0 (parts A and B). Message transfers that
include data, remote, error, and overload frames with an 11-bit identifier (standard) or a 29-bit
identifier (extended) are supported. Transfer rates can be programmed up to 1 Mbps.
The CAN module consists of three major parts:
■CAN protocol controller and message handler
■Message memory
■CAN register interface
The protocol controller transfers and receives the serial data from the CAN bus and passes the data
on to the message handler. The message handler then loads this information into the appropriate
message object based on the current filtering and identifiers in the message object memory. The
message handler is also responsible for generating interrupts based on events on the CAN bus.
The message object memory is a set of 32 identical memory blocks that hold the current configuration,
status, and actual data for each message object. These are accessed via the CAN message object
register interface. The message memory is not directly accessable in the Stellaris®memory map,
so the Stellaris®CAN controller provides an interface to communicate with the message memory.
The CAN message object register interface provides two register sets for communicating with the
message objects. Since there is no direct access to the message object memory, these two interfaces
must be used to read or write to each message object. The two message object interfaces allow
parallel access to the CAN controller message objects when multiple objects may have new
information that needs to be processed.
15.4.1 Initialization
The software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register,
with software or by a hardware reset, or by going bus-off, which occurs when the transmitter's error
counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus
are stopped and the status of the CAN transmit output is recessive (High). Entering the initialization
state does not change the configuration of the CAN controller, the message objects, or the error
counters. However, some configuration registers are only accessible when in the initialization state.
To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each
message object. If a message object is not needed, it is sufficient to set it as not valid by clearing
the MsgVal bit in the CANIFnARB2 register. Otherwise, the whole message object has to be
initialized, as the fields of the message object may not have valid information causing unexpected
results. Access to the CAN Bit Timing (CANBIT) register and to the CAN Baud Rate Prescalar
Extension (CANBRPE) register to configure the bit timing are enabled when both the INIT and
CCE bits in the CANCTL register are set. To leave the initialization state, the INIT bit must be
cleared. Afterwards, the internal Bit Stream Processor (BSP) synchronizes itself to the data transfer
on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (Bus
Idle) before it takes part in bus activities and starts message transfers. The initialization of the
message objects is independent of being in the initialization state and can be done on the fly, but
message objects should all be configured to particular identifiers or set to not valid before the BSP
starts the message transfer. To change the configuration of a message object during normal
operation, set the MsgVal bit in the CANIFnARB2 register to 0 (not valid). When the configuration
is completed, MsgVal is set to 1 again (valid).
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Controller Area Network (CAN) Module
15.4.2 Operation
Once the CAN module is initialized and the INIT bit in the CANCTL register is reset to 0, the CAN
module synchronizes itself to the CAN bus and starts the message transfer. As messages are
received, they are stored in their appropriate message objects if they pass the message handler's
filtering. The whole message (including all arbitration bits, data-length code, and eight data bytes)
is stored in the message object. If the Identifier Mask (the Msk bits in the CANIFnMSKn registers)
is used, the arbitration bits which are masked to "don't care" may be overwritten in the message
object.
The CPU may read or write each message any time via the CAN Interface Registers (CANIFnCRQ,
CANIFnCMSK,CANIFnMSKn,CANIFnARBn,CANIFnMCTL,CANIFnDAn, and CANIFnDBn).
The message handler guarantees data consistency in case of concurrent accesses.
The transmission of message objects are under the control of the software that is managing the
CAN hardware. These can be message objects used for one-time data transfers, or permanent
message objects used to respond in a more periodic manner. Permanent message objects have
all arbitration and control set up, and only the data bytes are updated. To start the transmission, the
TxRqst bit in the CANTXRQn register and the NewDat bit in the CANNWDAn register are set. If
several transmit messages are assigned to the same message object (when the number of message
objects is not sufficient), the whole message object has to be configured before the transmission of
this message is requested.
The transmission of any number of message objects may be requested at the same time; they are
transmitted according to their internal priority, which is based on the message identifier for the
message object. Messages may be updated or set to not valid any time, even when their requested
transmission is still pending. The old data is discarded when a message is updated before its pending
transmission has started. Depending on the configuration of the message object, the transmission
of a message may be requested autonomously by the reception of a remote frame with a matching
identifier.
There are two sets of CAN Interface Registers (CANIF1x and CANIF2x), which are used to access
the Message Objects in the Message RAM. The CAN controller coordinates transfers to and from
the Message RAM to and from the registers. The function of the two sets are independent and
identical and can be used to queue transactions.
15.4.3 Transmitting Message Objects
If the internal transmit shift register of the CAN module is ready for loading, and if there is no data
transfer between the CAN Interface Registers and message RAM, the valid message object with
the highest priority and that has a pending transmission request is loaded into the transmit shift
register by the message handler and the transmission is started. The message object's NewDat bit
is reset and can be viewed in the CANNWDAn register. After a successful transmission, and if no
new data was written to the message object since the start of the transmission, the TxRqst bit in
the CANIFnCMSK register is reset. If the TxIE bit in the CANIFnMCTL register is set, the IntPnd
bit in the CANIFnMCTL register is set after a successful transmission. If the CAN module has lost
the arbitration or if an error occurred during the transmission, the message is re-transmitted as soon
as the CAN bus is free again. If, meanwhile, the transmission of a message with higher priority has
been requested, the messages are transmitted in the order of their priority.
15.4.4 Configuring a Transmit Message Object
Table 15-1 on page 382 specifies the bit settings for a transmit message object.
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Table 15-1. Transmit Message Object Bit Settings
CANIFnMCTLCANIFnARB2CANIFnMCTLCANIFnCMSKCANIFnARB2Register
TxRqstRmtEnIntPndTxIERxIEMsgLstNewDatDirEoBMaskDataArbMsgValBit
0appl0appl00011applapplappl1Value
The Xtd and ID bit fields in the CANIFnARBn registers are set by an application. They define the
identifier and type of the outgoing message. If an 11-bit Identifier (Standard Frame) is used, it is
programmed to bits [28:18] of CANIFnARB1, as bits 17:0 of CANIFnARBn are not used by the
CAN controller for 11-bit identifiers.
If the TxIE bit is set, the IntPnd bit is set after a successful transmission of the message object.
If the RmtEn bit is set, a matching received Remote Frame causes the TxRqst bit to be set and
the Remote Frame is autonomously answered by a Data Frame with the data from the message
object.
The DLC bit in the CANIFnMCTL register is set by an application. TxRqst and RmtEn may not be
set before the data is valid.
The CAN mask registers (Msk bits in CANIFnMSKn,UMask bit in CANIFnMCTL register, and MXtd
and MDir bits in CANIFnMSK2 register) may be used (UMask=1) to allow groups of Remote Frames
with similar identifiers to set the TxRqst bit. The Dir bit should not be masked.
15.4.5 Updating a Transmit Message Object
The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface
Registers and neither the MsgVal nor the TxRqst bits have to be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes of the corresponding
CANIFnDAn or CANIFnDBn register have to be valid before the content of that register is transferred
to the message object. Either the CPU has to write all four bytes into the CANIFnDAn or CANIFnDBn
register or the message object is transferred to the CANIFnDAn or CANIFnDBn register before the
CPU writes the new data bytes.
In order to only update the data in a message object, the WR,NewDat,DataA, and DataB bits are
written to the CAN IFn Command Mask (CANIFnMSKn) register, followed by writing the CAN IFn
Data registers, and then the number of the message object is written to the CAN IFn Command
Request (CANIFnCRQ) register, to update the data bytes and the TxRqst bit at the same time.
To prevent the reset of TxRqst at the end of a transmission that may already be in progress while
the data is updated, NewDat has to be set together with TxRqst. When NewDat is set together
with TxRqst,NewDat is reset as soon as the new transmission has started.
15.4.6 Accepting Received Message Objects
When the arbitration and control field (ID +Xtd +RmtEn +DLC) of an incoming message is
completely shifted into the CAN module, the message handling capability of the module starts
scanning the message RAM for a matching valid message object. To scan the message RAM for
a matching message object, the Acceptance Filtering unit is loaded with the arbitration bits from the
core. Then the arbitration and mask fields (including MsgVal,UMask,NewDat, and EoB) of message
object 1 are loaded into the Acceptance Filtering unit and compared with the arbitration field from
the shift register. This is repeated with each following message object until a matching message
object is found or until the end of the message RAM is reached. If a match occurs, the scanning is
stopped and the message handler proceeds depending on the type of frame received.
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Controller Area Network (CAN) Module
15.4.7 Receiving a Data Frame
The message handler stores the message from the CAN module receive shift register into the
respective message object in the message RAM. It stores the data bytes, all arbitration bits, and
the Data Length Code into the corresponding message object. This is implemented to keep the data
bytes connected with the identifier even if arbitration mask registers are used. The
CANIFnMCTL.NewDat bit is set to indicate that new data has been received. The CPU should reset
CANIFnMCTL.NewDat when it reads the message object to indicate to the controller that the
message has been received and the buffer is free to receive more messages. If the CAN controller
receives a message and the CANIFnMCTL.NewDat bit was already set, the MsgLst bit is set to
indicate that the previous data was lost. If the CANIFnMCTL.RxIE bit is set, the
CANIFnMCTL.IntPnd bit is set, causing the CANINT interrupt register to point to the message
object that just received a message. The CANIFnMCTL.TxRqst bit of this message object is reset
to prevent the transmission of a Remote Frame, while the requested Data Frame has just been
received.
15.4.8 Receiving a Remote Frame
When a Remote Frame is received, three different configurations of the matching message object
have to be considered:
■Dir = 1 (direction = transmit), RmtEn = 1, UMask = 1 or 0
At the reception of a matching Remote Frame, the TxRqst bit of this message object is set. The
rest of the message object remains unchanged.
■Dir = 1 (direction = transmit), RmtEn = 0, UMask = 0
At the reception of a matching Remote Frame, the TxRqst bit of this message object remains
unchanged; the Remote Frame is ignored. This remote frame is disabled and will not automatically
respond or indicate that the remote frame ever happened.
■Dir = 1 (direction = transmit), RmtEn = 0, UMask = 1
At the reception of a matching Remote Frame, the TxRqst bit of this message object is reset.
The arbitration and control field (ID +Xtd +RmtEn +DLC) from the shift register is stored into
the message object in the message RAM and the NewDat bit of this message object is set. The
data field of the message object remains unchanged; the Remote Frame is treated similar to a
received Data Frame. This is useful for a remote data request from another CAN device for which
the Stellaris®controller does not have readily available data. The software must fill the data and
answer the frame manually.
15.4.9 Receive/Transmit Priority
The receive/transmit priority for the message objects is controlled by the message number. Message
object 1 has the highest priority, while message object 32 has the lowest priority. If more than one
transmission request is pending, the message objects are transmitted in order based on the message
object with the lowest message number. This should not be confused with the message identifier
as that priority is enforced by the CAN bus. This means that if message object 1 and message object
2 both have valid messages that need to be transmitted, message object 1 will always be transmitted
first regardless of the message identifier in the message object itself.
15.4.10 Configuring a Receive Message Object
Table 15-2 on page 384 specifies the bit settings for a transmit message object.
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Table 15-2. Receive Message Object Bit Settings
CANIFnMCTLCANIFnARB2CANIFnMCTLCANIFnCMSKCANIFnARB2Register
TxRqstRmtEnIntPndTxIERxIEMsgLstNewDatDirEoBMaskDataArbMsgValBit
0000appl0001applapplappl1Value
The Xtd and ID bit fields in the CANIFnARBn registers are set by an application. They define the
identifier and type of accepted received messages. If an 11-bit Identifier (Standard Frame) is used,
it is programmed to bits [28:18] of CANIFnARB1, and bits [17:0] are ignored by the CAN controller.
When a Data Frame with an 11-bit Identifier is received, bits [17:0] are set to 0.
If the RxIE bit is set, the IntPnd bit is set when a received Data Frame is accepted and stored in
the message object.
When the message handler stores a Data Frame in the message object, it stores the received Data
Length Code and eight data bytes. If the Data Length Code is less than 8, the remaining bytes of
the message object are overwritten by nonspecified values.
The CAN mask registers (Msk bits in CANIFnMSKn,UMask bit in CANIFnMCTL register, and MXtd
and MDir bits in CANIFnMSK2 register) may be used (UMask=1) to allow groups of Data Frames
with similar identifiers to be accepted. The Dir bit should not be masked in typical applications.
15.4.11 Handling of Received Message Objects
The CPU may read a received message any time via the CAN Interface registers because the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the CAN IFn Command Mask (CANIFnCMSK) register
and then writes the number of the message object to the CAN IFn Command Request
(CANIFnCRQ) register. That combination transfers the whole received message from the message
RAM into the Message Buffer registers (CANIFnMSKn,CANIFnARBn, and CANIFnMCTL).
Additionally, the NewDat and IntPnd bits are cleared in the message RAM, acknowledging that
the message has been read and clearing the pending interrupt being generated by this message
object.
If the message object uses masks for acceptance filtering, the arbitration bits show which of the
matching messages has been received.
The actual value of NewDat shows whether a new message has been received since the last time
this message object was read. The actual value of MsgLst shows whether more than one message
has been received since the last time this message object was read. MsgLst is not automatically
reset.
Using a Remote Frame, the CPU may request new data from another CAN node on the CAN bus.
Setting the TxRqst bit of a receive object causes the transmission of a Remote Frame with the
receive object's identifier. This Remote Frame triggers the other CAN node to start the transmission
of the matching Data Frame. If the matching Data Frame is received before the Remote Frame
could be transmitted, the TxRqst bit is automatically reset. This prevents the possible loss of data
when the other device on the CAN bus has already transmitted the data, slightly earlier than expected.
15.4.12 Handling of Interrupts
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. An interrupt remains pending until
the CPU has cleared it.
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The Status Interrupt has the highest priority. Among the message interrupts, the message object's
interrupt priority decreases with increasing message number. A message interrupt is cleared by
clearing the message object's IntPnd bit. The Status Interrupt is cleared by reading the CAN Status
(CANSTS) register.
The interrupt identifier IntId in the CANINT register indicates the cause of the interrupt. When no
interrupt is pending, the register holds the value to 0. If the value of CANINT is different from 0, then
there is an interrupt pending. If the IE bit is set in the CANCTL register, the interrupt line to the CPU
is active. The interrupt line remains active until CANINT is 0, all interrupt sources have been cleared,
(the cause of the interrupt is reset), or until IE is reset, which disables interrupts from the CAN
controller.
The value 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN
module has updated, but not necessarily changed, the CANSTS register (Error Interrupt or Status
Interrupt). This indicates that there is either a new Error Interrupt or a new Status Interrupt. A write
access can clear the RxOK,TxOK, and LEC flags in the CANSTS register, however, only a read
access to the CANSTS register will clear the source of the status interrupt.
IntId points to the pending message interrupt with the highest interrupt priority. The SIE bit in the
CANCTL register controls whether a change of the status register may cause an interrupt. The EIE
bit in the CANCTL register controls whether any interrupt from the CAN controller actually generates
an interrupt to the microcontroller's interrupt controller. The CANINT interrupt register is updated
even when the IE bit is set to zero.
There are two possibilities when handling the source of a message interrupt. The first is to read the
IntId bit in the CANINT interrupt register to determine the highest priority interrupt that is pending,
and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see
all of the message objects that have pending interrupts.
An interrupt service routine reading the message that is the source of the interrupt may read the
message and reset the message object's IntPnd at the same time by setting the ClrIntPnd bit
in the CAN IFn Command Mask (CANIFnCMSK) register. When the IntPnd bit is cleared, the
CANINT register will contain the message number for the next message object with a pending
interrupt.
15.4.13 Bit Timing Configuration Error Considerations
Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the
performance of a CAN network can be reduced significantly. In many cases, the CAN bit
synchronization amends a faulty configuration of the CAN bit timing to such a degree that only
occasionally an error frame is generated. In the case of arbitration, however, when two or more
CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the
transmitters to become error passive. The analysis of such sporadic errors requires a detailed
knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on
the CAN bus.
15.4.14 Bit Time and Bit Rate
The CAN system supports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member
of the CAN network has its own clock generator. The timing parameter of the bit time can be
configured individually for each CAN node, creating a common bit rate even though the CAN nodes'
oscillator periods may be different.
Because of small variations in frequency caused by changes in temperature or voltage and by
deteriorating components, these oscillators are not absolutely stable. As long as the variations
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remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the
different bit rates by periodically resynchronizing to the bit stream.
According to the CAN specification, the bit time is divided into four segments (see Figure
15-2 on page 386): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer
Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable
number of time quanta (see Table 15-3 on page 386). The length of the time quantum (tq), which
is the basic time unit of the bit time, is defined by the CAN controller's system clock (fsys) and the
Baud Rate Prescaler (BRP):
tq = BRP / fsys
The CAN module's system clock fsys is the frequency of its CAN module clock (CAN_CLK) input.
The Synchronization Segment Sync_Seg is that part of the bit time where edges of the CAN bus
level are expected to occur; the distance between an edge that occurs outside of Sync_Seg and
the Sync_Seg is called the phase error of that edge.
The Propagation Time Segment Prop_Seg is intended to compensate for the physical delay times
within the CAN network.
The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 surround the Sample Point.
The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the
Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase
errors.
A given bit rate may be met by different bit-time configurations, but for the proper function of the
CAN network, the physical delay times and the oscillator's tolerance range have to be considered.
Figure 15-2. CAN Bit Time
Table 15-3. CAN Protocol Rangesa
RemarkRangeParameter
Defines the length of the time quantum tq
[1 .. 32]BRP
Fixed length, synchronization of bus input to system clock1 tq
Sync_Seg
Compensates for the physical delay times[1 .. 8] tq
Prop_Seg
May be lengthened temporarily by synchronization[1 .. 8] tq
Phase_Seg1
May be shortened temporarily by synchronization[1 .. 8] tq
Phase_Seg2
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RemarkRangeParameter
May not be longer than either Phase Buffer Segment[1 .. 4] tq
SJW
a. This table describes the minimum programmable ranges required by the CAN protocol.
The bit timing configuration is programmed in two register bytes in the CANBIT register. The sum
of Prop_Seg and Phase_Seg1 (as TSEG1) is combined with Phase_Seg2 (as TSEG2) in one byte,
and SJW and BRP are combined in the other byte.
In these bit timing registers, the four components TSEG1,TSEG2,SJW, and BRP have to be
programmed to a numerical value that is one less than its functional value; so instead of values in
the range of [1..n], values in the range of [0..n-1] are programmed. That way, for example, SJW
(functional range of [1..4]) is represented by only two bits. Therefore, the length of the bit time is
(programmed values):
[TSEG1 + TSEG2 + 3] tq
or (functional values):
[Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq
The data in the bit timing registers are the configuration input of the CAN protocol controller. The
Baud Rate Prescalar (configured by BRP) defines the length of the time quantum, the basic time
unit of the bit time; the Bit Timing Logic (configured by TSEG1,TSEG2, and SJW) defines the number
of time quanta in the bit time.
The processing of the bit time, the calculation of the position of the Sample Point, and occasional
synchronizations are controlled by the CAN controller and are evaluated once per time quantum.
The CAN controller translates messages to and from frames. It generates and discards the enclosing
fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC code, performs the
error management, and decides which type of synchronization is to be used. It is evaluated at the
Sample Point and processes the sampled bus input bit. The time after the Sample Point that is
needed to calculate the next bit to be sent (that is, the data bit, CRC bit, stuff bit, error flag, or idle)
is called the Information Processing Time (IPT).
The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is
the lower limit of the programmed length of Phase_Seg2. In case of synchronization, Phase_Seg2
may be shortened to a value less than IPT, which does not affect bus timing.
15.4.15 Calculating the Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time. The
resulting bit time (1/bit rate) must be an integer multiple of the system clock period.
The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the desired bit
time, allowing iterations of the following steps.
The first part of the bit time to be defined is the Prop_Seg. Its length depends on the delay times
measured in the system. A maximum bus length as well as a maximum node delay has to be defined
for expandable CAN bus systems. The resulting time for Prop_Seg is converted into time quanta
(rounded up to the nearest integer multiple of tq).
The Sync_Seg is 1 tq long (fixed), which leaves (bit time - Prop_Seg - 1) tq for the two Phase
Buffer Segments. If the number of remaining tq is even, the Phase Buffer Segments have the same
length, that is, Phase_Seg2 =Phase_Seg1, else Phase_Seg2 =Phase_Seg1 + 1.
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The minimum nominal length of Phase_Seg2 has to be regarded as well. Phase_Seg2 may not
be shorter than the CAN controller's Information Processing Time, which is, depending on the actual
implementation, in the range of [0..2] tq.
The length of the Synchronization Jump Width is set to its maximum value, which is the minimum
of 4 and Phase_Seg1.
The oscillator tolerance range necessary for the resulting configuration is calculated by the formula
given below:
(1 -df) x fnom <= fosc <= (1+ df) x fnom
where:
■df = maximum tolerance of oscillator frequency
■fosc = actual oscillator frequency
■fnom = nominal oscillator frequency
Maximum frequency tolerance must take into account the following formulas:
df <= (Phase_Seg1,Phase_Seg2)min/ 2 x (13 x tbit - Phase_Seg2)
dfmax = 2 x df x fnom
where:
■Phase_Seg1 and Phase_Seg2 are from Table 15-3 on page 386
■tbit = Bit Time
■dfmax = maximum difference between two oscillators
If more than one configuration is possible, that configuration allowing the highest oscillator tolerance
range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same bit
rate. The calculation of the propagation time in the CAN network, based on the nodes with the
longest delay times, is done once for the whole network.
The CAN system's oscillator tolerance range is limited by the node with the lowest tolerance range.
The calculation may show that bus length or bit rate have to be decreased or that the oscillator
frequencies' stability has to be increased in order to find a protocol-compliant configuration of the
CAN bit timing.
The resulting configuration is written into the CAN Bit Timing (CANBIT) register :
(Phase_Seg2-1)&(Phase_Seg1+Prop_Seg-1)&(SynchronizationJumpWidth-1)&(Prescaler-1)
15.4.15.1 Example for Bit Timing at High Baud Rate
In this example, the frequency of CAN_CLK is 10 MHz, BRP is 0, and the bit rate is 1 Mbps.
tq 100 ns = tCAN_CLK
delay of bus driver 50 ns
delay of receiver circuit 30 ns
delay of bus line (40m) 220 ns
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tProp 600 ns = 6 × tq
tSJW 100 ns = 1 × tq
tTSeg1 700 ns = tProp + tSJW
tTSeg2 200 ns = Information Processing Time + 1 × tq
tSync-Seg 100 ns = 1 × tq
bit time 1000 ns = tSync-Seg + tTSeg1 + tTSeg2
tolerance for CAN_CLK 0.39 % =
min(PB1,PB2)/ 2 × (13 x bit time - PB2) =
0.1us/ 2 x (13x 1us - 2us)
In the above example, the concatenated bit time parameters are (2-1)3&(7-1)4&(1-1)2&(1-1)6, and
CANBIT is programmed to 0x1600.
15.4.15.2 Example for Bit Timing at Low Baud Rate
In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, and the bit rate is 100 Kbps.
tq 1 ms = 2 × tCAN_CLK
delay of bus driver 200 ns
delay of receiver circuit 80 ns
delay of bus line (40m) 220 ns
tProp 1 ms = 1 × tq
tSJW 4 ms = 4 × tq
tTSeg1 5 ms = tProp + tSJW
tTSeg2 4 ms = Information Processing Time + 3 × tq
tSync-Seg 1 ms = 1 × tq
bit time 10 ms = tSync-Seg + tTSeg1 + tTSeg2
tolerance for CAN_CLK 1.58 % =
min(PB1,PB2)/ 2 x (13 x bit time - PB2) =
4us/ 2 x (13 x 10us - 4us)
In this example, the concatenated bit time parameters are (4-1)3&(5-1)4&(4-1)2&(2-1)6, and CANBIT
is programmed to 0x34C1.
15.5 Controller Area Network Register Map
Table 15-4 on page 389 lists the registers. All addresses given are relative to the CAN base address
of:
■CAN0: 0x4004.0000
All accesses are on word (32-bit) boundaries.
Table 15-4. CAN Register Map
See
page
DescriptionResetTypeNameOffset
392CAN Control0x0000.0001R/WCANCTL0x000
394CAN Status0x0000.0000R/WCANSTS0x004
397CAN Error Counter0x0000.0000ROCANERR0x008
398CAN Bit Timing0x0000.2301R/WCANBIT0x00C
400CAN Interrupt0x0000.0000ROCANINT0x010
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See
page
DescriptionResetTypeNameOffset
401CAN Test0x0000.0000R/WCANTST0x014
403CAN Baud Rate Prescalar Extension0x0000.0000R/WCANBRPE0x018
404CAN IF1 Command Request0x0000.0001R/WCANIF1CRQ0x020
405CAN IF1 Command Mask0x0000.0000R/WCANIF1CMSK0x024
408CAN IF1 Mask 10x0000.FFFFR/WCANIF1MSK10x028
409CAN IF1 Mask 20x0000.FFFFR/WCANIF1MSK20x02C
410CAN IF1 Arbitration 10x0000.0000R/WCANIF1ARB10x030
411CAN IF1 Arbitration 20x0000.0000R/WCANIF1ARB20x034
412CAN IF1 Message Control0x0000.0000R/WCANIF1MCTL0x038
414CAN IF1 Data A10x0000.0000R/WCANIF1DA10x03C
414CAN IF1 Data A20x0000.0000R/WCANIF1DA20x040
414CAN IF1 Data B10x0000.0000R/WCANIF1DB10x044
414CAN IF1 Data B20x0000.0000R/WCANIF1DB20x048
404CAN IF2 Command Request0x0000.0001R/WCANIF2CRQ0x080
405CAN IF2 Command Mask0x0000.0000R/WCANIF2CMSK0x084
408CAN IF2 Mask 10x0000.FFFFR/WCANIF2MSK10x088
409CAN IF2 Mask 20x0000.FFFFR/WCANIF2MSK20x08C
410CAN IF2 Arbitration 10x0000.0000R/WCANIF2ARB10x090
411CAN IF2 Arbitration 20x0000.0000R/WCANIF2ARB20x094
412CAN IF2 Message Control0x0000.0000R/WCANIF2MCTL0x098
414CAN IF2 Data A10x0000.0000R/WCANIF2DA10x09C
414CAN IF2 Data A20x0000.0000R/WCANIF2DA20x0A0
414CAN IF2 Data B10x0000.0000R/WCANIF2DB10x0A4
414CAN IF2 Data B20x0000.0000R/WCANIF2DB20x0A8
415CAN Transmission Request 10x0000.0000ROCANTXRQ10x100
415CAN Transmission Request 20x0000.0000ROCANTXRQ20x104
416CAN New Data 10x0000.0000ROCANNWDA10x120
416CAN New Data 20x0000.0000ROCANNWDA20x124
417CAN Message 1 Interrupt Pending0x0000.0000ROCANMSG1INT0x140
417CAN Message 2 Interrupt Pending0x0000.0000ROCANMSG2INT0x144
418CAN Message 1 Valid0x0000.0000ROCANMSG1VAL0x160
418CAN Message 2 Valid0x0000.0000ROCANMSG2VAL0x164
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15.6 Register Descriptions
The remainder of this section lists and describes the CAN registers, in numerical order by address
offset. There are two sets of Interface Registers which are used to access the Message Objects in
the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used
to queue transactions.
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Register 1: CAN Control (CANCTL), offset 0x000
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting
or resetting INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT
has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11
consecutive High bits) before resuming normal operations. At the end of the bus-off recovery
sequence, the Error Management Counters are reset.
During the waiting time after INIT is reset, each time a sequence of 11 High bits has been monitored,
aBit0Error code is written to the CANSTS status register, enabling the CPU to readily check
whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding
of the bus-off recovery sequence.
CAN Control (CANCTL)
CAN0 base: 0x4004.0000
Offset 0x000
Type R/W, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INITIESIEEIEreservedDARCCETestreserved
R/WR/WR/WR/WROR/WR/WR/WROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:8
Test Mode Enable
0: Normal Operation
1: Test Mode
0R/WTest7
Configuration Change Enable
0: Do not allow write access to the CANBIT register.
1: Allow write access to the CANBIT register if the INIT bit is 1.
0R/WCCE6
Disable Automatic Retransmission
0: Auto retransmission of disturbed messages is enabled.
1: Auto retransmission is disabled.
0R/WDAR5
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved4
Error Interrupt Enable
0: Disabled. No Error Status interrupt is generated.
1: Enabled. A change in the Boff or EWarn bits in the CANSTS register
generates an interrupt.
0R/WEIE3
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DescriptionResetTypeNameBit/Field
Status Change Interrupt Enable
0: Disabled. No Status Change interrupt is generated.
1: Enabled. An interrupt is generated when a message has successfully
been transmitted or received, or a CAN bus error has been detected. A
change in the TxOk or RxOk bits in the CANSTS register generates an
interrupt.
0R/WSIE2
CAN Interrupt Enable
0: Interrupt disabled.
1: Interrupt enabled.
0R/WIE1
Initialization
0: Normal operation.
1: Initialization started.
1R/WINIT0
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Register 2: CAN Status (CANSTS), offset 0x004
The status register contains information for interrupt servicing such as Bus-Off, error count threshold,
and error types.
The LEC field holds the code that indicates the type of the last error to occur on the CAN bus. This
field is cleared to 0 when a message has been transferred (reception or transmission) without error.
The unused error code 7 may be written by the CPU to check for updates.
An Error Interrupt is generated by the BOff and EWarn bits and a Status Change Interrupt is
generated by the RxOk,TxOk, and LEC bits, assuming that the corresponding enable bits in the
CAN Control (CANCTL) register are set. A change of the EPass bit or a write to the RxOk,TxOk,
or LEC bits does not generate an interrupt.
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is
pending.
CAN Status (CANSTS)
CAN0 base: 0x4004.0000
Offset 0x004
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
LECTxOKRxOKEPassEWarnBOffreserved
R/WR/WR/WR/WR/WROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:8
Bus-Off Status
0: Module is not in bus-off state.
1: Module is in bus-off state.
0ROBOff7
Warning Status
0: Both error counters are below the error warning limit of 96.
1: At least one of the error counters has reached the error warning limit
of 96.
0ROEWarn6
Error Passive
0: The CAN module is in the Error Active state, that is, the receive or
transmit error count is less than or equal to 127.
1: The CAN module is in the Error Passive state, that is, the receive or
transmit error count is greater than 127.
0ROEPass5
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DescriptionResetTypeNameBit/Field
Received a Message Successfully
0: Since this bit was last reset to 0, no message has been successfully
received.
1: Since this bit was last reset to 0, a message has been successfully
received, independent of the result of the acceptance filtering.
This bit is never reset by the CAN module.
0R/WRxOK4
Transmitted a Message Successfully
0: Since this bit was last reset to 0, no message has been successfully
transmitted.
1: Since this bit was last reset to 0, a message has been successfully
transmitted error-free and acknowledged by at least one other node.
This bit is never reset by the CAN module.
0R/WTxOK3
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DescriptionResetTypeNameBit/Field
Last Error Code
This is the type of the last error to occur on the CAN bus.
DefinitionValue
No Error0x0
Stuff Error
More than 5 equal bits in a sequence have occurred in a part
of a received message where this is not allowed.
0x1
Form Error
A fixed format part of the received frame has the wrong format.
0x2
ACK Error
The message transmitted was not acknowledged by another
node.
0x3
Bit 1 Error
When a message is transmitted, the CAN controller monitors
the data lines to detect any conflicts. When the arbitration field
is transmitted, data conflicts are a part of the arbitration protocol.
When other frame fields are transmitted, data conflicts are
considered errors.
A Bit 1 Error indicates that the device wanted to send a High
level (logical 1) but the monitored bus value was Low (logical
0).
0x4
Bit 0 Error
A Bit 0 Error indicates that the device wanted to send a Low
level (logical 0) but the monitored bus value was High (logical
1).
During bus-off recovery, this status is set each time a sequence
of 11 High bits has been monitored. This enables the CPU to
monitor the proceeding of the bus-off recovery sequence without
any disturbances to the bus.
0x5
CRC Error
The CRC checksum was incorrect in the received message,
indicating that the calculated value received did not match the
calculated CRC of the data.
0x6
Unused
When the LEC bit shows this value, no CAN bus event was
detected since the CPU wrote this value to LEC.
0x7
0x0R/WLEC2:0
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Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
Offset 0x008
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TECRECRP
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Received Error Passive
0: The Receive Error counter is below the Error Passive level (127 or
less).
1: The Receive Error counter has reached the Error Passive level (128
or greater).
0RORP15
Receive Error Counter
State of the receiver error counter (0 to 127).
0x0ROREC14:8
Transmit Error Counter
State of the transmit error counter (0 to 255).
0x0ROTEC7:0
397November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 4: CAN Bit Timing (CANBIT), offset 0x00C
This register is used to program the bit width and bit quantum. Values are to be programmed to the
system clock frequency. This register is write-enabled by the CCE and INIT bits in the CANCTL
register.
With a CAN module clock (CAN_CLK) of 8 MHz, the register reset value of 0x230 configures the
CAN for a bit rate of 500 Kbps.
CAN Bit Timing (CANBIT)
CAN0 base: 0x4004.0000
Offset 0x00C
Type R/W, reset 0x0000.2301
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
BRPSJWTSeg1TSeg2reserved
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROType
1000000011000100Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:15
Time Segment after Sample Point
0x00-0x07: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, a reset value of 0x2 defines that there is 3(2+1) bit
time quanta defined for Phase_Seg2 (see Figure 15-2 on page 386).
The bit time quanta is defined by BRP.
0x2R/WTSeg214:12
Time Segment Before Sample Point
0x00-0x0F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x3 defines that there is 4(3+1) bit
time quanta defined for Phase_Seg1 (see Figure 15-2 on page 386).
The bit time quanta is define by BRP.
0x3R/WTSeg111:8
(Re)Synchronization Jump Width
0x00-0x03: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
During the start of frame (SOF), if the CAN controller detects a phase
error (misalignment), it can adjust the length of TSeg2 or TSeg1 by the
value in SJW. So the reset value of 0 adjusts the length by 1 bit time
quanta.
0x0R/WSJW7:6
November 30, 2007398
Preliminary
Controller Area Network (CAN) Module
DescriptionResetTypeNameBit/Field
Baud Rate Prescalar
0x00-0x03F: The value by which the oscillator frequency is divided for
generating the bit time quanta. The bit time is built up from a multiple
of this quantum. The actual interpretation by the hardware of this value
is such that one more than the value programmed here is used.
BRP defines the number of CAN clock periods that make up 1 bit time
quanta, so the reset value is 2 bit time quanta (1+1).
The BRPRE register can be used to further divide the bit time.
0x1R/WBRP5:0
399November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 5: CAN Interrupt (CANINT), offset 0x010
This register indicates the source of the interrupt.
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. An interrupt remains pending until
the CPU has cleared it. If the IntId bit is not 0x0000 (the default) and the IE bit in the CANCTL
register is set, the interrupt is active. The interrupt line remains active until the IntId bit is set back
to 0x0000 when the cause of all interrupts are reset or until IE is reset.
CAN Interrupt (CANINT)
CAN0 base: 0x4004.0000
Offset 0x010
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntId
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Interrupt Identifier
The number in this field indicates the source of the interrupt.
DefinitionValue
No interrupt pending0x0000
Number of the message object that caused the
interrupt
0x0001-0x0020
Unused0x0021-0x7FFF
Status Interrupt0x8000
Unused0x8001-0xFFFF
0x0000ROIntId15:0
November 30, 2007400
Preliminary
Controller Area Network (CAN) Module
Register 6: CAN Test (CANTST), offset 0x014
This is the test mode register for self-test and external pin access. It is write-enabled by the Test
bit in the CANCTL register. Different test functions may be combined but when the Tx bit is not
equal to 0x0, it disturbs message transmits.
CAN Test (CANTST)
CAN0 base: 0x4004.0000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedBasicSilentLBackTxRxreserved
ROROR/WR/WR/WR/WR/WROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:8
Receive Observation
Displays the value on the CANnRx pin.
0RORx7
Transmit Control
Overrides control of theCANnTx pin.
DescriptionValue
CAN_TX is controlled by the CAN module (default)00
Sample Point signal driven on the CAN_TX pin01
CAN_TX drives a Low value10
CAN_TX drives a High value11
0x0R/WTx6:5
Loopback Mode
0: Disabled.
1: Enabled.
0R/WLBack4
Silent Mode
Do not transmit data; monitor the bus. Also known as Bus Monitor mode.
0: Disabled.
1: Enabled.
0R/WSilent3
Basic Mode
0: Disabled.
1: Use CANIF1 registers as transmit buffer, and use CANIF2 registers
as receive buffer.
0R/WBasic2
401November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved1:0
November 30, 2007402
Preliminary
Controller Area Network (CAN) Module
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018
This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is
write-enabled with the CCE bit in the CANCTL register.
CAN Baud Rate Prescalar Extension (CANBRPE)
CAN0 base: 0x4004.0000
Offset 0x018
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
BRPEreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:4
Baud Rate Prescalar Extension.
0x00-0x0F: Extend the BRP bit to values up to 1023. The actual
interpretation by the hardware is one more than the value programmed
by BRPE (MSBs) and BRP (LSBs) are used.
0x0R/WBRPE3:0
403November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080
This register is used to start a transfer when its MNUM bit field is updated. Its Busy bit indicates that
the information is transferring from the CAN Interface Registers to the internal message RAM.
A message transfer is started as soon as there is a write of the message object number with the
MNUM bit. With this write operation, the Busy bit is automatically set to 1 to indicate that a transfer
is in progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the interface
register and the message RAM completes, which then sets the Busy bit back to 0.
CAN IF1 Command Request (CANIF1CRQ)
CAN0 base: 0x4004.0000
Offset 0x020
Type RO, reset 0x0000.0001
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MNUMreservedBusy
R/WR/WR/WR/WR/WR/WROROROROROROROROROROType
1000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Busy Flag
0: Reset when read/write action has finished.
1: Set when a write occurs to the message number in this register.
0x0ROBusy15
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved14:6
Message Number
Selects one of the 32 message objects in the message RAM for data
transfer. The message objects are numbered from 1 to 32.
DescriptionValue
0 is not a valid message number; it is interpreted as 0x20,
or object 32.
0x00
Indicates specified message object 1 to 32.0x01-0x20
Not a valid message number; values are shifted and it is
interpreted as 0x01-0x1F.
0x21-0x3F
0x01R/WMNUM5:0
November 30, 2007404
Preliminary
Controller Area Network (CAN) Module
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
The Command Mask registers specify the transfer direction and select which buffer registers are
the source or target of the data transfer.
CAN IF1 Command Mask (CANIF1CMSK)
CAN0 base: 0x4004.0000
Offset 0x024
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DataBDataA
TxRqst/NewDatClrIntPnd
ControlArbMaskWRNRDreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:8
Write, Not Read
0: Read. Transfer the message object address specified by the CAN
Command Request (CANIFnCRQ) register to the CAN message buffer
registers (CANIFnMSK1,CANIFnMSK2,CANIFnARB1,CANIFnARB2,
CANIFnCTL,CANIFnDA1,CANIFnDA2,CANIFnDB1, and
CANIFnDB2).
1: Write. Transfer data from the message buffer registers to the message
object address specified by the CANIFnCRQ register.
0R/WWRNRD7
Access Mask Bits
When WRNRD=1 (writes):
0: Mask bits unchanged.
1: Transfer IDMask +Dir +MXtd to message object.
When WRNRD=0 (reads):
0: Mask bits unchanged.
1: Transfer IDMask +Dir +MXtd of the message object into the
Interface Registers.
0x0R/WMask6
Access Arbitration Bits
When WRNRD=1 (writes):
0: Arbitration bits unchanged.
1: Transfer ID +Dir + Xtd + MsgVal to message object.
When WRNRD=0 (reads):
0: Arbitration bits unchanged.
1: Transfer ID +Dir +Xtd +MsgVal to Message Buffer Register.
0x0R/WArb5
405November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionResetTypeNameBit/Field
Access Control Bits
When WRNRD=1 (writes):
0: Control bits unchanged.
1: Transfer control bits to message object.
When WRNRD=0 (reads):
0: Control bits unchanged.
1: Transfer control bits to Message Buffer Register.
0x0R/WControl4
Clear Interrupt Pending Bit
Note: This bit is not used when in write (WRNRD=1).
0: IntPnd bit in CANIFnMCTL register remains unchanged.
1: Clear IntPnd bit in the CANIFnMCTL register in the message object.
0x0R/WClrIntPnd3
Access Transmission Request or New Data
When WRNRD=1 (writes):
Access Transmission Request Bit
0: TxRqst bit unchanged.
1: Set TxRqst bit
Note: If a transmission is requested by programming this TxRqst
bit, the parallel TxRqst in the CANIFnMCTL register is
ignored.
When WRNRD=0 (reads):
Access New Data Bit
0: NewDat bit unchanged.
1: Clear NewDat bit in the message object.
Note: A read access to a message object can be combined with the
reset of the control bits IntPdn and NewDat. The values of
these bits that are transferred to the CANIFnMCTL register
always reflect the status before resetting these bits.
0x0R/WTxRqst/NewDat2
Access Data Byte 0 to 3
When WRNRD=1 (writes):
0: Data bytes 0-3 are unchanged.
1: Transfer data bytes 0-3 (CANIFnDA1 and CANIFnDA2) to message
object.
When WRNRD=0 (reads):
0: Data bytes 0-3 are unchanged.
1: Transfer data bytes 0-3 in message object to CANIFnDA1 and
CANIFnDA2.
0x0R/WDataA1
November 30, 2007406
Preliminary
Controller Area Network (CAN) Module
DescriptionResetTypeNameBit/Field
Access Data Byte 4 to 7
When WRNRD=1 (writes):
0: Data bytes 4-7 unchanged.
1: Transfer data bytes 4-7 (CANIFnDB1 and CANIFnDB2) to message
object.
When WRNRD=0 (reads):
0: Data bytes 4-7 unchanged.
1: Transfer data bytes 4-7 in message object to CANIFnDB1 and
CANIFnDB2.
0x0R/WDataB0
407November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088
The mask information provided in this register accompanies the data (CANIFnDAn), arbitration
information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the
message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance
filtering. Additional mask information is contained in the CANIFnMSK2 register.
CAN IF1 Mask 1 (CANIF1MSK1)
CAN0 base: 0x4004.0000
Offset 0x028
Type RO, reset 0x0000.FFFF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Msk
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111100000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Identifier Mask
0: The corresponding identifier bit (ID) in the message object cannot
inhibit the match in acceptance filtering.
1: The corresponding identifier bit (ID) is used for acceptance filtering.
0xFFR/WMsk15:0
November 30, 2007408
Preliminary
Controller Area Network (CAN) Module
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C
This register holds extended mask information that accompanies the CANIFnMSK1 register.
CAN IF1 Mask 2 (CANIF1MSK2)
CAN0 base: 0x4004.0000
Offset 0x02C
Type RO, reset 0x0000.FFFF
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MskreservedMDirMXtd
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROR/WR/WType
1111111100000111Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Mask Extended Identifier
0: The extended identifier bit (Xtd in the CANIFnARB2 register) has
no effect on the acceptance filtering.
1: The extended identifier bit Xtd is used for acceptance filtering.
0x1R/WMXtd15
Mask Message Direction
0: The message direction bit (Dir in the CANIFnARB2 register) has
no effect for acceptance filtering.
1: The message direction bit Dir is used for acceptance filtering.
0x1R/WMDir14
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x1ROreserved13
Identifier Mask
0: The corresponding identifier bit (ID) in the message object cannot
inhibit the match in acceptance filtering.
1: The corresponding identifier bit (ID) is used for acceptance filtering.
0xFFR/WMsk12:0
409November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090
These registers hold the identifiers for acceptance filtering.
CAN IF1 Arbitration 1 (CANIF1ARB1)
CAN0 base: 0x4004.0000
Offset 0x030
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ID
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Message Identifier
This bit field is used with the ID field in the CANIFnARB2 register to
create the message identifier. ID[28:0] is the Extended Frame and
ID[28:18] is the Standard Frame.
0x00R/WID15:0
November 30, 2007410
Preliminary
Controller Area Network (CAN) Module
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094
These registers hold information for acceptance filtering.
CAN IF1 Arbitration 2 (CANIF1ARB2)
CAN0 base: 0x4004.0000
Offset 0x034
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IDDirXtdMsgVal
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Message Valid
0: The message object is ignored by the message handler.
1: The message object is configured and will be considered by the
message handler within the CAN controller.
All unused message objects should have this bit cleared during
initialization and before clearing the Init bit in the CANCTL register.
The MsgVal bit must also be cleared before any of the following bits
are modified or if the message object is no longer required: the ID bit
fields in the CANIFnARBn registers, the Xtd and Dir bits in the
CANIFnARB2 register, or the DLC bits in the CANIFnMCTL register.
0x0R/WMsgVal15
Extended Identifier
0: The 11-bit Standard Identifier will be used for this message object.
1: The 29-bit Extended Identifier will be used for this message object.
0x0R/WXtd14
Message Direction
0: Receive. On TxRqst, a Remote Frame with the identifier of this
message object is transmitted. On reception of a Data Frame with
matching identifier, that message is stored in this message object.
1: Transmit. On TxRqst, the respective message object is transmitted
as a Data Frame. On reception of a Remote Frame with matching
identifier, TxRqst bit of this message object is set (if RmtEn=1).
0x0R/WDir13
Message Identifier
Used with the ID bit in the CANIFnARB1 register to create the message
identifier. ID[28:0] is the Extended Frame and ID[28:18] is the Standard
Frame.
0x0R/WID12:0
411November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098
This register holds the control information associated with the message object to be sent to the
Message RAM.
CAN IF1 Message Control (CANIF1MCTL)
CAN0 base: 0x4004.0000
Offset 0x038
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DLCreservedEoBTxRqstRmtEnRxIETxIEUMaskIntPndMsgLstNewDat
R/WR/WR/WR/WROROROR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
New Data
0: No new data has been written into the data portion of this message
object by the message handler since the last time this flag was cleared
by the CPU.
1: The message handler or the CPU has written new data into the data
portion of this message object.
0x0R/WNewDat15
Message Lost
0 : No message was lost since the last time this bit was reset by the
CPU.
1: The message handler stored a new message into this object when
NewDat was set; the CPU has lost a message.
This bit is only valid for message objects with the Dir bit in the
CANIFnARB2 register set to 0 (receive).
0x0R/WMsgLst14
Interrupt Pending
0: This message object is not the source of an interrupt.
1: This message object is the source of an interrupt. The interrupt
identifier in the CAN Interrupt (CANINT) register will point to this
message object if there is not another interrupt source with a higher
priority.
0x0R/WIntPnd13
Use Acceptance Mask
0: Mask ignored.
1: Use mask (Msk,MXtd, and MDir) for acceptance filtering.
0x0R/WUMask12
November 30, 2007412
Preliminary
Controller Area Network (CAN) Module
DescriptionResetTypeNameBit/Field
Transmit Interrupt Enable
0: The IntPnd bit in the CANIFnMCTL register is unchanged after a
successful transmission of a frame.
1: The IntPnd bit in the CANIFnMCTL register is set after a successful
transmission of a frame.
0x0R/WTxIE11
Receive Interrupt Enable
0: The IntPnd bit in the CANIFnMCTL register is unchanged after a
successful reception of a frame.
1: The IntPnd bit in the CANIFnMCTL register is set after a successful
reception of a frame.
0x0R/WRxIE10
Remote Enable
0: At the reception of a Remote Frame, the TxRqst bit in the
CANIFnMCTL register is left unchanged.
1: At the reception of a Remote Frame, the TxRqst bit in the
CANIFnMCTL register is set.
0x0R/WRmtEn9
Transmit Request
0: This message object is not waiting for transmission.
1: The transmission of this message object is requested and is not yet
done.
0x0R/WTxRqst8
End of Buffer
0: Message object belongs to a FIFO Buffer and is not the last message
object of that FIFO Buffer.
1: Single message object or last message object of a FIFO Buffer.
This bit is used to concatenate two or more message objects (up to 32)
to build a FIFO buffer. For a single message object (thus not belonging
to a FIFO buffer), this bit must be set to 1.
0x0R/WEoB7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved6:4
Data Length Code
DescriptionValue
Specifies the number of bytes in the Data Frame.0x0-0x8
Defaults to a Data Frame with 8 bytes.0x9-0xF
The DLC bit in the CANIFnMCTL register of a message object must be
defined the same as in all the corresponding objects with the same
identifier at other nodes. When the message handler stores a data frame,
it writes DLC to the value given by the received message.
0x0R/WDLC3:0
413November 30, 2007
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LM3S2016 Microcontroller
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8
These registers contain the data to be sent or that has been received. In a CAN Data Frame, data
byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted
or received. In CAN's serial bit stream, the MSB of each byte is transmitted first.
CAN IF1 Data A1 (CANIF1DA1)
CAN0 base: 0x4004.0000
Offset 0x03C
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
Data
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Data
The CANIFnDA1 registers contain data bytes 1 and 0; CANIFnDA2
data bytes 3 and 2; CANIFnDB1 data bytes 5 and 4; and CANIFnDB2
data bytes 7 and 6.
0x00R/WData15:0
November 30, 2007414
Preliminary
Controller Area Network (CAN) Module
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104
The CANTXRQ1 and CANTXRQ2 registers hold the TxRqst bits of the 32 message objects. By
reading out these bits, the CPU can check which message object has a transmission request pending.
The TxRqst bit of a specific message object can be changed by three sources: (1) the CPU via the
CAN IFn Message Control (CANIFnMCTL) register, (2) the message handler state machine after
the reception of a Remote Frame, or (3) the message handler state machine after a successful
transmission.
The CANTXRQ1 register contains the TxRqst bit of the first 16 message objects in the message
RAM; the CANTXRQ2 register contains the TxRqst bit of the second 16 message objects.
CAN Transmission Request 1 (CANTXRQ1)
CAN0 base: 0x4004.0000
Offset 0x100
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TxRqst
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Transmission Request Bits
(of all message objects)
0: The message object is not waiting for transmission.
1: The transmission of the message object is requested and is not yet
done.
0x00ROTxRqst15:0
415November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124
The CANNWDA1 and CANNWDA2 registers hold the NewDat bits of the 32 message objects. By
reading these bits, the CPU can check which message object has its data portion updated. The
NewDat bit of a specific message object can be changed by three sources: (1) the CPU via the
CAN IFn Message Control (CANIFnMCTL) register, (2) the message handler state machine after
the reception of a Data Frame, or (3) the message handler state machine after a successful
transmission.
The CANNWDA1 register contains the NewDat bit of the first 16 message objects in the message
RAM; the CANNWDA2 register contains the NewDat bit of the second 16 message objects.
CAN New Data 1 (CANNWDA1)
CAN0 base: 0x4004.0000
Offset 0x120
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
NewDat
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
New Data Bits
(of all message objects)
0: No new data has been written into the data portion of this message
object by the message handler since the last time this flag was cleared
by the CPU.
1: The message handler or the CPU has written new data into the data
portion of this message object.
0x00RONewDat15:0
November 30, 2007416
Preliminary
Controller Area Network (CAN) Module
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144
The CANMSG1INT and CANMSG2INT registers hold the IntPnd bits of the 32 message objects.
By reading these bits, the CPU can check which message object has an interrupt pending. The
IntPnd bit of a specific message object can be changed through two sources: (1) the CPU via the
CAN IFn Message Control (CANIFnMCTL) register, or (2) the message handler state machine
after the reception or transmission of a frame.
This field is also encoded in the CAN Interrupt (CANINT) register.
The CANMSG1INT register contains the IntPnd bit of the first 16 message objects in the message
RAM; the CANMSG2INT register contains the IntPnd bit of the second 16 message objects.
CAN Message 1 Interrupt Pending (CANMSG1INT)
CAN0 base: 0x4004.0000
Offset 0x140
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IntPnd
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Interrupt Pending Bits
(of all message objects)
0: This message object is not the source of an interrupt.
1: This message object is the source of an interrupt.
0x00ROIntPnd15:0
417November 30, 2007
Preliminary
LM3S2016 Microcontroller
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164
The CANMSG1VAL and CANMSG2VAL registers hold the MsgVal bits of the 32 message objects.
By reading these bits, the CPU can check which message object is valid. The message value of a
specific message object can be changed with the CAN IFn Message Control (CANIFnMCTL)
register.
The CANMSG1VAL register contains the MsgVal bit of the first 16 message objects in the message
RAM; the CANMSG2VAL register contains the MsgVal bit of the second 16 message objects in
the message RAM.
CAN Message 1 Valid (CANMSG1VAL)
CAN0 base: 0x4004.0000
Offset 0x160
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
MsgVal
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000ROreserved31:16
Message Valid Bits
(of all message objects)
0: This message object is not configured and is ignored by the message
handler.
1: This message object is configured and should be considered by the
message handler.
0x00ROMsgVal15:0
November 30, 2007418
Preliminary
Controller Area Network (CAN) Module
16 Pin Diagram
Figure 16-1 on page 419 shows the pin diagram and pin-to-signal-name mapping.
Figure 16-1. Pin Connection Diagram
LM3S2016
38
39
40
41
42
43
44
45
46
47
48
49
50
1 75
26 100
2
27
5
6
3
4
7
8
11
9
10
99
28 98
29 97
30 96
31 95
32 94
33 93
34 92
35 91
36 90
73
72
74
71
69
68
70
67
65
66
12
13
14
17
18
15
16
19
20
23
21
22
24
25
64
37 89
88
87
86
85
84
83
82
81
80
79
78
77
76
63
61
60
62
59
57
56
58
55
53
54
52
51
ADC0
ADC1
VDDA
GNDA
ADC2
ADC3
LDO
VDD
GND
PD0/CAN0Rx
PD1/CAN0Tx
PD2/U1Rx
PD3/U1Tx
VDD25
GND
NC
NC
NC
NC
VDD
GND
PC7
PC6/CCP3
PC5
PC4
PA0/U0Rx
PA1/U0Tx
PA2/SSI0Clk
PA3/SSI0Fss
PA4/SSI0Rx
PA5/SSI0Tx
VDD
GND
PA6/CCP1
NC
NC
NC
VDD25
GND
NC
NC
NC
NC
VDD
GND
PF5
PF0
OSC0
OSC1
NC
NC
NC
NC
GND
VDD
VDD
GND
PF4
PF3
PF2
PF1
VDD25
GND
RST
CMOD0
PB0/CCP0
PB1/CCP2
VDD
GND
PB2/I2C0SCL
PB3/I2C0SDA
PE0
PE1
PE2
PE3
CMOD1
PC3/TDO/SWO
PC2/TDI
PC1/TMS/SWDIO
PC0/TCK/SWCLK
VDD
GND
NC
NC
NC
NC
GND
VDD25
PB7/TRST
PB6
PB5
PB4
VDD
GND
PD4
PD5
GNDA
VDDA
NC
NC
419November 30, 2007
Preliminary
LM3S2016 Microcontroller
17 Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register.
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
Table 17-1 on page 420 shows the pin-to-signal-name mapping, including functional characteristics
of the signals. Table 17-2 on page 423 lists the signals in alphabetical order by signal name.
Table 17-3 on page 427 groups the signals by functionality, except for GPIOs. Table 17-4 on page
430 lists the GPIO pins and their alternate functionality.
Table 17-1. Signals by Pin Number
DescriptionBuffer TypePin TypePin NamePin Number
Analog-to-digital converter input 0.AnalogIADC01
Analog-to-digital converter input 1.AnalogIADC12
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
Power-VDDA3
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
Power-GNDA4
Analog-to-digital converter input 2.AnalogIADC25
Analog-to-digital converter input 3.AnalogIADC36
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
Power-LDO7
Positive supply for I/O and some logic.Power-VDD8
Ground reference for logic and I/O pins.Power-GND9
GPIO port D bit 0TTLI/OPD010
CAN module 0 receiveTTLICAN0Rx
GPIO port D bit 1TTLI/OPD111
CAN module 0 transmitTTLOCAN0Tx
GPIO port D bit 2TTLI/OPD212
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
TTLIU1Rx
GPIO port D bit 3TTLI/OPD313
UART module 1 transmit. When in IrDA mode,
this signal has IrDA modulation.
TTLOU1Tx
November 30, 2007420
Preliminary
Signal Tables
DescriptionBuffer TypePin TypePin NamePin Number
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Power-VDD2514
Ground reference for logic and I/O pins.Power-GND15
No connect--NC16
No connect--NC17
No connect--NC18
No connect--NC19
Positive supply for I/O and some logic.Power-VDD20
Ground reference for logic and I/O pins.Power-GND21
GPIO port C bit 7TTLI/OPC722
GPIO port C bit 6TTLI/OPC623
Capture/Compare/PWM 3TTLI/OCCP3
GPIO port C bit 5TTLI/OPC524
GPIO port C bit 4TTLI/OPC425
GPIO port A bit 0TTLI/OPA026
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
TTLIU0Rx
GPIO port A bit 1TTLI/OPA127
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
TTLOU0Tx
GPIO port A bit 2TTLI/OPA228
SSI module 0 clockTTLI/OSSI0Clk
GPIO port A bit 3TTLI/OPA329
SSI module 0 frameTTLI/OSSI0Fss
GPIO port A bit 4TTLI/OPA430
SSI module 0 receiveTTLISSI0Rx
GPIO port A bit 5TTLI/OPA531
SSI module 0 transmitTTLOSSI0Tx
Positive supply for I/O and some logic.Power-VDD32
Ground reference for logic and I/O pins.Power-GND33
GPIO port A bit 6TTLI/OPA634
Capture/Compare/PWM 1TTLI/OCCP1
No connect--NC35
No connect--NC36
No connect--NC37
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Power-VDD2538
Ground reference for logic and I/O pins.Power-GND39
No connect--NC40
No connect--NC41
No connect--NC42
No connect--NC43
421November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionBuffer TypePin TypePin NamePin Number
Positive supply for I/O and some logic.Power-VDD44
Ground reference for logic and I/O pins.Power-GND45
GPIO port F bit 5TTLI/OPF546
GPIO port F bit 0TTLI/OPF047
Main oscillator crystal input or an external
clock reference input.
AnalogIOSC048
Main oscillator crystal output.AnalogIOSC149
No connect--NC50
No connect--NC51
No connect--NC52
No connect--NC53
Ground reference for logic and I/O pins.Power-GND54
Positive supply for I/O and some logic.Power-VDD55
Positive supply for I/O and some logic.Power-VDD56
Ground reference for logic and I/O pins.Power-GND57
GPIO port F bit 4TTLI/OPF458
GPIO port F bit 3TTLI/OPF359
GPIO port F bit 2TTLI/OPF260
GPIO port F bit 1TTLI/OPF161
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Power-VDD2562
Ground reference for logic and I/O pins.Power-GND63
System reset input.TTLIRST64
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
TTLI/OCMOD065
GPIO port B bit 0TTLI/OPB066
Capture/Compare/PWM 0TTLI/OCCP0
GPIO port B bit 1TTLI/OPB167
Capture/Compare/PWM 2TTLI/OCCP2
Positive supply for I/O and some logic.Power-VDD68
Ground reference for logic and I/O pins.Power-GND69
GPIO port B bit 2TTLI/OPB270
I2C module 0 clockODI/OI2C0SCL
GPIO port B bit 3TTLI/OPB371
I2C module 0 dataODI/OI2C0SDA
GPIO port E bit 0TTLI/OPE072
GPIO port E bit 1TTLI/OPE173
GPIO port E bit 2TTLI/OPE274
GPIO port E bit 3TTLI/OPE375
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
TTLI/OCMOD176
November 30, 2007422
Preliminary
Signal Tables
DescriptionBuffer TypePin TypePin NamePin Number
GPIO port C bit 3TTLI/OPC377
JTAG TDO and SWOTTLOTDO
JTAG TDO and SWOTTLOSWO
GPIO port C bit 2TTLI/OPC278
JTAG TDITTLITDI
GPIO port C bit 1TTLI/OPC179
JTAG TMS and SWDIOTTLI/OTMS
JTAG TMS and SWDIOTTLI/OSWDIO
GPIO port C bit 0TTLI/OPC080
JTAG/SWD CLKTTLITCK
JTAG/SWD CLKTTLISWCLK
Positive supply for I/O and some logic.Power-VDD81
Ground reference for logic and I/O pins.Power-GND82
No connect--NC83
No connect--NC84
No connect--NC85
No connect--NC86
Ground reference for logic and I/O pins.Power-GND87
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Power-VDD2588
GPIO port B bit 7TTLI/OPB789
JTAG TRSTnTTLITRST
GPIO port B bit 6TTLI/OPB690
GPIO port B bit 5TTLI/OPB591
GPIO port B bit 4TTLI/OPB492
Positive supply for I/O and some logic.Power-VDD93
Ground reference for logic and I/O pins.Power-GND94
GPIO port D bit 4TTLI/OPD495
GPIO port D bit 5TTLI/OPD596
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
Power-GNDA97
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
Power-VDDA98
No connect--NC99
No connect--NC100
Table 17-2. Signals by Signal Name
DescriptionBuffer TypePin TypePin NumberPin Name
Analog-to-digital converter input 0.AnalogI1ADC0
423November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionBuffer TypePin TypePin NumberPin Name
Analog-to-digital converter input 1.AnalogI2ADC1
Analog-to-digital converter input 2.AnalogI5ADC2
Analog-to-digital converter input 3.AnalogI6ADC3
CAN module 0 receiveTTLI10CAN0Rx
CAN module 0 transmitTTLO11CAN0Tx
Capture/Compare/PWM 0TTLI/O66CCP0
Capture/Compare/PWM 1TTLI/O34CCP1
Capture/Compare/PWM 2TTLI/O67CCP2
Capture/Compare/PWM 3TTLI/O23CCP3
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
TTLI/O65CMOD0
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
TTLI/O76CMOD1
Ground reference for logic and I/O pins.Power-9GND
Ground reference for logic and I/O pins.Power-15GND
Ground reference for logic and I/O pins.Power-21GND
Ground reference for logic and I/O pins.Power-33GND
Ground reference for logic and I/O pins.Power-39GND
Ground reference for logic and I/O pins.Power-45GND
Ground reference for logic and I/O pins.Power-54GND
Ground reference for logic and I/O pins.Power-57GND
Ground reference for logic and I/O pins.Power-63GND
Ground reference for logic and I/O pins.Power-69GND
Ground reference for logic and I/O pins.Power-82GND
Ground reference for logic and I/O pins.Power-87GND
Ground reference for logic and I/O pins.Power-94GND
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
Power-4GNDA
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
Power-97GNDA
I2C module 0 clockODI/O70I2C0SCL
I2C module 0 dataODI/O71I2C0SDA
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
Power-7LDO
No connect--16NC
No connect--17NC
November 30, 2007424
Preliminary
Signal Tables
DescriptionBuffer TypePin TypePin NumberPin Name
No connect--18NC
No connect--19NC
No connect--35NC
No connect--36NC
No connect--37NC
No connect--40NC
No connect--41NC
No connect--42NC
No connect--43NC
No connect--50NC
No connect--51NC
No connect--52NC
No connect--53NC
No connect--83NC
No connect--84NC
No connect--85NC
No connect--86NC
No connect--99NC
No connect--100NC
Main oscillator crystal input or an external
clock reference input.
AnalogI48OSC0
Main oscillator crystal output.AnalogI49OSC1
GPIO port A bit 0TTLI/O26PA0
GPIO port A bit 1TTLI/O27PA1
GPIO port A bit 2TTLI/O28PA2
GPIO port A bit 3TTLI/O29PA3
GPIO port A bit 4TTLI/O30PA4
GPIO port A bit 5TTLI/O31PA5
GPIO port A bit 6TTLI/O34PA6
GPIO port B bit 0TTLI/O66PB0
GPIO port B bit 1TTLI/O67PB1
GPIO port B bit 2TTLI/O70PB2
GPIO port B bit 3TTLI/O71PB3
GPIO port B bit 4TTLI/O92PB4
GPIO port B bit 5TTLI/O91PB5
GPIO port B bit 6TTLI/O90PB6
GPIO port B bit 7TTLI/O89PB7
GPIO port C bit 0TTLI/O80PC0
GPIO port C bit 1TTLI/O79PC1
GPIO port C bit 2TTLI/O78PC2
GPIO port C bit 3TTLI/O77PC3
GPIO port C bit 4TTLI/O25PC4
GPIO port C bit 5TTLI/O24PC5
425November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionBuffer TypePin TypePin NumberPin Name
GPIO port C bit 6TTLI/O23PC6
GPIO port C bit 7TTLI/O22PC7
GPIO port D bit 0TTLI/O10PD0
GPIO port D bit 1TTLI/O11PD1
GPIO port D bit 2TTLI/O12PD2
GPIO port D bit 3TTLI/O13PD3
GPIO port D bit 4TTLI/O95PD4
GPIO port D bit 5TTLI/O96PD5
GPIO port E bit 0TTLI/O72PE0
GPIO port E bit 1TTLI/O73PE1
GPIO port E bit 2TTLI/O74PE2
GPIO port E bit 3TTLI/O75PE3
GPIO port F bit 0TTLI/O47PF0
GPIO port F bit 1TTLI/O61PF1
GPIO port F bit 2TTLI/O60PF2
GPIO port F bit 3TTLI/O59PF3
GPIO port F bit 4TTLI/O58PF4
GPIO port F bit 5TTLI/O46PF5
System reset input.TTLI64RST
SSI module 0 clockTTLI/O28SSI0Clk
SSI module 0 frameTTLI/O29SSI0Fss
SSI module 0 receiveTTLI30SSI0Rx
SSI module 0 transmitTTLO31SSI0Tx
JTAG/SWD CLKTTLI80SWCLK
JTAG TMS and SWDIOTTLI/O79SWDIO
JTAG TDO and SWOTTLO77SWO
JTAG/SWD CLKTTLI80TCK
JTAG TDITTLI78TDI
JTAG TDO and SWOTTLO77TDO
JTAG TMS and SWDIOTTLI/O79TMS
JTAG TRSTnTTLI89TRST
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
TTLI26U0Rx
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
TTLO27U0Tx
UART module 1 receive. When in IrDA mode,
this signal has IrDA modulation.
TTLI12U1Rx
UART module 1 transmit. When in IrDA mode,
this signal has IrDA modulation.
TTLO13U1Tx
Positive supply for I/O and some logic.Power-8VDD
Positive supply for I/O and some logic.Power-20VDD
Positive supply for I/O and some logic.Power-32VDD
Positive supply for I/O and some logic.Power-44VDD
Positive supply for I/O and some logic.Power-55VDD
November 30, 2007426
Preliminary
Signal Tables
DescriptionBuffer TypePin TypePin NumberPin Name
Positive supply for I/O and some logic.Power-56VDD
Positive supply for I/O and some logic.Power-68VDD
Positive supply for I/O and some logic.Power-81VDD
Positive supply for I/O and some logic.Power-93VDD
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Power-14VDD25
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Power-38VDD25
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Power-62VDD25
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Power-88VDD25
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
Power-3VDDA
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
Power-98VDDA
Table 17-3. Signals by Function, Except for GPIO
DescriptionBuffer
Type
Pin TypePin
Number
Pin NameFunction
Analog-to-digital converter input 0.AnalogI1ADC0ADC
Analog-to-digital converter input 1.AnalogI2ADC1
Analog-to-digital converter input 2.AnalogI5ADC2
Analog-to-digital converter input 3.AnalogI6ADC3
CAN module 0 receiveTTLI10CAN0RxController Area
Network CAN module 0 transmitTTLO11CAN0Tx
Capture/Compare/PWM 0TTLI/O66CCP0General-Purpose
Timers Capture/Compare/PWM 1TTLI/O34CCP1
Capture/Compare/PWM 2TTLI/O67CCP2
Capture/Compare/PWM 3TTLI/O23CCP3
I2C module 0 clockODI/O70I2C0SCLI2C
I2C module 0 dataODI/O71I2C0SDA
427November 30, 2007
Preliminary
LM3S2016 Microcontroller
DescriptionBuffer
Type
Pin TypePin
Number
Pin NameFunction
JTAG/SWD CLKTTLI80SWCLKJTAG/SWD/SWO
JTAG TMS and SWDIOTTLI/O79SWDIO
JTAG TDO and SWOTTLO77SWO
JTAG/SWD CLKTTLI80TCK
JTAG TDITTLI78TDI
JTAG TDO and SWOTTLO77TDO
JTAG TMS and SWDIOTTLI/O79TMS
November 30, 2007428
Preliminary
Signal Tables
DescriptionBuffer
Type
Pin TypePin
Number
Pin NameFunction
Ground reference for logic and I/O pins.Power-9GNDPower
Ground reference for logic and I/O pins.Power-15GND
Ground reference for logic and I/O pins.Power-21GND
Ground reference for logic and I/O pins.Power-33GND
Ground reference for logic and I/O pins.Power-39GND
Ground reference for logic and I/O pins.Power-45GND
Ground reference for logic and I/O pins.Power-54GND
Ground reference for logic and I/O pins.Power-57GND
Ground reference for logic and I/O pins.Power-63GND
Ground reference for logic and I/O pins.Power-69GND
Ground reference for logic and I/O pins.Power-82GND
Ground reference for logic and I/O pins.Power-87GND
Ground reference for logic and I/O pins.Power-94GND
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
Power-4GNDA
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
Power-97GNDA
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. When the on-chip LDO is
used to provide power to the logic, the LDO pin
must also be connected to the VDD25 pins at the
board level in addition to the decoupling
capacitor(s).
Power-7LDO
Positive supply for I/O and some logic.Power-8VDD
Positive supply for I/O and some logic.Power-20VDD
Positive supply for I/O and some logic.Power-32VDD
Positive supply for I/O and some logic.Power-44VDD
Positive supply for I/O and some logic.Power-55VDD
Positive supply for I/O and some logic.Power-56VDD
Positive supply for I/O and some logic.Power-68VDD
Positive supply for I/O and some logic.Power-81VDD
Positive supply for I/O and some logic.Power-93VDD
Positive supply for most of the logic function,
including the processor core and most peripherals.
Power-14VDD25
Positive supply for most of the logic function,
including the processor core and most peripherals.
Power-38VDD25
Positive supply for most of the logic function,
including the processor core and most peripherals.
Power-62VDD25
Positive supply for most of the logic function,
including the processor core and most peripherals.
Power-88VDD25
Power-3VDDA
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LM3S2016 Microcontroller
DescriptionBuffer
Type
Pin TypePin
Number
Pin NameFunction
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
Power-98VDDA
SSI module 0 clockTTLI/O28SSI0ClkSSI
SSI module 0 frameTTLI/O29SSI0Fss
SSI module 0 receiveTTLI30SSI0Rx
SSI module 0 transmitTTLO31SSI0Tx
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
TTLI/O65CMOD0System Control &
Clocks
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
TTLI/O76CMOD1
Main oscillator crystal input or an external clock
reference input.
AnalogI48OSC0
Main oscillator crystal output.AnalogI49OSC1
System reset input.TTLI64RST
JTAG TRSTnTTLI89TRST
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
TTLI26U0RxUART
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
TTLO27U0Tx
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
TTLI12U1Rx
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
TTLO13U1Tx
Table 17-4. GPIO Pins and Alternate Functions
Multiplexed FunctionMultiplexed FunctionPin NumberGPIO Pin
U0Rx26PA0
U0Tx27PA1
SSI0Clk28PA2
SSI0Fss29PA3
SSI0Rx30PA4
SSI0Tx31PA5
CCP134PA6
CCP066PB0
CCP267PB1
I2C0SCL70PB2
I2C0SDA71PB3
92PB4
November 30, 2007430
Preliminary
Signal Tables
Multiplexed FunctionMultiplexed FunctionPin NumberGPIO Pin
91PB5
90PB6
TRST89PB7
SWCLKTCK80PC0
SWDIOTMS79PC1
TDI78PC2
SWOTDO77PC3
25PC4
24PC5
CCP323PC6
22PC7
CAN0Rx10PD0
CAN0Tx11PD1
U1Rx12PD2
U1Tx13PD3
95PD4
96PD5
72PE0
73PE1
74PE2
75PE3
47PF0
61PF1
60PF2
59PF3
58PF4
46PF5
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18 Operating Characteristics
Table 18-1. Temperature Characteristics
UnitValueSymbolCharacteristic
°C-40 to +85TA
Operating temperature rangea
a. Maximum storage temperature is 150°C.
Table 18-2. Thermal Characteristics
UnitValueSymbolCharacteristic
°C/W55.3ΘJA
Thermal resistance (junction to ambient)a
°CTA+ (PAVG • ΘJA)TJ
Average junction temperatureb
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
b. Power dissipation is a function of temperature.
November 30, 2007432
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Operating Characteristics
19 Electrical Characteristics
19.1 DC Characteristics
19.1.1 Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note: The device is not guaranteed to operate properly at the maximum ratings.
Table 19-1. Maximum Ratings
UnitValueSymbolCharacteristic
a
MaxMin
V40VDD
I/O supply voltage (VDD)
V40VDD25
Core supply voltage (VDD25)
V40VDDA
Analog supply voltage (VDDA)
V5.5-0.3VIN
Input voltage
mA25-IMaximum current per output pins
a. Voltages are measured with respect to GND.
Important: This device contains circuitry to protect the inputs against damage due to high-static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
19.1.2 Recommended DC Operating Conditions
Table 19-2. Recommended DC Operating Conditions
UnitMaxNomMinParameter NameParameter
V3.63.33.0I/O supply voltageVDD
V2.752.52.25Core supply voltageVDD25
V3.63.33.0Analog supply voltageVDDA
V5.0-2.0High-level input voltageVIH
V1.3--0.3Low-level input voltageVIL
VVDD
-0.8 * VDD
High-level input voltage for Schmitt trigger inputsVSIH
V0.2 * VDD
-0Low-level input voltage for Schmitt trigger inputsVSIL
V--2.4High-level output voltageVOH
V0.4--Low-level output voltageVOL
High-level source current, VOH=2.4 VIOH
mA--2.02-mA Drive
mA--4.04-mA Drive
mA--8.08-mA Drive
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UnitMaxNomMinParameter NameParameter
Low-level sink current, VOL=0.4 VIOL
mA--2.02-mA Drive
mA--4.04-mA Drive
mA--8.08-mA Drive
19.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics
Table 19-3. LDO Regulator Characteristics
UnitMaxNomMinParameter NameParameter
V2.752.52.25Programmable internal (logic) power supply output valueVLDOOUT
%-2%-Output voltage accuracy
µs100--Power-on timetPON
µs200--Time ontON
µs100--Time offtOFF
mV-50-Step programming incremental voltageVSTEP
µF3.0-1.0External filter capacitor size for internal power supplyCLDO
19.1.4 Power Specifications
The power measurements specified in the tables that follow are run on the core processor using
SRAM with the following specifications (except as noted):
■VDD = 3.3 V
■VDD25 = 2.50 V
■VDDA = 3.3 V
■Temperature = 25°C
■Clock Source (MOSC) =3.579545 MHz Crystal Oscillator
■Main oscillator (MOSC) = enabled
■Internal oscillator (IOSC) = disabled
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Electrical Characteristics
Table 19-4. Detailed Power Specifications
Unit2.5 V VDD25
3.3 V VDD, VDDA,
VDDPHY
ConditionsParameter NameParameter
MaxNomMaxNom
mApendinga
108pendinga
3VDD25 = 2.50 V
Code= while(1){} executed in Flash
Peripherals = All ON
System Clock = 50 MHz (with PLL)
Run mode 1 (Flash
loop)
IDD_RUN
mApendinga
53pendinga
0VDD25 = 2.50 V
Code= while(1){} executed in Flash
Peripherals = All OFF
System Clock = 50 MHz (with PLL)
Run mode 2 (Flash
loop)
mApendinga
102pendinga
3VDD25 = 2.50 V
Code= while(1){} executed in SRAM
Peripherals = All ON
System Clock = 50 MHz (with PLL)
Run mode 1 (SRAM
loop)
mApendinga
47pendinga
0VDD25 = 2.50 V
Code= while(1){} executed in SRAM
Peripherals = All OFF
System Clock = 50 MHz (with PLL)
Run mode 2 (SRAM
loop)
mApendinga
17pendinga
0VDD25 = 2.50 V
Peripherals = All OFF
System Clock = 50 MHz (with PLL)
Sleep modeIDD_SLEEP
mApendinga
0.18pendinga
0.143LDO = 2.25 V
Peripherals = All OFF
System Clock = IOSC30KHZ/64
Deep-Sleep modeIDD_DEEPSLEEP
a. Pending characterization completion.
19.1.5 Flash Memory Characteristics
Table 19-5. Flash Memory Characteristics
UnitMaxNomMinParameter NameParameter
cycles-100,00010,000Number of guaranteed program/erase cycles before failurea
PECYC
years--10Data retention at average operating temperature of 85˚CTRET
µs--20Word program timeTPROG
ms--20Page erase timeTERASE
ms--200Mass erase timeTME
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
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19.2 AC Characteristics
19.2.1 Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.
Figure 19-1. Load Conditions
CL= 50 pF
GND
pin
19.2.2 Clocks
Table 19-6. Phase Locked Loop (PLL) Characteristics
UnitMaxNomMinParameter NameParameter
MHz8.192-3.579545Crystal referencea
fref_crystal
MHz8.192-3.579545External clock referencea
fref_ext
MHz-400-PLL frequencyb
fpll
ms0.5--PLL lock timeTREADY
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration
(RCC) register.
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
Table 19-7. Clock Characteristics
UnitMaxNomMinParameter NameParameter
MHz15.6128.4Internal 12 MHz oscillator frequencyfIOSC
KHz393021Internal 30 KHz oscillator frequencyfIOSC30KHZ
MHz8-1Main oscillator frequencyfMOSC
ns1000-125Main oscillator periodtMOSC_per
MHz8-1Crystal reference using the main oscillator (PLL in BYPASS mode)
a
fref_crystal_bypass
MHz50-0External clock reference (PLL in BYPASS mode)a
fref_ext_bypass
MHz50-0System clockfsystem_clock
a. The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly.
Table 19-8. Crystal Characteristics
UnitsValueParameter Name
MHz3.5468Frequency
ppm±50±50±50±50Frequency tolerance
ppm/yr±5±5±5±5Aging
ParallelParallelParallelParallelOscillation mode
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Preliminary
Electrical Characteristics
UnitsValueParameter Name
ppm±25±25±25±25Temperature stability (0 - 85 °C)
pF63.555.637.027.8Motional capacitance (typ)
mH32.728.619.114.3Motional inductance (typ)
Ω220200160120Equivalent series resistance (max)
pF10101010Shunt capacitance (max)
pF16161616Load capacitance (typ)
µW100100100100Drive level (typ)
19.2.3 Analog-to-Digital Converter
Table 19-9. ADC Characteristics
UnitMaxNomMinParameter NameParameter
V3.0--Maximum single-ended, full-scale analog input voltageVADCIN
V0--Minimum single-ended, full-scale analog input voltage
V1.5--Maximum differential, full-scale analog input voltage
V-1.5--Minimum differential, full-scale analog input voltage
pF-1-Equivalent input capacitanceCADCIN
bits-10-ResolutionN
MHz987ADC internal clock frequencyfADC
tADCcyclesa
16--Conversion timetADCCONV
k samples/s563500438Conversion ratef ADCCONV
LSB±1--Integral nonlinearityINL
LSB±1--Differential nonlinearityDNL
LSB±1--OffsetOFF
LSB±1--GainGAIN
a. tADC= 1/fADC clock
19.2.4 I2C
Table 19-10. I2C Characteristics
UnitMaxNomMinParameter NameParameterParameter No.
system clocks--36Start condition hold timetSCH
I1a
system clocks--36Clock Low periodtLP
I2a
ns(see note b)--I2CSCL/I2CSDA rise time (VIL =0.5 V to V IH =2.4 V)tSRT
I3b
system clocks--2Data hold timetDH
I4a
ns109-I2CSCL/I2CSDA fall time (VIH =2.4 V to V IL =0.5 V)tSFT
I5c
system clocks--24Clock High timetHT
I6a
system clocks--18Data setup timetDS
I7a
system clocks--36Start condition setup time (for repeated start condition
only)
tSCSR
I8a
system clocks--24Stop condition setup timetSCS
I9a
a. Values depend on the value programmed into the TPR bit in the I2C Master Timer Period (I2CMTPR) register; a TPR
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
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LM3S2016 Microcontroller
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
c. Specified at a nominal 50 pF load.
Figure 19-2. I2C Timing
I2CSCL
I2CSDA
I1
I2
I4
I6
I7 I8
I5
I3 I9
19.2.5 Synchronous Serial Interface (SSI)
Table 19-11. SSI Characteristics
UnitMaxNomMinParameter NameParameterParameter No.
system clocks65024-2SSIClk cycle timetclk_per
S1
t clk_per-1/2-SSIClk high timetclk_high
S2
t clk_per-1/2-SSIClk low timetclk_low
S3
ns267.4-SSIClk rise/fall timetclkrf
S4
ns20-0Data from master valid delay timetDMd
S5
ns--20Data from master setup timetDMs
S6
ns--40Data from master hold timetDMh
S7
ns--20Data from slave setup timetDSs
S8
ns--40Data from slave hold timetDSh
S9
Figure 19-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
SSIClk
SSIFss
SSITx
SSIRx MSB LSB
S2
S3
S1
S4
4 to 16 bits
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Preliminary
Electrical Characteristics
Figure 19-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
0
SSIClk
SSIFss
SSITx
SSIRx
MSB LSB
MSB LSB
S2
S3
S1
8-bit control
4 to 16 bits output data
Figure 19-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
SSIClk
(SPO=1)
SSITx
(master)
SSIRx
(slave) LSB
SSIClk
(SPO=0)
S2
S1
S4
SSIFss
LSB
S3
MSB
S5
S6 S7
S9S8
MSB
19.2.6 JTAG and Boundary Scan
Table 19-12. JTAG Characteristics
UnitMaxNomMinParameter NameParameterParameter No.
MHz10-0TCK operational clock frequencyfTCK
J1
ns--100TCK operational clock periodtTCK
J2
ns-tTCK
-TCK clock Low timetTCK_LOW
J3
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UnitMaxNomMinParameter NameParameterParameter No.
ns-tTCK
-TCK clock High timetTCK_HIGH
J4
ns10-0TCK rise timetTCK_R
J5
ns10-0TCK fall timetTCK_F
J6
ns--20TMS setup time to TCK risetTMS_SU
J7
ns--20TMS hold time from TCK risetTMS_HLD
J8
ns--25TDI setup time to TCK risetTDI_SU
J9
ns--25TDI hold time from TCK risetTDI_HLD
J10
ns3523-2-mA driveTCK fall to Data Valid from High-ZJ11
tTDO_ZDV ns26154-mA drive
ns25148-mA drive
ns29188-mA drive with slew rate control
ns3521-2-mA driveTCK fall to Data Valid from Data ValidJ12
tTDO_DV ns25144-mA drive
ns24138-mA drive
ns28188-mA drive with slew rate control
ns119-2-mA driveTCK fall to High-Z from Data ValidJ13
tTDO_DVZ ns974-mA drive
ns868-mA drive
ns978-mA drive with slew rate control
ns--100TRST assertion timetTRST
J14
ns--10TRST setup time to TCK risetTRST_SU
J15
Figure 19-6. JTAG Test Clock Input Timing
TCK
J6 J5
J3 J4
J2
November 30, 2007440
Preliminary
Electrical Characteristics
Figure 19-7. JTAG Test Access Port (TAP) Timing
TDO Output Valid
TCK
TDO Output Valid
J12
TDO
TDI
TMS
TDI Input Valid TDI Input Valid
J13
J9 J10
TMS Input Valid
J9 J10
TMS Input Valid
J11
J7 J8J8J7
Figure 19-8. JTAG TRST Timing
TCK
J14 J15
TRST
19.2.7 General-Purpose I/O
Note: All GPIOs are 5 V-tolerant.
Table 19-13. GPIO Characteristics
UnitMaxNomMinConditionParameter NameParameter
ns2617-2-mA driveGPIO Rise Time (from 20% to 80% of VDD)tGPIOR
ns1394-mA drive
ns968-mA drive
ns12108-mA drive with slew rate control
ns2517-2-mA driveGPIO Fall Time (from 80% to 20% of VDD)tGPIOF
ns1284-mA drive
ns1068-mA drive
ns13118-mA drive with slew rate control
19.2.8 Reset
Table 19-14. Reset Characteristics
UnitMaxNomMinParameter NameParameterParameter No.
V-2.0-Reset thresholdVTH
R1
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LM3S2016 Microcontroller
UnitMaxNomMinParameter NameParameterParameter No.
V2.952.92.85Brown-Out thresholdVBTH
R2
ms-10-Power-On Reset timeoutTPOR
R3
µs-500-Brown-Out timeoutTBOR
R4
ms11-6Internal reset timeout after PORTIRPOR
R5
µs1-0Internal reset timeout after BORa
TIRBOR
R6
ms1-0Internal reset timeout after hardware reset (RST pin)TIRHWR
R7
µs20-2.5Internal reset timeout after software-initiated system reset a
TIRSWR
R8
µs20-2.5Internal reset timeout after watchdog reseta
TIRWDR
R9
ms100--Supply voltage (VDD) rise time (0V-3.3V)TVDDRISE
R10
µs--2Minimum RST pulse widthTMIN
R11
a. 20 * t MOSC_per
Figure 19-9. External Reset Timing (RST)
RST
/Reset
(Internal)
R7
R11
Figure 19-10. Power-On Reset Timing
VDD
/POR
(Internal)
/Reset
(Internal)
R3
R1
R5
Figure 19-11. Brown-Out Reset Timing
VDD
/BOR
(Internal)
/Reset
(Internal)
R2
R4
R6
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Electrical Characteristics
Figure 19-12. Software Reset Timing
R8
SW Reset
/Reset
(Internal)
Figure 19-13. Watchdog Reset Timing
WDOG
Reset
(Internal)
/Reset
(Internal)
R9
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LM3S2016 Microcontroller
20 Package Information
Figure 20-1. 100-Pin LQFP Package
Note: The following notes apply to the package drawing.
1. All dimensions shown in mm.
2. Dimensions shown are nominal with tolerances indicated.
3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.
November 30, 2007444
Preliminary
Package Information
Body +2.00 mm Footprint, 1.4 mm package thickness
100LLeadsSymbols
1.60Max.A
0.05 Min./0.15 Max.A1
1.40±0.05A2
16.00±0.20D
14.00±0.05D1
16.00±0.20E
14.00±0.05E1
0.60±0.15/-0.10L
0.50BASICe
0.22±0.05b
0˚~7˚===θ
0.08Max.ddd
0.08Max.ccc
MS-026JEDEC Reference Drawing
BEDVariation Designator
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LM3S2016 Microcontroller
A Serial Flash Loader
A.1 Serial Flash Loader
The Stellaris®serial flash loader is a preprogrammed flash-resident utility used to download code
to the flash memory of a device without the use of a debug interface. The serial flash loader uses
a simple packet interface to provide synchronous communication with the device. The flash loader
runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both
the data format and communication protocol are identical for both serial interfaces.
A.2 Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that interface
is used until the flash loader is reset or new code takes over. For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are disabled
until the device is reset.
A.2.1 UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris®device
which is calculated as follows:
Max Baud Rate = System Clock Frequency / 16
In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash loader
to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows
the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received
after at least twice the time required to transfer the two bytes, the host can resend another pattern
of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has
received a synchronization pattern correctly. For example, the time to wait for data back from the
flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate
of 115200, this time is 2*(20/115200) or 0.35 ms.
A.2.2 SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame
Formats” on page 308 in the SSI chapter for more information on formats for this transfer protocol.
Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI
clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running
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Serial Flash Loader
the flash loader. Since the host device is the master, the SSI on the flash loader device does not
need to determine the clock as it is provided directly by the host.
A.3 Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.3.1 Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
ucSize The first byte received holds the total size of the transfer including
the size and checksum bytes.
ucChecksum This holds a simple checksum of the bytes in the data buffer only.
The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3].
Data This is the raw data intended for the device, which is formatted in
some form of command interface. There should be ucSize–2
bytes of data provided in this buffer to or from the device.
A.3.2 Sending Packets
The actual bytes of the packet can be sent individually or all at once; the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing bytes
during flash programming. This limitation is discussed further in the section that describes the serial
flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA
(0x24)” on page 449).
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned
from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from
the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This
does not indicate that the actual contents of the command issued in the data portion of the packet
were valid, just that the packet was received correctly.
A.3.3 Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash loader
may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte
is the size of the packet followed by a checksum byte, and finally followed by the data itself. There
is no break in the data after the first non-zero byte is sent from the flash loader. Once the device
communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to
indicate that the transmission was successful. The appropriate response after sending a NAK to
the flash loader is to resend the command that failed and request the data again. If needed, the
host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the
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flash loader only accepts the first non-zero data as a valid response. This zero padding is needed
by the SSI interface in order to receive data to or from the flash loader.
A.4 Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
A.4.1 COMMAND_PING (0X20)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one
byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status,
the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.4.2 COMMAND_GET_STATUS (0x23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.4.3 COMMAND_DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit
values that are both transferred MSB first. The first 32-bit value is the address to start programming
data into, while the second is the 32-bit size of the data that will be sent. This command also triggers
an erase of the full area to be programmed so this command takes longer than other commands.
This results in a longer time to receive the ACK/NAK back from the board. This command should
be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size
are valid for the device running the flash loader.
The format of the packet to send this command is a follows:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]
November 30, 2007448
Preliminary
Serial Flash Loader
Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.4.4 COMMAND_SEND_DATA (0x24)
This command should only follow a COMMAND_DOWNLOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been
received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to
ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK
to this command, the flash loader does not increment the current address to allow retransmission
of the previous data.
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.4.5 COMMAND_RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.
Byte[0] = 7
Byte[1] = checksum(Bytes[2:6])
Byte[2] = COMMAND_RUN
Byte[3] = Execute Address[31:24]
Byte[4] = Execute Address[23:16]
Byte[5] = Execute Address[15:8]
Byte[6] = Execute Address[7:0]
A.4.6 COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set
up for the new code. It can also be used to reset the flash loader if a critical error occurs and the
host device wants to restart communication with the flash loader.
449November 30, 2007
Preliminary
LM3S2016 Microcontroller
Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the command
was received successfully and the part will be reset.
November 30, 2007450
Preliminary
Serial Flash Loader
B Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset -
CLASSVER
MINORMAJOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD
BORIOR
LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000
VADJ
RIS, type RO, offset 0x050, reset 0x0000.0000
BORRISPLLLRIS
IMC, type R/W, offset 0x054, reset 0x0000.0000
BORIMPLLLIM
MISC, type R/W1C, offset 0x058, reset 0x0000.0000
BORMISPLLLMIS
RESC, type R/W, offset 0x05C, reset -
EXTPORBORWDTSWLDO
RCC, type R/W, offset 0x060, reset 0x07A0.3AD1
USESYSDIV
SYSDIVACG
MOSCDISIOSCDISOSCSRCXTALBYPASSPWRDN
PLLCFG, type RO, offset 0x064, reset -
RF
RCC2, type R/W, offset 0x070, reset 0x0780.2800
SYSDIV2USERCC2
OSCSRC2BYPASS2PWRDN2
DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000
DSDIVORIDE
DSOSCSRC
DID1, type RO, offset 0x004, reset -
PARTNOFAMVER
QUALROHSPKGTEMPPINCOUNT
DC0, type RO, offset 0x008, reset 0x001F.001F
SRAMSZ
FLASHSZ
DC1, type RO, offset 0x010, reset 0x0101.329F
ADCCAN0
JTAGSWDSWOWDTPLLMPUMAXADCSPDMINSYSDIV
DC2, type RO, offset 0x014, reset 0x0003.1013
TIMER0TIMER1
UART0UART1SSI0I2C0
DC3, type RO, offset 0x018, reset 0x0F0F.0000
ADC0ADC1ADC2ADC3CCP0CCP1CCP2CCP3
451November 30, 2007
Preliminary
LM3S2016 Microcontroller
16171819202122232425262728293031
0123456789101112131415
DC4, type RO, offset 0x01C, reset 0x0000.00FF
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOH
RCGC0, type R/W, offset 0x100, reset 0x00000040
ADCCAN0
WDTMAXADCSPD
SCGC0, type R/W, offset 0x110, reset 0x00000040
ADCCAN0
WDTMAXADCSPD
DCGC0, type R/W, offset 0x120, reset 0x00000040
ADCCAN0
WDTMAXADCSPD
RCGC1, type R/W, offset 0x104, reset 0x00000000
TIMER0TIMER1
UART0UART1SSI0I2C0
SCGC1, type R/W, offset 0x114, reset 0x00000000
TIMER0TIMER1
UART0UART1SSI0I2C0
DCGC1, type R/W, offset 0x124, reset 0x00000000
TIMER0TIMER1
UART0UART1SSI0I2C0
RCGC2, type R/W, offset 0x108, reset 0x00000000
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOH
SCGC2, type R/W, offset 0x118, reset 0x00000000
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOH
DCGC2, type R/W, offset 0x128, reset 0x00000000
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOH
SRCR0, type R/W, offset 0x040, reset 0x00000000
ADCCAN0
WDT
SRCR1, type R/W, offset 0x044, reset 0x00000000
TIMER0TIMER1
UART0UART1SSI0I2C0
SRCR2, type R/W, offset 0x048, reset 0x00000000
GPIOAGPIOBGPIOCGPIODGPIOEGPIOFGPIOGGPIOH
Internal Memory
Flash Control Offset
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
OFFSET
FMD, type R/W, offset 0x004, reset 0x0000.0000
DATA
DATA
FMC, type R/W, offset 0x008, reset 0x0000.0000
WRKEY
WRITEERASEMERASECOMT
November 30, 2007452
Preliminary
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
ARISPRIS
FCIM, type R/W, offset 0x010, reset 0x0000.0000
AMASKPMASK
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
AMISCPMISC
Internal Memory
System Control Offset
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x31
USEC
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
DATANW
DBG0DBG1DATA
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
DATANW
DATA
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
DATANW
DATA
FMPRE1, type R/W, offset 0x204, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPRE2, type R/W, offset 0x208, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPRE3, type R/W, offset 0x20C, reset 0x0000.0000
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
FMPPE3, type R/W, offset 0x40C, reset 0x0000.0000
PROG_ENABLE
PROG_ENABLE
General-Purpose Input/Outputs (GPIOs)
453November 30, 2007
Preliminary
LM3S2016 Microcontroller
16171819202122232425262728293031
0123456789101112131415
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
GPIODATA, type R/W, offset 0x000, reset 0x0000.0000
DATA
GPIODIR, type R/W, offset 0x400, reset 0x0000.0000
DIR
GPIOIS, type R/W, offset 0x404, reset 0x0000.0000
IS
GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000
IBE
GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000
IEV
GPIOIM, type R/W, offset 0x410, reset 0x0000.0000
IME
GPIORIS, type RO, offset 0x414, reset 0x0000.0000
RIS
GPIOMIS, type RO, offset 0x418, reset 0x0000.0000
MIS
GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000
IC
GPIOAFSEL, type R/W, offset 0x420, reset -
AFSEL
GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF
DRV2
GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000
DRV4
GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000
DRV8
GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000
ODE
GPIOPUR, type R/W, offset 0x510, reset -
PUE
November 30, 2007454
Preliminary
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000
PDE
GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000
SRL
GPIODEN, type R/W, offset 0x51C, reset -
DEN
GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001
LOCK
LOCK
GPIOCR, type -, offset 0x524, reset -
CR
GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061
PID0
GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
General-Purpose Timers
455November 30, 2007
Preliminary
LM3S2016 Microcontroller
16171819202122232425262728293031
0123456789101112131415
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000
GPTMCFG
GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000
TAMRTACMRTAAMS
GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000
TBMRTBCMRTBAMS
GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000
TAENTASTALLTAEVENTRTCENTAOTETAPWMLTBENTBSTALLTBEVENTTBOTETBPWML
GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000
TATOIMCAMIMCAEIMRTCIMTBTOIMCBMIMCBEIM
GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000
TATORISCAMRISCAERISRTCRISTBTORISCBMRISCBERIS
GPTMMIS, type RO, offset 0x020, reset 0x0000.0000
TATOMISCAMMISCAEMISRTCMISTBTOMISCBMMISCBEMIS
GPTMICR, type W1C, offset 0x024, reset 0x0000.0000
TATOCINTCAMCINTCAECINTRTCCINTTBTOCINTCBMCINTCBECINT
GPTMTAILR, type R/W, offset 0x028, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TAILRH
TAILRL
GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF
TBILRL
GPTMTAMATCHR, type R/W, offset 0x030, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TAMRH
TAMRL
GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF
TBMRL
GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000
TAPSR
GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000
TBPSR
GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000
TAPSMR
GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000
TBPSMR
GPTMTAR, type RO, offset 0x048, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode)
TARH
TARL
November 30, 2007456
Preliminary
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF
TBRL
Watchdog Timer
Base 0x4000.0000
WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF
WDTLoad
WDTLoad
WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF
WDTValue
WDTValue
WDTCTL, type R/W, offset 0x008, reset 0x0000.0000
INTENRESEN
WDTICR, type WO, offset 0x00C, reset -
WDTIntClr
WDTIntClr
WDTRIS, type RO, offset 0x010, reset 0x0000.0000
WDTRIS
WDTMIS, type RO, offset 0x014, reset 0x0000.0000
WDTMIS
WDTTEST, type R/W, offset 0x418, reset 0x0000.0000
STALL
WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000
WDTLock
WDTLock
WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005
PID0
WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018
PID1
WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
457November 30, 2007
Preliminary
LM3S2016 Microcontroller
16171819202122232425262728293031
0123456789101112131415
WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Analog-to-Digital Converter (ADC)
Base 0x4003.8000
ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000
ASEN0ASEN1ASEN2ASEN3
ADCRIS, type RO, offset 0x004, reset 0x0000.0000
INR0INR1INR2INR3
ADCIM, type R/W, offset 0x008, reset 0x0000.0000
MASK0MASK1MASK2MASK3
ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000
IN0IN1IN2IN3
ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000
OV0OV1OV2OV3
ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000
EM0EM1EM2EM3
ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000
UV0UV1UV2UV3
ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210
SS0SS1SS2SS3
ADCPSSI, type WO, offset 0x028, reset -
SS0SS1SS2SS3
ADCSAC, type R/W, offset 0x030, reset 0x0000.0000
AVG
ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000
MUX4MUX5MUX6MUX7
MUX0MUX1MUX2MUX3
ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000
D4END4IE4D5END5IE5D6END6IE6D7END7IE7
D0END0IE0D1END1IE1D2END2IE2D3END3IE3
ADCSSFIFO0, type RO, offset 0x048, reset 0x0000.0000
DATA
November 30, 2007458
Preliminary
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
ADCSSFIFO1, type RO, offset 0x068, reset 0x0000.0000
DATA
ADCSSFIFO2, type RO, offset 0x088, reset 0x0000.0000
DATA
ADCSSFIFO3, type RO, offset 0x0A8, reset 0x0000.0000
DATA
ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100
TPTRHPTREMPTYFULL
ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100
TPTRHPTREMPTYFULL
ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100
TPTRHPTREMPTYFULL
ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100
TPTRHPTREMPTYFULL
ADCSSMUX1, type RO, offset 0x060, reset 0x0000.0000
MUX0MUX1MUX2MUX3
ADCSSMUX2, type RO, offset 0x080, reset 0x0000.0000
MUX0MUX1MUX2MUX3
ADCSSCTL1, type RO, offset 0x064, reset 0x0000.0000
D0END0IE0D1END1IE1D2END2IE2D3END3IE3
ADCSSCTL2, type RO, offset 0x084, reset 0x0000.0000
D0END0IE0D1END1IE1D2END2IE2D3END3IE3
ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000
MUX0
ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002
D0END0IE0
ADCTMLB, type RO, offset 0x100, reset 0x0000.0000
MUXDIFFCONTCNT
ADCTMLB, type WO, offset 0x100, reset 0x0000.0000
LB
Universal Asynchronous Receivers/Transmitters (UARTs)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UARTDR, type R/W, offset 0x000, reset 0x0000.0000
DATAFEPEBEOE
459November 30, 2007
Preliminary
LM3S2016 Microcontroller
16171819202122232425262728293031
0123456789101112131415
UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000
FEPEBEOE
UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000
DATA
UARTFR, type RO, offset 0x018, reset 0x0000.0090
BUSYRXFETXFFRXFFTXFE
UARTILPR, type R/W, offset 0x020, reset 0x0000.0000
ILPDVSR
UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000
DIVINT
UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000
DIVFRAC
UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000
BRKPENEPSSTP2FENWLENSPS
UARTCTL, type R/W, offset 0x030, reset 0x0000.0300
UARTENSIRENSIRLPLBETXERXE
UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012
TXIFLSELRXIFLSEL
UARTIM, type R/W, offset 0x038, reset 0x0000.0000
RXIMTXIMRTIMFEIMPEIMBEIMOEIM
UARTRIS, type RO, offset 0x03C, reset 0x0000.000F
RXRISTXRISRTRISFERISPERISBERISOERIS
UARTMIS, type RO, offset 0x040, reset 0x0000.0000
RXMISTXMISRTMISFEMISPEMISBEMISOEMIS
UARTICR, type W1C, offset 0x044, reset 0x0000.0000
RXICTXICRTICFEICPEICBEICOEIC
UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
November 30, 2007460
Preliminary
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011
PID0
UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Synchronous Serial Interface (SSI)
SSI0 base: 0x4000.8000
SSICR0, type R/W, offset 0x000, reset 0x0000.0000
DSSFRFSPOSPHSCR
SSICR1, type R/W, offset 0x004, reset 0x0000.0000
LBMSSEMSSOD
SSIDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
SSISR, type RO, offset 0x00C, reset 0x0000.0003
TFETNFRNERFFBSY
SSICPSR, type R/W, offset 0x010, reset 0x0000.0000
CPSDVSR
SSIIM, type R/W, offset 0x014, reset 0x0000.0000
RORIMRTIMRXIMTXIM
SSIRIS, type RO, offset 0x018, reset 0x0000.0008
RORRISRTRISRXRISTXRIS
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000
RORMISRTMISRXMISTXMIS
SSIICR, type W1C, offset 0x020, reset 0x0000.0000
RORICRTIC
461November 30, 2007
Preliminary
LM3S2016 Microcontroller
16171819202122232425262728293031
0123456789101112131415
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000
PID4
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000
PID5
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000
PID6
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000
PID7
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022
PID0
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000
PID1
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018
PID2
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001
PID3
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D
CID0
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0
CID1
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005
CID2
SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1
CID3
Inter-Integrated Circuit (I2C) Interface
I2C Master
I2C Master 0 base: 0x4002.0000
I2CMSA, type R/W, offset 0x000, reset 0x0000.0000
R/SSA
I2CMCS, type RO, offset 0x004, reset 0x0000.0000
BUSYERRORADRACKDATACKARBLSTIDLEBUSBSY
I2CMCS, type WO, offset 0x004, reset 0x0000.0000
RUNSTARTSTOPACK
I2CMDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
November 30, 2007462
Preliminary
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
TPR
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
IM
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
RIS
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
MIS
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
IC
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000
LPBKMFESFE
Inter-Integrated Circuit (I2C) Interface
I2C Slave
I2C Slave 0 base: 0x4002.0800
I2CSOAR, type R/W, offset 0x000, reset 0x0000.0000
OAR
I2CSCSR, type RO, offset 0x004, reset 0x0000.0000
RREQTREQFBR
I2CSCSR, type WO, offset 0x004, reset 0x0000.0000
DA
I2CSDR, type R/W, offset 0x008, reset 0x0000.0000
DATA
I2CSIMR, type R/W, offset 0x00C, reset 0x0000.0000
IM
I2CSRIS, type RO, offset 0x010, reset 0x0000.0000
RIS
I2CSMIS, type RO, offset 0x014, reset 0x0000.0000
MIS
I2CSICR, type WO, offset 0x018, reset 0x0000.0000
IC
Controller Area Network (CAN) Module
CAN0 base: 0x4004.0000
CANCTL, type R/W, offset 0x000, reset 0x0000.0001
INITIESIEEIEDARCCETest
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LM3S2016 Microcontroller
16171819202122232425262728293031
0123456789101112131415
CANSTS, type R/W, offset 0x004, reset 0x0000.0000
LECTxOKRxOKEPassEWarnBOff
CANERR, type RO, offset 0x008, reset 0x0000.0000
TECRECRP
CANBIT, type R/W, offset 0x00C, reset 0x0000.2301
BRPSJWTSeg1TSeg2
CANINT, type RO, offset 0x010, reset 0x0000.0000
IntId
CANTST, type R/W, offset 0x014, reset 0x0000.0000
BasicSilentLBackTxRx
CANBRPE, type R/W, offset 0x018, reset 0x0000.0000
BRPE
CANIF1CRQ, type RO, offset 0x020, reset 0x0000.0001
MNUMBusy
CANIF2CRQ, type RO, offset 0x080, reset 0x0000.0001
MNUMBusy
CANIF1CMSK, type RO, offset 0x024, reset 0x0000.0000
DataBDataA
TxRqst/NewDatClrIntPnd
ControlArbMaskWRNRD
CANIF2CMSK, type RO, offset 0x084, reset 0x0000.0000
DataBDataA
TxRqst/NewDatClrIntPnd
ControlArbMaskWRNRD
CANIF1MSK1, type RO, offset 0x028, reset 0x0000.FFFF
Msk
CANIF2MSK1, type RO, offset 0x088, reset 0x0000.FFFF
Msk
CANIF1MSK2, type RO, offset 0x02C, reset 0x0000.FFFF
MskMDirMXtd
CANIF2MSK2, type RO, offset 0x08C, reset 0x0000.FFFF
MskMDirMXtd
CANIF1ARB1, type RO, offset 0x030, reset 0x0000.0000
ID
CANIF2ARB1, type RO, offset 0x090, reset 0x0000.0000
ID
CANIF1ARB2, type RO, offset 0x034, reset 0x0000.0000
IDDirXtdMsgVal
November 30, 2007464
Preliminary
Register Quick Reference
16171819202122232425262728293031
0123456789101112131415
CANIF2ARB2, type RO, offset 0x094, reset 0x0000.0000
IDDirXtdMsgVal
CANIF1MCTL, type RO, offset 0x038, reset 0x0000.0000
DLCEoBTxRqstRmtEnRxIETxIEUMaskIntPndMsgLstNewDat
CANIF2MCTL, type RO, offset 0x098, reset 0x0000.0000
DLCEoBTxRqstRmtEnRxIETxIEUMaskIntPndMsgLstNewDat
CANIF1DA1, type R/W, offset 0x03C, reset 0x0000.0000
Data
CANIF1DA2, type R/W, offset 0x040, reset 0x0000.0000
Data
CANIF1DB1, type R/W, offset 0x044, reset 0x0000.0000
Data
CANIF1DB2, type R/W, offset 0x048, reset 0x0000.0000
Data
CANIF2DA1, type R/W, offset 0x09C, reset 0x0000.0000
Data
CANIF2DA2, type R/W, offset 0x0A0, reset 0x0000.0000
Data
CANIF2DB1, type R/W, offset 0x0A4, reset 0x0000.0000
Data
CANIF2DB2, type R/W, offset 0x0A8, reset 0x0000.0000
Data
CANTXRQ1, type RO, offset 0x100, reset 0x0000.0000
TxRqst
CANTXRQ2, type RO, offset 0x104, reset 0x0000.0000
TxRqst
CANNWDA1, type RO, offset 0x120, reset 0x0000.0000
NewDat
CANNWDA2, type RO, offset 0x124, reset 0x0000.0000
NewDat
CANMSG1INT, type RO, offset 0x140, reset 0x0000.0000
IntPnd
CANMSG2INT, type RO, offset 0x144, reset 0x0000.0000
IntPnd
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LM3S2016 Microcontroller
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0123456789101112131415
CANMSG1VAL, type RO, offset 0x160, reset 0x0000.0000
MsgVal
CANMSG2VAL, type RO, offset 0x164, reset 0x0000.0000
MsgVal
November 30, 2007466
Preliminary
Register Quick Reference
C Ordering and Contact Information
C.1 Ordering Information
L M 3 S n n n n – g p p s s – r r m
Part Number
Temperature
Package
Speed
Revision
Shipping Medium
I = -40 C to 85 C
T = Tape-and-reel
Omitted = Default shipping (tray or tube)
Omitted = Default to current shipping
revision
A0 = First all-layer mask
A1 = Metal layers update to A0
A2 = Metal layers update to A1
B0 = Second all-layer mask revision
RN = 28-pin SOIC
QN = 48-pin LQFP
QC = 100-pin LQFP
20 = 20 MHz
25 = 25 MHz
50 = 50 MHz
Table C-1. Part Ordering Information
DescriptionOrderable Part Number
Stellaris®LM3S2016 MicrocontrollerLM3S2016-IQC50
Stellaris®LM3S2016 MicrocontrollerLM3S2016-IQC50(T)
C.2 Kits
The Luminary Micro Stellaris®Family provides the hardware and software tools that engineers need
to begin development quickly.
■Reference Design Kits accelerate product development by providing ready-to-run hardware, and
comprehensive documentation including hardware design files:
http://www.luminarymicro.com/products/reference_design_kits/
■Evaluation Kits provide a low-cost and effective means of evaluating Stellaris®microcontrollers
before purchase:
http://www.luminarymicro.com/products/evaluation_kits/
■Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box:
http://www.luminarymicro.com/products/boards.html
See the Luminary Micro website for the latest tools available or ask your Luminary Micro distributor.
C.3 Company Information
Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3-based microcontrollers (MCUs).
Austin, Texas-based Luminary Micro is the lead partner for the Cortex-M3 processor, delivering the
world's first silicon implementation of the Cortex-M3 processor. Luminary Micro's introduction of the
467November 30, 2007
Preliminary
LM3S2016 Microcontroller
Stellaris® family of products provides 32-bit performance for the same price as current 8- and 16-bit
microcontroller designs. With entry-level pricing at $1.00 for an ARM technology-based MCU,
Luminary Micro's Stellaris product line allows for standardization that eliminates future architectural
upgrades or software tool changes.
Luminary Micro, Inc.
108 Wild Basin, Suite 350
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
sales@luminarymicro.com
C.4 Support Information
For support on Luminary Micro products, contact:
support@luminarymicro.com +1-512-279-8800, ext. 3
November 30, 2007468
Preliminary
Ordering and Contact Information
