LTC6954 Low Phase Noise, Triple Output Clock Distribution Divider/Driver Description Features n n n n n n n n n n Low Noise Clock Distribution: Suitable for High Speed/High Resolution ADC Clocking Additive Jitter < 20fsRMS (12kHz to 20MHz) Additive Jitter < 85fsRMS (10Hz to Nyquist) 1.8GHz Maximum Input Frequency (LTC6954-1 When DELAY = 0) 1.4GHz Maximum Input Frequency (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4) EZSyncTM Clock Synchronization Compatible Three Independent, Low Noise Outputs Four Output Combinations Available Three Independent Programmable Dividers Covering All Integers From 1 to 63 Three Independent Programmable Delays Covering All Integers From 0 to 63 -40C to 105C Junction Temperature Range The LTC(R)6954 is a family of very low phase noise clock distribution parts. Each part has three outputs and each output has an individually programmable frequency divider and delay. There are four members of the family, differing in their output logic signal type: LTC6954-1: Three LVPECL outputs LTC6954-2: Two LVPECL and one LVDS/CMOS outputs LTC6954-3: One LVPECL and two LVDS/CMOS outputs LTC6954-4: Three LVDS/CMOS outputs Each output is individually programmable to divide the input frequency by any integer from 1 to 63, and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50%, regardless of the divide number. The LVDS/CMOS outputs are jumper selectable via the OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output. Applications n n The LTC6954 also features Linear Technology's EZSync system for perfect clock synchronization and alignment every time. Clocking High Speed, High Resolution ADCs, DACs and Data Acquisition Systems Low Jitter Clock Distribution All device settings are controlled through an SPI-compatible serial port. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and EZSync is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 8319551, 8819472. Typical Application 0.1F Additive Phase Noise vs Offset Frequency, fIN = 622.08MHz, Mx[5:0] = 4, fOUTx = 155.52MHz 3.3V UP TO 1.4GHz 49.9 V+ IN+ 49.9 49.9 SYNC SYNC CONTROL OUT0SEL 3.3V OUT1SEL OUT2SEL SDO SPI SERIAL PORT SDI SERIAL PORT AND DIGITAL DELAY 0 TO 63 -120 LTC6954-3 IN- DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 OUT0+ OUT0- OUT1+ OUT1- OUT2+ OUT2- LVPECL OUTPUT FREQUENCY UP TO 1.8GHz LVDS OUTPUT FREQUENCY UP TO 1.4GHz CMOS OUTPUT FREQUENCY UP TO 250MHz SCLK CS ADDITIVE PHASE NOISE (dBc/Hz) n -130 -140 -150 -160 -170 -180 GND 6954 TA01a 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 6954 TA01b 6954f For more information www.linear.com/LTC6954 1 LTC6954 Absolute Maximum Ratings Pin Configuration (Note 1) OUT2SEL GND VA+ OUT1SEL GND TEMP TOP VIEW 36 35 34 33 32 31 VOUT2+ 1 30 VIN+ OUT2- 29 GND 2 OUT2+ 3 28 IN- + 4 27 IN+ + 5 26 GND VOUT2 VOUT1 OUT1- 6 25 VIN+ 37 GND OUT1+ 7 24 VA+ VOUT1+ 8 23 VA+ VOUT0+ 9 22 SYNC OUT0- 10 21 VD+ OUT0+ 11 20 SDI VOUT0+ 12 17 18 VD+ VA+ 16 CS 15 SDO 14 GND 19 SCLK 13 OUT0SEL Supply Voltages (VA+, VD+, VIN+, VOUT0+, VOUT1+ and VOUT2+ to GND).........................................................3.6V LTC6954-1, -2, -3 LVPECL Outputs OUTx Output Voltage High.......................VOUT+ + 0.3V OUTx Output Voltage Low...................... Source 25mA LTC6954-2, -3, -4 LVDS/CMOS Outputs OUTx...........................................-0.3V to (VA+ +0.3V) TEMP Input Current................................................10mA TEMP Low Voltage .................................................-0.3V Voltage on All Other Pins............... -0.3V to (VA+ + 0.3V) Operating Junction Temperature Range, TJ (Note 2) LTC6954I................................................ -40C to 105C Junction Temperature, TJMAX................................. 150C Storage Temperature Range................... -65C to 150C UFF PACKAGE 36-LEAD (4mm x 7mm) PLASTIC QFN 0.5mm LEAD PITCH TJMAX = 150C, JCbottom = 2C/W, JCtop = 18C/W EXPOSED PAD (PIN 37) IS GND, MUST BE SOLDERED TO PCB GND Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION JUNCTION TEMPERATURE RANGE LTC6954IUFF-1#PBF LTC6954IUFF-1#TRPBF 69541 36-Lead (4mm x 7mm) Plastic QFN -40C to 105C LTC6954IUFF-2#PBF LTC6954IUFF-2#TRPBF 69542 36-Lead (4mm x 7mm) Plastic QFN -40C to 105C LTC6954IUFF-3#PBF LTC6954IUFF-3#TRPBF 69543 36-Lead (4mm x 7mm) Plastic QFN -40C to 105C LTC6954IUFF-4#PBF LTC6954IUFF-4#TRPBF 69544 36-Lead (4mm x 7mm) Plastic QFN -40C to 105C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part markings, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 6954f 2 For more information www.linear.com/LTC6954 LTC6954 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V, unless otherwise specified. All voltages are with respect to GND. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1800 1400 MHz MHz 1.5 VP-P Input (IN+, IN - ) fIN Input Frequency LTC6954-1, DELx = 0 LTC6954-1 (DELx > 0), LTC6954-2, -3, -4 l l VIN Input Signal Level Single-Ended l 0.2 l 100 Input Slew Rate DCIN 0.8 V/s Input Duty Cycle 50 Self-Bias Voltage l 1.9 % 2.05 2.2 V Minimum Common Mode Level 400mVP-P Differential Input 1.8 V Maximum Common Mode Level 400mVP-P Differential Input 2.3 V Input Resistance Differential Input Capacitance Differential l 1.8 2.2 2.7 k 0.5 pF Output Divider (M) Mx[5:0] Divider Range M0[5:0], M1[5:0], M2[5:0] All Integers Included l 1 63 Cycles DELx[5:0] Divider Delay in Input Clock Cycles DEL0[5:0], DEL1[5:0], DEL2[5:0] All Integers Included l 0 63 Cycles LVPECL Clock Outputs fOUT Frequency LTC6954-1, DELx = 0 LTC6954-1 (DELx > 0), LTC6954-2, -3, -4 l l |VOD| Differential Voltage (Output Static) Single-Ended Termination = 50 to (VOUTx+ - 2V) l 640 Differential Termination = 100, Internal Bias On l 640 VCM Common Mode Voltage (Output Static) tRISE Rise Time, 20% to 80% tFALL Fall Time, 80% to 20% DCLVPECL Duty Cycle + - 2V) Single-Ended Termination = 50 to (VOUTx l Differential Termination = 100, Internal Bias On l 775 780 1800 1400 MHz MHz 950 mVPK 950 mVPK + VOUTx - 1.67 + VOUTx - 1.42 + VOUTx - 1.14 V VOUTx+ - 1.67 VOUTx+ - 1.42 VOUTx+ - 1.14 V Single-Ended Termination = 50 to (VOUTx+ - 2V) 110 ps Differential Termination = 100, Internal Bias On 110 ps Single-Ended Termination = 50 to (VOUTx+ - 2V) 110 ps Differential Termination = 100, Internal Bias On 110 ps Mx[5:0] = 1 DCIN % Mx[5:0] > 1 (Even or Odd) l 45 50 55 % 250 MHz CMOS Clock Outputs fOUT Frequency l VOH High Voltage (Output Static) 2.5mA Load l VOL Low Voltage (Output Static) 2.5mA Load l tRISE Rise Time, 20% to 80% CLOAD = 2pF, CMSINV = 1 tFALL Fall Time, 80% to 20% DCCMOS Duty Cycle V+ - 0.4 V 0.4 V 200 ps CLOAD = 2pF, CMSINV = 1 170 ps Mx[5:0] = 1 DCIN % Mx[5:0] > 1 (Even or Odd) l 45 50 55 % 6954f For more information www.linear.com/LTC6954 3 LTC6954 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V, unless otherwise specified. All voltages are with respect to GND. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LVDS Clock Outputs fOUT |VOD| |VOD| VOS Frequency Differential Voltage (Output Static) Delta VOD (Output Static) Offset Voltage (Output Static) Differential Termination = 100, 3.5mA Mode l 800 MHz Differential Termination = 50, 7mA Mode l 1400 MHz Differential Termination = 100, 3.5mA Mode l 290 370 450 mVPK Differential Termination = 50, 7mA Mode l 290 370 450 mVPK Differential Termination = 100, 3.5mA Mode l -30 30 mV Differential Termination = 50, 7mA Mode l -30 30 mV Differential Termination = 100, 3.5mA Mode l 1.16 1.23 1.32 Differential Termination = 50, 7mA Mode l 1.15 1.23 1.32 V V |VOS| Delta VOS (Output Static) Differential Termination = 100, 3.5mA Mode l -15 Differential Termination = 50, 7mA Mode l -15 tRISE Rise Time, 20% to 80% Differential Termination = 100, 3.5mA Mode Differential Termination = 50, 7mA Mode 120 ps tFALL Fall Time, 80% to 20% Differential Termination = 100, 3.5mA Mode 240 ps Differential Termination = 50, 7mA Mode 120 ps |ISA|, |ISB| Short-Circuit Current to Common Shorted to GND, 3.5mA Mode 16 mA Shorted to GND, 7mA Mode 25 mA |ISAB| Short-Circuit Current to Complementary 3.5mA Mode 4 mA 7mA Mode 8 mA DCLVDS Duty Cycle Mx[5:0] = 1 DCIN % 15 mV 15 mV 240 ps Mx[5:0] > 1 (Even or Odd) l 45 50 55 % Propagation Delay From IN to Any LVPECL Output Mx[5:0] = 1 l 290 360 480 ps Mx[5:0] > 1 l 360 430 550 ps Temperature Variation of the Propagation Delay From IN to Any LVPECL Output Mx[5:0] = 1 l 0.65 ps/C Mx[5:0] > 1 l 0.68 ps/C Propagation Delay From IN to Any LVDS Output, LVCSx = 1 (7mA Mode) Mx[5:0] = 1 l 350 420 545 ps Mx[5:0] > 1 l 415 480 625 ps Temperature Variation of the Propagation Delay From IN to Any LVDS Output, LVCSx = 1 (7mA Mode) Mx[5:0] = 1 l 0.8 ps/C Mx[5:0] > 1 l 0.85 ps/C Propagation Delay From IN to Any LVDS Output, LVCSx = 0 (3.5mA Mode) Mx[5:0] = 1 480 ps Mx[5:0] > 1 550 ps Temperature Variation of the Propagation Delay From IN to Any LVDS Output, LVCSx = 0 (3.5mA Mode) Mx[5:0] = 1 l 0.8 ps/C Mx[5:0] > 1 l 0.85 ps/C Output Propagation Delays tPD(LVPECL) tpd(LVDS) tpd(CMOS) Propagation Delay From IN to Any CMOS Output, Complementary Outputs (CMSINVx = 1) Mx[5:0] = 1 1.25 ns Mx[5:0] > 1 1.32 ns Temperature Variation of the Propagation Delay From IN to Any CMOS Output (CMSINVx = 1) Mx[5:0] = 1 l 1.3 ps/C Mx[5:0] > 1 l 1.4 ps/C 6954f 4 For more information www.linear.com/LTC6954 LTC6954 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V, unless otherwise specified. All voltages are with respect to GND. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Output Skews tSKEW Skew: Any LVPECL Output to Any LVPECL Output Mx[5:0], My[5:0] Both = 1 or Both > 1 IBIASx = 0 or 1 Skew: Any LVPECL Output to Any LVDS Output MLVPECL[5:0], MLVDS[5:0] Both = 1 or Both > 1 IBIASx = 0 or 1, LVCSy = 1 65 ps Skew: Any LVPECL Output to Any LVDS Output MLVPECL[5:0] = MLVDS[5:0] = 1 or Both > 1 IBIASx = 0 or 1, LVCSx = 0 120 ps Skew: Any LVPECL Output to Any CMOS Output MLVPECL[5:0], MCMOS[5:0] Both = 1 or Both > 1 IBIASx = 0 or 1, CMSINVy = 1 875 ps Skew: Any LVDS Output to Any LVDS Output Mx[5:0], My[5:0] Both = 1 or Both > 1 LVCSx = 1 for Both Outputs Skew: Any LVDS Output to Any LVDS Output Mx[5:0], My[5:0] Both = 1 or Both > 1 LVCSx = 0 for Both Outputs 5 ps Skew: Any LVDS Output (LVCSx = 1) to Mx[5:0], My[5:0] Both = 1 or Both > 1 Any LVDS Output (LVCSy = 0) LVCSx = 1, LVCSy = 0 50 ps 800 ps l l -50 50 -50 50 ps ps Skew: Any LVDS Output to Any CMOS Output MLVDS[5:0], MCMOS[5:0] Both = 1 or Both > 1 LVCSx = 1, CMSINV = 1 Skew: Any CMOS Output to Any CMOS Output Mx[5:0], My[5:0] Both = 1 or Both > 1 CMSINV = 1 5 ps Skew: Any CMOS Output to Any CMOS Output, the First Output is Complementary, the Second Output is In-Phase CMSINVx = 1, CMSINVy = 0 30 ps Additional Skew: Any Output to Any Output, Dividers Not the Same Mx[5:0] = 1, My[5:0] > 1 l 35 70 120 ps 6954f For more information www.linear.com/LTC6954 5 LTC6954 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V, unless otherwise specified. All voltages are with respect to GND. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltages VA+ Supply Range l 3.15 3.3 3.45 V VD+ Supply Range l 3.15 3.3 3.45 V l 3.15 3.3 3.45 V l 3.15 3.3 3.45 V + Supply Range VIN +, V VOUT0 Range OUT1 +, V OUT2 + Supply Supply Current (Sum of VA+, VD+, VIN+, VOUT0+, VOUT1+, VOUT2+ Supply Currents) LTC6954-1 LTC6954-2 LTC6954-3 LTC6954-4 ALL LTC6954 Variants fIN = 1400MHz, Power-Up Default Configuration, OUT0SEL = OUT1SEL = OUT2SEL = VA+, IBIAS On for All Outputs, Outputs Terminated with 100 Differential l 300 335 mA fIN = 1400MHz, Power-Up Default Configuration, OUT0SEL = OUT1SEL = OUT2SEL = GND, IBIAS Off for All Outputs, Outputs Terminated with 50 to (VOUTx+ - 2V) l 310 350 mA fIN = 1400MHz, Power-Up Default Configuration, OUT0SEL = OUT1SEL = OUT2SEL = VA+, IBIAS On for LVPECL Outputs, LVDS/CMOS = LVDS, Outputs Terminated with 100 Differential l 290 325 mA fIN = 1400MHz, Power-Up Default Configuration, OUT0SEL = OUT1SEL = VA+, OUT2SEL = GND, IBIAS On for LVPECL Outputs, LVDS/CMOS = CMOS, M2[5:0] = 28, fOUT2 = 50MHz, LVPECL Outputs Terminated with 100 Differential l 280 320 mA fIN = 1400MHz, Power-Up Default Configuration, OUT0SEL = OUT1SEL = OUT2SEL = VA+, IBIAS On for LVPECL Output, LVDS/CMOS = LVDS, Outputs Terminated with 100 Differential l 280 320 mA fIN = 1400MHz, Power-Up Default Configuration, OUT0SEL = VA+, OUT1SEL = OUT2SEL = GND, IBIAS On for LVPECL Output, LVDS/CMOS = CMOS, M1[5:0] = M2[5:0] = 28, fOUT1 = fOUT2 = 50MHz, LVPECL Output Terminated with 100 Differential l 278 315 mA fIN = 1400MHz, Power-Up Default Configuration, OUT0SEL = OUT1SEL = OUT2SEL = VA+, LVDS/CMOS = LVDS, Outputs Terminated with 100 Differential l 270 315 fIN = 1400MHz, Power-Up Default Configuration, OUT0SEL = OUT1SEL = OUT2SEL = GND, LVDS/CMOS = CMOS, M0[5:0], M1[5:0] = M2[5:0] = 28, fOUT0 = fOUT1 = fOUT2 = 50MHz l 282 310 PD(ALL) = 1 0.8 mA mA 6954f 6 For more information www.linear.com/LTC6954 LTC6954 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V, unless otherwise specified. All voltages are with respect to GND. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Current Delta (Note 3) Output Divider On, LVPECL Output Output Driver Only, LVPECL Output Driver Only, LVDS Output Driver Only, CMOS PD_DIVx = 0, Mx[5:0] = 1, PD_OUTx = 1 l 28 32 mA PD_DIVx = 0, Mx[5:0] > 1, PD_OUTx = 1 l 46 54 mA PD_OUTx = 0, Termination = 50 to (VOUTx l 43 50 mA PD_OUTx = 0, IBIASx = 1 (Internal Bias On) l 39 46 mA PD_OUTx = 0, No Internal/External Bias l 19 24 mA PD_OUTx = 0, 3.5mA Mode, LVCSx = 0 l 31 37 mA PD_OUTx = 0, 7mA Mode, LVCSx = 1 l 48 58 mA PD_OUTx = 0, CMOS at 50MHz l 35 43 mA + - 2V) Digital Inputs (CS, SDI, SCLK, SYNC, OUT0SEL, OUT1SEL, OUT2SEL) VIH Input High Voltage l VIL Input Low Voltage l VIHYS Input Voltage Hysteresis 1.55 0.8 CS, SDI and SCLK Only Input Current V 250 l -1 V mV 1 A -1.5 mA Digital Outputs (SDO) IOH High Level Output Current SDO, VOH = VD+ - 400mV l IOL Low Level Output Current SDO, VOL = 400mV l 2.2 l -1 SDO Hi-Z Current -2.4 3.4 mA 1 A Digital Timing Specifications (See Figure 11 and Figure 12) tCKH SCLK HIGH Pulse Width l 25 ns tCKL SCLK LOW Pulse Width l 25 ns tCSS CS Setup Time l 10 ns tCSH CS HIGH Pulse Width l 10 ns tCS SDI to SCLK Setup Time l 6 ns tCH SDI to SCLK Hold Time l 6 ns l 1 tDO SDO Propagation Delay tSYNCH SYNC HIGH Pulse Width tSYNCL Minimum SYNC LOW Pulse Width CLOAD = 10pF Before Next SYNC HIGH Pulse 16 ns ms 1 ms 6954f For more information www.linear.com/LTC6954 7 LTC6954 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V, unless otherwise specified. All voltages are with respect to GND. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LVPECL Additive Phase Noise/Time Jitter (Note 5) Phase Noise: fIN = 622.08MHz, Mx[5:0] = 1, fOUT = 622.08MHz 10Hz Offset -130 dBc/Hz 100Hz Offset -139 dBc/Hz 1kHz Offset -148 dBc/Hz 10kHz Offset -156 dBc/Hz 100kHz Offset -158 dBc/Hz >1MHz Offset -158 dBc/Hz Jitter: fIN = 622.08MHz, Mx[5:0] = 1, fOUT = 622.08MHz 12kHz to 20MHz Integration Bandwidth 20 fsRMS 10Hz to 311.04MHz Integration Bandwidth 80 fsRMS Phase Noise: fIN = 622.08MHz, Mx[5:0] = 4, fOUT = 155.52MHz 10Hz Offset -138 dBc/Hz 100Hz Offset -147 dBc/Hz 1kHz Offset -156 dBc/Hz 10kHz Offset -163 dBc/Hz 100kHz Offset -165 dBc/Hz >1MHz Offset -165 dBc/Hz Jitter: fIN = 622.08MHz, Mx[5:0] = 4, fOUT = 155.52MHz 12kHz to 20MHz Integration Bandwidth 36 fsRMS 10Hz to 77.75MHz Integration Bandwidth 72 fsRMS Phase Noise: fIN = 622.08MHz, Mx[5:0] = 16, fOUT = 38.88MHz 10Hz Offset -147 dBc/Hz 100Hz Offset -159 dBc/Hz 1kHz Offset -167 dBc/Hz 10kHz Offset -170 dBc/Hz 100kHz Offset -171 dBc/Hz Phase Noise: fIN = 245.76MHz, Mx[5:0] = 1, fOUT = 245.76MHz >1MHz Offset -171 dBc/Hz 10Hz Offset -137 dBc/Hz 100Hz Offset -147 dBc/Hz 1kHz Offset -156 dBc/Hz 10kHz Offset -161 dBc/Hz 100kHz Offset -162 dBc/Hz >1MHz Offset -162 dBc/Hz 33 fsRMS Jitter: fIN = 245.76MHz, Mx[5:0] = 1, fOUT = 245.76MHz 12kHz to 20MHz Integration Bandwidth 81 fsRMS Phase Noise: fIN = 245.76MHz, Mx[5:0] = 4, fOUT = 61.44MHz 10Hz Offset -140 dBc/Hz 100Hz Offset -153 dBc/Hz 1kHz Offset -161 dBc/Hz 10kHz Offset -166 dBc/Hz 100kHz Offset -168 dBc/Hz >1MHz Offset -168 dBc/Hz 65 fsRMS Jitter: fIN = 245.76MHz, Mx[5:0] = 4, fOUT = 61.44MHz 10Hz to 122.88MHz Integration Bandwidth 12kHz to 20MHz Integration Bandwidth 6954f 8 For more information www.linear.com/LTC6954 LTC6954 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V, unless otherwise specified. All voltages are with respect to GND. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LVPECL Additive Phase Noise/Time Jitter (Note 5) Phase Noise: fIN = 1400MHz, Mx[5:0] = 1, fOUT = 1400MHz 10Hz Offset -126 dBc/Hz 100Hz Offset -132 dBc/Hz 1kHz Offset -143 dBc/Hz 10kHz Offset -149 dBc/Hz 100kHz Offset -152.5 dBc/Hz >1MHz Offset -152.5 dBc/Hz Jitter: fIN = 1400MHz, Mx[5:0] = 1, fOUT = 1400MHz 12kHz to 20MHz Integration Bandwidth 17 fsRMS 10Hz to 700MHz Integration Bandwidth 100 fsRMS Phase Noise: fIN = 1400MHz, Mx[5:0] = 4, fOUT = 350MHz 10Hz Offset -132 dBc/Hz 100Hz Offset -139 dBc/Hz 1kHz Offset -151 dBc/Hz 10kHz Offset -157 dBc/Hz 100kHz Offset -160 dBc/Hz >1MHz Offset Jitter: fIN = 1400MHz, Mx[5:0] = 4, fOUT = 350MHz -160 dBc/Hz 12kHz to 20MHz Integration Bandwidth 29 fsRMS 10Hz to 175MHz Integration Bandwidth 85 fsRMS 10Hz Offset -130 dBc/Hz 100Hz Offset -138 dBc/Hz 1kHz Offset -148 dBc/Hz 10kHz Offset -156 dBc/Hz 100kHz Offset -157.5 dBc/Hz >1MHz Offset -157.5 dBc/Hz 21 fsRMS LVDS Additive Phase Noise/Time Jitter LVCS = 1 (Note 5) Phase Noise: fIN = 622.08MHz, Mx[5:0] = 1, fOUT = 622.08MHz Jitter: fIN = 622.08MHz, Mx[5:0] = 1, fOUT = 622.08MHz 12kHz to 20MHz Integration Bandwidth 83 fsRMS Phase Noise: fIN = 622.08MHz, Mx[5:0] = 4, fOUT = 155.52MHz 10Hz Offset -140 dBc/Hz 100Hz Offset -147 dBc/Hz 1kHz Offset -157 dBc/Hz 10kHz Offset -163 dBc/Hz 100kHz Offset -165 dBc/Hz >1MHz Offset -165 dBc/Hz 36 fsRMS 10Hz to 311.04MHz Integration Bandwidth Jitter: fIN = 622.08MHz, Mx[5:0] = 4, fOUT = 155.52MHz 12kHz to 20MHz Integration Bandwidth 72 fsRMS Phase Noise: fIN = 622.08MHz, Mx[5:0] = 16, fOUT = 38.88MHz 10Hz Offset -147 dBc/Hz 100Hz Offset -159 dBc/Hz 1kHz Offset -166 dBc/Hz 10kHz Offset -170 dBc/Hz 100kHz Offset -170 dBc/Hz >1MHz Offset -170 dBc/Hz 10Hz to 77.75MHz Integration Bandwidth 6954f For more information www.linear.com/LTC6954 9 LTC6954 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V, unless otherwise specified. All voltages are with respect to GND. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LVDS Additive Phase Noise/Time Jitter LVCS = 1 (Note 5) Phase Noise: fIN = 245.76MHz, Mx[5:0] = 1, fOUT = 245.76MHz 10Hz Offset -138 dBc/Hz 100Hz Offset -146 dBc/Hz 1kHz Offset -155 dBc/Hz 10kHz Offset -160 dBc/Hz 100kHz Offset -162 dBc/Hz >1MHz Offset -162 dBc/Hz 34 fsRMS Jitter: fIN = 245.76MHz, Mx[5:0] = 1, fOUT = 245.76MHz 12kHz to 20MHz Integration Bandwidth 83 fsRMS Phase Noise: fIN = 245.76MHz, Mx[5:0] = 4, fOUT = 61.44MHz 10Hz Offset -142 dBc/Hz 100Hz Offset -153 dBc/Hz 1kHz Offset -162 dBc/Hz 10kHz Offset -167 dBc/Hz 100kHz Offset -168 dBc/Hz >1MHz Offset -168 dBc/Hz 65 fsRMS 10Hz to 122.88MHz Integration Bandwidth Jitter: fIN = 245.76MHz, Mx[5:0] = 4, fOUT = 61.4MHz 12kHz to 20MHz Integration Bandwidth Phase Noise: fIN = 1400MHz, Mx[5:0] = 1, fOUT = 1400MHz 10Hz Offset -121 dBc/Hz 100Hz Offset -133 dBc/Hz 1kHz Offset -142 dBc/Hz 10kHz Offset -148 dBc/Hz 100kHz Offset -152 dBc/Hz >1MHz Offset -152 dBc/Hz 18 fsRMS Jitter: fIN = 1400MHz, Mx[5:0] = 1, fOUT = 1400MHz 12kHz to 20MHz Integration Bandwidth 10Hz to 700MHz Integration Bandwidth 109 fsRMS Phase Noise: fIN = 1400MHz, Mx[5:0] = 4, fOUT = 350MHz 10Hz Offset -129 dBc/Hz 100Hz Offset -137 dBc/Hz 1kHz Offset -148 dBc/Hz 10kHz Offset -156 dBc/Hz 100kHz Offset -159 dBc/Hz >1MHz Offset -160 dBc/Hz 12kHz to 20MHz Integration Bandwidth 30 fsRMS 10Hz to 175MHz Integration Bandwidth 90 fsRMS Jitter: fIN = 1400MHz, Mx[5:0] = 4, fOUT = 350MHz 6954f 10 For more information www.linear.com/LTC6954 LTC6954 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V, unless otherwise specified. All voltages are with respect to GND. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LVDS Additive Phase Noise/Time Jitter LVCS = 0 (Note 5) Phase Noise: fIN = 622.08MHz, Mx[5:0] = 1, fOUT = 622.08MHz 10Hz Offset -123 dBc/Hz 100Hz Offset -135 dBc/Hz 1kHz Offset -146 dBc/Hz 10kHz Offset -151 dBc/Hz 100kHz Offset -153 dBc/Hz >1MHz Offset -153 dBc/Hz 36 fsRMS Jitter: fIN = 622.08MHz, Mx[5:0] = 1, fOUT = 622.08MHz 12kHz to 20MHz Integration Bandwidth 10Hz to 311.04MHz Integration Bandwidth 140 fsRMS Phase Noise: fIN = 622.08MHz, Mx[5:0] = 4, fOUT = 155.52MHz 10Hz Offset -135 dBc/Hz 100Hz Offset -146 dBc/Hz 1kHz Offset -154 dBc/Hz 10kHz Offset -160 dBc/Hz 100kHz Offset -161 dBc/Hz >1MHz Offset -161 dBc/Hz 29 fsRMS Jitter: fIN = 622.08MHz, Mx[5:0] = 4, fOUT = 155.52MHz 12kHz to 20MHz Integration Bandwidth 10Hz to 77.75MHz Integration Bandwidth 114 fsRMS Phase Noise: fIN = 622.08MHz, Mx[5:0] = 16, fOUT = 38.88MHz 10Hz Offset -147 dBc/Hz 100Hz Offset -157 dBc/Hz 1kHz Offset -165 dBc/Hz 10kHz Offset -167 dBc/Hz 100kHz Offset -167 dBc/Hz >1MHz Offset -167 dBc/Hz 6954f For more information www.linear.com/LTC6954 11 LTC6954 Electrical Characteristics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V, unless otherwise specified. All voltages are with respect to GND. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Additive Phase Noise/Time Jitter (Note 5) Phase Noise: fIN = 622.08MHz, Mx[5:0] = 4, fOUT = 155.52MHz 10Hz Offset -129 dBc/Hz 100Hz Offset -143 dBc/Hz 1kHz Offset -158 dBc/Hz 10kHz Offset -161 dBc/Hz 100kHz Offset -162 dBc/Hz >1MHz Offset -162 dBc/Hz Jitter: fIN = 622.08MHz, Mx[5:0] = 4, fOUT = 155.52MHz 12kHz to 20MHz Integration Bandwidth 52 fsRMS 10Hz to 77.75MHz Integration Bandwidth 102 fsRMS Phase Noise: fIN = 245.76MHz, Mx[5:0] = 1, fOUT = 245.76MHz 10Hz Offset -129 dBc/Hz 100Hz Offset -139 dBc/Hz Jitter: fIN = 245.76MHz, Mx[5:0] = 1, fOUT = 245.76MHz Phase Noise: fIN = 245.76MHz, Mx[5:0] = 4, fOUT = 61.44MHz Jitter: fIN = 245.76MHz, Mx[5:0] = 4, fOUT = 61.44MHz 1kHz Offset -146 dBc/Hz 10kHz Offset -155 dBc/Hz 100kHz Offset -159 dBc/Hz >1MHz Offset -160 dBc/Hz 12kHz to 20MHz Integration Bandwidth 42 fsRMS 10Hz to 122.88MHz Integration Bandwidth 102 fsRMS 10Hz Offset -135 dBc/Hz 100Hz Offset -147 dBc/Hz 1kHz Offset -156 dBc/Hz 10kHz Offset -163 dBc/Hz 100kHz Offset -166 dBc/Hz >1MHz Offset -166 dBc/Hz 82 fsRMS 12kHz to 20MHz Integration Bandwidth Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6954I is guaranteed to meet specified performance limits over the full operating junction temperature range of -40C to 105C. Under maximum operating conditions, air flow or heat sinking may be required to maintain a junction temperature of 105C or lower. It is strongly recommended that the exposed pad (pin 37) be soldered directly to the ground plane with an array of thermal vias as described in the Applications Information section. Note 3: The supply current delta specifications refer to the amount of supply current that each individual block consumes. Powering on or off this circuit block adds or subtracts this much current from the total supply current consumed in any given configuration. Note 4: The skews are defined as the second listed output's transition relative to the first listed output's transition. If the second listed output transitions after the first listed output, the skew is positive. For the same divider setting, LVPECL outputs have nominally the same skew regardless of the IBIAS setting (IBIASx = 0 or 1), for the same divider setting, all LVDS and CMOS outputs transition after the LVPECL outputs, thus these skews are positive. For the same divider setting, all CMOS outputs transition after all LVDS outputs, thus these skews are positive. For the same divider setting, LVDS outputs with the 3.5mA current setting (LVCS = 0) transition after LVDS outputs with the 7mA current setting (LVCS = 1), thus these skews are positive. For the same divider setting, in-phase CMOS outputs (CMSINVx = 0) transition after complementary outputs (CMSINVx = 1), thus this skew is positive. For the same output type, outputs with the divider setting greater than one (Mx[5:0] > 1) transition after outputs with the divider equal to one (Mx[5:0] = 1), thus this additional skew is positive. Note 5: Additive phase noise and jitter are the phase noise added by the LTC6954. It does not include noise from the external signal source. 6954f 12 For more information www.linear.com/LTC6954 LTC6954 Typical Performance Characteristics VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V. TA = 25C, unless otherwise specified. All voltages are with respect to GND. LVPECL Differential Output at 800MHz, IBIAS Enabled, RTERM = 100 Differential 1.6 0.6 0.6 1.5 0.4 0.4 0.2 0 -0.2 -0.4 0.2 0 -0.2 -0.4 -0.6 0.5 1.0 1.5 2.0 TIME (ns) 2.5 -0.8 3.0 0.6 0.6 0.4 0.4 AMPLITUDE (VPP_DIFF) AMPLITUDE (VPP_DIFF) 0.8 0.2 0 -0.2 -0.4 3.0 0.4 0.4 0.3 0.3 AMPLITUDE (VPP_DIFF) 0.5 0.2 0.1 0 -0.1 -0.2 1.0 0.9 1.6 0 1 2 3 TIME (ns) 4 5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.6 6 5 6954 G07 2000 6954 G06 0.80 -0.2 -0.5 500 1000 1500 FREQUENCY (MHz) 0 LVDS Differential Output Swing vs Frequency, ILVDS = 3.5mA, RTERM = 100 (Differential) 0 -0.4 2000 6954 G03 LVPECL Differential Output Swing vs Frequency, IBIAS Disabled, RTERM = 50 to V+ - 2V 6954 G05 -0.1 -0.4 500 1000 1500 FREQUENCY (MHz) 0 0.7 0.1 -0.3 4 1.1 6954 G02 0.2 -0.3 2 3 TIME (ns) 1.2 LVDS Differential Output at 300MHz, ILVDS = 3.5mA, RTERM = 100 (Differential) 0.5 1 1.3 1.5 6954 G04 LVDS Differential Output at 800MHz, ILVDS = 3.5mA, RTERM = 100 (Differential) 0 1.4 0.8 6 -0.4 -0.8 -0.5 5 -0.2 -0.8 2.5 4 0 -0.6 1.5 2.0 TIME (ns) 3 TIME (ns) 0.2 -0.6 1.0 2 LVPECL Differential Output at 800MHz, IBIAS Disabled, RTERM = 50 to V+ - 2V 0.8 0.5 1 6954 G01 LVPECL Differential Output at 1400MHz, IBIAS Disabled, RTERM = 50 to V+ - 2V 0 0 DIFFERENTIAL AMPLITUDE (VPP) 0 DIFFERENTIAL AMPLITUDE (VPP) -0.8 DIFFERENTIAL AMPLITUDE (VPP) 0.8 -0.6 AMPLITUDE (VPP_DIFF) LVPECL Differential Output Swing vs Frequency, IBIAS Enabled, RTERM = 100 Differential 0.8 AMPLITUDE (VPP_DIFF) AMPLITUDE (VPP_DIFF) LVPECL Differential Output at 1400MHz, IBIAS Enabled, RTERM = 100 Differential 0 2 4 6 TIME (ns) 8 10 12 6954 G08 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0 200 400 600 800 1000 1200 1400 FREQUENCY (MHz) 6954 G09 6954f For more information www.linear.com/LTC6954 13 LTC6954 Typical Performance Characteristics VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V. TA = 25C, unless otherwise specified. All voltages are with respect to GND. 0.5 0.8 0.4 0.6 AMPLITUDE (VPP_DIFF) 0.2 0.1 0 -0.1 -0.2 -0.3 0.4 0.2 0 -0.2 -0.4 -0.8 0 0.25 0.50 0.75 1.0 1.25 1.50 1.75 2.0 2.25 2.50 TIME (ns) 6954 G10 3.0 3.0 2.5 2.5 2.0 1.5 1.0 0.5 0 2 0 4 6 8 10 TIME (ns) 12 14 2 2.5 3 TIME (ns) 3.5 4 -140 -150 DIV = 4 DIV = 16 -170 0.60 0.55 0.50 0.45 500 0 6954 G11 1000 1500 FREQUENCY (MHz) 2000 6954 G12 CMOS Output Swing vs Frequency and CLOAD 2pF 3.0 1.5 1.0 -120 SINGLE-ENDED SINE WAVE INPUT +7dBm AT 1.4GHz -160 0.65 0.40 5 4.5 0.70 3.2 4.7pF 10pF 2.8 2.6 2.4 2.2 0 5 6954 G13 -130 -180 1.5 2.0 0 16 ADDITIVE PHASE NOISE (dBc/Hz) ADDITIVE PHASE NOISE (dBc/Hz) -120 1 0.5 LVPECL Output Additive Phase Noise, fIN = 1400MHz, IBIAS Enabled, RTERM = 100 Differential -110 0.5 0.75 CMOS Output at 100MHz, CMSINV = 1, CLOAD = 2pF AMPLITUDE (V) AMPLITUDE (V) CMOS Output at 250MHz, CMSINV = 1, CLOAD = 2pF 0 VPP SINGLE-ENDED (V) -0.5 0.80 -0.6 -0.4 LVDS Differential Output Swing vs Frequency, ILVDS = 7mA, RTERM = 100||100 (Differential) 10 15 20 25 TIME (ns) 30 2.0 40 35 LVPECL Output Additive Phase Noise, fIN = 622.08MHz, IBIAS Enabled, RTERM = 100 Differential -130 SINGLE-ENDED SINE WAVE INPUT +7dBm AT 622.08MHz -130 -140 -150 DIV = 1 -160 0 6954 G14 ADDITIVE PHASE NOISE (dBc/Hz) AMPLITUDE (VPP_DIFF) 0.3 LVDS Differential Output at 800MHz, ILVDS = 7mA, RTERM = 100||100 (Differential) DIFFERENTIAL AMPLITUDE (VPP) LVDS Differential Output at 1400MHz, ILVDS = 7mA, RTERM = 100||100 (Differential) DIV = 4 -170 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) 6954 G15 LVPECL Output Additive Phase Noise, fIN = 245.76MHz, IBIAS Enabled, RTERM = 100 Differential SINGLE-ENDED SINE WAVE INPUT +7dBm AT 245.76MHz -140 -150 DIV = 1 -160 DIV = 4 -170 DIV = 16 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 6954 G16 -180 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 6954 G17 -180 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 6954 G18 6954f 14 For more information www.linear.com/LTC6954 LTC6954 Typical Performance Characteristics TA = 25C, unless otherwise specified. All voltages are with respect to GND. LVPECL Output Additive Phase Noise, fIN = 622.08MHz, IBIAS Disabled, RTERM = 50 to V+ - 2V LVPECL Output Additive Phase Noise, fIN = 1400MHz, IBIAS Disabled, RTERM = 50 to V+ - 2V -120 -140 DIV = 1 -150 DIV = 4 -160 -170 -180 DIV = 16 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) DIV = 1 -150 DIV = 4 -160 DIV = 16 -170 -180 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10 ADDITIVE PHASE NOISE (dBc/Hz) ADDITIVE PHASE NOISE (dBc/Hz) -150 DIV = 4 DIV = 16 -170 -180 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 6954 G25 1k 10k 100k 1M OFFSET FREQUENCY (Hz) -150 DIV = 1 -160 -170 DIV = 4 10 DIV = 1 -160 DIV = 4 -170 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) -140 -150 DIV = 1 -160 DIV = 4 -170 DIV = 16 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) SINGLE-ENDED SINE WAVE INPUT +7dBm AT 122.88MHz -150 DIV = 1 -160 DIV = 4 -170 10 100 6954 G23 LVDS Output Additive Phase Noise, fIN = 622.08MHz, ILVDS = 7mA, RTERM = 100||100 (Differential) -130 10M 6954 G26 10M 6954 G21 -140 -180 10M SINGLE-ENDED SINE WAVE INPUT +7dBm AT 622.08MHz 1k 10k 100k 1M OFFSET FREQUENCY (Hz) LVDS Output Additive Phase Noise, fIN = 122.88MHz, ILVDS = 3.5mA, RTERM = 100 Differential -130 SINGLE-ENDED SINE WAVE INPUT +7dBm AT 245.76MHz -150 100 6954 G20 -140 -180 -140 -180 10M SINGLE-ENDED SINE WAVE INPUT +7dBm AT 245.76MHz LVDS Output Additive Phase Noise, fIN = 245.76MHz, ILVDS = 3.5mA, RTERM = 100 Differential -120 DIV = 1 -160 100 6954 G22 -130 -140 DIV = 16 -130 -180 10M SINGLE-ENDED SINE WAVE INPUT +7dBm AT 1.4GHz -120 DIV = 4 -170 LVDS Output Additive Phase Noise, fIN = 1400MHz, ILVDS = 7mA, RTERM = 100||100 (Differential) -110 DIV = 1 -160 -120 ADDITIVE PHASE NOISE (dBc/Hz) ADDITIVE PHASE NOISE (dBc/Hz) -140 -150 6954 G19 SINGLE-ENDED SINE WAVE INPUT +7dBm AT 622.08MHz -130 -140 -180 10M LVDS Output Additive Phase Noise, fIN = 622.08MHz, ILVDS = 3.5mA, RTERM = 100 Differential -120 -130 ADDITIVE PHASE NOISE (dBc/Hz) -130 -130 SINGLE-ENDED SINE WAVE INPUT +7dBm AT 622.08MHz ADDITIVE PHASE NOISE (dBc/Hz) -120 LVPECL Output Additive Phase Noise, fIN = 245.76MHz, IBIAS Disabled, RTERM = 50 to V+ - 2V -120 ADDITIVE PHASE NOISE (dBc/Hz) SINGLE-ENDED SINE WAVE INPUT +7dBm AT 1.4GHz ADDITIVE PHASE NOISE (dBc/Hz) ADDITIVE PHASE NOISE (dBc/Hz) -110 VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V. 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 6954 G24 LVDS Output Additive Phase Noise, fIN = 245.76MHz, ILVDS = 7mA, RTERM = 100||100 (Differential) SINGLE-ENDED SINE WAVE INPUT +7dBm AT 245.76MHz -130 -140 -150 DIV = 1 -160 DIV = 4 -170 -180 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 6954 G27 6954f For more information www.linear.com/LTC6954 15 LTC6954 Typical Performance Characteristics TA = 25C, unless otherwise specified. All voltages are with respect to GND. -140 DIV = 1 -150 -160 DIV = 4 -170 -150 SINGLE-ENDED SINE WAVE INPUT +7dBm AT 122.88MHz -130 -153 PHASE NOISE FLOOR (dBc/Hz) ADDITIVE PHASE NOISE (dBc/Hz) ADDITIVE PHASE NOISE (dBc/Hz) -120 SINGLE-ENDED SINE WAVE INPUT +7dBm AT 245.76MHz -130 Additive Phase Noise Floor vs Divider Ratio FIN = 1GHz, LVPECL IBIAS Enabled RTERM = 100 Differential CMOS Output Additive Phase Noise, fIN = 122.88MHz CMOS Output Additive Phase Noise, fIN = 245.76MHz -120 VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V. -140 DIV = 1 -150 -160 DIV = 4 -170 -156 -159 -162 -165 -168 -171 -174 -177 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M -180 260 280 240 260 220 240 200 220 180 160 140 120 100 140 100 40 80 2000 ALL DIVIDERS AND LVPECL OUTPUTS ON, DIV BY 1 TWO DIVIDERS AND LVPECL OUTPUTS ON, DIV BY 1 DIVIDER DIV BY 2 AND LVPECL OUTPUT ON DIVIDER DIV BY 1 AND LVPECL OUTPUT ON DIVIDER DIV BY 1 ON, LVPECL OUTPUT OFF 6954 G31 60 0 400 1200 800 1600 FREQUENCY (MHz) 1 2 4 8 16 DIVIDER RATIO 32 64 6954 G30 Supply Current vs Frequency, CMOS Output 160 60 1200 800 1600 FREQUENCY (MHz) 10M 6954 G29 180 80 400 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 200 120 0 100 Supply Current vs Frequency, LVPECL Output, IBIAS Disabled, RTERM = 50 to V+ - 2V CURRENT (mA) CURRENT (mA) Supply Current vs Frequency, LVPECL Output, IBIAS Enabled, RTERM = 100 Differential 20 10 6954 G28 -180 CURRENT (mA) -180 2000 ALL DIVIDERS AND LVPECL OUTPUTS ON, DIV BY 1 TWO DIVIDERS AND LVPECL OUTPUTS ON, DIV BY 1 DIVIDER DIV BY 2 AND LVPECL OUTPUT ON DIVIDER DIV BY 1 AND LVPECL OUTPUT ON DIVIDER DIV BY 1 ON, LVPECL OUTPUT OFF 6954 G32 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 100 300 200 400 OUTPUT FREQUENCY (MHz) 500 ALL DIVIDERS AND CMOS OUTPUTS ON, DIV BY 1 TWO DIVIDERS AND CMOS OUTPUTS ON, DIV BY 1 DIVIDER DIV BY 2 AND CMOS OUTPUT ON DIVIDER DIV BY 1 AND CMOS OUTPUT ON DIVIDER DIV BY 1 ON, CMOS OUTPUT OFF 6954 G33 6954f 16 For more information www.linear.com/LTC6954 LTC6954 Typical Performance Characteristics VA+ = VD+ = VIN+ = VOUT0+ = VOUT1+ = VOUT2+ = 3.3V. TA = 25C, unless otherwise specified. All voltages are with respect to GND. Supply Current vs Frequency, LVDS Output, ILVDS = 3.5mA, RTERM = 100 Differential Supply Current vs Frequency, LVDS Output, ILVDS = 7mA, RTERM = 100||100 (Differential) 240 280 220 260 200 240 220 160 CURRENT (mA) CURRENT (mA) 180 140 120 100 200 180 160 140 120 80 100 60 80 40 60 20 0 200 400 600 800 1000 1200 1400 FREQUENCY (MHz) ALL DIVIDERS AND LVDS OUTPUTS ON, DIV BY 1 TWO DIVIDERS AND LVDS OUTPUTS ON, DIV BY 1 DIVIDER DIV BY 2 AND LVDS OUTPUT ON DIVIDER DIV BY 1 AND LVDS OUTPUT ON DIVIDER DIV BY 1 ON, LVDS OUTPUT OFF 6954 G34 40 0 400 1200 800 1600 FREQUENCY (MHz) 2000 ALL DIVIDERS AND LVDS OUTPUTS ON, DIV BY 1 TWO DIVIDERS AND LVDS OUTPUTS ON, DIV BY 1 DIVIDER DIV BY 2 AND LVDS OUTPUT ON DIVIDER DIV BY 1 AND LVDS OUTPUT ON DIVIDER DIV BY 1 ON, LVDS OUTPUT OFF 6954 G35 6954f For more information www.linear.com/LTC6954 17 LTC6954 Pin Functions LTC6954 VOUT0+, VOUT1+, VOUT2+ (Pins 1, 4, 5, 8, 9, 12): Output Supply Voltages. The supply range is from 3.15V to 3.45V. This supply should be kept free of noise and ripple. The use of a low impedance power plane is recommended. All VOUTx+ pins must be connected to the same supply voltage as the VA+, VD+ and VIN+ pins. Each pin, or in some cases pin pairs, must be separately bypassed directly to GND with a 0.01F ceramic capacitor as close to the pin as possible. Refer to the Applications Information section for more details on supply connections and bypassing. GND (Pins 14, 26, 29, 32, 35): Ground Connections. Should be tied directly to the exposed pad (pin 37) and to a low impedance ground plane for best performance. Refer to the Applications Information section for more details on grounding for signal integrity and thermal considerations. VA+ (Pins 15, 23, 24, 34): Analog Supply Voltages. The supply range is from 3.15V to 3.45V. This supply should be kept free of noise and ripple. The use of a low impedance power plane is recommended. All VA+ pins must be connected to the same supply voltage as the VOUTx+, VD+ and VIN+ pins. Each pin, or in some cases pin pairs, must be separately bypassed directly to GND with a 0.1F ceramic capacitor as close to the pin as possible. Refer to the Applications Information section for more details on supply connections and bypassing. CS (Pin 16): Serial Port Chip Select Input. This active LOW CMOS logic input initiates a serial port transaction when brought LOW. It finalizes the serial port transaction when brought HIGH after 16 serial port clock cycles. Refer to the Operation section for more details. SDO (Pin 17): Serial Data Output. Data read from the serial port is presented on this CMOS logic pin. Refer to the Operation section for more details. VD+ (Pins 18, 21): Digital Supply Voltages. The supply range is from 3.15V to 3.45V. This supply should be kept free of noise and ripple. The use of a low impedance power plane is recommended. All VD+ pins must be connected to the same supply voltage as the VOUTx+, VA+ and VIN+ pins. Each pin must be separately bypassed directly to GND with a 0.1F ceramic capacitor as close to the pin as possible. Refer to the Applications Informa- tion section for more details on supply connections and bypassing. SCLK (Pin 19): Serial Port Clock Input. This positive edge triggered CMOS logic input signal clocks serial port data in on the rising edge. Refer to the Operation section for more details. SDI (Pin 20): Serial Port Data Input. Data written into the serial port is presented on this CMOS logic pin. Refer to the Operation section for more details. SYNC (Pin 22): The Synchronization Input Pin. A rising edge on this CMOS logic input initiates an output clock synchronization sequence. Precision output synchronization of one or more parts is handled on-chip, so the timing of this signal is not critical. Refer to the Operation and the Applications Information sections for more details. VIN+ (Pins 25, 30): Analog Supply Voltages. The supply range is from 3.15V to 3.45V. This supply should be kept free of noise and ripple. The use of a low impedance power plane is recommended. All VIN+ pins must be connected to the same supply voltage as the VOUTx+, VA+ and VD+ pins. Each pin must be separately bypassed directly to GND with a 0.1F ceramic capacitor as close to the pin as possible. Refer to the Applications Information section for more details on supply connections and bypassing. IN+, IN - (Pins 27, 28): The Signal Input Pins. The input signal can be either differential or single ended. It can be a sine wave, LVPECL logic, LVDS logic or CMOS logic. Refer to the Operation and Applications Information sections for more details on the correct use of the inputs. TEMP (Pin 31): Temperature Monitoring Diode. This pin is connected to the anode of a diode that may be used to measure the die temperature, by forcing a current and measuring the voltage. Refer to the Applications Information section for more details on monitoring the die temperature. GND (Exposed Pad Pin 37): Ground Connection. The package exposed pad must be soldered directly to the PCB land. The PCB land pattern should have multiple thermal vias to the ground plane for both low ground inductance and low thermal resistance. Refer to the Applications Information section for more details on grounding for signal integrity and thermal considerations. 6954f 18 For more information www.linear.com/LTC6954 LTC6954 Pin Functions LTC6954-1 OUTPUTS and Mode Select LTC6954-2 OUTPUTS and Mode Select OUT0SEL (Pin 13): OUT0 Mode Select. Connecting this pin to the VA+ supply enables the internal, active biasing of the OUT0 output emitter followers. Connecting this pin to GND disables this internal bias circuit. Refer to the Operation and Applications Information sections for more details on the LVPECL internal bias. OUT0SEL (Pin 13): OUT0 Mode Select. Connecting this pin to the VA+ supply enables the internal, active biasing of the OUT0 output emitter followers. Connecting this pin to GND disables this internal bias circuit. Refer to the Operation and Applications Information sections for more details on the LVPECL internal bias. OUT0-, OUT0+ (Pins 10, 11): LVPECL Output Pins. Differential logic outputs typically terminated by 50 connected to a supply 2V below the VOUT0+ supply. Refer to the Operation and Applications Information sections for more details. OUT0-, OUT0+ (Pins 10, 11): LVPECL Output Pins. Differential logic outputs typically terminated by 50 connected to a supply 2V below the VOUT0+ supply. Refer to the Operation and Applications Information sections for more details. OUT1SEL (Pin 33): OUT1 Mode Select. Connecting this pin to the VA+ supply enables the internal, active biasing of the OUT1 output emitter followers. Connecting this pin to GND disables this internal bias circuit. Refer to the Operation and Applications Information sections for more details on the LVPECL internal bias. OUT1SEL (Pin 33): OUT1 Mode Select. Connecting this pin to the VA+ supply enables the internal, active biasing of the OUT1 output emitter followers. Connecting this pin to GND disables this internal bias circuit. Refer to the Operation and Applications Information sections for more details on the LVPECL internal bias. OUT1 -, OUT1+ (Pins 6, 7): LVPECL Output Pins. Differential logic outputs typically terminated by 50 connected to a supply 2V below the VOUT1+ supply. Refer to the Operation and Applications Information sections for more details. OUT1-, OUT1+ (Pins 6, 7): LVPECL Output Pins. Differential logic outputs typically terminated by 50 connected to a supply 2V below the VOUT1+ supply. Refer to the Operation and Applications Information sections for more details. OUT2SEL (Pin 36): OUT2 Mode Select. Connecting this pin to the VA+ supply enables the internal, active biasing of the OUT2 output emitter followers. Connecting this pin to GND disables this internal bias circuit. Refer to the Operation and Applications Information sections for more details on the LVPECL internal bias. OUT2 -, OUT2+ (Pins 2, 3): LVPECL Output Pins. Differential logic outputs typically terminated by 50 connected to a supply 2V below the VOUT2+ supply. Refer to the Operation and Applications Information sections for more details. OUT2SEL (Pin 36): OUT2 Mode Select. Connecting this pin to ground configures OUT2 as a CMOS logic type output. Connecting this pin to the VA+ supply configures OUT2 as an LVDS logic type output. OUT2-, OUT2+ (Pins 2, 3): LVDS/CMOS Output Pins. These outputs may be programmed as LVDS or CMOS outputs using the OUT2SEL pin. Refer to the Operation and the Applications Information sections for more details. 6954f For more information www.linear.com/LTC6954 19 LTC6954 Pin Functions LTC6954-3 OUTPUTS and Mode Select LTC6954-4 OUTPUTS and Mode Select OUT0SEL (Pin 13): OUT0 Mode Select. Connecting this pin to the VA+ supply enables the internal, active biasing of the OUT0 output emitter followers. Connecting this pin to GND disables this internal bias circuit. Refer to the Operation and Applications Information sections for more details on the LVPECL internal bias. OUT0SEL (Pin 13): OUT0 Mode Select. Connecting this pin to GND configures OUT0 as a CMOS logic type output. Connecting this pin to the VA+ supply configures OUT0 as an LVDS logic type output. OUT0-, OUT0+ (Pins 10, 11): LVPECL Output Pins. Differential logic outputs typically terminated by 50 connected to a supply 2V below the VOUT0+ supply. Refer to the Operation and Applications Information sections for more details. OUT1SEL (Pin 33): OUT1 Mode Select. Connecting this pin to GND configures OUT1 as a CMOS logic type output. Connecting this pin to the VA+ supply configures OUT1 as an LVDS logic type output. OUT1-, OUT1+ (Pins 6, 7): LVDS/CMOS Output Pins. These outputs may be programmed as LVDS or CMOS outputs using the OUT1SEL pin. Refer to the Operation and the Applications Information sections for more details. OUT2SEL (Pin 36): OUT2 Mode Select. Connecting this pin to GND configures OUT2 as a CMOS logic type output. Connecting this pin to the VA+ supply configures OUT2 as an LVDS logic type output. OUT2-, OUT2+ (Pins 2, 3): LVDS/CMOS Output Pins. These outputs may be programmed as LVDS or CMOS outputs using the OUT2SEL pin. Refer to the Operation and the Applications Information sections for more details. OUT0-, OUT0+ (Pins 10, 11): LVDS/CMOS Output Pins. These outputs may be programmed as LVDS or CMOS outputs using the OUT0SEL pin. Refer to the Operation and the Applications Information sections for more details. OUT1SEL (Pin 33): OUT1 Mode Select. Connecting this pin to GND configures OUT1 as a CMOS logic type output. Connecting this pin to the VA+ supply configures OUT1 as an LVDS logic type output. OUT1-, OUT1+ (Pins 6, 7): LVDS/CMOS Output Pins. These outputs may be programmed as LVDS or CMOS outputs using the OUT1SEL pin. Refer to the Operation and the Applications Information sections for more details. OUT2SEL (Pin 36): OUT2 Mode Select. Connecting this pin to GND configures OUT2 as a CMOS logic type output. Connecting this pin to the VA+ supply configures OUT2 as an LVDS logic type output. OUT2-, OUT2+ (Pins 2, 3): LVDS/CMOS Output Pins. These outputs may be programmed as LVDS or CMOS outputs using the OUT2SEL pin. Refer to the Operation and the Applications Information sections for more details. 6954f 20 For more information www.linear.com/LTC6954 LTC6954 Block Diagram 25 VIN+ 15 23 24 34 VA+ VA+ VA+ VA+ 26 GND IN+ 27 IN- 28 DELAY 0 DEL0 = 0 TO 63 OUTPUT 0 DRIVER M0 DIVIDER M0 = 1 TO 63 VOUT0+ 9 OUT0+ 11 OUT0- 10 VOUT0+ 12 29 GND 30 VIN+ 22 13 33 36 SYNC 20 16 31 DELAY 1 DEL1 = 0 TO 63 M1 DIVIDER M1 = 1 TO 63 OUT1SEL SDO VOUT1+ 5 OUT1+ 7 OUT1- 6 VOUT1+ 8 OUT2SEL 18 VD+ 19 OUTPUT 1 DRIVER OUT0SEL 21 VD+ 17 SYNC CONTROL SPI SERIAL PORT AND DIGITAL LOGIC OUTPUT 2 DRIVER DELAY 2 DEL2 = 0 TO 63 M2 DIVIDER M2 = 1 TO 63 VOUT2+ 1 OUT2+ 3 OUT2- 2 VOUT2+ 4 SCLK SDI CS TEMP 32 GND 14 GND 35 GND EXPOSED GND PAD GND 37 6954 BD 6954f For more information www.linear.com/LTC6954 21 LTC6954 Timing Diagrams Output Propagation Delays and Skews, Mx[5:0] = 1 IN- IN+ tSKEWP0 OUT0- OUT0+ tpdP1 OUT1- OUT1+ tSKEWP2 OUT2- OUT2+ 6954 TD01 Differential LVPECL Rise/Fall Times 80% 20% tRISE tFALL 6954 TD02 Differential LVDS Rise/Fall Times Single-Ended CMOS Rise/Fall Times 80% 80% 20% 20% tRISE tFALL 6954 TD03 tRISE tFALL 6954 TD04 6954f 22 For more information www.linear.com/LTC6954 LTC6954 Operation LTC6954 INTRODUCTION As shown in Figure 1, the LTC6954 consists of two distinct circuit sections: multioutput clock distribution and digital control. The LTC6954 is a family of low phase noise clock distribution parts. Each part provides three outputs, each with programmable frequency divider and delay blocks. There are four members of the family differing in their output logic signal type: The clock distribution section of the LTC6954 receives an input signal up to 1.4GHz (1.8GHz for the LTC6954-1 when DELx = 0) and delivers three output signals based on the input. The output signal logic type depends on the LTC6954 part version and the connection of the OUTxSEL output mode selection pins. Table 1 shows all four part versions, each version's available output types and the effect of OUTxSEL pin connection on the output. LTC6954-1: Three LVPECL outputs LTC6954-2: Two LVPECL and one LVDS/CMOS outputs LTC6954-3: One LVPECL and two LVDS/CMOS outputs The LVPECL logic outputs are capable of operation up to 1.4GHz (1.8GHz for the LTC6954-1 when DELx = 0). Connecting the OUTxSEL pin to the VA+ supply enables the internal, active biasing of the output emitter followers. Connecting this pin to GND disables this internal bias circuit. LTC6954-4: Three LVDS/CMOS outputs IN+ LTC6954-X IN- SYNC SYNC CONTROL OUT0SEL OUT1SEL OUT2SEL DIGITAL CONTROL SDO SPI SERIAL PORT SDI SERIAL PORT AND DIGITAL DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 OUT0+ OUT0- OUT1+ OUT1- CLOCK DISTRIBUTION OUT2+ OUT2- SCLK CS 6954 F01 Figure 1.The LTC6954 Highlighting the Circuit Blocks Table 1. LTC6954 Versions and Output Configurations LTC6954 VERSION OUTPUT 0 OUTPUT 1 OUTPUT 2 OUT0SEL = GND OUT0SEL = VA+ OUT1SEL = GND OUT1SEL = VA+ OUT2SEL = GND OUT2SEL = VA+ LTC6954-1 LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LTC6954-2 LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LVPECL (IBIAS is Off) LVPECL (IBIAS is On) CMOS LVDS LTC6954-3 LVPECL (IBIAS is Off) LVPECL (IBIAS is On) CMOS LVDS CMOS LVDS LTC6954-4 CMOS LVDS CMOS LVDS CMOS LVDS 6954f For more information www.linear.com/LTC6954 23 LTC6954 Operation The LVDS/CMOS output can be either a CMOS logic type or an LVDS logic type as configured by the OUTxSEL pin connection. Connecting the OUTxSEL pin to ground configures the output as a CMOS logic output capable of operation up to 250MHz. Connecting the OUTxSEL pin to the VA+ supply configures the output as an LVDS logic output capable of operation up to 800MHz for LVCSx set to 0 (far end line termination only), and up to 1400MHz for LVCSx set to 1 (doubly terminated). Refer to the Operation and Applications Information sections for more details. Regardless of the LTC6954 part version and the output logic configuration, all three outputs are individually programmable to divide the input frequency by any integer from 1 to 63 and to delay any output by 0 to 63 input clock cycles. For an input signal with a 50% duty cycle, the output duty cycle will always be 50% regardless of the divide number. The digital control section contains a full SPI-compatible serial control bus, the three output mode selection pins (OUT0SEL, OUT1SEL and OUT2SEL) and the EZSync clock synchronization (SYNC) function. Most device settings and operating modes are controlled through the SPI bus. To minimize power consumption, many sections of the LTC6954 can be powered down when not in use. As shown in Figure 2, the LTC6954 can be used as an independent clock distribution part. Any unused outputs from the clock distribution section may be powered down. Figure 3 highlights an LTC6950 driving the LTC6954. This example shows a single LTC6954 device, but each output from the LTC6950 can drive a separate LTC6954 device for support of up to five LTC6954 devices. The effortlessto-use EZSync multipart synchronization feature assures consistent edge alignment of all outputs from all devices. See the EZSync Clock Output Synchronization section for more details on EZSync operation. 0.1F 49.9 3.3V V+ IN+ LTC6954-x IN- 49.9 49.9 SYNC SYNC CONTROL OUT0SEL OUT1SEL OUT2SEL SDO SPI SERIAL PORT SDI SERIAL PORT AND DIGITAL DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 OUT0+ OUT0- OUT1+ OUT1- OUT2+ OUT2- SCLK CS GND 6954 F02 Figure 2. The LTC6954 Connected as an Independent Clock Distribution Part 6954f 24 For more information www.linear.com/LTC6954 LTC6954 Operation 0.1F 0.1F 3.3V REF OSC 49.9 - REF VCP+ V+ REF+ R DIVIDER 49.9 5V N DIVIDER PHASE FREQUENCY DETECTOR LTC6950 VCO CP CHARGE PUMP CP 49.9 RZ CI VCO+ 49.9 VCO- SYNC SYNC SYNC CONTROL STAT2 STAT1 SDO SDI SERIAL PORT SCLK CS DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 49.9 PECL0+ PECL0- 49.9 PECL1+ TO DATA ACQUISITION, FPGA, ASICs PECL1- PECL2+ PECL2- PECL3+ PECL3- LV/CM+ LV/CM- TO FPGA, ASICs GND 0.1F 3.3V 100 V+ IN+ LTC6954-X IN- SYNC SYNC CONTROL OUT0SEL OUT1SEL 3.3V OUT2SEL SDO SPI SERIAL PORT SDI SERIAL PORT AND DIGITAL DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 OUT0+ OUT0- OUT1+ TO DATA ACQUISITION, FPGA, ASICs OUT1- OUT2+ OUT2- SCLK CS GND 6954 F03 Figure 3. The LTC6950 in Controller Mode Clocking an LTC6954. For Best Performance Use One of the LVPECL Outputs From the LTC6950 (with the IBIAS Enabled) to Clock the LTC6954. All Outputs From Both Devices Are Easily Synchronized by Applying a 1ms (Min) Wide Pulse on the SYNC Pins. 6954f For more information www.linear.com/LTC6954 25 LTC6954 Operation INPUT BUFFER OUTPUT DIVIDER (M) The LTC6954's input buffer (IN+, IN-) provides a flexible interface to either differential or single-ended frequency sources. The maximum input signal frequency is 1.4GHz (1.8GHz for the LTC6954-1 when DELx = 0). Differential signals may be applied directly to the input as long as the signal swing is less than 1.5VP-P to avoid turning on the input protection diodes (see Figure 4). Each clock distribution path includes a 6-bit output (M) divider that reduces the input frequency by the programmed divide modulus, M. By programming the Mx[5:0] bits for each output divider, the divide modulus is set to any integer from 1 to 63, inclusive. Circuitry within the output divider ensures the output duty cycle will always be 50% for a programmed divide modulus greater than 1. When the output divider has been programmed for a divide modulus of 1 or 0, the output duty cycle will be the same as the input and the output divider is bypassed and powered down. See Table 2 for a summary of the registers containing the output divider control bits for each clock output distribution path. See Table 6, Serial Port Register Mapping, for complete register mapping information. It is also important that the IN inputs be low noise and have a slew rate of at least 100V/s. See the Applications Information section for more information on IN signal requirements and interfacing. BIAS VIN+ VIN+ 2.05V 1.2k 27 Table 2. Output (M) Divider Control Registers 1.2k CLOCK OUTPUT IN+ OUT0 28 IN- DIVIDE MODULUS BITS REG ADDR (HEX) M0 [5:0] h02 OUT1 M1 [5:0] h04 OUT2 M2 [5:0] h06 6954 F04 INPUT CLOCK CYCLE DELAY (DEL) Figure 4. Simplified IN Input Schematic CLOCK DISTRIBUTION The LTC6954 provides low noise clock distribution capability via three low skew distribution paths. Each distribution path includes an output divider, an input clock cycle delay block and an output driver. The output driver can be LVPECL, LVDS or CMOS compatible depending on which LTC6954 part is selected and the configuration of the corresponding OUTxSEL pin. Each clock distribution path includes a 6-bit input cycle delay block, which is used in conjunction with the synchronization input pin, SYNC, to force phase alignments of the various clock outputs. When the SYNC input de-asserts, the delay block begins counting input clock cycles. When the count reaches the programmed configuration for each path, the output driver begins transitioning. To save power, the input cycle delay block powers down when all output phase alignments are complete. The number of cycles of delay adjustment allowed for each output may be any integer from 0 to 63, inclusive, and is configured by enabling the specific delay block and then directly programming the number of delay cycles into the appropriate DELx[5:0] bits. Setting the SYNC_ENx bit to 1 enables each delay block. Alternatively, setting SYNC_ENx to 0 results in the selected cycle delay block being bypassed and powered down. 6954f 26 For more information www.linear.com/LTC6954 LTC6954 Operation Because the input clock cycle delay block operates independently of the output divider block, the programmed cycle delay adjustment occurs regardless of the modulus setting of the output divider (see the example in Figure 5). 0 1 2 3 4 5 6 7 8 9 10 11 IN 1 INPUT CYCLE OUT0 1 INPUT CYCLE DELAY OUT1 11 INPUT CYCLE DELAY OUT2 6954 F05 SYNC DE-ASSERTED EARLIER LVDS/CMOS OUTPUT DRIVER The LTC6954-2/LTC6954-3/LTC6954-4 have the capability to provide one or more LVDS or CMOS outputs. Connecting the corresponding output's OUTxSEL pin to VA+enables LVDS compatible operation at frequencies up to 1.4GHz, while connecting it to GND configures two CMOS compatible output drivers with a maximum operating frequency of 250MHz. When the output driver is configured for CMOS operation, programming the bit CMSINVx to 1 inverts the OUT - relative to OUT +. Setting CMSINVx to 0 results in both OUT+ and OUT - being in phase. See Table 4 for a summary of the registers containing the CMOS phase control bits for each clock output distribution path. Table 4. CMOS Phase-Select Registers Figure 5. Input Clock Delay Operation (M0 = M1 = M2 = 4, DEL0 = 0, DEL1 = 1, DEL2 = 11) Refer to the EZSync Clock Output Synchronization section for more information about using the SYNC input pin to achieve specific output phase alignments. See Table 3 for a summary of the registers containing the output delay control bits for each clock output distribution path. For complete register mapping information, see Table 6, Serial Port Register Mapping. Table 3. Output Delay (DEL) Control Registers CLOCK OUTPUT OUTPUT DELAY BITS SYNC ENABLE BIT REG ADDR (HEX) OUT0 DEL0 [5:0] SYNC_EN0 [7] h01 OUT1 DEL1 [5:0] SYNC_EN1 [7] h03 OUT2 DEL2 [5:0] SYNC_EN2 [7] h05 CLOCK OUTPUT OUT0 BIT DESCRIPTOR BIT REG ADDR (HEX) CMSINV0 [6] h01 OUT1 CMSINV1 [6] h03 OUT2 CMSINV2 [6] h05 When the output is configured for LVDS operation, the output driver can be further configured for different output current modes using the LVCSx bits. See Table 5 for a summary of the registers containing the LVDS current settings. The higher current setting is ideal for applications where the LVDS output driver is double-terminated. For example, if the LVDS output is terminated at the near end with a differential 100 resistor and at the far end with a differential 100 resistor, programming LVCS for 7mA operation will allow full LVDS swings. See the Applications Information section for LVDS and CMOS output driver interface circuits. Table 5. LVDS Current Settings CLOCK OUTPUT OUT0 OUT1 OUT2 BIT DESCRIPTOR BIT REG ADDR (HEX) VALUE ILVDS DIFFERENTIAL TERMINATION LVCS0 [6] h02 0 3.5mA 100 1 7mA 50 (100 || 100) 0 3.5mA 100 1 7mA 50 (100 || 100) 0 3.5mA 100 1 7mA 50 (100 || 100) LVCS1 LVCS2 [6] [6] h04 h06 6954f For more information www.linear.com/LTC6954 27 LTC6954 Operation LVPECL OUTPUT DRIVER The LTC6954-1/LTC6954-2/LTC6954-3 have the capability to provide one or more low noise, low skew LVPECL compatible output drivers depending on the part version selected. The output drivers are designed to operate at frequencies up to 1.4GHz (1.8GHz for the LTC6954-1 when DELx = 0). The outputs also provide considerable flexibility for biasing and termination. Internal biasing for the output emitter followers may be selected by setting the OUTxSEL pin to VA+ for the appropriate output driver block. See Figure 6 for a simplified schematic. Enabling the internal bias will usually reduce the number of passive components required off-chip. In many cases, a single 100 differential termination at the far end is all that is required. In addition, more symmetrical rise/fall times may result from using the constant current internal bias. Setting OUTxSEL to 0 disables the internal bias and allows the LVPECL output driver to be configured using standard LVPECL bias and termination networks. See the Applications Information section for more information about recommended bias and termination networks. EZSync CLOCK OUTPUT SYNCHRONIZATION The LTC6954 allows easy synchronization of the rising edges of clock outputs from a single independent part by simply pulsing the CMOS logic compatible SYNC input pin. VOUTx+ Multiple part synchronization is also easily achieved by driving the LTC6954's IN input with one of Linear Technology's EZSync control mode capable drivers, such as the LTC6950. Using an EZSync control mode part as the driver, synchronization of its outputs and up to five LTC6954 parts is also as easy as pulsing the parts' SYNC input pins. There are no precision timing requirements for this pulse. The EZSync Controller part provides all of the precision timing. SINGLE PART, INDEPENDENT SYNCHRONIZATION To synchronize the rising edges of the outputs of a single, independent LTC6954, a CMOS logic pulse of at least 1ms duration is required on the SYNC input. Each synchronized clock output should be sync-enabled, by programming its SYNC_ENx bit to 1. Programming an output to be sync-enabled results in that clock output being gated, or noncontinuous, during the synchronization process. Therefore, clock outputs that must not be disturbed (gated) during a synchronization operation should have their SYNC_ENx bits programmed to 0. A synchronization operation is performed by forcing the SYNC input (Pin 22) to a logic HIGH for at least 1ms. The LTC6954 then retimes the SYNC input with respect to the VOUTx+ OUT+ OUT - IBIAS IBIAS 6954 F06 Figure 6. Simplified LVPECL Output Schematic 6954f 28 For more information www.linear.com/LTC6954 LTC6954 Operation input signal to create an internal SYNC_RET signal, as shown in Figure 7. When SYNC_RET transitions HIGH, all sync-enabled clock outputs remain LOW once they transition to that state. Note that the LTC6954 has circuitry to prevent runt pulses, even during a synchronization operation, so the clock outputs only transition LOW when they would do so normally. Once the internal SYNC_RET signal transitions LOW, all sync-enabled outputs transition HIGH simultaneously, and the synchronization operation is complete. By programming the delay bits, DELx[5:0], the LTC6954 may also provide clock outputs with phase relationships other than synchronized first rising edges. When DELx[5:0] are programmed, each sync-enabled output may be independently configured to wait up to 63 additional input clock cycles before rising, relative to the 0 delay case. For example, assuming the OUT0 and OUT1 outputs are both configured to divide by four, programming DEL0[5:0] to 0 and DEL1[5:0] to 1 allows the outputs to have a quadrature relationship once a synchronization operation completes (see Figure 8). To conserve power, the input cycle delay circuitry is turned off after a synchronization completes. IN SYNC_RET ... ... OUT0 ... OUT1 ... 6954 F08 Figure 8. Synchronization to Obtain I/Q Clocks, SYNC_EN0 = SYNC_EN1 = 1, M0[5:0] = M1[5:0] = 4, DEL0[5:0] = 0, DEL1[5:0] = 1 0.1F 3.3V REF OSC IN+ V+ IN- LTC6954-X SYNC SYNC CONTROL OUT0SEL SYNC_RET OUT0+ OUT0 DIVIDE AND DELAY OUT1+ OUT1SEL OUT2SEL SDO SPI SERIAL PORT SDI OUT0- SERIAL PORT AND DIGITAL OUT1 DIVIDE AND DELAY LV/CM DIVIDE AND DELAY OUT2 DIVIDE AND DELAY SYNC_EN4 = 1, FLRDRV = 0 OUT1- OUT2+ OUT2- SCLK CS GND 6954 F07 Figure 7. SYNC_RET Propagation 6954f For more information www.linear.com/LTC6954 29 LTC6954 Operation MULTIPLE PART SYNCHRONIZATION Multiple LTC6954 parts may be easily configured to provide more synchronized outputs than are available on a single part provided that the parts are all driven by an EZSync controller part. All parts being synchronized should share a common SYNC input, but there is no requirement for precise timing of this signal between the different parts. The only requirements are the skew of the SYNC pulse between the different parts is no greater than 10s, and the SYNC pulse is at least 1ms in duration. The general concept behind synchronizing multiple parts is to have one part as the EZSync "controller," while all other parts are "followers." The controller part controls the timing of all parts because it provides gated clock inputs to all follower parts. By providing an appropriate gated clock signal to each follower part, the controller ensures the outputs of all follower parts will have their first rising edge synchronized. Furthermore, any output of the controller part not being used as a follower-driver may be configured to be followersynchronous, which forces its output to have a first rising edge synchronized with all follower parts' outputs. The LTC6954 is not capable of control mode operation. It can only be used as a follower. Parts such as the LTC6950 are capable of control or follow mode. With five outputs available, the LTC6950 can control and drive up to five follower devices. These followers may be additional LTC6950 parts, LTC6954 parts or any combination of each part. The EZSync feature allows easy multipart synchronization of rising clock edges, so outputs of multiple parts will have a repeatable phase alignment. EZSync does not guarantee absolute time synchronization. That is, EZSync makes input cycle delay adjustments only, so any PCB trace delay from the controller to the follower, plus the propagation delay of the follower device, will be reflected as a delta in absolute time between the follower and controller when measured at their respective output pins. The simplest configuration for synchronizing multiple EZSync compatible parts is shown in Figure 9. The LTC6950 has its SYNCMD[1:0] bits programmed to control mode. Because the PECL0 output of the LTC6950 is used as an input to the LTC6954, the LTC6950 should be configured to make that output a follower-driver, which is accomplished by programming FLDRV0 to 1. To configure the PECL1, PECL2, PECL3 and LV/CM outputs of the LTC6950 as follower-synchronous, an internal VCO cycle delay cell must be enabled, which is accomplished by programming the FLDRV1, FLDRV2, FLDRV3 and FLDRV4 bits to 0. All outputs should have their SYNC_ENx bits programmed to 1 to allow synchronization. If there is an output which should not be disturbed (gated), program its SYNC_ENx bit to 0. The example in Figure 9 makes an arbitrary choice of using the PECL0 differential outputs to drive the LVPECL compatible input of the LTC6954. Any of the outputs from the LTC6950 may be used as long as the appropriate FLDRVx bit is programmed to 1. All LTC6954 outputs that are to be synchronized must have its SYNC_ENx bit programmed to 1. As noted earlier, if there is an output which should not be disturbed (gated), program its SYNC_ENx bit to 0. 6954f 30 For more information www.linear.com/LTC6954 LTC6954 Operation 0.1F 3.3V REF OSC V+ REF+ REF- R DIVIDER PHASE FREQUENCY DETECTOR SYNC_RET STAT2 SDO SERIAL PORT SDI PECL0 DIVIDE AND DELAY SYNC_EN0 = 1, FLRDRV = 1 PECL2 DIVIDE AND DELAY SYNC_EN2 = 1, FLRDRV = 0 SCLK PECL3 DIVIDE AND DELAY SYNC_EN3 = 1, FLRDRV = 0 CS LV/CM DIVIDE AND DELAY SYNC_EN4 = 1, FLRDRV = 0 GND VCO CP CHARGE PUMP VCO- PECL1 DIVIDE AND DELAY SYNC_EN1 = 1, FLRDRV = 0 STAT1 LTC6950 VCO+ SYNC RETIME CONTROL SYNC 5V VCP+ N DIVIDER SYNC 0.1F PECL0+ PECL0- PECL1+ PECL1- PECL2+ PECL2- PECL3+ PECL3- LV/CM+ LV/CM- 0.1F 3.3V 100 V+ IN+ IN- SYNC SYNC CONTROL SYNC_RET OUT0 DIVIDE AND DELAY SYNC_EN0 = 1 OUT0SEL OUT1SEL OUT2SEL SDO SPI SERIAL PORT SDI SERIAL PORT AND DIGITAL OUT1 DIVIDE AND DELAY SYNC_EN1 = 1 OUT2 DIVIDE LV/CM DIVIDE AND AND DELAY DELAY SYNC_EN2 =1 =0 SYNC_EN4 = 1, FLRDRV LTC6954-X OUT0+ OUT0- OUT1+ OUT1- OUT2+ OUT2- SCLK CS GND 6954 F09 Figure 9. LTC6950 Controller Part Driving an LTC6954 Follower Part. The PECL0 Output of the LTC6950 Drives the LTC6954 Input. All Other LTC6950 Outputs Are Programmed as Follower-Synchronous, Enabling All Seven Outputs to Be Rising Edge Synchronized 6954f For more information www.linear.com/LTC6954 31 LTC6954 Operation The timing diagram in Figure 10 illustrates multipart output synchronization of the circuit shown in Figure 9. The configurations of both the LTC6950 (controller) and the LTC6954 (follower) are as described in the preceding paragraphs. Figure 10 highlights that once the SYNC input transitions to a logic low, both outputs of the LTC6954 (LTC6954.OUT0 and LTC6954.OUT1) have their first rising edges aligned with each other, as well as with the followersynchronous output of the LTC6950 (LTC6950.PECL1). EZSync control mode parts have numerous timing details available including clock synchronization to not only the VCO SYNC ... ... ... ... VCO input, but also synchronization to the PLL's feedback N divider. This allows for synchronization to the reference frequency when the controller's PLL is locked. Consult the data sheet for the EZSync controller part (e.g., LTC6950) for the details of control mode operation. As illustrated in Figure 9 and Figure 10, the EZSync feature allows a device configured in control mode to generate appropriately gated clock signals that guarantee all devices in follow mode will be synchronized with each other and with any follower-synchronous outputs of the controller, making multipart synchronization easy. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... LTC6954.OUT0 ... ... ... ... LTC6954.OUT1 ... ... ... ... LTC6950.SYNC_RET ... LTC6950.PECL0 ... LTC6950.PECL1 LTC6954.SYNC_RET ... ... EDGE SYNCHRONIZED 6954 F10 Figure 10. Timing Diagram of Circuit Shown in Figure 9 with Edge Synchronized Outputs Highlighted; LTC6950: M0[5:0] = 1, M1[5:0] = 4, DEL1[5:0] = 0, FLDRV0 = 1, FLDRV1 = 0, SYNC_EN0 = SYNC_EN1 = 1, LTC6954: M0[5:0] = 4, M1[5:0] = 4, DEL0[5:0] = DEL1[5:0] = 0, SYNC_EN0 = SYNC_EN1 = 1 6954f 32 For more information www.linear.com/LTC6954 LTC6954 Operation SERIAL PORT Data is read from the part during a communication burst using SDO. Read back may be multidrop (more than one LTC6954 connected in parallel on the serial bus), as SDO is set to a high impedance (Hi-Z) when CS is HIGH or when data is not being read from the part. If the LTC6954 is not used in a multidrop configuration, or if the serial port master is not capable of setting the SDO line level between read sequences, attaching a high value resistor of at least 200k between SDO and GND to ensure the line returns to a known level during Hi-Z states is highly recommended. See Figure 12 for details. The LTC6954 SPI-compatible serial port provides chip control. COMMUNICATION SEQUENCE The serial bus is comprised of chip select (CS), serial clock (SCLK), serial data input (SDI) and serial data output (SDO) signals. Data transfers to the LTC6954 are accomplished by the serial bus master device first taking CS LOW, which enables the LTC6954's serial port. Input data applied on SDI is clocked on the rising edge of SCLK, with most significant bits transferred first. The communication burst is terminated by the serial bus master device returning CS HIGH. See Figure 11 for details. MASTER-CS tCSS tCKL tCKH tCSS tCSH MASTER-SCLK tCS MASTER-SDI tCH DATA DATA 6954 F11 Figure 11. Serial Port Write Timing Diagram MASTER-CS 8TH CLOCK MASTER-SCLK tDO LTC6954-SDO Hi-Z tDO DON'T CARE tDO tDO DATA DATA Hi-Z 6954 F12 Figure 12. Serial Port Read Timing Diagram 6954f For more information www.linear.com/LTC6954 33 LTC6954 Operation SINGLE BYTE TRANSFERS The serial port is arranged in a straightforward memory map, with status and control available in eight bytewide registers. All data bursts are comprised of at least two bytes. The seven most significant bits (MSB) of the first byte are the register address, with a least significant bit (LSB) of 1 indicating a read from the part, and an LSB of 0 indicating a write to the part. The subsequent byte, or bytes, is data from/to the specified register address. See Figure 13 for an example of a detailed write sequence, and Figure 14 for a read sequence. master device contains a first byte of data on SDI that includes the 7-bit destination register address (Addr0) and an LSB of 0 indicating a write operation. The second byte on SDI is the data to be written into address Addr0. To terminate the first communication burst, CS is taken HIGH. The second communication burst is structured the same way as the first. The first byte on SDI contains a 7-bit destination register address (Addr1) and an LSB of 0 to indicate a write operation. The next byte on SDI is the data intended for the register at address Addr1. And finally, the transfer is terminated by taking CS HIGH. Figure 15 shows an example of two write communication bursts. The first communication burst from the serial bus MASTER-CS 16 CLOCKS MASTER-SCLK 7-BIT REGISTER ADDRESS MASTER-SDI 8 BITS OF DATA A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 = WRITE Hi-Z LTC6954-SDO 6954 F13 Figure 13. Serial Port Write Sequence MASTER-CS 16 CLOCKS MASTER-SCLK 7-BIT REGISTER ADDRESS MASTER-SDI 1 = READ A6 A5 A4 A3 A2 A1 A0 1 8 BITS OF DATA LTC6954-SDO Hi-Z X D7 D6 D5 D4 D3 D2 D1 D0 DX Hi-Z 6954 F14 Figure 14. Serial Port Read Sequence 6954f 34 For more information www.linear.com/LTC6954 LTC6954 Operation MULTIPLE BYTE TRANSFERS More efficient data transfer of multiple bytes is accomplished by using the LTC6954's register address autoincrement feature, as shown in Figure 16. Like Figure 15, Figure 16 shows the serial bus master device sending the destination register address and an LSB of 0 in the first byte, followed by a second byte of data for that destination register. But instead of terminating the burst by taking CS back HIGH, the serial port master device continues sending bytes destined for subsequent registers. Byte 1's destination address is Addr0+1, Byte 2's destination address is Addr0+2 and so on. If the register address pointer attempts to increment past 7 (h07), it is automatically reset to 0. An example of an auto-increment read from the part is shown in Figure 17. The first byte of the burst from the serial bus master device contains the 7-bit destination register address (Addr0) and an LSB of 1 to indicate a read operation. Once the LTC6954 detects a read burst, it takes SDO out of the Hi-Z condition and begins to send data bytes sequentially, starting with data from register Addr0. The part ignores all other data on SDI until the burst is terminated by taking CS HIGH. MASTER-CS Addr0 + Wr MASTER-SDI LTC6954-SDO Byte 0 Addr1 + Wr Byte 1 Hi-Z 6954 F15 Figure 15. Serial Port Single Byte Write MASTER-CS Addr0 + Wr MASTER-SDI LTC6954-SDO Byte 0 Byte 1 Byte 2 Hi-Z 6954 F16 Figure 16. Serial Port Auto-Increment Write MASTER-CS Addr0 + Rd MASTER-SDI LTC6954-SDO Hi-Z DON'T CARE Byte 0 Byte 1 Hi-Z Byte 2 6954 F17 Figure 17. Serial Port Auto-Increment Read 6954f For more information www.linear.com/LTC6954 35 LTC6954 Operation MULTIDROP CONFIGURATION BLOCK POWER-DOWN Several LTC6954's may share the serial bus. In this multidrop configuration SCLK, SDI and SDO are common between all parts. The serial bus master must use a separate CS for each LTC6954 and ensure that only one device has CS asserted at any time. It is recommended to attach a high value resistor from SDO to GND to ensure the line returns to a known level during Hi-Z states. The LTC6954 provides considerable flexibility to power down unused blocks. A summary of power-down bits is shown in Table 7. To determine the power savings in shutting down a particular section, consult the Supply Current Delta area of the Electrical Characteristics section. SERIAL PORT REGISTERS The LTC6954's memory map is shown in Table 6. Detailed bit descriptions are shown in Table 8. As noted earlier, to achieve maximum power savings when an LVPECL output is unused and powered down, it is recommended that no terminations or other bias circuitry be connected to the output driver pins. Table 7. Block Power-Down Descriptions BIT NAME DESCRIPTION PDALL Power-Down Whole Chip PD_OUT2 Power-Down OUT2 Output Driver PD_DIV2 Power-Down OUT2 Output Driver and Output Divider PD_OUT1 Power-Down OUT1 Output Driver PD_DIV1 Power-Down OUT1 Output Driver and Output Divider PD_OUT0 Power-Down OUT0 Output Driver PD_DIV0 Power-Down OUT0 Output Driver and Output Divider Table 6. LTC6954 Serial Port Register Mapping ADDR (HEX) [7] MSB [6] [5] [4] [3] [2] [1] [0] LSB R/W DEFAULT (HEX) h00 * PDALL PD_OUT2 PD_DIV2 PD_OUT1 PD_DIV1 PD_OUT0 PD_DIV0 R/W h00 h01 SYNC_EN0 CMSINV0 DEL0[5] DEL0[4] DEL0[3] DEL0[2] DEL0[1] DEL0[0] R/W hC0 h02 * LVCS0 M0[5] M0[4] M0[3] M0[2] M0[1] M0[0] R/W h02 h03 SYNC_EN1 CMSINV1 DEL1[5] DEL1[4] DEL1[3] DEL1[2] DEL1[1] DEL1[0] R/W hC0 h04 * LVCS1 M1[5] M1[4] M1[3] M1[2] M1[1] M1[0] R/W h04 h05 SYNC_EN2 CMSINV2 DEL2[5] DEL2[4] DEL2[3] DEL2[2] DEL2[1] DEL2[0] R/W hC0 h06 * LVCS2 M2[5] M2[4] M2[3] M2[2] M2[1] M2[0] R/W h08 h07 REV2 REV1 REV0 PART4 PART3 PART2 PART1 PART0 R h2X *Unused 6954f 36 For more information www.linear.com/LTC6954 LTC6954 Operation Table 8. Serial Port Register Bit Descriptions NAME DESCRIPTION BIT(s) DEFAULT VALUE (b: BINARY h: HEX) CMSINV0 CMOS Output Phase Relationship on OUT0. IF CMSINV0 = 0, Then OUT0+ and OUT0- Are In-Phase; If CMSINV0 = 1, Then OUT0+ and OUT0- Are Inverted Relative to the Other. Ignore if Configured for LVPECL or LVDS. h01[6] R/W b1 CMSINV1 CMOS Output Phase Relationship on OUT1. IF CMSINV1 = 0, Then OUT1+ and OUT1- Are In-Phase; If CMSINV1 = 1, Then OUT1+ and OUT1- Are Inverted Relative to the Other. Ignore if Configured for LVPECL or LVDS. h03[6] R/W b1 CMSINV2 CMOS Output Phase Relationship on OUT2; IF CMSINV2 = 0, Then OUT2+ and OUT2- Are In-Phase; If CMSINV2 = 1, Then OUT2+ and OUT2- Are Inverted Relative to the Other. Ignore if Configured for LVPECL or LVDS. h05[6] R/W b1 DEL0[5:0] Sets the OUT0 Delay Value, 0 DEL0[5:0] 63 Input Clock Cycles. h01[5:0] R/W h00 REG ADDR (HEX) DEL1[5:0] Sets the OUT1 Delay Value, 0 DEL1[5:0] 63 Input Clock Cycles. h03[5:0] R/W h00 DEL2[5:0] Sets the OUT2 Delay Value, 0 DEL2[5:0] 63 Input Clock Cycles. h05[5:0] R/W h00 LVCS0 Sets the LVDS Output Current for OUT0, (0 = 3.5mA,1 = 7mA). Ignore if the Output Is LVPECL or CMOS. h02[6] R/W b0 LVCS1 Sets the LVDS Output Current for OUT1, (0 = 3.5mA,1 = 7mA). Ignore if the Output Is LVPECL or CMOS. h04[6] R/W b0 LVCS2 Sets the LVDS Output Current for OUT2, (0 = 3.5mA,1 = 7mA). Ignore if the Output Is LVPECL or CMOS. h06[6] R/W b0 M0[5:0] M0[5:0] Sets the OUT0 Output Divider Modulus to Any Integer From 1 to 63. Programming M0[5:0] to a Value of Hex 0 or 1 Results in a Divide Modulus of 1. h02[5:0] R/W h02 M1[5:0] M1[5:0] Sets the OUT1 Output Divider Modulus to Any Integer From 1 to 63. Programming M1[5:0] to a Value of Hex 0 or 1 Results in a Divide Modulus of 1. h04[5:0] R/W h04 M2[5:0] M2[5:0] Sets the OUT2 Output Divider Modulus to Any Integer From 1 to 63. Programming M2[5:0] to a Value of Hex 0 or 1 Results in a Divide Modulus of 1. h06[5:0] R/W h08 PART[4:0] Part code (h00 = LTC6954-1, h01 = LTC6954-2, h02 = LTC6954-3, h03 = LTC6954-4). h07[4:0] R PDALL For PDALL = 1, the Full Chip Is Powered Down. h00[6] R/W b0 PD_DIV0 For PD_DIV0 = 1, the OUT0 Divider and the Output Buffer Is Powered Down. h00[0] R/W b0 PD_DIV1 For PD_DIV1 = 1, the OUT1 Divider and the Output Buffer Is Powered Down. h00[2] R/W b0 PD_DIV2 For PD_DIV2 = 1, the OUT2 Divider and the Output Buffer Is Powered Down. h00[4] R/W b0 PD_OUT0 For PD_OUT0 = 1, the OUT0 Output Buffer Is Powered Down. h00[1] R/W b0 PD_OUT1 For PD_OUT1 = 1, the OUT1 Output Buffer Is Powered Down. h00[3] R/W b0 PD_OUT2 For PD_OUT2 = 1, the OUT2 Output Buffer Is Powered Down. h00[5] R/W b0 REV[2:0] Part Revision Code. h07[7:5] R b001 SYNC_EN0 For SYNC_EN0 = 1, the OUT0 Output Will Synchronize to the Clock Input During the SYNC Procedure. If SYNC_EN0 = 0, Then the OUT0 Output Ignores the Input to the SYNC Pin. h01[7] R/W b1 SYNC_EN1 For SYNC_EN1 = 1, the OUT1 Output Will Synchronize to the Clock Input During the SYNC Procedure. If SYNC_EN1 = 0, Then the OUT1 Output Ignores the Input to the SYNC Pin. h03[7] R/W b1 SYNC_EN2 For SYNC_EN2 = 1, the OUT2 Output Will Synchronize to the Clock Input During the SYNC Procedure. If SYNC_EN2 = 0, Then the OUT2 Output Ignores the Input to the SYNC Pin. h05[7] R/W b1 6954f For more information www.linear.com/LTC6954 37 LTC6954 Applications Information I/O INTERFACE The LTC6954 is a high performance clock distribution chip. To achieve the best performance, it is important to select the proper circuitry to interface to the high frequency, low noise inputs and outputs. INPUT BUFFER The LTC6954 provides a flexible interface to either differential or single-ended frequency sources. The maximum input signal frequency is 1.4GHz (1.8GHz for the LTC6954-1 when DELx = 0). Any signal source may be directly coupled (DC) to the LTC6954, as long as its signal swing is less than 1.5VP-P and its common mode voltage is approximately the self-bias voltage of the input buffer (see Figure 18). If the input signal is too large, it should be attenuated to avoid turning on the input protection diodes. If the common mode voltage is too high or low, the signal must be level shifted or AC-coupled. To achieve the best noise performance, it is important that the input frequency source have low phase noise and a slew rate of at least 100V/s. Additionally, the input signal transmission line should be terminated as close to the input pins as possible to minimize reflections. Refer to the Electrical Characteristics table for the specified input impedance of the LTC6954. Common signals that may be DC-coupled into the LTC6954's input include 2.5V CML and 3.3V LVPECL. Common signals that must be AC-coupled into the LTC6954's input include 3.3V CML, LVDS, CMOS and RF style, 50 output sine wave oscillators (<7.5dBm signal). 2.5V CML and 3.3V LVPECL signals may optionally be AC-coupled if system design considerations require it. Figure 19 shows many common IN input signal interfaces. Note that all signal traces are assumed to be 50 transmission lines. BIAS VIN+ VIN+ 2.05V 1.2k 27 28 1.2k IN+ IN- 6954 F18 Figure 18. Simplified IN Input Schematic 6954f 38 For more information www.linear.com/LTC6954 LTC6954 Applications Information SINE WAVE OSCILLATOR 50 OUTPUT IN+ ZO ZO PI ATTENUATOR 49.9 IN+ 49.9 LTC6954 LTC6954 49.9 49.9 IN - 49.9 IN - 49.9 AC-COUPLED RF SINE WAVE OSCILLATOR, OUTPUT >7.5dBm AC-COUPLED RF SINE WAVE OSCILLATOR, OUTPUT 7.5dBm IN+ ZO IN+ ZO 2.5V CML 100 3.3V LVPECL LTC6954 ZO 150 IN - ZO IN - 150 DC-COUPLED 2.5V CML AC-COUPLED 3.3V LVPECL IN+ ZO 49.9 3.3V LVPECL IN+ ZO 5V PECL LTC6954 100 49.9 IN - 330 LTC6954 IN - ZO ZO 150 LTC6954 100 330 150 DC-COUPLED 3.3V LVPECL AC-COUPLED 5V PECL PREFERRED IMPLEMENTATION ZO IN+ ZO IN - 3.3V LVPECL LTC6954 49.9 IN+ ZO 3.3V CML 2.5V CML 100 ZO LTC6954 IN - 49.9 AC-COUPLED 2.5V/3.3V CML 46.4 ALTERNATIVE DC-COUPLED 3.3V LVPECL IN+ ZO LVDS 100 ZO LTC6954 IN - 6954 F19 AC-COUPLED LVDS Figure 19. Common IN Input Interface Configurations. All ZO Signal Traces Are 50 Transmission Lines. All Capacitors Are 0.1F. All Resistors and Capacitors Are Placed as Close as Possible to the Driver or Receiver with the Transmission Line in Between 6954f For more information www.linear.com/LTC6954 39 LTC6954 Applications Information LVPECL OUTPUTS (LTC6954-1/LTC6954-2/LTC6954-3) Disabling the internal bias, by connecting OUTxSEL to GND, allows the LVPECL output driver to be configured using standard LVPECL bias and termination networks. The LTC6954 provides up to three low noise, low skew LVPECL compatible output drivers designed for frequencies up to 1.4GHz (1.8GHz for the LTC6954-1 when DELx = 0). Refer to Table 9 For the output configurations available. The output driver provides considerable flexibility for biasing and termination. Refer to Figure 20 for a simplified schematic of the LVPECL output. The LTC6954 allows powering down of many blocks, including the LVPECL output drivers. When an LVPECL output driver is powered down, the output pins will float to approximately 0.8V below VOUTx+. Depending on the external bias and termination circuits connected to the LVPECL output pins, the output driver may actually source current in this mode. To achieve maximum power savings, it is recommended that no terminations or other bias circuitry be connected to an unused LVPECL output that will be powered down. Additionally, if the output is expected to be turned on and off, using the internal IBIAS with the single 100 differential termination configuration gives the lowest power consumption in the powered down state. The output driver can be biased internally by setting the appropriate OUTxSEL HIGH. Using the internal bias is ideal for AC-coupling applications as it replaces the need for a 150 resistor to ground to provide the necessary bias for each output. It is also useful when the receiving chip can handle 3.3V LVPECL inputs directly, then only a 100 differential resistor located near the receiver input is required for proper transmission line termination. VOUTx+ The LVPECL outputs are emitter followers and thus have a low output impedance. LVPECL output signals also have very fast rise and fall times. To maintain proper signal integrity (sharp rise and fall times with minimal ringing), route signals with well controlled transmission lines with proper far-end termination. In cases where the full LVPECL signal swing is not required, consider using a series resistor to provide additional near-end transmission line termination. With both near- and far-end termination, manufacturing variations of the transmission lines in production are more easily tolerated. This configuration is also recommended for driving ADCs as discussed in the "Using the LTC6954 to Clock ADC Sample Clock Inputs" section. VOUTx+ OUT+ OUT - OUTxSEL OUTxSEL 6954 F20 Figure 20. Simplified LVPECL Output Schematic Table 9.LTC6954 OUTPUT Configuration with LVPECL Outputs Highlighted LTC6954 VERSION OUTPUT 0 OUTPUT 1 OUTPUT 2 OUT0SEL = GND OUT0SEL = VA+ OUT1SEL = GND OUT1SEL = VA+ OUT2SEL = GND OUT2SEL = VA+ LTC6954-1 LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LTC6954-2 LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LVPECL (IBIAS is Off) LVPECL (IBIAS is On) CMOS LVDS LTC6954-3 LVPECL (IBIAS is Off) LVPECL (IBIAS is On) CMOS LVDS CMOS LVDS LTC6954-4 CMOS LVDS CMOS LVDS CMOS LVDS 6954f 40 For more information www.linear.com/LTC6954 LTC6954 Applications Information Figure 21 shows how to interface the LVPECL outputs to many typical input receivers. Driving an LVDS input is a somewhat special case. Most LVDS inputs are designed to accept a wide range of input signal swings and common mode levels. For many LVDS inputs, a simple connection is fine. For LVDS inputs operating on a lower power supply voltage, a 1.2V common mode level is required. This requirement is easily met by using a few resistors LVPECL+ to level-shift the signal from 1.85V down to 1.2V. In this configuration, the signal's peak-to-peak amplitude is also reduced, but the LVPECL signal is much larger than the LVDS signal (1600mVP-PDIFF vs 750mVP-PDIFF) so the signal at the LVDS receiver is at the correct level for both the common mode level and the voltage swing. As a side benefit, this configuration also provides both near and far-end transmission line termination. LVPECL+ ZO 54.9 ZO 49.9 100 LTC6954 LVPECL- 3.3V CML 2.5V CML 3.3V LVPECL LTC6954 LVPECL- ZO 95.3 DC-COUPLED INTO A 2.5V/3.3V CML, 3.3V LVPECL (LVPECL INTERNAL IBIAS ENABLED) ZO 95.3 DC-COUPLED INTO AN LVDS OR AN ADC WITH A 1.2V COMMON MODE LEVEL (LVPECL INTERNAL IBIAS DISABLED) PREFERRED IMPLEMENTATION LVPECL+ 49.9 54.9 LVPECL+ ZO 27.4 ZO 49.9 3.3V CML 2.5V CML 3.3V LVLVPECL LTC6954 49.9 LVPECL- 150 27.4 ZO LVDS OR ADCs THAT CAN ACCEPT A 1.8V COMMON MODE LEVEL 150 BACK TERMINATED DC-COUPLED INTO AN ADC THAT CAN ACCEPT A 1.85V COMMON MODE LEVEL (LVPECL INTERNAL IBIAS ENABLED) ZO 3.3V CML 2.5V CML 3.3V LVPECL LTC6954 LVPECL- 100 LTC6954 LVPECL- ZO DC-COUPLED INTO A 2.5V/3.3V CML, 3.3V LVPECL (LVPECL INTERNAL IBIAS DISABLED) LVPECL+ LVDS OR ADCs WITH 1.2V COMMON MODE LEVEL ZO 49.9 LVPECL+ LTC6954 LVPECL- 27.4 27.4 ZO 100 ZO AC-COUPLED INTO LVDS OR ADCs WITH A SELF-BIASED INPUT 49.9 46.4 AC-COUPLED INTO AN LVDS OR AN ADC WITH A SELF-BIASED INPUT (LVPECL INTERNAL IBIAS ENABLED) ALTERNATIVE DC-COUPLED INTO A 2.5V/3.3V CML, 3.3V LVPECL (LVPECL INTERNAL IBIAS DISABLED) 6954 F21 Figure 21. Common LVPECL Output Interface Configurations. All ZO Signal Traces Are 50 Transmission Lines. All Capacitors Are 0.1F. All Resistors and Capacitors Are Placed as Close as Possible to the Driver or Receiver with the Transmission Line in Between 6954f For more information www.linear.com/LTC6954 41 LTC6954 Applications Information LVDS/CMOS OUTPUTS (LTC6954-2/LTC6954-3/ LTC6954-4) part versions with LVDS/CMOS outputs and the available OUTxSEL configurations. The LTC6954-2/LTC6954-3/LTC6954-4 have the capability to provide one or more LVDS or CMOS outputs. See Figure 22 and Figure 23 for simplified schematics of this output. Connecting the corresponding output's OUTxSEL pin to VA+ enables LVDS compatible operation at frequencies up to 1.4GHz, while connecting it to GND configures two CMOS compatible output drivers with a maximum operating frequency of 250MHz. Table 10 shows the LVDS OUTPUT MODE (OUTxSEL = VA+) When the output is configured for LVDS operation, the output current has two settings controlled by the LVCS bit, as shown in Table 11. LVCSx = 0 supplies current for 100 differential termination and has a maximum operating frequency of 800MHz. The termination resistor should be located near the receiver input to reduce signal reflections. VOUTx+ VOUTx+ OUTx+ OUTx+ V+ OUTx- V+ OUTx- 6954 F23 6954 F22 Figure 22. Simplified LVDS/CMOS Output Schematic (LVDS Mode, CMOS Circuit Shutdown) Figure 23. Simplified LVDS/CMOS Output Schematic (CMOS Mode, LVDS Circuit Shutdown) Table 10. LTC6954 Output Configuration with LVDS/CMOS Outputs Highlighted LTC6954 VERSION OUTPUT 0 OUTPUT 1 + OUTPUT 2 + OUT0SEL = GND OUT0SEL = VA OUT1SEL = GND OUT1SEL = VA OUT2SEL = GND OUT2SEL = VA+ LTC6954-1 LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LTC6954-2 LVPECL (IBIAS is Off) LVPECL (IBIAS is On) LVPECL (IBIAS is Off) LVPECL (IBIAS is On) CMOS LVDS LTC6954-3 LVPECL (IBIAS is Off) LVPECL (IBIAS is On) CMOS LVDS CMOS LVDS LTC6954-4 CMOS LVDS CMOS LVDS CMOS LVDS Table 11. LVDS Current Settings CLOCK OUTPUT OUT0 BIT DESCRIPTOR BIT REG ADDR (HEX) VALUE ILVDS LVCS0 [6] h02 0 3.5mA 100 1 7mA 50 (100 || 100) 0 3.5mA 100 1 7mA 50 (100 || 100) 0 3.5mA 100 1 7mA 50 (100 || 100) OUT1 LVCS1 [6] h04 OUT2 LVCS2 [6] h06 DIFFERENTIAL TERMINATION 6954f 42 For more information www.linear.com/LTC6954 LTC6954 Applications Information variations. Figure 24 shows many common LVDS output interfaces to various logic types of inputs. Setting LVCSx = 1 provides twice the current and enables a maximum operating frequency of 1.4GHz. The higher current setting (ILVDS = 7mA) is ideal for applications where the LVDS output driver is double-terminated (near- and far-end termination). For example, if the LVDS output is terminated at the near end with a differential 100 resistor, and at the far end with a differential 100 resistor, programming LVCSx = 1 for 7mA operation will allow full LVDS swings. This configuration is properly terminated at both ends, and is therefore more forgiving of the transmission line design and PCB production Each LVDS output can be independently powered down using the PD_OUTx bit. Refer to Table 6, Serial Port Register Mapping, for the name and location of the power down bits. When the LVDS output is powered down it will be in a Hi-Z state. When the LVDS/CMOS output is configured to LVDS output mode, the CMSINVx bits are ignored. These bits only apply to a CMOS configured output. V+ CMOS+ 10 ZO CMOS+ CMOS LTC6954 10 100 ZO CMOS 100 LTC6954 CMOS- CMOS- CMOS OUTPUT MODE, DC-COUPLED AND DOUBLY TERMINATED INTO CMOS (SIGNAL SWING AT THE LOAD WILL BE REDUCED) CMOS OUTPUT MODE, DC-COUPLED INTO CMOS WITH A SERIES SOURCE TERMINATION (TRANSMISSION LINE SHOULD BE NO LONGER THAN 10cm) V+ 10 CMOS+ 100 ZO CMOS 100 LTC6954 CMOS- CMOS OUTPUT MODE, AC-COUPLED AND DOUBLY TERMINATED INTO CMOS (SIGNAL SWING AT THE LOAD WILL BE REDUCED) LVDS+ LTC6954 LVDS LVDS+ ZO LVDS 100 - LTC6954 ZO LVDS ZO 100 - LVDS OR ADC 100 ZO LVDS OUTPUT MODE, DC-COUPLED AND DOUBLY TERMINATED INTO LVDS (ILVDS = 7mA) LVDS OUTPUT MODE, DC-COUPLED AND FAR-END TERMINATED INTO LVDS (ILVDS = 3.5mA) 3.3V 680 LVDS+ ZO LTC6954 LVDS- 680 3.3V LVPECL CML 100 ZO 1.00k 1.00k THIS CIRCUIT WORKS WITH MANY LVPECL RECEIVER PARTS THAT CAN ACCEPT THE SMALLER LVDS SIGNAL SWING (700mVP-P DIFF FOR LVDS COMPARED TO 1600mVP-P DIFF FOR LVPECL) LVDS OUTPUT MODE, AC-COUPLED INTO LVPECL OR CML (ILVDS = 3.5mA) 6954 F24 Figure 24. Common LVDS/CMOS Output Interface Configurations. All ZO Signal Traces Are 50 Transmission Lines. All Capacitors Are 0.1F. All Resistors and Capacitors Are Placed as Close as Possible to the Driver or Receiver with the Transmission Line in Between 6954f For more information www.linear.com/LTC6954 43 LTC6954 Applications Information CMOS OUTPUT MODE (OUTxSEL = GND) POWER SUPPLIES FOR CMOS OPERATION When the output driver is configured for CMOS operation, programming the bit CMSINVx to 1 inverts the OUT - relative to OUT+. Setting CMSINVx to 0 results in both OUT+ and OUT - being in-phase. See Table 12 for a summary of the registers containing the CMOS phase control bits for each clock output distribution path. Note that degradation of the phase noise performance can occur if the output supply, VOUTx+, is noisy because of additional broadband noise or discrete spectral tones. Noise on the VOUTx+ supply will amplitude-modulate the clock signal. This AM noise may then corrupt the spectral purity through AM to PM conversion. However, using the LTC6954 in LVDS mode will greatly reduce the power supply noise coupling relative to CMOS mode, due to the differential nature of the LVDS outputs. CLOCK OUTPUT BIT DESCRIPTOR BITS REG ADDR (HEX) OUT0 CMSINV0 [6] h01 OUT1 CMSINV1 [6] h03 OUT2 CMSINV2 [6] h05 Each CMOS output can be independently powered down using the PD_OUTx bit. Refer to Table 6, Serial Port Register Mapping, for the name and location of the power down bits. When the CMOS output is powered down and CMSINVx = 0 both outputs will be LOW. When CMSINVx = 1, OUTx+ will be LOW and OUTx- will be HIGH. When the LVDS/CMOS output is configured to CMOS output mode, the LVCSx bits are ignored. These bits only apply to a LVDS configured output. While the CMOS output is rated at 250MHz, it is recommended that the LVDS output mode be used for operation at frequencies beyond 50MHz. The nature of CMOS signaling (single-ended, large current spikes, large signal swing, poor capacitive load driving) makes it most useful for lower frequencies and short interconnection length. For higher frequencies or longer interconnection lengths, LVDS output mode is a much better choice. LVDS is designed to drive transmission lines and its inherent differential nature provides superior noise immunity. When a CMOS signal is required, Figure 24 shows some common interfaces. The use of the series termination is the most common configuration and is suitable for short interconnection lengths as the transmission line and the receiver's input capacitance will reduce the rise and fall times. The doubly-terminated circuits suffer from reduced signal swing at the far end and may not be acceptable with some CMOS input circuits. TEMPERATURE MONITOR The LTC6954 provides an on-chip diode at Pin 31 (TEMP) for chip temperature measurement. Pin 31 is connected to the anode of an internal diode with its cathode connected to internal ground. The chip temperature can be measured by injecting a constant DC current into Pin 31 and measuring its DC voltage. The voltage vs temperature coefficient of the diode is about -1.73mV/C with 10A current injected into the TEMP pin. Figure 25 shows a typical temperature voltage behavior when 10A and 100A currents are injected into Pin 31. A significant percentage of the total current used in the LTC6954 is connected to ground through the exposed pad. The temperature measurement provides a good indicator that the exposed package pad has a good thermal and electrical connection. 900 850 TEMP DIODE VOLTAGE (mV) Table 12. CMOS Phase-Select Registers 800 750 700 650 600 100A 10A 550 500 450 400 -40 -20 20 40 60 80 100 120 0 JUNCTION TEMPERATURE (C) 6954 F25 Figure 25. TEMP Diode Voltage vs Junction Temperature (TJ) 6954f 44 For more information www.linear.com/LTC6954 LTC6954 Applications Information Use of a diode based temperature monitoring part such as the LTC2997 is recommended for an accurate measurement. Refer to the LTC2997 Data Sheet for specific information regarding it's use. If the temperature monitoring feature is not used, connect TEMP to GND. PCB LAYOUT GUIDELINES The LTC6954 requires a printed circuit board (PCB) with a clean unbroken ground plane in the first layer beneath the part. A multilayer board with an internal ground plane is recommended. Care must be taken when creating a PCB layout to minimize power supply and ground inductances and to prevent signals from interfering with each other. Layout for the printed circuit board should ensure that digital signals (serial port, SYNC and OUTxSEL pins) and analog signals (all other signal pins) are separated as much as possible. Additionally, top layer ground fill and grounded vias should be used as barriers to isolate signals from each other. The LTC6954 input and all signal outputs must be routed using transmission lines. Traces should be as short as possible to minimize capacitance and interference pickup. The LTC6954's demonstration circuit, DC1954, provides a good example of proper PCB layout. The files for this demo circuit are found on the Linear Technology (www. linear.com) website's LTC6954 landing page. and minimizes channel-to-channel crosstalk. Demo circuit DC1954 provides a good example of good supply connections, proper bypassing and capacitor ground connections. Bypass capacitors must be located as close to the pins as possible and connected to ground through a low impedance path. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The ground connection for each capacitor must have its own ground via and should also be connected to the top layer ground pour. THE EXPOSED PAD CONNECTION: SIGNAL GROUNDING AND HEAT TRANSFER The exposed pad on the bottom of the package is the primary ground connection for the LTC6954 and its connection is as important as any other pin on this part. The inductance to the ground plane must be kept to a minimum to ensure peak performance and good signal integrity. The exposed pad must be soldered directly to a matching PCB land. The PCB land pattern should be connected to the internal ground planes by an array of vias, as shown in Figure 26. Consult the QFN Package User's Guide on Linear Technology website's Packaging Information page for specific recommendations concerning land patterns and land via solder masks. VIA ARRAY CONNECTS EXPOSED PAD 18 17 16 15 14 13 19 12 SUPPLY BYPASSING 20 11 21 10 High quality ceramic bypass capacitors such as X5R, X7R or X6S dielectrics should be used at all of the V+ supply pins (VA+, VD+, VIN+, VOUT0+, VOUT1+ and VOUT2+). Each pin should have its own bypass capacitor if possible. This is easily achieved with 0201 size capacitors located on the top side layer with the LTC6954. A good strategy is to use 0.01F, size 0201 capacitors, at one capacitor per pin, on the top side of the PCB with additional 0.1F size 0402 connected to selected pin pairs on the back side of the PCB. This provides good, high frequency bypassing 22 9 23 8 24 7 25 6 26 5 27 4 28 3 29 2 30 1 31 32 33 34 35 36 6954 F26 Figure 26. Exposed Pad Land Pattern Highlighting the Array of Ground Vias. Also Note Pins 14, 26, 29, 32 and 35 Are Signal Ground and Connected Directly to the Exposed Pad Land 6954f For more information www.linear.com/LTC6954 45 LTC6954 Applications Information Additionally, most of the heat generated by the LTC6954 is removed from the die through the bottom side exposed pad onto the printed circuit board. Fortunately, the previously mentioned guidelines for signal grounding also yield the best thermal assembly and layout. Soldering of the exposed pad to a matching PCB land provides the most direct thermal connection. Connecting this PCB land to all ground layers through an array of vias also is the best way to add thermal mass and to spread the heat as much as possible. For best thermal transfer, the array of vias should extend to the back side of the PCB where a sizable area of the solder mask should be cleared to open the plated copper directly to the air. The exposed area should be at least as large as the land pattern on the top of the PCB. Again, demo circuit DC1954 provides a good example of grounding the LTC6954 from both the signal and thermal standpoints. In a standard laboratory environment, without moving air, demo circuit DC1954's PCB layout yields a junction temperature rise of about 20C for every watt of power dissipated. Following the previously mentioned guidelines achieves a good ground signal connection and a good thermal connection. However, much of this good practice can be undone if the ground plane has a significant void or narrowing near the part. This often occurs inadvertently when there is a long row of adjacent signal or power vias. The clearance around these vias can be very close to each other or overlapping, creating a void in the plane. In extreme cases a small ground island can form. One area on the LTC6954 where a ground plane void could occur is on the side of the part with the outputs OUT0 through OUT2 (Pins 1 to 12). The most difficult case is when all three outputs are to be routed using stripline transmission lines (transmission lines buried between ground planes inside the PCB). Figure 27 illustrates the issue. Using stripline transmission lines necessitates vias to a lower layer preferably located close to each output pin. Additionally, all of the VOUTx+ power pins require a via to the power plane that should ideally also be located close to each pin. As shown in Figure 27, when all of these vias are located as close to each pin as possible (which is good for many reasons) and in a row, there is a significant void in the ground plane in this area. This void is undesirable both electrically and thermally. The empty space increases the ground inductance for the output return signal path and decreases the flow of heat in that direction. Figure 27 also illustrates that by pulling some of the vias away from the part, in this case the OUTx output vias, significant paths for current and heat flow are opened. This is not ideal from the transmission line design standpoint, but definitely improves the ground path inductance and VIAS CONNECT EXPOSED PAD 18 17 16 15 14 VIAS CONNECT EXPOSED PAD 13 18 17 16 15 14 13 19 12 19 12 20 11 20 11 21 10 21 10 22 9 22 9 23 8 23 8 24 7 24 7 25 6 25 6 26 5 26 5 27 4 27 4 28 3 28 3 29 2 29 2 30 1 30 31 THERMAL FLOW PATH IS BLOCKED 32 33 34 35 36 SIGNAL RETURN PATHS ARE BLOCKED GROUND PLANE IMPROVED SIGNAL RETURN PATHS 1 31 32 33 BETTER THERMAL FLOW PATHS 34 35 36 GROUND PLANE 6954 F27 Figure 27. The Ground Plane Can Be Inadvertently Split by a Row of Vias Resulting in Higher Ground Impedance and Poor Heat Transfer. Moving Some Vias or Staggering Them Fixes the Problem 6954f 46 For more information www.linear.com/LTC6954 LTC6954 Applications Information the thermal flow. Alternatively, the VOUTx+ supply vias could be pulled farther away from the part or a microstrip transmission line on layer 1 of the PCB could be utilized instead of the strip lines eliminating the need for output vias entirely. ADC CLOCKING AND JITTER REQUIREMENTS Adding noise directly to a clean signal clearly reduces its signal-to-noise ratio (SNR). In data acquisition applications, digitizing a clean signal with a noisy clock signal also degrades the SNR. This issue is best explained in the time domain using jitter instead of phase noise. For this discussion, assume that the jitter is white (flat with frequency) and of Gaussian distribution. Figure 28 shows a sine wave signal entering a typical data acquisition circuit composed of an ADC, an input signal amplifier and a sampling clock. Also shown are three signal sampling scenarios for sampling the sine wave at its zero crossing. In the first scenario, a perfect sine wave input is buffered by a noiseless amplifier to drive the ADC. Sampling is performed by a perfect, zero jitter clock. Without any added SINE WAVE INPUT SIGNAL AMP noise or sampling clock jitter, the ADC's digitized output value is very clearly determined and perfectly repeatable from cycle to cycle. In the second scenario, a perfect sine wave input is buffered by a noisy amplifier to drive the ADC. Sampling is performed by a perfect, zero jitter clock. The added noise results in an uncertainty in the digitized value developing an error term which degrades the SNR. The degraded SNR in this scenario, adding noise to the signal, is expected. In the third scenario, a perfect sine wave input is buffered by a noiseless amplifier to drive the ADC. Sampling is performed by a clock signal with added jitter. Note that as the signal is slewing, the jitter of the clock signal leads to an uncertainty in the digitized value and an error term just as in the previous scenario. Again, this error term degrades the SNR. A real world system will have both some additive amplifier noise and some sample clock jitter. Once the signal is digitized, determining the root cause of any SNR degradation--amplifier noise or sampling clock jitter--is often impossible. ADC BITS SAMPLING CLOCK SINE WAVE INPUT SIGNAL WITH NOISELESS AMP VSAMPLE SINE WAVE INPUT SIGNAL WITH NOISY AMP V = VERROR SINE WAVE INPUT SIGNAL WITH NOISELESS AMP V = VERROR tJ PERFECT SAMPLING CLOCK PERFECT SAMPLING CLOCK 6954 F28 SAMPLING CLOCK WITH ADDED JITTER Figure 28. A Typical Data Acquisition Circuit Showing the Sampling Error Effects of a Noisy Amplifier and a Jittery Sampling Clock 6954f For more information www.linear.com/LTC6954 47 LTC6954 Applications Information Degradation of the SNR due to sample clock jitter only occurs if the input signal is slewing. If the input signal is stationary (DC), then it does not matter when in time the sampling occurs. Additionally, a faster slewing signal yields a greater error (more noise) than a slower slewing signal. Figure 29 demonstrates this effect. Note how much larger the error term is with the fast slewing signal than with the slow slewing signal. The conclusion is to maintain the data converter's SNR performance, digitization of high input frequency signals requires a clock with much less jitter than applications with lower frequency input signals. FAST SINE WAVE SLOW SINE WAVE V = VERROR(FAST) V = VERROR(SLOW) tJ 6954 F29 Figure 29. Fast and Slow Sine Wave Signals Sampled with a Jittery Clock jitter is the RMS sum of the ADC's aperture jitter and the sample clock jitter calculated as follows: t J(TOTAL) = t2J(CLK) + t2J(ADC) Alternatively, for a given total jitter, the attainable SNR limitation is calculated as follows: SNRdB = -20 * Iog10 (2 * * fSIG * tJ(TOTAL)) These calculations assume a full-scale sine wave input signal. If the input signal is a complex, modulated signal with a moderate crest factor, the peak slew rate of the signal may be lower and the sample clock jitter requirement may be relaxed. These calculations are also theoretical. They assume a noiseless ADC with infinite resolution. All realistic ADCs have both added noise and a resolution limit. The limitations of the ADC must be accounted for to prevent overspecifying the sampling clock. Figure 30 plots the previous equations and provides a simple and quick way to estimate the sampling clock jitter requirement for a given input signal or the expected SNR performance for a given sample clock jitter. It is important to note that the frequency of the input signal determines the sample clock's jitter requirement. The actual sample clock frequency does not matter. Many ADC applications that undersample high frequency signals have especially challenging sample clock jitter requirements. 102 TOTAL CLOCK JITTER (RMS) 10fs 20fs 50fs 100fs 200fs 500fs 1ps 2ps 5ps 10ps 20ps 50ps 96 90 SNR (dB) The previous discussion was useful for gaining an intuitive feel for the SNR degradation due to sampling clock jitter. Quantitatively, the actual sample clock jitter requirement for a given application is calculated as follows: 108 84 78 72 66 60 54 -SNRdB 20 t J(TOTAL) = 2 * * fSIG 10 48 10 100 1000 FREQUENCY OF FULL-SCALE INPUT SIGNAL (MHz) 6954 F30 Where fSIG is the highest frequency signal to be digitized expressed in Hz, SNRdB is the SNR requirement in decibels and tJ(TOTAL) is the total RMS jitter in seconds. The total Figure 30. SNR vs Input Signal Frequency vs Sample Clock Jitter 6954f 48 For more information www.linear.com/LTC6954 LTC6954 Applications Information ADC SAMPLE CLOCK INPUT DRIVE REQUIREMENTS Modern high speed, high resolution ADCs are incredibly sensitive components able to match laboratory instruments in many regards. With wide bandwidth and wide dynamic range, noise or interfering signals on the analog signal input, the voltage reference or the sampling clock input can easily appear in the digitized data. To deliver the full performance of any ADC, the sampling clock input must be driven with a clean, low jitter signal. Figure 31 shows a simplified version of a typical ADC sample clock input. In this case, the input pins are labeled ENC for encode, while some ADCs label the inputs CLK for clock. The input is composed of a differential limiting amplifier stage followed by a buffer that directly controls the ADC's track-and-hold stage. The input amplifier requires a minimum input signal amplitude to enter limiting. The sampling clock signal's amplitude should be somewhat greater than the minimum requirement to assure that the amplifier is limiting under all conditions, but not so large as to damage the ADC. A typical minimum input signal level is in the 300mVP-PDIFF to 400mVP-PDIFF range. The sample clock input amplifier also benefits from a fast slewing input signal as the amplifier has noise of its own. By slewing through the crossover region quickly, the amplifier noise creates less jitter than if the transition was slow. As shown in Figure 31, the ADC's sample clock input is typically differential. Although the amplifier will work fine with a single-ended input signal, a differential sampling clock typically delivers the best performance. The LTC6954 meets all of these sample clock input requirements. The output signals are differential, low phase noise (thus low jitter), have sharp rise and fall times and drive high speed transmission lines with more than enough signal swing. The LTC6954's LVPECL outputs are recommended for the best phase noise performance. While the LVDS and CMOS signals provide good phase noise performance, the LVPECL outputs have the lowest phase noise. TRANSMISSION LINES AND TERMINATION Interconnection of high speed signaling with fast rise and fall times requires the use of transmission lines with properly matched termination. The transmission lines may be stripline, microstrip or any other design topology. A detailed discussion of transmission line design is beyond the scope of this data sheet. Any mismatch between the transmission line's characteristic impedance and the terminating impedance results in a portion of the signal reflecting back toward the other end of the transmission line. In the extreme case of an open- or short-circuit termination, all of the signal is reflected back. This signal reflection leads to overshoot and ringing on the waveform. The frequency of ringing is proportional to the propagation delay through the transmission line, which is mostly dependent on the length of the line. The VDD 1.2V ENC+ 10k ENC- 6954 G31 Figure 31. Simplified ADC Sample Clock Input Circuit 6954f For more information www.linear.com/LTC6954 49 LTC6954 Applications Information amplitude of the ringing is dependent on the degree of mismatch between the transmission line's characteristic impedance and the termination impedance at each end of the line. The greater the mismatch, the larger the reflection and the greater the amplitude of the ringing. Figure 32 shows three methods of transmission line termination with a low impedance driver and a high impedance receiver. Near- and far-end termination is sometimes referred to as double termination. The advantage of double termination over the simpler far-end or near-end termination is if there is any mismatch at the far end, its reflection will be largely absorbed by the near-end termination and the reflected energy dies out rapidly as each re-reflected signal is considerably smaller at each turn. ZO 100 ZO FAR END TERMINATION (PARALLEL OR SHUNT TERMINATION) 50 50 ZO The disadvantage of double termination is that the signal level at the receiver is only half the amplitude of the source's signal. However, this loss of signal amplitude is acceptable in many cases. The series resistor used in near-end termination also adds some noise to the signal. ZO NEAR END TERMINATION (SERIES TERMINATION) 50 50 ZO 100 ZO being re-reflected back to the receiver. The far-end receiver is a high impedance and is poorly matched to the transmission line resulting in most of the signal being reflected back to the driver. The termination at the source absorbs most of this reflected signal, but if there is a mismatch in the impedance, some of the signal is re-reflected back to the receiver. This back-and-forth signaling continues until the reflected signal energy eventually dies out. 6954 F32 NEAR AND FAR END TERMINATION (DOUBLE TERMINATION) Figure 32. Transmission Line Termination Methods (ZO = 50) Far-end termination is sometimes referred to as parallel or shunt termination of the transmission line. Its purpose is to match the transmission line's impedance and prevent signal reflection back to the driver. Any mismatch at the far end results in a portion of the initial signal being reflected back to the driver. As the low impedance driver is poorly matched to the transmission line, most of this reflected signal is re-reflected back to the receiver. This back and forth signaling continues until the reflected signal energy eventually dies out. Near-end termination is sometimes referred to as series or back termination. Its purpose is to match the transmission line and prevent any reflected signal from the far end from Double termination makes for a more robust and forgiving system design. Production variation of the printed circuit board (PCB) that would affect the transmission line's characteristic impedance are more easily accommodated. Variation of the termination resistor value and its nonidealities are also less critical. Delivering good signal integrity is more easily achieved with double termination of transmission lines at the cost of some added noise. ADC SAMPLE CLOCK INPUT SIGNAL INTEGRITY REQUIREMENTS Figure 31 is a simplified ADC sample clock input circuit. The simplification omits many of the circuit details and also omits parasitic elements in the circuit. These parasitic elements play an important role in the ADC's sample clock input signal integrity requirements. Logic applications tolerate signal overshoot and ringing to a very high level. For a logic system to work properly, the only requirement is that logic 0 and logic 1 states are separable. A logic 0 or logic 1 state signal with large amounts of ringing, ripple and interference causes little concern in a logic system. 6954f 50 For more information www.linear.com/LTC6954 LTC6954 Applications Information The ADC sample clock input has a different signal integrity requirement than a logic input. In fact, the ADC sample clock should never be thought of as a logic signal. It is more like the local oscillator (LO) input signal of a mixer where signal noise, ringing and interferers are imprinted onto the signal of interest. However, in a mixer application, undesired out of band signals are often easily filtered away at the output. Due to the sampling nature of an ADC, undesired high frequency signals can fold back into the frequency band of interest and corrupt the desired signal. In the case of an ADC, noise, ringing and interference can appear in the digitized data along with the analog input signal and are not easily removed with digital filtering. Without considering parasitic signal paths, it appears that once the input amplifier is limiting, any noise or ringing at the ADC's sample clock input has no affect. However, the ADC's sample clock input has several parasitic elements that provide a signal path to the track-and-hold circuit and ultimately to the digitized data. On-chip layout and device parasitic capacitance present one path for undesired high frequency signals to couple into the track-and-hold. Another path is the ADC's substrate resistance. As this resistance is finite, coupling through this path is also possible. The coupling through these paths is heavily attenuated, but with SFDR in excess of 100dB in modern ADCs, it does not take very much coupled signal to appear in the digitized data. USING THE LTC6954 TO DRIVE ADC SAMPLE CLOCK INPUTS As noted earlier, the LTC6954's LVPECL outputs are recommended for the best phase noise performance. These outputs are designed to interface with standard LVPECL devices while driving transmission lines with far-end termination only. Configured this way, the signal conforms to the LVPECL standard and the swing is very large, at 1.6VP-PDIFF. The use of far-end termination only in LVPECL systems presents trade-offs of power consumption, signal swing and signal integrity (overshoot and ringing). As the LTC6954's LVPECL output signal's rise and fall times are very fast (typically less than 135ps), there is typically no need for a signal as large as the full LVPECL level at the ADC sample clock input. An approach to consider is to use the LVPECL outputs and provide both near-end and far-end termination of the transmission line. The signal is attenuated at the far end and does not meet the LVPECL signal level specifications, but most ADC sample clock inputs do not require a proper LVPECL level signal. Figure 33 shows three LVPECL output configurations that satisfy this requirement. One configuration has the standard LVPECL common mode voltage and the other is level-shifted down to a 1.2V common mode voltage. Being 50% duty cycle signals, AC-coupling the outputs is also a viable solution, as shown in the last configuration. LVPECL+ 27.4 ZO LTC6954 100 LVPECL- 27.4 ADC ADCs THAT CAN ACCEPT A 1.8V COMMON MODE SIGNAL ADC ADCs WITH 1.2V COMMON MODE VOLTAGE ADC AC-COUPLED INTO ADCs WITH A SELFBIASED INPUT ZO LVPECL OUTPUT IBIAS ENABLED LVPECL+ 54.9 ZO 49.9 LTC6954 LVPECL- 49.9 54.9 ZO 95.3 95.3 LVPECL OUTPUT IBIAS DISABLED LVPECL+ LTC6954 LVPECL- 27.4 27.4 ZO 100 ZO LVPECL OUTPUT IBIAS ENABLED 6954 F33 Figure 33. LVPECL Output Connections to ADC Sample Clock Inputs (ZO = 50) 6954f For more information www.linear.com/LTC6954 51 LTC6954 Applications Information Note that the series, near-end termination is 27.4, not 50. The LTC6954's LVPECL output impedance is about 5 and must also be accounted for, but the biggest reason the near-term resistor is less than 50 is because it adds noise to the signal. So, the near-end termination shown here presents a trade-off of transmission line impedance matching over production variations (signal integrity) against the added noise. If the far-end termination is perfectly matched to the transmission line's characteristic impedance, then the near-end termination is not needed at all. However, perfect matching is elusive, and making provisions in the PCB layout for near-end series termination, even if initially populated with 0 resistors, is highly recommended. While the LVPECL outputs provide the best ADC sample clock driver performance, the LVDS output can still provide very good performance. Compared to the LVPECL output, the LVDS output has slightly higher 1/f phase noise and LVDS+ phase noise floor. This slightly higher phase noise, and jitter, are still suitable for many ADC applications. When driving the sample clock input of an ADC with the LVDS output driver, it is best to use the highest current setting (LVCSx = 1 for ILVDS = 7mA), and a doubly-terminated transmission line, as shown in Figure 34. This configuration is properly terminated at both ends, and is therefore more forgiving of the transmission line design and PCB production variations. Using the CMOS output to drive the sample clock input of high performance, high frequency ADCs is not recommended. Using the same output pins in LVDS output mode is a better performing choice and certainly better for routing the signal any significant length. However, some ADCs require a CMOS level sample clock signal. In these cases, the connection between the LTC6954 and the ADC should be as short as possible with partial source termination, as shown in Figure 35. ZO LTC6954 100 LVDS- ADC 100 ZO ADCs WITH 1.2V COMMON MODE VOLTAGE LVDS OUTPUT MODE, DC-COUPLED AND DOUBLY TERMINATED INTO THE ADC SAMPLE CLOCK INPUT (LV/CM OUTPUT IN LVDS MODE, ILVDS = 7mA) 6954 F34 Figure 34. LVDS Output Connections to ADC Sample Clock Inputs (ZO = 50) CMOS+ LTC6954 10 ZO ADC ADC REQUIRING A CMOS LEVEL SAMPLE CLOCK CMOS- CMOS OUTPUT MODE, DC-COUPLED INTO AN ADC REQUIRING A CMOS LEVEL SAMPLE CLOCK (TRANSMISSION LINE SHOULD BE NO LONGER THAN 10cm) 6954 F35 Figure 35. CMOS Output Connections to ADC Sample Clock Inputs (ZO = 50) 6954f 52 For more information www.linear.com/LTC6954 LTC6954 Typical Applications SDO 50 0.1F SENSE 1.8V C19 0.1F C23 2.2F 48 47 46 45 44 43 42 41 40 39 VDD VDD SENSE VREF SDO GND OF DNC D15 D14 ANALOG 0.1F 1 V CM INPUT 0.1F T1 2 25 315.5MHz AIN+ -1dBFS 3 AIN- 25 4 GND 5 REFH 0.1F - + 0.1F 6 REFL + CN1 - LTC2165 7 REFH - + 8 REFL C21 + - 0.1F 9 PAR/SER PAR/SER 10 T1: MACOM ETC1-1-13 GND RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 11 CN1: 2.2F LOW INDUCTANCE GND INTERDIGITATED CAPACITOR 12 VDD TDK CLLE1AX780G225M 1.8V MURATA LLA219C70G225M VDD GND ENC+ ENC- CS SCK SDI GND D0 D1 C18 AVX W2L14Z225M 13 14 15 16 17 18 19 20 21 22 0.1F OR EQUIVALENT 100pF 0.1F 49.9 100pF 49.9 OUT0+ SYNC SYNC CONTROL OUT0SEL OUT1SEL OUT2SEL 3.3V SDO SPI SERIAL PORT D3 24 LTC6954-3 IN- 49.9 C37 0.1F 3.3V V+ IN+ D2 23 DIGITAL OUTPUTS 1.8V C32 0.1F C28 0.1F 100pF 37 D13 D12 36 D11 35 D10 34 D9 33 D8 32 OVDD 31 OGND 30 CLKOUT+ 29 CLKOUT- 28 D7 27 D6 26 D5 25 D4 SPI PORT R51 100 1GHz 38 SERIAL PORT AND DIGITAL DEL = 0 DIV = 10 DELAY 0 TO 63 DIVIDE 1 TO 63 DELAY 0 TO 63 DIVIDE 1 TO 63 100MHz OUT0- OUT1+ OUT1- OUT2+ OUT2- SDI SCLK CS GND 6954 F36 Figure 36. LTC6954 Driving the Encode Sample Clock Input of an LTC2165, 125Msps, 16-Bit ADC 6954f For more information www.linear.com/LTC6954 53 LTC6954 Typical Applications 0 TOTAL SYSTEM SNR = 68.8dB LTC6954 JITTER = 113fsRMS -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 FREQUENCY (MHz) 40 50 6954 F37 Figure 37. LTC2165 64k Point FFT, fIN = 315MHz, -1dBFS, 100Msps. Sample Clock Provided by the LTC6954 at 100MHz 6954f 54 For more information www.linear.com/LTC6954 LTC6954 Package Description Please refer to http://www.linear.com/product/LTC6954#packaging for the most recent package drawings. UFF Package 36-Lead Plastic QFN (4mm x 7mm) (Reference LTC DWG # 05-08-1863 Rev O) 0.70 0.05 4.50 0.05 3.10 0.05 5.61 0.05 2.50 REF 2.64 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 5.50 REF 6.10 0.05 7.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 PIN 1 NOTCH R = 0.30 OR 0.25 x 45 CHAMFER R = 0.10 TYP 0.75 0.05 2.50 REF 35 36 0.40 0.10 PIN 1 TOP MARK (NOTE 6) 7.00 0.10 1 2 5.50 REF 5.61 0.10 2.64 0.10 (UFF36) QFN 0810 REV O 0.200 REF 0.00 - 0.05 R = 0.125 TYP 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC6954 6954f 55 LTC6954 Typical Application UP TO 1.4GHz Additive Phase Noise vs Offset Frequency, fIN = 622.08MHz, Mx[5:0] = 4, fOUTx = 155.52MHz 3.3V V+ IN+ IN 50 SYNC 50 DELAY 0 TO 63 SYNC CONTROL OUT0SEL DELAY 0 TO 63 OUT1SEL 3.3V OUT2SEL SDO SPI SERIAL PORT SDI SERIAL PORT AND DIGITAL DELAY 0 TO 63 -120 LTC6954-3 - DIVIDE 1 TO 63 DIVIDE 1 TO 63 DIVIDE 1 TO 63 OUT0+ OUT0- OUT1+ OUT1- OUT2+ OUT2- LVPECL OUTPUT FREQUENCY UP TO 1.4GHz LVDS OUTPUT FREQUENCY UP TO 1.4GHz CMOS OUTPUT FREQUENCY UP TO 250MHz SCLK ADDITIVE PHASE NOISE (dBc/Hz) 0.1F -130 -140 -150 -160 -170 -180 CS GND 6954 TA02a 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 6954 TA02b Related Parts PART NUMBER DESCRIPTION COMMENTS LTC6945 Ultralow Noise and Spurious Integer-N Synthesizer 350MHz to 6GHz, -226dBc/Hz Normalized In-Band Phase Noise Floor, -157dBc/Hz Wideband Output Phase Noise Floor LTC6946 Ultralow Noise and Spurious Integer-N Synthesizer with Integrated VCO 370MHz to 6.4GHz, -226dBc/Hz Normalized In-Band Phase Noise Floor, -157dBc/Hz Wideband Output Phase Noise Floor LTC6947 Ultralow Noise and Spurious Fractional-N Synthesizer 350MHz to 6GHz, -226dBc/Hz Normalized In-Band Phase Noise Floor, -157dBc/Hz Wideband Output Phase Noise Floor, Integer-N Spurious Performance LTC6948 Ultralow Noise and Spurious Fractional-N Synthesizer with Integrated VCO 370MHz to 6.4GHz, -226dBc/Hz Normalized In-Band Phase Noise Floor, -157dBc/Hz Wideband Output Phase Noise Floor, Integer-N Spurious Performance LTC6950 Low Phase Noise and Spurious Integer-N PLL Core with Five Output Clock Distribution and EZSync Clock Edge Synchronization 1.4GHz Max VCO Frequency, Additive Jitter <20fsRMS, -226dBc/Hz Normalized In-Band Phase Noise Floor, -274dBc/Hz Normalized 1/f Phase Noise Floor LTC6957 Low Phase Noise, Dual Output Buffer/Driver/Logic Converter Optimized Conversion of Sine Waves to Logic Levels, LVPECL/LVDS/CMOS Outputs, DC-300MHz, 45fsRMS additive jitter (LVPECL) 6954f 56 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC6954 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC6954 LT 1115 * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2015