TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
TAOS091D − DECEMBER 2008
5
The LUMENOLOGY r Company r
r
Copyright E 2008, TAOS Inc.
www.taosinc.com
NOTES: 2. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 640 nm LEDs
and infrared 940 nm LEDs are used for final product testing for compatibility with high-volume production.
3. The 640 nm irradiance Ee is supplied by an AlInGaP light-emitting diode with the following characteristics: peak wavelength
λp = 640 nm and spectral halfwidth Δλ½ = 17 nm.
4. The 940 nm irradiance Ee is supplied by a GaAs light-emitting diode with the following characteristics: peak wavelength
λp = 940 nm and spectral halfwidth Δλ½ = 40 nm.
5. Integration time Tint, is dependent on internal oscillator frequency (fosc) and on the integration field value in the timing register as
described in the Register Set section. For nominal fosc = 735 kHz, nominal Tint = (number of clock cycles)/fosc.
Field value 00: Tint = (11 × 918)/fosc = 13.7 ms
Field value 01: Tint = (81 × 918)/fosc = 101 ms
Field value 10: Tint = (322 × 918)/fosc = 402 ms
Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01),
and 322/322 = 1 (field value 10).
6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also
by a 2-count offset.
Full scale ADC count value = ((number of clock cycles)/2 − 2)
Field value 00: Full scale ADC count value = ((11 × 918)/2 − 2) = 5047
Field value 01: Full scale ADC count value = ((81 × 918)/2 − 2) = 37177
Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached
for 131074 clock cycles, which occurs for Tint = 178 ms for nominal fosc = 735 kHz.
7. Low gain mode has 16 lower gain than high gain mode: (1/16 = 0.0625).
8. The sensor Lux is calculated using the empirical formula shown on p. 22 of this data sheet based on measured Ch0 and Ch1 ADC
count values for the light source specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual
Lux) ratio is estimated based on the variation of the 640 nm and 940 nm optical parameters. Devices are not 100% tested with
fluorescent or incandescent light sources.
AC Electrical Characteristics, VDD = 3 V, TA = 25C (unless otherwise noted)
PARAMETER†TEST CONDITIONS MIN TYP MAX UNIT
t(CONV) Conversion time 12 100 400 ms
Clock frequency (I2C only) 0 400 kHz
f(SCL) Clock frequency (SMBus only) 10 100 kHz
t(BUF) Bus free time between start and stop condition 1.3 μs
t(HDSTA)
Hold time after (repeated) start condition. After
this period, the first clock is generated. 0.6 μs
t(SUSTA) Repeated start condition setup time 0.6 μs
t(SUSTO) Stop condition setup time 0.6 μs
t(HDDAT) Data hold time 0 0.9 μs
t(SUDAT) Data setup time 100 ns
t(LOW) SCL clock low period 1.3 μs
t(HIGH) SCL clock high period 0.6 μs
t(TIMEOUT) Detect clock/data low timeout (SMBus only) 25 35 ms
tFClock/data fall time 300 ns
tRClock/data rise time 300 ns
CiInput pin capacitance 10 pF
†Specified by design and characterization; not production tested.