Complete, High Speed 16-Bit A/D Converters AD1376/AD1377 Digital output data is provided in parallel form with corresponding clock and status outputs. All digital inputs and outputs are TTL-compatible. FEATURES Complete 16-bit converters with reference and clock 0.003% maximum nonlinearity No missing codes to 14 bits over temperature Fast conversion 17 s to 16 bits (AD1376) 10 s to 16 bits (AD1377) Short cycle capability Adjustable clock rate Parallel outputs Low power 645 mW typical (AD1376) 585 mW typical (AD1377) Industry-standard pinout For the AD1376, the serial output function is no longer available after date code 0111. For the AD1377, the serial output function is no longer available after date code 0210. The option of applying an external clock on the CONVERT START pin to slow down the internally set conversion time is no longer supported for either part. PRODUCT HIGHLIGHTS GENERAL DESCRIPTION The AD1376/AD1377 are high resolution, 16-bit analog-todigital converters with internal reference, clock, and lasertrimmed thin-film applications resistors. The AD1376/AD1377 are excellent for use in high resolution applications requiring moderate speed and high accuracy or stability over commercial temperature ranges (0C to 70C). They are packaged in compact 32-lead, ceramic seam-sealed (hermetic), dual in-line packages (DIP). Thin-film scaling resistors provide bipolar input ranges of 2.5 V, 5 V, and 10 V and unipolar input ranges of 0 V to +5 V, 0 V to +10 V, and 0 V to +20 V. 1. The AD1376/AD1377 provide 16-bit resolution with a maximum linearity error of 0.003% (1/2 LSB14) at 25C. 2. The AD1376 conversion time is 14 s (typical) short cycled to 14 bits, and 16 s to 16 bits. 3. The AD1377 conversion time is 8 s (typical) short cycled to 14 bits, and 9 s to 16 bits. 4. Two binary codes are available on the digital output. They are CSB (complementary straight binary) for unipolar input voltage ranges and COB (complementary offset binary) for bipolar input ranges. Complementary twos complement (CTC) coding may be obtained by inverting Pin 1 (MSB). 5. The AD1376/AD1377 include internal reference and clock with external clock rate adjust pin, and parallel digital outputs. FUNCTIONAL BLOCK DIAGRAM (MSB) BIT 1 1 BIT 2 2 32 SHORT CYCLE AD1376/AD1377 31 CONVERT START BIT 3 3 REFERENCE BIT 4 4 30 +5V DC SUPPLY VL 29 GAIN ADJUST 28 +15V DC SUPPLY VCC BIT 6 6 27 COMPARATOR IN 16-BIT DAC BIT 5 5 BIT 7 7 BIT 8 8 BIT 9 9 7.5k 26 BIPOLAR OFFSET 25 +10V 3.75k 3.75k BIT 10 10 23 CLK RATE CTRL BIT 11 11 22 ANALOG COMMON 16-BIT SAR 21 -15V DC SUPPLY V EE (LSB FOR 13 BITS) BIT 13 13 (LSB FOR 14 BITS) BIT 14 14 20 CLOCK OUT COMPARATOR CLOCK 19 DIGITAL COMMON BIT 15 15 18 STATUS BIT 16 16 17 NC 00699-001 BIT 12 12 24 +20V Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.481.3113 (c) 2005 Analog Devices, Inc. All rights reserved. AD1376/AD1377 TABLE OF CONTENTS Specifications..................................................................................... 3 Input Scaling ..................................................................................7 Absolute Maximum Ratings............................................................ 5 Calibration (14-Bit Resolution Examples) .................................8 ESD Caution.................................................................................. 5 Grounding, Decoupling, and Layout Considerations ..............9 Description of Operation ................................................................ 6 Clock Rate Control........................................................................9 Gain Adjustment .......................................................................... 6 High Resolution Data Acquisition System.............................. 10 Zero Offset Adjustment............................................................... 6 Applications..................................................................................... 11 Timing............................................................................................ 7 Outline Dimensions ....................................................................... 12 Digital Output Data ..................................................................... 7 Ordering Guide .......................................................................... 12 REVISION HISTORY 6/05--Rev. C to Rev. D Updated Format..................................................................Universal Updated Outline Dimensions ....................................................... 12 6/03--Rev. B to Rev. C Removed Serial Output Function and Adjustable Clock Rate ........................................................Universal Updated Format..................................................................Universal Changes to General Description .................................................... 1 Changes to Product Highlights....................................................... 1 Changes to Functional Block Diagram.......................................... 1 Inserted ESD Warning ..................................................................... 3 Change to Ordering Guide.............................................................. 3 Change to Figure 7 ........................................................................... 5 Deleted text from Digital Output Data.......................................... 5 Deleted Figure 9 and Renumbered Remainder of Figures.......... 5 Deleted the `Using the AD1376 or AD1377 at Slower Conversion Times' Section ............................................... 8 Deleted Figure 16.............................................................................. 8 Change to Figure 13 ......................................................................... 9 Change to Figure 14 ......................................................................... 9 Updated Outline Dimensions ....................................................... 10 Rev. D | Page 2 of 12 AD1376/AD1377 SPECIFICATIONS Typical at TA = 25C, VS = 15 V, +5 V, unless otherwise noted. Table 1. Model RESOLUTION ANALOG INPUTS Voltage Ranges Bipolar Min Unipolar Impedance (Direct Input) 0 V to +5 V, 2.5 V 0 V to +10 V, 5.0 V 0 V to +20 V, 10 V DIGITAL INPUTS1 Convert Command Logic Loading TRANSFER CHARACTERISTICS2 (ACCURACY) Gain Error Offset Error Unipolar Bipolar Linearity Error (Max) Inherent Quantization Error Differential Linearity Error POWER SUPPLY SENSITIVITY 15 V DC (0.75 V) +5 V DC (0.25 V) CONVERSION TIME5 12 Bits (AD1376) 14 Bits (AD1376) 16 Bits (AD1376) 14 Bits (AD1377) 16 Bits (AD1377) POWER SUPPLY REQUIREMENTS Analog Supplies Digital Supply AD1376 Power Consumption +15 V Supply Drain -15 V Supply Drain +5 V Supply Drain AD1377 Power Consumption +15 V Supply Drain -15 V Supply Drain +5 V Supply Drain WARM-UP TIME AD1376JD/AD1377JD Typ Max 16 Min 2.5 5 10 0 to 5 0 to 10 0 to 20 2.5 5 10 0 to 5 0 to 10 0 to 20 1.88 3.75 7.50 1.88 3.75 7.50 1 Unit Bits V V V V V V V k k k Trailing edge of positive 50 ns (min) pulse 1 LS TTL Load 0.053 0.2 0.053 0.2 % 0.053 0.053 0.006 1/2 0.003 0.1 0.2 0.053 0.053 0.003 1/2 0.003 0.1 0.2 % of FSR4 % of FSR % of FSR LSB % of FSR 0.0015 0.001 +14.5 -14.5 +4.75 AD1376KD/AD1377KD Typ Max 16 0.0015 0.001 11.5 13.5 15.5 13 15 17 8.75 10 +15 -15 +5 600 +10 -23 +18 600 +10 -23 +18 1 +15.5 -15.5 +5.25 800 800 Rev. D | Page 3 of 12 +14.5 -14.5 +4.75 % of FSR/% VS % of FSR/% VS 11.5 13.5 15.5 13 15 17 8.75 10 s s s s s +15 -15 +5 600 +10 -23 +18 600 +10 -23 +18 1 +15.5 -15.5 +5.25 800 V dc V dc V dc mW mA mA mA mW mA mA mA Minutes 800 AD1376/AD1377 Model DRIFT6 Gain Offset Unipolar Bipolar Linearity Guaranteed No Missing Code Temperature Range DIGITAL OUTPUT1 (All Codes Complementary) Parallel Output Codes7 Unipolar Bipolar Output Drive Status Status Output Drive Internal Clock9 Clock Output Drive Frequency TEMPERATURE RANGE Specification Operating Storage Min AD1376JD/AD1377JD Typ Max 2 2 Min AD1376KD/AD1377KD Typ Max Unit 15 5 15 ppm/C 4 10 3 2 3 0.3 4 10 2 ppm of FSR/C ppm of FSR/C ppm of FSR/C 0 to 70 (13 Bits) 0 to 70 (14 Bits) C CSB COB, CTC8 5 Logic 1 During Conversion CSB COB, CTC8 5 Logic 1 During Conversion LSTTL Loads 5 5 5 LSTTL Loads 5 1040/1750 1040/1750 LSTTL Loads kHz 0 to 70 -25 to +85 -55 to +125 0 to 70 -25 to +85 -55 to +125 C C C 1 Logic 0 = 0.8 V max; Logic 1 = 2.0 V min for inputs. For digital outputs, Logic 0 = 0.4 V max. Logic 1 = 2.4 V min. Tested on 10 V and 0 V to +10 V ranges. 3 Adjustable to zero. 4 Full-scale range. 5 Conversion time may be shortened with "short cycle" set for lower resolution. 6 Guaranteed but not 100% production tested. 7 CSB-Complementary Straight Binary. COB-Complementary Offset Binary. CTC-Complementary Twos Complement. 8 CTC coding obtained by inverting MSB (Pin 1). 9 With Pin 23, clock rate controls tied to digital ground. 2 Rev. D | Page 4 of 12 AD1376/AD1377 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Logic Supply Voltage Analog Inputs (Pin 24 and Pin 25) Analog Ground to Digital Ground Digital Inputs Junction Temperature Storage Temperature Lead Temperature (10 sec) Rating 18 V +7 V 25 V 0.3 V -0.3 V to VDD + 0.3 V 175C 150C 300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 5 of 12 AD1376/AD1377 DESCRIPTION OF OPERATION 0.0120 0.0080 0.0060 0.0030 0 -0.0030 0 GAIN ADJUSTMENT -0.0120 The gain adjustment circuit consists of a 100 ppm/C potentiometer connected across VS with its slider connected through a 300 k resistor to Pin 29 (GAIN ADJ) as shown in Figure 5. -0.0060 -0.0080 -0.0135 -0.0195 0 25 TEMPERATURE (C) 00699-002 70 If no external trim adjustment is desired, Pin 27 (COMPARATOR IN) and Pin 29 can be left open. +15V AD1376 300k 29 AD1376/AD1377 0.01F -15V Figure 5. Gain Adjustment Circuit (0.2% FSR) 0.100 SHORT CYCLED TO 12 BITS ZERO OFFSET ADJUSTMENT SHORT CYCLED TO 13 BITS The zero offset adjustment circuit consists of a 100 ppm/C potentiometer connected across VS with its slider connected through a 1.8 M resistor to Pin 27 for all ranges. As shown in Figure 6, the tolerance of this fixed resistor is not critical; a carbon composition type is generally adequate. Using a carbon composition resistor having a -1200 ppm/C temperature coefficient contributes a worst-case offset temperature coefficient of 32 LSB14 x 61 ppm/LSB14 x 1200 ppm/C = 2.3 ppm/C of FSR, if the offset adjustment potentiometer is set at either end of its adjustment range. Since the maximum offset adjustment required is typically no more than 16 LSB14, use of a carbon composition offset summing resistor typically contributes no more than 1 ppm/C of FSR offset temperature coefficient. SHORT CYCLED TO 14 BITS 1/2LSB 12-BIT 0.010 0.006 1/2LSB 13-BIT 0.003 1/2LSB 14-BIT 0.001 5 10 15 CONVERSION TIME (s) 20 Figure 3. AD1376 Nonlinearity vs. Conversion Time 0.100 GAIN DRIFT ERROR (% FSR) 10k TO 100k 100ppm/C 00699-003 LINEARITY AND DIFFERENTIAL LINEARITY ERROR (% OF FSR) Figure 2. Linearity Error vs. Temperature 0.068 0.038 +15V 0 10k TO 100k 0 -0.038 1.8M 27 AD1376/AD1377 00699-006 LINEARITY ERROR (% FSR) 2ppm/C, 0.003%, @ 25C 0.0135 feedback DAC. The analog input is successively compared to the feedback DAC output, one hit at a time (MSB first, LSB last). The decision to keep or reject each bit is then made at the completion of each bit comparison period, depending on the state of the comparator at that time. 0.0195 3ppm/C, 0.006%, @ 25C 00699-005 AD1376/AD1377JD AD1376/AD1377KD -15V -0.068 Figure 6. Zero Offset Adjustment Circuit (0.3% FSR) 00699-004 -0.100 0 10 20 30 40 50 60 70 Figure 4. Gain Drift Error vs. Temperature An alternate offset adjustment circuit, which contributes a negligible offset temperature coefficient if metal film resistors (temperature coefficient <100 ppm/C) are used, is shown in Figure 7. +15V OFFSET ADJ Rev. D | Page 6 of 12 10k TO 100k 180k M.F. 180k M.F. 27 AD1376/AD1377 22k M.F. -15V Figure 7. Low Temperature Coefficient Zero Adjustment Circuit 00699-007 On receipt of a CONVERT START command, the AD1376/ AD1377 convert the voltage at the analog input into an equivalent 16-bit binary number. This conversion is accomplished as follows: the 16-bit successive approximation register (SAR) has its 16-bit outputs connected both to the device bit output pins and to the corresponding bit inputs of the AD1376/AD1377 In either adjustment circuit, the fixed resistor connected to Pin 27 should be located close to this pin to keep the pin connection short. Pin 27 is quite sensitive to external noise pickup and should be guarded by ANALOG COMMON. DIGITAL OUTPUT DATA The timing diagram is shown in Figure 8. Receipt of a CONVERT START signal sets the STATUS flag, indicating conversion in progress. This in turn removes the inhibit applied to the gated clock, permitting it to run through 17 cycles. All the SAR parallel bits, the STATUS flip-flops, and the gated clock inhibit signal are initialized on the trailing edge of the CONVERT START signal. At time t0, B1 is reset and B2-B16 are set unconditionally. At t1, the Bit 1 decision is made (keep) and Bit 2 is reset unconditionally. This sequence continues until the Bit 16 (LSB) decision (keep) is made at t16. The STATUS flag is reset, indicating that the conversion is complete and that the parallel output data is valid. Resetting the STATUS flag restores the gated clock inhibit signal, forcing the clock output to the low Logic 0 state. Note that the clock remains low until the next conversion. Corresponding parallel data bits become valid on the same positive-going clock edge. (1) MAXIMUM THROUGHPUT TIME CONVERT START CONVERSION TIME (2) INTERNAL CLOCK MSB t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 (2) 0 20ns MIN TO 90ns Figure 9. LSB Valid to Status Low Short Cycle Input Pin 32 (SHORT CYCLE) permits the timing cycle shown in Figure 8 to be terminated after any number of desired bits has been converted, allowing somewhat shorter conversion times in applications not requiring full 16-bit resolution. When 10-bit resolution is desired, Pin 32 is connected to Bit 11 output Pin 11. The conversion cycle then terminates and the STATUS flag resets after the Bit 10 decision (Figure 8). Short cycle connections and associated 8-, 10-, 12-, 13-, 14-, and 15-bit conversion times are summarized in Table 3 for a 1.6 MHz clock (AD1377) or 933 kHz clock (AD1376). Table 3. Short Cycle Connections 1 BIT 2 BIT 3 1 0 BIT 4 Resolution (% Bits FSR) 16 0.0015 15 0.003 14 0.006 13 0.012 12 0.024 10 0.100 8 0.390 0 BIT 5 BIT 6 1 BIT 7 1 BIT 8 1 0 BIT 9 1 BIT 10 1 BIT 11 BIT 12 1 1 BIT 13 0 BIT 14 BIT 15 LSB t16 BUSY (STATUS) (3) t17 1 0 MSB 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 LSB 0 NOTES: 1. THE CONVERT START PULSEWIDTH IS 50ns MIN AND MUST REMAIN LOW DURING A CONVERSION. THE CONVERSION IS INITIATED BY THE TRAILING EDGE OF THE CONVERT COMMAND. 2. MSB DECISION. 3. CLOCK REMAINS LOW AFTER LAST BIT DECISION. Figure 8. Timing Diagram (Binary Code 0110011101111010) 00699-008 STATUS BIT 16 VALID 00699-009 TIMING Parallel data from TTL storage registers is in negative true form (Logic 1 = 0 V and Logic 0 = 2.4 V). Parallel data output coding is complementary binary for unipolar ranges and complementtary offset binary for bipolar ranges. Parallel data becomes valid at least 20 ns before the STATUS flag returns to Logic 0, permitting parallel data transfer to be clocked on the 1 to 0 transition of the STATUS flag (see Figure 9). Parallel data output changes state on positive going clock edges. Maximum Conversion Time (s) Status Flag AD1377 AD1376 Reset 10 17.1 t16 9.4 16.1 t15 8.7 15.0 t1 8.1 13.9 t13 7.5 12.9 t12 6.3 10.7 t10 5.0 8.6 t8 Connect Short Cycle Pin 32 to NC (Open) Pin 16 Pin 15 Pin 14 Pin 13 Pin 11 Pin 9 INPUT SCALING The ADC inputs should be scaled as close to the maximum input signal range as possible to use the maximum signal resolution of the ADC. Connect the input signal as shown in Table 4. See Figure 10 for circuit details. Rev. D | Page 7 of 12 AD1376/AD1377 Table 4. Input Scaling Connections Input Signal Line 10 V 5 V 2.5 V 0 V to +5 V 0 V to +10 V 0 V to +20 V Connect Pin 26 to Pin 271 Pin 271 Pin 271 Pin 22 Pin 22 Pin 22 Connect Pin 24 to Input Signal Open Pin 271 Pin 271 Open Input Signal Connect Input Signal to Pin 24 Pin 25 Pin 25 Pin 25 Pin 25 Pin 24 Pin 27 is extremely sensitive to noise and should be guarded by ANALOG COMMON. 10V SPAN R1 3.75k GAIN ADJ -15V COMP IN 27 REF CONTROL 29 0.01F TO SAR FROM DAC 1F + IOS = 1.3mA COMPARATOR 1F ANALOG 22 COMMON + 21 -15V 00699-010 VREF A 3.75k 22 7.5k BIPOLAR 26 OFFSET 16-BIT DAC 7.5k 28 +15V KEEP/ REJECT 16-BIT SUCCESSIVE APPROMIXATION REGISTER AD1376/ AD1377 300k 30 19 23 26 27 24 IIN 25 +5V + eIN 1F Figure 10. Input Scaling Circuit 10k TO 100k CALIBRATION (14-BIT RESOLUTION EXAMPLES) (0V TO +10V) 1.8M +15V ZERO ADJ -15V NOTE: ANALOG ( External zero adjustment and gain adjustment potentiometers, connected as shown in Figure 5 and Figure 6, are used for device calibration. To prevent interaction of these two adjustments, zero is always adjusted first and then gain. Zero is adjusted with the analog input near the most negative end of the analog range (0 for unipolar and minus full scale for bipolar input ranges). Gain is adjusted with the analog input near the most positive end of the analog range. ) AND DIGITAL ( ) GROUNDS ARE NOT TIED INTERNALLY AND MUST BE CONNECTED EXTERNALLY. Figure 11. Analog and Power Connections for Unipolar 0 V to 10 V Input Range +15V GAIN ADJ -15V REF CONTROL 29 0.01F +15V + IOS = 1.3mA -10 V to +10 V Range Set analog input to -9.99878 V; adjust zero for 1111111111110 digital output (complementary offset binary) code. Set analog input to 9.99756 V; adjust gain for 00000000000001 digital output (complementary offset binary) code. Half-scale calibration check: set analog input to 0.00000 V; digital output (complementary offset binary) code should be 01111111111111. -15V 3.75k 22 1F 16-BIT DAC 7.5k 28 1F KEEP/ REJECT 16-BIT SUCCESSIVE APPROMIXATION REGISTER AD1376/ AD1377 300k 10k TO 100k 0 V to 10 V Range Set analog input to +1 LSB14 = 0.00061 V. Adjust zero for digital output = 11111111111110. Zero is now calibrated. Set analog input to +FSR - 2 LSB = 9.99878 V. Adjust gain for 00000000000001 digital output code; full scale (gain) is now calibrated. Half-scale calibration check: set analog input to 5.00000 V; digital output code should be 01111111111111. 00699-011 20V SPAN +15V 10k TO 100k + 21 30 19 23 26 27 24 A IIN 25 +5V + eIN 1F +15V 10k TO 100k 1.8M (-10V TO +10V) ZERO ADJ -15V NOTE: ANALOG ( ) AND DIGITAL ( ) GROUNDS ARE NOT TIED INTERNALLY AND MUST BE CONNECTED EXTERNALLY 00699-012 R2 3.75k 24 3.75k 25 3.75k 1 Output Code COB COB COB CSB CSB CSB Figure 12. Analog and Power Connections for Bipolar -10 V to +10 V Input Range Other Ranges Representative digital coding for 0 V to +10 V and -10 V to +10 V ranges is given in the 0 V to 10 V Range section and -10 V to +10 V Range section. Coding relationships and calibration points for 0 V to +5 V, -2.5 V to +2.5 V, and -5 V to +5 V ranges can be found by halving proportionally the corresponding code equivalents listed for the 0 V to +10 V and -10 V to +10 V ranges, respectively, as indicated in Table 5. Rev. D | Page 8 of 12 AD1376/AD1377 Table 5. Transition Values vs. Calibration Codes Output Code MSB LSB1 000 .........0002 Range +Full Scale 011.........111 Midscale 111.........110 -Full Scale 1 2 10 V +10 V -3/2 LSB 0V -1/2 LSB -10 V +1/2 LSB 5 V +5 V -3/2 LSB 0V -1/2 LSB -5 V +1/2 LSB 2.5 V +2.5 V -3/2 LSB 0V -1/2 LSB -2.5 V +1/2 LSB 0 V to +10 V +10 V -3/2 LSB +5 V -1/2 LSB 0V +1/2 LSB 0 V to +5 V +5 V -3/2 LSB +2.5 V -1/2 LSB 0V +1/2 LSB For LSB value for range and resolution used, see Table 6. Voltages given are the nominal value for transition to the code specified. Table 6. Input Voltage Range and LSB Values Analog Input Voltage Range Code Designation One Least Significant Bit (LSB) FSR 2n n=8 n = 10 n = 12 n = 13 n = 14 n = 15 2 3 5 V COB1 or CTC2 2.5 V COB1 or CTC2 0 V to +10 V CSB3 0 V to +5 V CSB3 20 V 10 V 5V 10 V 5V n n 2 78.13 mV 19.53 mV 4.88 mV 2.44 mV 1.22 mV 0.61 mV n 2 39.06 mV 9.77 mV 2.44 mV 1.22 mV 0.61 mV 0.31 mV n 2 19.53 mV 4.88 mV 1.22 mV 0.61 mV 0.31 mV 0.15 mV 2 39.06 mV 9.77 mV 2.44 mV 1.22 mV 0.61 mV 0.31 mV 2n 19.53 mV 4.88 mV 1.22 mV 0.61 mV 0.31 mV 0.15 mV COB = complementary offset binary. CTC = complementary twos complement--achieved by using an inverter to complement the most significant bit to produce MSB. CSB = complementary straight binary Zero- and full-scale calibration can be accomplished to a precision of approximately 1/2 LSB using the static adjustment procedure described previously. By summing a small sine or triangular wave voltage with the signal applied to the analog input, the output can be cycled through each of the calibration codes of interest to more accurately determine the center (or end points) of each discrete quantization level. A detailed description of this dynamic calibration technique is presented in Analog-Digital Conversion Handbook, edited by D. H. Sheingold, Prentice Hall, Inc., 1986. GROUNDING, DECOUPLING, AND LAYOUT CONSIDERATIONS Many data acquisition components have two or more ground pins that are not connected together within the device. These grounds are usually referred to as DIGITAL COMMON (logic power return), ANALOG COMMON (analog power return), or analog signal ground. These grounds (Pin 19 and Pin 22) must be tied together at one point as close as possible to the converter. Ideally, a single solid analog ground plane under the converter would be desirable. Current flows through the wires and etch stripes of the circuit cards, and since these paths have resistance and inductance, hundreds of millivolts can be generated between the system analog ground point and the ground pins of the ADC. Separate wide conductor stripe ground returns should be provided for high resolution converters to minimize noise and IR losses from the current flow in the path from the converter to the system ground point. In this way, ADC supply currents and other digital logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. Each of the ADC supply terminals should be capacitively decoupled as close to the ADC as possible. A large value (such as 1 F) capacitor in parallel with a 0.1 F capacitor is usually sufficient. Analog supplies are to be bypassed to the ANALOG COMMON (analog power return) Pin 22 and the logic supply is bypassed to DIGITAL COMMON (logic power return) Pin 19. The metal cover is internally grounded with respect to the power supplies, grounds, and electrical signals. Do not externally ground the cover. CLOCK RATE CONTROL The AD1376/AD1377 can be operated at faster conversion times by connecting the clock rate control (Pin 23) to an external multiturn trim potentiometer (TCR <100 ppm/C) as shown in Figure 13. Rev. D | Page 9 of 12 15V DC 5k 2.25MHz @ 5V 23 AD1376/AD1377 1750kHz @ DGND Figure 13. Clock Rate Control Circuit 00699-013 1 10 V COB1 or CTC2 AD1376/AD1377 HIGH RESOLUTION DATA ACQUISITION SYSTEM The essential details of a high resolution data acquisition system using a 16-bit sample-and-hold amplifier (SHA) and the AD1376/AD1377 are shown in Figure 14. Conversion is initiated by the falling edge of the CONVERT START pulse. This edge drives the device's STATUS line high. The inverter then drives the SHA into hold mode. STATUS remains high throughout the conversion and returns low once the conversion is completed. This allows the SHA to re-enter track mode. This circuit can exhibit nonlinearities arising from transients produced at the ADC's input by the falling edge of CONVERT START. This edge resets the ADC's internal DAC; the resulting transient depends on the SHA's present output voltage and the ADC's prior conversion result. In the circuit of Figure 15, the falling edge of CONVERT START also places the SHA into hold mode (via the ADC's STATUS output), causing the reset transient to occur at the same moment as the SHA's track-andhold transition. Timing skews and capacitive coupling can cause some of the transient signal to add to the signal being acquired by the SHA, introducing nonlinearity. A much safer approach is to add a flip-flop, as shown in Figure 15. The rising edge of CONVERT START places the track-and-hold device into hold mode before the ADC reset transients begin. The falling edge of STATUS places the SHA back into track mode. System throughput will be reduced if a long CONVERT START pulse is used. Throughput can be calculated from Throughput = 1 TACQ + TCONV + TCS where: TACQ is the track-and-hold acquisition time. TCONV is the time required for the ADC conversion. TCS is the duration of CONVERT START. The combination of the AD1376 and a 16-bit SHA can provide greater than 50 kHz throughput. No significant track-and-hold droop error will be introduced, provided the width of CONVERT START is small compared with the ADC's conversion time. +15V -15V 10F 10F + + 10F ANALOG INPUT -10V TO +10V +5V + SHA -10V TO +10V +15V -15V 10F 30 26 21 27 24 AD1376/ AD1377 22 10F + + 10F 28 SHA -10V TO +10V ANALOG INPUT -10V TO +10V +5V + 30 26 21 27 24 AD1376/ AD1377 22 BITS 1-16 28 BITS 1-16 19 19 18 31 +5V 31 S J Q HC112 00699-014 CONVERT START K Figure 14. Basic Data Acquisition System Interconnections 16-Bit SHA R Q 00699-015 18 CONVERT START Figure 15. Improved Data Acquisition System 1 Rev. D | Page 10 of 12 AD1376/AD1377 APPLICATIONS The AD1376/AD1377 are excellent for use in high resolution applications requiring moderate speed and high accuracy or stability over commercial (0C to 70C) temperature ranges. Typical applications include medical and analytic instrumentation, precision measurement for industrial robotics, automatic test equipment (ATE), multichannel data acquisition systems, servo control systems, or anywhere wide dynamic range is required. A proprietary monolithic DAC and laser-trimmed thin-film resistors guarantee a maximum nonlinearity of 0.003% (1/2 LSB14). The converters may be short cycled to achieve faster conversion times--15 s to 14 bits for the AD1376 or 8 s to 14 bits for the AD1377. Rev. D | Page 11 of 12 AD1376/AD1377 OUTLINE DIMENSIONS 1.728 (43.89) MAX 32 17 1.102 (27.99) 1.079 (27.41) 16 1 PIN 1 INDICATOR (NOTE 1) 0.225 (5.72) MAX 0.025 (0.64) 0.015 (0.38) 0.206 (5.23) 0.186 (4.72) 0.192 (4.88) 0.152 (3.86) 0.025 (0.64) MIN 0.100 (2.54) BSC 0.023 (0.58) 0.014 (0.36) 0.120 (3.05) MAX 0.910 (23.11) 0.890 (22.61) 0.015 (0.38) 0.008 (0.20) 0.070 (1.78) 0.030 (0.76) NOTES: 1. INDEX AREA IS INDICATED BY A NOTCH OR LEAD ONE IDENTIFICATION MARK LOCATED ADJACENT TO LEAD ONE. 2. CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 16. 32 Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] (DH-32E) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model AD1376JD AD1376KD AD1377JD AD1377KD 1 Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C Maximum Linearity Error 0.006% 0.003% 0.006% 0.003% DH-32E = Ceramic DIP. (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00699-0-6/05(D) Rev. D | Page 12 of 12 Conversion Time (16 Bits) 17 s 17 s 10 s 10 s Package Option1 DH-32E DH-32E DH-32E DH-32E