TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Wide Range of Supply Voltages Over
Specified Temperature Range:
TA = –40°C to 85°C...2 V to 8 V
D
Fully Characterized at 3 V and 5 V
D
Single-Supply Operation
D
Common-Mode Input-Voltage Range
Extends Below the Negative Rail and up to
VDD –1 V at 25°C
D
Output Voltage Range Includes Negative
Rail
D
High Input Impedance...10
12 Ω Typ
D
Low Noise...25 nV/√Hz Typically at
f = 1 kHz (High-Bias Mode)
D
ESD-Protection Circuitry
D
Designed-In Latch-Up Immunity
D
Bias-Select Feature Enables Maximum
Supply Current Range From 17 µA to
1.5 mA at 25°C
1
2
3
4
8
7
6
5
OFFSET N1
IN–
IN+
GND
BIAS SELECT
VDD
OUT
OFFSET N2
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
OFFSET N1
IN–
IN+
GND
BIAS SELECT
VDD
OUT
OFFSET N2
PW PACKAGE
(TOP VIEW)
description
The TL V2341 operational amplifier has been specifically developed for low-voltage, single-supply applications
and is fully specified to operate over a voltage range of 2 V to 8 V. The device uses the Texas Instruments
silicon-gate LinCMOS technology to facilitate low-power, low-voltage operation and excellent offset-voltage
stability. LinCMOS technology also enables extremely high input impedance and low bias currents allowing
direct interface to high-impedance sources.
The TLV2341 offers a bias-select feature, which allows the device to be programmed with a wide range of
different supply currents and therefore different levels of ac performance. The supply current can be set at
17 µA, 250 µA, or 1.5 mA, which results in slew-rate specifications between 0.02 and 2.1 V/µs (at 3 V).
The TLV2341 operational amplifiers are especially well suited to single-supply applications and are fully
specified and characterized at 3-V and 5-V power supplies. This low-voltage single-supply operation combined
with low power consumption makes this device a good choice for remote, inaccessible, or portable
battery-powered applications. The common-mode input range includes the negative rail.
The device inputs and outputs are designed to withstand –100-mA currents without sustaining latch-up. The
TLV2341 incorporates internal ESD-protection circuits that prevents functional failures at voltages up to
2000 V as tested under MIL-STD 883 C, Methods 3015.2; however , care should be exercised in handling these
devices as exposure to ESD may result in the degradation of the device parametric performance.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
TAVIOmax
AT 25°CSMALL
OUTLINE
(D)
PLASTIC
DIP
(P)
TSSOP
(PW)
CHIP
FORM
(Y)
–40°C to 85°C8 mV TLV2341ID TLV2341IP TLV2341IPWLE TLV2341Y
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLV2341IDR).
The PW package is only available left-end taped and reeled (e.g., TLV2341IPWLE).
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
LinCMOS is a trademark of Texas Instruments Incorporated.
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
bias-select feature
The TLV2342 offers a bias-select feature that allows the user to select any one of three bias levels, depending
on the level of performance desired. The tradeoffs between bias levels involve ac performance and power
dissipation (see Table 1).
Table 1. Effect of Bias Selection on Performance
TYPICAL PARAMETER VALUES
MODE
TYPICAL
PARAMETER
VALUES
TA = 25°C, VDD = 3 V HIGH BIAS
RL = 10 kΩMEDIUM BIAS
RL = 100 kΩLOW BIAS
RL = 1 MΩUNIT
PDPower dissipation 975 195 15 µW
SR Slew rate 2.1 0.38 0.02 V/µs
VnEquivalent input noise voltage at f = 1 kHz 25 32 68 nV/√Hz
B1Unity-gain bandwidth 790 300 27 kHz
φmPhase margin 46°39°34°
AVD Large-signal differential voltage amplification 11 83 400 V/mV
bias selection
Bias selection is achieved by connecting BIAS SELECT to one of three voltage levels (see Figure 1). For
medium-bias applications, it is recommended that the bias-select pin be connected to the midpoint between the
supply rails. This procedure is simple in split-supply applications since this point is ground. In single-supply
applications, the medium-bias mode necessitates using a voltage divider as indicated in Figure 1. The use of
large-value resistors in the voltage divider reduces the current drain of the divider from the supply line. However,
large-value resistors used in conjunction with a large-value capacitor require significant time to charge up to
the supply midpoint after the supply is switched on. A voltage other than the midpoint may be used if it is within
the voltages specified in the following table.
To the Bias-Select Pin
1 MΩ
High
Medium
Low
VDD
1 MΩ
0.01 µF
BIAS MODE BIAS-SELECT VOLTAGE
(single supply)
Low
Medium
High
VDD
1 V to VDD –1 V
GND
Figure 1. Bias Selection for Single-Supply Applications
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
high-bias mode
In the high-bias mode, the TL V2341 series feature low offset voltage drift, high input impedance, and low noise.
Speed in this mode approaches that of BiFET devices but at only a fraction of the power dissipation.
medium-bias mode
The TL V2341 in the medium-bias mode features a low offset voltage drift, high input impedance, and low noise.
Speed in this mode is similar to general-purpose bipolar devices but power dissipation is only a fraction of that
consumed by bipolar devices.
low-bias mode
In the low-bias mode, the TL V2341 features low offset voltage drift, high input impedance, extremely low power
consumption, and high differential voltage gain.
ORDER OF CONTENTS
TOPIC BIAS MODE
Schematic all
Absolute maximum ratings all
Recommended operating conditions all
Electrical characteristics
Operating characteristics
Typical characteristics
high
(Figures 2 – 31)
Electrical characteristics
Operating characteristics
Typical characteristics
medium
(Figures 32 – 61)
Electrical characteristics
Operating characteristics
Typical characteristics
low
(Figures 62 – 91)
Parameter measurement information all
Application information all
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2341Y chip information
This chip, when properly assembled, displays characteristics similar to the TLV2341. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
+
–OUT
IN+
IN–
VDD
(7)
(3)
(2) (6)
(4)
GND
(1)
(5)
OFFSET N1
OFFSET N2
(8)
BIAS SELECT
48
55
(8) (7)(2) (1)
(6)(5)(4)
(3)
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MAY 1992 – REVISED AUGUST 1994
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•5
equivalent schematic
P3
P1
R1
P2 R2
P4 P5
R6 P9B
P9A
P6A P6B P7B P7A P8
P10 N11
N12
N13
N10
N9
N7
R7R4R3
N1 N2
N3
R5 C1
D1 D2
N6
N4
VDD
OFFSET
N1 OFFSET
N2 OUT GND BIAS
SELECT
IN–
IN+
P11
P12
N5
COMPONENT COUNT†
Transistors
Diodes
Resistors
Capacitors
27
2
7
1
†Includes the amplifier and all
ESD, bias, and trim circuitry
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage (see Note 2) VDD±
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input) –0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current at (or below) TA = 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may effect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at the noninverting input with respect to the inverting input.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE
T
A
≤ 25°CDERATING FACTOR T
A
= 85°C
PACKAGE
A
POWER RATING ABOVE TA = 25°C
A
POWER RATING
D725 mW 5.8 mW/°C 377 mW
P 1000 mW 8.0 mW/°C 520 mW
PW 525 mW 4.2 mW/°C 273 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD 2 8 V
Common mode in
p
ut voltage VIC
VDD = 3 V –0.2 1.8
V
Common
-
mode
inp
u
t
v
oltage
,
V
IC VDD = 5 V –0.2 3.8
V
Operating free-air temperature, TA–40 85 °C
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
HIGH-BIAS MODE
electrical characteristics at specified free-air temperature
TEST
TLV2341I
PARAMETER
TEST
CONDITIONS
TA†VDD = 3 V VDD = 5 V UNIT
CONDITIONS
MIN TYP MAX MIN TYP MAX
VIO
In
p
ut offset voltage
VO = 1 V,
V
IC
= 1 V, 25°C 0.6 8 1.1 8
mV
V
IO
Inp
u
t
offset
v
oltage
IC ,
RS = 50 Ω,
RL = 10 kΩFull range 10 10
mV
αVIO
Average temperature of input 25°C to
27
27
µV/
°
C
αVIO
g
offset voltage 85°C
2
.
7
2
.
7
µ
V/°C
IIO
In
p
ut offset current (see Note 4)
V
O
= 1 V, 25°C 0.1 0.1 p
A
I
IO
Inp
u
t
offset
c
u
rrent
(see
Note
4)
O,
VIC = 1 V 85°C 22 1000 24 1000
pA
IIB
In
p
ut bias current (see Note 4)
V
O
= 1 V, 25°C 0.6 0.6 p
A
I
IB
Inp
u
t
bias
c
u
rrent
(see
Note
4)
O,
VIC = 1 V 85°C 175 2000 200 2000
pA
25
°
C
–0.2
to
–0.3
to
–0.2
to
–0.3
to
V
VICR
Common-mode input voltage range
25°C
t
o
2
t
o
2.3
t
o
4
t
o
4.2
V
V
ICR
gg
(see Note 5)
Full range
–0.2
to
–0.2
to
V
F
u
ll
range
t
o
1.8
t
o
3.8
V
VOH
High level out
p
ut voltage
VIC = 1 V,
VID 100 mV
25°C 1.75 1.9 3.2 3.7
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
V
ID =
100
m
V
,
IOH = –1 mA Full range 1.7 3
V
VOL
Low level out
p
ut voltage
VIC = 1 V,
VID 100 mV
25°C 120 150 90 150
mV
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
V
ID = –
100
m
V
,
IOL = 1 mA Full range 190 190
mV
AVD
Large-signal differential VIC = 1 V,
RL10 kΩ
25°C 3 11 5 23
V/mV
A
VD
gg
voltage amplification
R
L =
10
kΩ
,
See Note 6 Full range 2 3.5
V/mV
CMRR
Common mode rejection ratio
VO = 1 V,
VIC VICRmin
25°C 65 78 65 80
dB
CMRR
Common
-
mode
rejection
ratio
V
IC =
V
ICRm
i
n,
RS = 50 ΩFull range 60 60
dB
kSVR
Supply-voltage rejection ratio VIC = 1 V,
VO1V
25°C 70 95 70 95
dB
k
SVR
ygj
(∆VDD/∆VIO)
V
O =
1
V
,
RS = 50 ΩFull range 65 65
dB
II(SEL) Bias select current VI(SEL) = 025°C –1.2 –1.4 µA
IDD
Su
pp
ly current
VO = 1 V,
VIC =1V
25°C 325 1500 675 1600
µA
I
DD
S
u
ppl
y
c
u
rrent
VIC
=
1
V
,
No load Full range 2000 2200 µ
A
†Full range is –40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
HIGH-BIAS MODE
operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA
TLV2341I
UNIT
PARAMETER
TEST
CONDITIONS
T
AMIN TYP MAX
UNIT
SR
Slew rate at unity gain
VIC = 1 V,
RL=10kΩ
VI(PP) = 1 V,
CL=20
p
F
25°C 2.1
V/µs
SR
Sle
w
rate
at
u
nit
y
gain
R
L =
10
kΩ
,
See Figure 92
C
L =
20
pF
,85°C1.7
V/
µ
s
V
Equivalent in
p
ut noise voltage
f = kHz, R
S
= 20 Ω,
25
°
C
25
nV/√Hz
V
n
Eq
u
i
v
alent
inp
u
t
noise
v
oltage
,
See Figure 93
S,
25°C
25
n
V/√H
z
BOM
Maximum out
p
ut swing bandwidth
V
O
= V
OH
, C
L
= 20 pF, 25°C 170
kHz
B
OM
Ma
x
im
u
m
o
u
tp
u
t
-
s
w
ing
band
w
idth
OOH
,
RL = 10 kΩ,
L,
See Figure 92 85°C145
kH
z
B1
Unity gain bandwidth
V
I
= 10 mV, C
L
= 20 pF, 25°C 790
kHz
B
1
Unit
y-
gain
band
w
idth
I,
RL = 10 kΩ,
L,
See Figure 94 85°C 690
kH
z
V
I
= 10 mV
,
f = B
1,
–40°C53°
φmPhase margin
VI
10
mV,
C
L
= 20 pF,
f
B
1
,
R
L
= 1 MΩ,25°C49°
See Figure 94 85°C 47°
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLV2341I
UNIT
PARAMETER
TEST
CONDITIONS
T
AMIN TYP MAX
UNIT
VIC =1V
VI(PP) =1V
25°C 3.6
SR
Slew rate at unity gain
VIC
=
1
V
,
RL = 10 kΩ,
V
I(PP) =
1
V
85°C 2.8
V/µs
SR
Sle
w
rate
at
u
nit
y
gain
L,
CL = 20 pF,
SFi 92
VI(PP) =25V
25°C 2.9
V/
µ
s
See Figure 92
V
I(PP) =
2
.
5
V
85°C 2.3
V
Equivalent in
p
ut noise voltage
f = 1 kHz, R
S
= 20 Ω,
25
°
C
25
nV/√Hz
V
n
Eq
u
i
v
alent
inp
u
t
noise
v
oltage
,
See Figure 93
S,
25°C
25
n
V/√H
z
BOM
Maximum out
p
ut swing bandwidth
V
O
= V
OH
, C
L
= 20 pF, 25°C 320
kHz
B
OM
Ma
x
im
u
m
o
u
tp
u
t
-
s
w
ing
band
w
idth
OOH
,
RL = 10 kΩ,
L,
See Figure 92 85°C250
kH
z
B1
Unity gain bandwidth
V
I
= 10 mV, C
L
= 20 pF, 25°C 1.7
MHz
B
1
Unit
y-
gain
band
w
idth
I,
RL = 10 kΩ,
L,
See Figure 94 85°C1.2
MH
z
V
I
= 10 mV
,
f = B
1,
–40°C49°
φmPhase margin
VI
10
mV,
C
L
= 20 pF,
f
B
1
,
R
L
= 10 kΩ,25°C46°
See Figure 94 85°C 43°
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
HIGH-BIAS MODE
electrical characteristics, TA = 25°C
TLV2341I
PARAMETER TEST CONDITIONS VDD = 3 V VDD = 5 V UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage VO = 1 V,
RS = 50 Ω,VIC = 1 V,
RL = 10 kΩ0.6 8 1.1 8 mV
IIO Input of fset current (see Note 4) VO = 1 V, VIC = 1 V 0.1 0.1 pA
IIB Input bias current (see Note 4) VO = 1 V, VIC = 1 V 0.6 0.6 pA
Common mode input voltage
–0.2 –0.3 –0.2 –0.3
VICR
C
ommon-mo
d
e
i
npu
t
vo
lt
age
range (see Note 5)
to to to to V
ICR
range
(see
Note
5)
2 2.3 4 4.2
VOH
High level out
p
ut voltage
VIC = 1 V,
IOH =1
VID = 100 mV,
175
19
32
37
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
I
OH = –
1
mA
1
.
75
1
.
9
3
.
2
3
.
7
V
VOL
Low level out
p
ut voltage
V
IC
= 1 V, V
ID
= –100 mV,
120
150
90
150
mV
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
IC ,
IOL = 1 mA
ID ,
120
150
90
150
mV
AVD Large-signal differential voltage
amplification VIC = 1 V,
See Note 6 RL = 10 kΩ,311 50 23 V/mV
CMRR
Common mode rejection ratio
V
O
= 1 V, V
IC
= V
ICR
min,
65
78
65
80
dB
CMRR
Common
-
mode
rejection
ratio
O,
RS = 50 Ω
IC ICR ,
65
78
65
80
dB
kSVR
Supply-voltage rejection ratio V
O
= 1 V, V
IC
= 1 V,
70
95
70
95
dB
k
SVR
ygj
(∆VDD/∆VIO)
O,
RS = 50 Ω
IC ,
70
95
70
95
dB
II(SEL) Bias select current VI(SEL) = 0 –1.2 –1.4 µA
IDD
Su
pp
ly current
VO = 1 V, VIC = 1 V,
325
1500
675
1600
µA
I
DD
S
u
ppl
y
c
u
rrent
O
No load
IC
325
1500
675
1600
µ
A
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)
Table of Graphs
FIGURE
VIO Input of fset voltage Distribution 2,3
αVIO Input offset voltage temperature coef ficient Distribution 4,5
vs Output current 6
VOH High-level output voltage vs Supply voltage 7
OH
gg
g
vs Temperature 8
vs Common-mode input volta
g
e 9
VOL
Low level out
p
ut voltage
vs
Common mode
in ut
voltage
vs Temperature
9
10, 12
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
vs Differential input voltage
,
11
vs Low-level output current 13
vs Supply voltage 14
AVD Large-signal differential voltage amplification
yg
vs Temperature 15
VD
gg g
vs Frequency 26, 27
IIB Input bias current vs Temperature 16
IIO Input offset current vs Temperature 16
VIC Common-mode input voltage vs Supply voltage 17
IDD
Su
pp
ly current
vs Supply voltage 18
I
DD
S
u
ppl
y
c
u
rrent
yg
vs Temperature 19
SR
Slew rate
vs Supply voltage 20
SR
Sle
w
rate
yg
vs Temperature 21
Bias select current vs Supply voltage 22
VO(PP) Maximum peak-to-peak output voltage vs Frequency 23
B1
Unity gain bandwidth
vs Temperature 24
B
1
Unit
y-
gain
band
w
idth
vs Supply voltage 25
vs Supply voltage 28
φmPhase margin
yg
vs Temperature 29
φm
g
vs Load capacitance 30
VnEquivalent input noise voltage vs Frequency 31
Phase shift vs Frequency 26, 27
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)
Figure 2
50
40
20
10
0
30
–1 0 1
Percentage of Units – %
2345
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
VIO – Input Offset Voltage – mV
VDD = 3 V
TA = 25°C
P Package
–5 –4 –3 –2
Figure 3
50
40
20
10
0
30
–1 0 1
60
2345
Percentage of Units – %
VIO – Input Offset Voltage – mV
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
VDD = 5 V
TA = 25°C
P Package
–5 –4 –3 –2
Figure 4
–10 0 2
Percentage of Units – %
46810
α
VIO – Temperature Coefficient – µV/°C
50
40
20
10
0
30
VDD = 3 V
TA = 25°C to 85°C
P Package
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
–8 –6 –4 –2
Figure 5
αVIO – Temperature Coefficient – µV/°C
Percentage of Units – %
–10 0246810
50
40
20
10
0
30
60
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
VDD = 5 V
TA = 25°C to 85°C
P Package
Outliers:
(1) 20.5 mV/°C
–8 –6 –4 –2
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)
Figure 6
V0H – High-Level Output Voltage – V
VOH
3
2
1
00 – 2– 4– 6
4
5
– 8
IOH – High-Level Output Current – mA
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VIC = 1 V
VID = 100 mV
TA = 25°C
VDD = 3 V
VDD = 5 V
Figure 7
V0H – High-Level Output Voltage – V
VOH
4
2
0
8
6
02468
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
VIC = 1 V
VID = 100 mV
RL = 1 MΩ
TA = 25°C
Figure 8
1.8
1.2
0.6
0
2.4
3
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
– 75 – 50 – 25 0 25 50 75 100 125
TA – Free-Air Temperature – °C
V0H – High-Level Output Voltage – V
VOH
VDD = 3 V
VIC = 1 V
VID = 100 mV
IOH = –500 µA
IOH = –1 mA
IOH = –2 mA
IOH = –3 mA
IOH = –4 mA
Figure 9
VOL – Low-Level Output Voltage – mV
VOL
500
400
300 01 2
600
700
34
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VIC – Common-Mode Input Voltage – V
VDD = 5 V
IOL = 5 mA
TA = 25°C
VID = –100 mV
VID = –1 V
600
650
550
450
350
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)
Figure 10
– 75 – 50 – 25 0 25 50 75 100 125
185
150
100
75
50
125
200
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
VOL – Low-Level Output Voltage – mV
VOL
VDD = 3 V
VIC = 1 V
VID = –100 mV
IOL = 1 mA
Figure 11
400
200
100
00
600
700
800
500
300
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
VOL – Low-Level Output Voltage – mV
VOL
VID – Differential Input Voltage – V
VDD = 5 V
VIC = |VID /2|
I
OL = 5 mA
TA = 25°C
–1 –2 –3 –4 –5 –6 –7 –8
Figure 12
400
200
100
0
600
700
800
500
300
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
900
– 75 – 50 – 25 0 25 50 75 100 125
TA – Free-Air Temperature – °C
VOL – Low-Level Output Voltage – mV
VOL
VDD = 5 V
VIC = 0.5 V
VID = –1 V
IOL = 5 mA
Figure 13
0.5
0.4
0.2
0.1
0
0.9
0.3
0123456
0.7
0.6
0.8
1
78
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL – Low-Level Output Voltage – V
VOL
IOL – Low-Level Output Current – mA
VIC = 1 V
VID = –100 mV
TA = 25°C
VDD = 3 V
VDD = 5 V
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)
Figure 14
02468
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
40
30
0
20
50
10
RL = 10 kΩ
TA = –40°C
TA = 25°C
TA = 85°C
60
– Large-Signal Differential Voltage
AVD Amplification – V/mV
Figure 15
TA – Free-Air Temperature – °C
20
15
35
30
45
50
10
40
25
5
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
–75 –50 –25 0 25 50 75 100 125
VDD = 3 V
RL = 10 kΩ
0
VDD = 5 V
– Large-Signal Differential Voltage
AVD Amplification – V/mV
Figure 16
INPUT BIAS CURRENT AND INPUT OFFSET
CURRENT
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
IIB and IIO – Input Bias and Offset Currents – pA
IIB IIO
104
103
102
101
1
0.125 45 65 85 105 125
VDD = 3 V
VIC = 1 V
See Note A
IIB
IIO
35 55 75 95 115
NOTE: The typical values of input bias current and input offset
current below 5 pA were determined mathematically. Figure 17
COMMON-MODE INPUT VOLTAGE
POSITIVE LIMIT
vs
SUPPLY VOLTAGE
4
2
0
8
6
02468
V
DD – Supply Voltage – V
VIC – Common-Mode Input Voltage – V
IC
V
TA = 25°C
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)
Figure 18
1.2
0.8
0.4
00246
1.6
2
8
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
IDD – Supply Current – mA
DD
I
TA = 25°C
TA = –40°C
VIC = 1 V
VO = 1 V
No Load
TA = 85°C
Figure 19
IDD – Supply Current – mA
DD
I
1
0.5
0
–75 0 25 50
1.5
2
75 100 125
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
VIC = 1 V
VO = 1 V
No Load
VDD = 3 V
1.75
0.75
0.25
1.25
–50 –25
VDD = 5 V
Figure 20
02468
SLEW RATE
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
4
2
1
0
6
3
SR – Slew Rate – V/us
5
sµV/
8
7
VI(PP) = 1 V
AV = 1
RL = 10 kΩ
CL = 20 pF
TA = 25°C
Figure 21
4
2
1
0
6
3
5
8
7
–75 –50 –25 0 25 50 75 100 125
SLEW RATE
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
VI(PP) = 1 V
AV = 1
RL = 10 kΩ
CL = 20 pF
VDD = 5 V
VDD = 3 V
SR – Slew Rate – V/ussµV/
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)
Figure 22
Bias Select Current – nA
– 1.2
0246
– 3
8
– 2.4
– 1.8
– 0.6
VDD – Supply Voltage – V
BIAS SELECT CURRENT
vs
SUPPLY VOLTAGE
TA = 25°C
VI(SEL) = 0
Aµ
Figure 23
10 10 1000 10000
3
2
1
0
4
5
f – Frequency – kHz
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
RL = 10 kΩ
TA = –40°C
TA = 85°C
TA = 25°C
0
VDD = 3 V
VDD = 5 V
– Maximum Peak-to-Peak Output Voltage – V
VO(PP)
Figure 24
–75 –50 –25 0 25 50 75 100 125
B1 – Unity-Gain Bandwidth – MHz
1.1
2.3
2.9
3.5
1.7
0.5
B
1
VDD = 3 V
VI = 10 mV
RL = 10 kΩ
CL = 20 pF
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
VDD = 5 V
Figure 25
1.3
0.9
0.7
0.5
1.7
1.9
1.5
1.1
2.1
012345678
V
I
= 10 mV
RL = 10 kΩ
CL = 20 pF
TA = 25°C
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
0.3
0.1
B1 – Unity-Gain Bandwidth – MHz
B
1
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 100 1 K 10 K 100 K 1 M
f – Frequency – Hz 10 M
Phase Shift
–60°
–30°
0°
30°
60°
90°
120°
150°
180°
107
106
105
104
103
102
101
0.1
VDD = 3 V
RL = 10 kΩ
CL = 20 pF
TA = 25°C
AVD
Phase Shift
1
– Large-Signal Differential Voltage Amplification
AVD
Figure 26
107
106
105
104
103
102
101
1
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 100 1 k 10 k 100 k 1 M 10 M
f – Frequency – Hz
Phase Shift
–60°
–30°
0°
30°
60°
90°
120°
150°
180°
AVD
Phase Shift
0.1
VDD = 5 V
RL = 10 kΩ
CL = 20 pF
TA = 25°C
– Large-Signal Differential Voltage Amplification
AVD
Figure 27
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (HIGH-BIAS MODE)
Figure 28
024 68
om – Phase Margin
PHASE MARGIN
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
φm
VI = 10 mV
RL = 10 kΩ
CL = 20 pF
TA = 25°C
53°
51°
49°
47°
45°
Figure 29
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
–75 –50 –25 –0 25 50 75 100 125
TA – Free-Air Temperature – °C
VI = 10 mV
RL = 10 kΩ
CL = 20 pF
om – Phase Margin
φm
60°
58°
56°
54°
52°
50°
48°
46°
44°
42°
40°
VDD = 5 V
VDD = 3 V
Figure 30
020406080100
PHASE MARGIN
vs
LOAD CAPACITANCE
om – Phase Margin
φm
CL – Load Capacitance – pF
VDD = 5 V
VI = 10 mV
RL = 10 kΩ
TA = 25°C
50°
45°
40°
35°
30°
25°10 30 50 70 90
VDD = 3 V
Figure 31
f – Frequency – Hz
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
1 10 100 1000
Vn – Equivalent Input Noise Voltage – nV Hz
VnnV/ Hz
200
100
0
300
400 RS = 20 Ω
TA = 25°C
VDD = 5 V
VDD = 3 V
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MEDIUM-BIAS MODE
electrical characteristics at specified free-air temperature
TEST
TLV2341I
PARAMETER
TEST
CONDITIONS
TA†VDD = 3 V VDD = 5 V UNIT
CONDITIONS
MIN TYP MAX MIN TYP MAX
V
Itfftlt
VO = 1 V,
V
IC
= 1 V
,
25°C 0.6 8 1.1 8
V
VIO Input offset voltage
VIC
1
V,
R
S
= 50 Ω,
Full range
10
10
mV
S
RL = 100 kΩ
F
u
ll
range
10
10
αVIO
Average temperature coef ficient of 25°C to
1
17
µV/
°
C
αVIO
g
input offset voltage 85°C
1
1
.
7
µ
V/°C
IIO
In
p
ut offset current (see Note 4)
V
O
= 1 V, 25°C 0.1 0.1 p
A
I
IO
Inp
u
t
offset
c
u
rrent
(see
Note
4)
O,
VIC = 1 V 85°C 22 1000 24 1000
pA
IIB
In
p
ut bias current (see Note 4)
V
O
= 1 V, 25°C 0.6 0.6 p
A
I
IB
Inp
u
t
bias
c
u
rrent
(see
Note
4)
O,
VIC = 1 V 85°C 175 2000 200 2000
pA
25
°
C
–0.2
to
–0.3
to
–0.2
to
–0.3
to
V
VICR
Common-mode input voltage range
25°C
to
2
to
2.3
to
4
to
4.2
V
V
ICR
gg
(see Note 5)
Full range
–0.2
to
–0.2
to
V
F
u
ll
range
to
1.8
to
3.8
V
VOH
High level out
p
ut voltage
VIC = 1 V,
VID = 100 mV
25°C 1.75 1.9 3.2 3.9
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
V
ID =
100
mV
,
IOH = –1 mA Full range 1.7 3
V
VOL
Low level out
p
ut voltage
VIC = 1 V,
VID = 100 mV
25°C115 150 95 150
mV
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
V
ID = –
100
mV
,
IOL = 1 mA Full range 190 190
mV
AVD
Large-signal differential VIC = 1 V,
RL= 100 kΩ
25°C 25 83 25 170
V/mV
A
VD
gg
voltage amplification
R
L =
100
kΩ
,
See Note 6 Full range 15 15
V/mV
CMRR
Common mode rejection ratio
VO = 1 V,
VIC =V
ICRmin
25°C 65 92 65 91
dB
CMRR
Common
-
mode
rejection
ratio
V
IC =
V
ICR
min
,
RS = 50 ΩFull range 60 60
dB
kSVR
Supply-voltage rejection ratio VIC = 1 V,
VO=1V
25°C 70 94 70 94
dB
k
SVR
ygj
(∆VDD/∆VIO)
V
O =
1
V
,
RS = 50 ΩFull range 65 65
dB
II(SEL) Bias select current VI(SEL) = 025°C –100 –130 nA
IDD
Su
pp
ly current
VO = 1 V,
VIC =1V
25°C 65 250 105 280
µA
I
DD
S
u
ppl
y
c
u
rrent
V
IC =
1
V
,
No load Full range 360 400 µ
A
†Full range is –40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MEDIUM-BIAS MODE
operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA
TLV2341I
UNIT
PARAMETER
TEST
CONDITIONS
T
AMIN TYP MAX
UNIT
SR
Slew rate at unity gain
VIC = 1 V,
RL= 100 kΩ
VI(PP) = 1 V,
CL=20
p
F
25°C 0.38
V/µs
SR
Sle
w
rate
at
u
nit
y
gain
R
L =
100
kΩ
,
See Figure 92
C
L =
20
pF
,85°C0.29
V/
µ
s
V
Equivalent in
p
ut noise voltage
f = kHz, R
S
= 20 Ω,
25
°
C
32
nV/√Hz
V
n
Eq
u
i
v
alent
inp
u
t
noise
v
oltage
,
See Figure 93
S,
25°C
32
n
V/√H
z
BOM
Maximum out
p
ut swing bandwidth
V
O
= V
OH
, C
L
= 20 pF, 25°C 34
kHz
B
OM
Ma
x
im
u
m
o
u
tp
u
t
-
s
w
ing
band
w
idth
OOH
,
RL = 100 kΩ,
L,
See Figure 92 85°C32
kH
z
B1
Unity gain bandwidth
V
I
= 10 mV, C
L
= 20 pF, 25°C 300
kHz
B
1
Unit
y-
gain
band
w
idth
I,
RL = 100 kΩ,
L,
See Figure 94 85°C 235
kH
z
V
I
= 10 mV
,
f = B
1,
–40°C42°
φmPhase margin
VI
10
mV,
C
L
= 20 pF,
f
B
1
,
R
L
= 100 kΩ,25°C39°
See Figure 94 85°C 36°
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLV2341I
UNIT
PARAMETER
TEST
CONDITIONS
T
AMIN TYP MAX
UNIT
VIC =1V
VI(PP) =1V
25°C 0.43
SR
Slew rate at unity gain
VIC
=
1
V
,
RL = 100 kΩ,
V
I(PP) =
1
V
85°C 0.35
V/µs
SR
Sle
w
rate
at
u
nit
y
gain
L,
CL = 20 pF,
SFi 92
VI(PP) =25V
25°C 0.40
V/
µ
s
See Figure 92
V
I(PP) =
2
.
5
V
85°C 0.32
V
Equivalent in
p
ut noise voltage
f =1 kHz, R
S
= 20 Ω,
25
°
C
32
nV/√Hz
V
n
Eq
u
i
v
alent
inp
u
t
noise
v
oltage
,
See Figure 93
S,
25°C
32
n
V/√H
z
BOM
Maximum out
p
ut swing bandwidth
V
O
= V
OH
, C
L
= 20 pF, 25°C 55
kHz
B
OM
Ma
x
im
u
m
o
u
tp
u
t
-
s
w
ing
band
w
idth
OOH
,
RL = 100 kΩ,
L,
See Figure 92 85°C45
kH
z
B1
Unity gain bandwidth
V
I
= 10 mV, C
L
= 20 pF, 25°C 525
kHz
B
1
Unit
y-
gain
band
w
idth
I,
RL = 100 kΩ,
L,
See Figure 94 85°C370
kH
z
V
I
= 10 mV
,
f = B
1,
–40°C43°
φmPhase margin
VI
10
mV,
C
L
= 20 pF,
f
B
1
,
R
L
= 100 kΩ,25°C40°
See Figure 94 85°C 38°
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MEDIUM-BIAS MODE
electrical characteristics, TA = 25°C
TLV2341I
PARAMETER TEST CONDITIONS VDD = 3 V VDD = 5 V UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage VO = 1 V,
RS = 50 Ω,VIC = 1 V,
RL = 100 kΩ0.6 8 1.1 8 mV
IIO Input of fset current (see Note 4) VO = 1 V, VIC = 1 V 0.1 0.1 pA
IIB Input bias current (see Note 4) VO = 1 V, VIC = 1 V 0.6 0.6 pA
VICR
Common-mode input voltage –0.2
to
–0.3
to
–0.2
to
–0.3
to
V
V
ICR
g
range (see Note 5)
to
2
to
2.3
to
4
to
4.2
V
VOH
High level out
p
ut voltage
V
IC
= 1 V, V
ID
= 100 mV,
175
19
32
39
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
IC ,
IOH = –1 mA
ID ,
1
.
75
1
.
9
3
.
2
3
.
9
V
VOL
Low level out
p
ut voltage
V
IC
= 1 V, V
ID
= –100 mV,
115
150
95
150
mV
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
IC ,
IOL = 1 mA
ID ,
115
150
95
150
mV
AVD Large-signal differential voltage
amplification VIC = 1 V,
See Note 6 RL = 100 kΩ,25 83 25 170 V/mV
CMRR
Common mode rejection ratio
V
O
= 1 V, V
IC
= V
ICR
min,
65
92
65
91
dB
CMRR
Common
-
mode
rejection
ratio
O,
RS = 50 Ω
IC ICR ,
65
92
65
91
dB
kSVR
Supply-voltage rejection ratio V
O
= 1 V, V
IC
= 1 V,
70
94
70
94
dB
k
SVR
ygj
(∆VDD/∆VID)
O,
RS = 50 Ω
IC ,
70
94
70
94
dB
II(SEL) Bias select current VI(SEL) = 0 –100 –130 nA
IDD
Su
pp
ly current
VO = 1 V, VIC = 1 V,
65
250
105
280
µA
I
DD
S
u
ppl
y
c
u
rrent
O
No load
IC
65
250
105
280
µ
A
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)
Table of Graphs
FIGURE
VIO Input of fset voltage Distribution 32, 33
αVIO Input offset voltage temperature coef ficient Distribution 34, 35
vs Output current 36
VOH High-level output voltage vs Supply voltage 37
OH
gg
g
vs Temperature 38
vs Common-mode input volta
g
e 39
VOL
Low level out
p
ut voltage
vs
Common mode
in ut
voltage
vs Temperature
39
40, 42
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
vs Differential input voltage
,
41
vs Low-level output current 43
vs Supply voltage 44
AVD Large-signal differential voltage amplification
yg
vs Temperature 45
VD
gg g
vs Frequency 56, 57
IIB Input bias current vs Temperature 46
IIO Input offset current vs Temperature 46
VIC Common-mode input voltage vs Supply voltage 47
IDD
Su
pp
ly current
vs Supply voltage 48
I
DD
S
u
ppl
y
c
u
rrent
yg
vs Temperature 49
SR
Slew rate
vs Supply voltage 50
SR
Sle
w
rate
yg
vs Temperature 51
Bias select current vs Supply current 52
VO(PP) Maximum peak-to-peak output voltage vs Frequency 53
B1
Unity gain bandwidth
vs Temperature 54
B
1
Unit
y-
gain
band
w
idth
vs Supply voltage 55
vs Supply voltage 58
φmPhase margin
yg
vs Temperature 59
φm
g
vs Load capacitance 60
VnEquivalent input noise voltage vs Frequency 61
Phase shift vs Frequency 56, 57
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)
Figure 32
50
40
20
10
0
30
–1 0 1
Percentage of Units – %
2345
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
VIO – Input Offset Voltage – mV
VDD = 3 V
TA = 25°C
P Package
–5 –4 –3 –2
Figure 33
50
40
20
10
0
30
–1 0 1
60
2345
Percentage of Units – %
VIO – Input Offset Voltage – mV
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
VDD = 5 V
TA = 25°C
P Package
–5 –4 –3 –2
Figure 34
–10 0 2
Percentage of Units – %
46810
α
VIO – Temperature Coefficient – µV/°C
50
40
20
10
0
30
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
–8 –6 –4 –2
VDD = 3 V
TA = 25°C to 85°C
P Package
Figure 35
αVIO – Temperature Coefficient – µV/°C
Percentage of Units – %
–10 0246810
50
40
20
10
0
30
60
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
VDD = 5 V
TA = 25°C to 85°C
P Package
Outliers:
(1) 33 mV/°C
–8 –6 –4 –2
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)
Figure 36
V0H – High-Level Output Voltage – V
VOH
3
2
1
00
4
5
IOH – High-Level Output Current – mA
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VDD = 3 V
VDD = 5 V
VIC = 1 V
VID = 100 mV
TA = 25°C
–2 –4 –6 –8
Figure 37
V0H – High-Level Output Voltage – V
VOH
4
2
0
8
6
02468
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
VIC = 1 V
VID = 100 mV
RL = 100 kΩ
TA = 25°C
Figure 38
1.8
1.2
0.6
0
2.4
3
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
–75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature – °C
VDD = 3 V
VIC = 1 V
VID = 100 mV
V0H – High-Level Output Voltage – V
VOH
IOH = –500 µA
IOH = –1 mA
IOH = –2 mA
IOH = –3 mA
IOH = –4 mA
Figure 39
VOL – Low-Level Output Voltage – mV
VOL
500
400
300 01 2
600
700
34
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VIC – Common-Mode Input Voltage – V
VDD = 5 V
IOL = 5 mA
TA = 25°C
VID = –100 mV
VID = –1 V
650
550
450
350
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)
Figure 40
–75 –50 –25 0 25 50 75 100 125
125
110
80
65
50
185
95
155
140
170
200
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
VOL – Low-Level Output Voltage – mV
VOL
VDD = 3 V
VIC = 1 V
VID = –100 mV
IOL = 1 mA
Figure 41
400
200
100
00–2–4
600
700
800
–6 –8
500
300
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
VOL – Low-Level Output Voltage – mV
VOL
VID – Differential Input Voltage – V
VDD = 5 V
VIC = |VID /2|
I
OL = 5 mA
TA = 25°C
Figure 42
400
200
100
0
600
700
800
500
300
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
900
–75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature – °C
VOL – Low-Level Output Voltage – mV
VOL
VDD = 5 V
VIC = 0.5 V
VID = –1 V
IOL = 5 mA
Figure 43
500
400
200
100
0
900
300
0123456
700
600
800
1000
78
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL – Low-Level Output Voltage – mV
VOL
IOL – Low-Level Output Current – mA
VDD = 5 V
VIC = 1 V
VID = –100 mV
TA = 25°C
VDD = 3 V
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)
Figure 44
02468
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
200
150
350
0
300
450
500
100
400
250
50
RL = 100 kΩ
TA = –40°C
TA = 25°C
TA = 85°C
– Large-Signal Differential Voltage
AVD Amplification – V/mV
Figure 45
200
150
350
300
450
500
100
400
250
50
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
–75 –50 –25 0 25 50 75 100 125
VDD = 5 V
VDD = 3 V
RL = 100 kΩ
0
TA – Free-Air Temperature – °C
– Large-Signal Differential Voltage
AVD Amplification – V/mV
Figure 46
INPUT BIAS CURRENT AND INPUT OFFSET CURREN
T
vs
FREE-AIR TEMPERATURE
TA – Free-sAir Temperature – °C
IIB and IIO – Input Bias and Offset Currents – pA
IIB IIO
104
103
102
101
1
.0125 45 65 85 105 125
VDD = 3 V
VIC = 1 V
See Note A
IIB
IIO
NOTE A: The typical values of input bias current and input offset
current below 5 pA are determined mathematically.
Figure 47
COMMON-MODE INPUT VOLTAGE POSITIVE LIMIT
vs
SUPPLY VOLTAGE
4
2
0
8
6
02468
V
DD – Supply Voltage – V
VIC – Common-Mode Input Voltage
IC
V
TA = 25°C
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)
Figure 48
IDD – Supply Current – uA
100
50
25
002 4
150
175
200
68
125
75
VDD – Supply Voltage – V
DD
IAµ
250
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VIC = 1 V
VO = 1 V
No Load
TA = –40°C
TA = 25°C
TA = 85°C
Figure 49
75
50
25
0
–75 –50 –25 0 25 50
100
125
150
75 100 125
TA – Free-Air Temperature – °C
175
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
VIC = 1 V
VO = 1 V
No Load
VDD = 5 V
VDD = 3 V
IDD – Supply Current – uA
DD
IAµ
Figure 50
02468
0.7
0.5
0.4
0.3
0.9
0.6
SR – Slew Rate – V/us
0.8
sµV/
VIC = 1 V
VI(PP) = 1 V
AV = 1
RL = 100 kΩ
CL = 20 pF
TA = 25°C
VDD – Supply Voltage – V
SLEW RATE
vs
SUPPLY VOLTAGE
Figure 51
0.7
0.5
0.4
0.3
0.9
0.6
0.8
–75 –50 –25 0 25 50 75 100 125
VDD = 5 V
VDD = 3 V
VIC = 1 V
VI(PP) = 1 V
AV = 1
RL = 100 kΩ
CL = 20 pF
0.2
TA – Free-Air Temperature – °C
SLEW RATE
vs
FREE-AIR TEMPERATURE
SR – Slew Rate – V/us
sµV/
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)
Figure 52
VDD – Supply Voltage – V
– 150
– 120
– 30
00246
Bias Select Current – nA
BIAS SELECT CURRENT
vs
SUPPLY VOLTAGE
8
– 90
– 180
– 60
TA = 25°C
VI(SEL) = 1/2 VDD
– 300
– 270
– 240
– 210
Figure 53
10 10 100 1000
3
2
1
0
4
5
f – Frequency – kHz
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
RL = 100 kΩ
TA = –40°C
VDD = 3 V
TA = 85°C
TA = 25°C
VDD = 5 V
– Maximum Peak-to-Peak Output Voltage – V
VO(PP)
Figure 54
–75 –50 –25 0 25 50 75 100
600
400
300
200
800
900
1000
700
500
VDD = 5 V
VDD = 3 V
VI = 10 mV
RL = 100 kΩ
CL = 20 pF
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
B1 – Unity-Gain Bandwidth – kHz
B
1
125
Figure 55
B1 – Unity-Gain Bandwidth – kHz
B
1
600
400
300
200
800
900
700
500
1000
012345678
V
I
= 10 mV
RL = 100 kΩ
CL = 20 pF
TA = 25°C
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)
107
106
105
104
103
102
101
1
0.1 1 10 100 1 k 10 k 100 k
f – Frequency – Hz
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
1 M
Phase Shift
60°
30°
90°
120°
150°
180°
Phase Shift
AVD
VDD = 3 V
RL = 100 kΩ
CL = 20 pF
TA = 25°C
–60°
–30°
– Large-Signal Differential Voltage Amplification
AVD
0°
Figure 56
1 10 100 1 k 10 k 100 k 1 M
107
106
105
104
103
102
101
0.1
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
f – Frequency – Hz
Phase Shift
VDD = 5 V
RL = 100 kΩ
CL = 20 pF
TA = 25°C
1
60°
30°
90°
–60°
–30°
0°
120°
150°
180°
Phase Shift
AVD
– Large-Signal Differential Voltage Amplification
AVD
Figure 57
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (MEDIUM-BIAS MODE)
Figure 58
VDD – Supply Voltage – V
0123456
PHASE MARGIN
vs
SUPPLY VOLTAGE
78
V
I
= 10 mV
RL = 100 kΩ
CL = 20 pF
TA = 25°C
om – Phase Margin
φm
50°
48°
46°
44°
42°
40°
38°
36°
34°
32°
30°
Figure 59
TA – Free-Air Temperature – °C
– 75 – 25 0 50 100 125– 50 25 75
VDD = 3 V
VI = 10 mV
RL = 100 kΩ
CL = 20 pF
VDD = 5 V
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
om – Phase Margin
φm
45°
43°
41°
39°
37°
35°
Figure 60
om – Phase Margin
φm
44°
42°
40°
38°
36°
34°
32°
30°
0204060
PHASE MARGIN
vs
LOAD CAPACITANCE
80 100
VI = 10 mV
TA = 25°C
RL = 100 kΩ
VDD = 3 V
VDD = 5 V
CL – Load Capacitance – pF
28°10 30 50 70 90
Figure 61
200
150
100
0110
250
f – Frequency – Hz
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
300
1000100
RS = 20Ω
TA = 25°C
VDD = 3 V
50
Vn – Equivalent Input Noise Voltage – nV Hz
VnnV/ Hz
VDD = 5 V
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LOW-BIAS MODE
electrical characteristics at specified free-air temperature
TEST
TLV2341I
PARAMETER
TEST
CONDITIONS
TA†VDD = 3 V VDD = 5 V UNIT
CONDITIONS
MIN TYP MAX MIN TYP MAX
VIO
In
p
ut offset voltage
VO = 1 V,
VI
C
= 1 V, 25°C 0.6 8 1.1 8
mV
V
IO
Inp
u
t
offset
v
oltage
IC ,
RS = 50 Ω,
RL = 1 MΩFull range 10 10
mV
αVIO
Average temperature of 25°C to
1
11
µV/
°
C
αVIO
g
input offset voltage 85°C
1
1
.
1
µ
V/°C
IIO
In
p
ut offset current (see Note 4)
V
O
= 1 V, 25°C 0.1 0.1 p
A
I
IO
Inp
u
t
offset
c
u
rrent
(see
Note
4)
O,
VIC = 1 V 85°C 22 1000 24 1000
pA
IIB
In
p
ut bias current (see Note 4)
V
O
= 1 V, 25°C 0.6 0.6 p
A
I
IB
Inp
u
t
bias
c
u
rrent
(see
Note
4)
O,
VIC = 1 V 85°C 175 2000 200 2000
pA
25
°
C
–0.2
to
–0.3
to
–0.2
to
–0.3
to
V
VICR
Common-mode input
25°C
to
2
to
2.3
to
4
to
4.2
V
V
ICR voltage range (see Note 5)
Full range
–0.2
to
–0.2
to
V
F
u
ll
range
to
1.8
to
3.8
V
VOH
High level out
p
ut voltage
VIC = 1 V,
VID = 100 mV
25°C 1.75 1.9 3.2 3.8
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
V
ID =
100
mV
,
IOH = –1 mA Full range 1.7 3
V
VOL
Low level out
p
ut voltage
VIC = 1 V,
VID = 100 mV
25°C115 150 95 150
mV
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
V
ID = –
100
mV
,
IOL = 1 mA Full range 190 190
mV
AVD
Large-signal differential VIC = 1 V,
RL=1MΩ
25°C 50 400 50 520
V/mV
A
VD
gg
voltage amplification
R
L =
1
MΩ
,
See Note 6 Full range 50 50
V/mV
CMRR
Common mode rejection ratio
VO = 1 V,
VIC =V
ICRmin
25°C 65 88 65 94
dB
CMRR
Common
-
mode
rejection
ratio
V
IC =
V
ICR
min
,
RS = 50 ΩFull range 60 60
dB
kSVR
Supply-voltage rejection ratio VIC = 1 V,
VO=1V
25°C 70 86 70 86
dB
k
SVR
ygj
(∆VDD/∆VIO)
V
O =
1
V
,
RS = 50 ΩFull range 65 65
dB
II(SEL) Bias select current VI(SEL) = 025°C 10 65 nA
IDD
Su
pp
ly current
VO = 1 V,
VIC =1V
25°C 5 17 10 17
µA
I
DD
S
u
ppl
y
c
u
rrent
V
IC =
1
V
,
No load Full range 27 27 µ
A
†Full range is –40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO(PP) = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LOW-BIAS MODE
operating characteristics at specified free-air temperature, VDD = 3 V
PARAMETER
TEST CONDITIONS
TA
TLV2341I
UNIT
PARAMETER
TEST
CONDITIONS
T
AMIN TYP MAX
UNIT
SR
Slew rate at unity gain
VIC = 1 V,
RL=1MΩ
VI(PP) = 1 V,
CL=20
p
F
25°C 0.02
V/µs
SR
Sle
w
rate
at
u
nit
y
gain
R
L =
1
MΩ
,
See Figure 92
C
L =
20
pF
,85°C0.02
V/
µ
s
V
Equivalent in
p
ut noise voltage
f = kHz, R
S
= 20 Ω,
25
°
C
68
nV/√Hz
V
n
Eq
u
i
v
alent
inp
u
t
noise
v
oltage
,
See Figure 93
S,
25°C
68
n
V/√H
z
BOM
Maximum out
p
ut swing bandwidth
V
O
= V
OH
, C
L
= 20 pF, 25°C 2.5
kHz
B
OM
Ma
x
im
u
m
o
u
tp
u
t
-
s
w
ing
band
w
idth
OOH
,
RL = 1 MΩ,
L,
See Figure 92 85°C2
kH
z
B1
Unity gain bandwidth
V
I
= 10 mV, C
L
= 20 pF, 25°C 27
kHz
B
1
Unit
y-
gain
band
w
idth
I,
RL = 1 MΩ,
L,
See Figure 94 85°C 21
kH
z
V
I
= 10 mV
,
f = B
1,
–40°C39°
φmPhase margin
VI
10
mV,
C
L
= 20 pF,
f
B
1
,
R
L
= 1 MΩ,25°C34°
See Figure 94 85°C 28°
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLV2341I
UNIT
PARAMETER
TEST
CONDITIONS
T
AMIN TYP MAX
UNIT
VIC =1V
VI(PP) =1V
25°C 0.03
SR
Slew rate at unity gain
VIC
=
1
V
,
RL = 1 MΩ,
V
I(PP) =
1
V
85°C 0.03
V/µs
SR
Sle
w
rate
at
u
nit
y
gain
L,
CL = 20 pF,
SFi 92
VI(PP) =25V
25°C 0.03
V/
µ
s
See Figure 92
V
I(PP) =
2
.
5
V
85°C 0.02
V
Equivalent in
p
ut noise voltage
f =1 kHz, R
S
= 20 Ω,
25
°
C
68
nV/√Hz
V
n
Eq
u
i
v
alent
inp
u
t
noise
v
oltage
,
See Figure 93
S,
25°C
68
n
V/√H
z
BOM
Maximum out
p
ut swing bandwidth
V
O
= V
OH
, C
L
= 20 pF, 25°C 5
kHz
B
OM
Ma
x
im
u
m
o
u
tp
u
t
-
s
w
ing
band
w
idth
OOH
,
RL = 1 MΩ,
L,
See Figure 92 85°C4
kH
z
B1
Unity gain bandwidth
V
I
= 10 mV, C
L
= 20 pF, 25°C 85
kHz
B
1
Unit
y-
gain
band
w
idth
I,
RL = 1 MΩ,
L,
See Figure 94 85°C55
kH
z
V
I
= 10 mV
,
f = B
1,
–40°C38°
φmPhase margin
VI
10
mV,
C
L
= 20 pF,
f
B
1
,
R
L
= 1 MΩ,25°C34°
See Figure 94 85°C 28°
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LOW-BIAS MODE
electrical characteristics, TA = 25°C
TLV2341Y
PARAMETER TEST CONDITIONS VDD = 3 V VDD = 5 V UNIT
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage VO = 1 V,
RS = 50 Ω,VIC = 1 V,
RL = 1 MΩ0.6 8 1.1 8 mV
IIO Input offset current
(see Note 4) VO = 1 V, VIC = 1 V 0.1 0.1 pA
IIB Input bias current
(see Note 4) VO = 1 V, VIC = 1 V 0.6 0.6 pA
Common mode input voltage
–0.2 –0.3 –0.2 –0.3
VICR
C
ommon-mo
d
e
i
npu
t
vo
lt
age
range (see Note 5)
to to to to V
ICR
range
(see
Note
5)
2 2.3 4 4.2
VOH
High level out
p
ut voltage
V
IC
= 1 V, V
ID
= 100 mV,
175
19
32
38
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
IC ,
IOH = –1 mA
ID ,
1
.
75
1
.
9
3
.
2
3
.
8
V
VOL
Low level out
p
ut voltage
V
IC
= 1 V, V
ID
= –100 mV,
115
150
95
150
mV
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
IC ,
IOL = 1 mA
ID ,
115
150
95
150
mV
AVD Large-signal differential
voltage amplification VIC = 1 V,
See Note 6 RL = 1 MΩ,50 400 50 520 V/mV
CMRR
Common mode rejection ratio
V
O
= 1 V, V
IC
= V
ICR
min,
65
88
65
94
dB
CMRR
Common
-
mode
rejection
ratio
O,
RS = 50 Ω
IC ICR ,
65
88
65
94
dB
kSVR
Supply-voltage rejection ratio V
DD
= 3 V to 5 V, V
IC
= 1 V,
70
86
70
86
dB
k
SVR
ygj
(∆VDD/∆VID)
DD ,
VO = 1 V,
IC ,
RS = 50 Ω
70
86
70
86
dB
II(SEL) Bias select current VI(SEL) = 0 10 65 nA
IDD
Su
pp
ly current
VO = 1 V, VIC = 1 V,
5
17
10
17
µA
I
DD
S
u
ppl
y
c
u
rrent
O
No load
IC
5
17
10
17
µ
A
NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (LOW-BIAS MODE)
Table of Graphs
FIGURE
VIO Input of fset voltage Distribution 62, 63
αVIO Input offset voltage temperature coef ficient Distribution 64, 65
vs Output current 66
VOH High-level output voltage vs Supply voltage 67
OH
gg
g
vs Temperature 68
vs Common-mode input volta
g
e 69
VOL
Low level out
p
ut voltage
vs
Common mode
in ut
voltage
vs Temperature
69
70, 72
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
vs Differential input voltage
,
71
vs Low-level output current 73
vs Supply voltage 74
AVD Large-signal differential voltage amplification
yg
vs Temperature 75
VD
gg g
vs Frequency 86, 87
IIB Input bias current vs Temperature 76
IIO Input offset current vs Temperature 76
VIC Common-mode input voltage vs Supply voltage 77
IDD
Su
pp
ly current
vs Supply voltage 78
I
DD
S
u
ppl
y
c
u
rrent
yg
vs Temperature 79
SR
Slew rate
vs Supply voltage 80
SR
Sle
w
rate
yg
vs Temperature 81
Bias select current vs Supply current 82
VO(PP) Maximum peak-to-peak output voltage vs Frequency 83
B1
Unity gain bandwidth
vs Temperature 84
B
1
Unit
y-
gain
band
w
idth
vs Supply voltage 85
vs Supply voltage 88
φmPhase margin
yg
vs Temperature 89
φm
g
vs Load capacitance 90
VnEquivalent input noise voltage vs Frequency 91
Phase shift vs Frequency 86, 87
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (LOW-BIAS MODE)
Figure 62
50
40
20
10
0
30
–1 0 1
Percentage of Units – %
2345
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
VIO – Input Offset Voltage – mV
VDD = 3 V
TA = 25°C
P Package
–5 –4 –3 –2
Figure 63
50
40
20
10
0
30
–1 0 1
70
60
2345
Percentage of Units – %
VIO – Input Offset Voltage – mV
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
VDD = 5 V
TA = 25°C
P Package
–5 –4 –3 –2
Figure 64
–8 –6 –4 –2
–10 0 2
Percentage of Units – %
46810
50
40
20
10
0
30
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
VDD = 3 V
TA = 25°C to 85°C
P Package
αVIO – Temperature Coefficient – µV/°CFigure 65
αVIO – Temperature Coefficient – µV/°C
Percentage of Units – %
–10 0246810
50
40
20
10
0
30
70
60
DISTRIBUTION OF TLV2341
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
VDD = 5 V
TA = 25°C to 85°C
P Package
Outliers:
(1) 19.2 mV/°C
(1) 12.1 mV/°C
–8 –6 –4 –2
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (LOW-BIAS MODE)
Figure 66
V0H – High-Level Output Voltage – V
VOH
3
2
1
00
4
5
IOH – High-Level Output Current – mA
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VDD = 3 V
VDD = 5 V
VIC = 1 V
VID = 100 mV
TA = 25°C
–2 –4 –6 –8
Figure 67
V0H – High-Level Output Voltage – V
VOH
4
2
0
8
6
02468
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
VIC = 1 V
VID = 100 mV
RL = 1 MΩ
TA = 25°C
Figure 68
1.8
1.2
0.6
0
2.4
3
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
–75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature – °C
V0H – High-Level Output Voltage – V
VOH
VDD = 3 V
VIC = 1 V
VID = 100 mV
IOH = – 500 µA
IOH = –1 mA
IOH = –2 mA
IOH = –3 mA
IOH = –4 mA
Figure 69
VOL – Low-Level Output Voltage – mV
VOL
500
400
350
300 01 2
600
650
700
34
550
450
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VIC – Common-Mode Input Voltage – V
VID = –1 V
VID = –100 mV
VDD = 5 V
IOL = 5 mA
TA = 25°C
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (LOW-BIAS MODE)
Figure 70
–75 –50 –25 0 25 50 75 100 125
125
110
80
65
50
185
95
155
140
170
200
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
VOL – Low-Level Output Voltage – mV
VOL
VDD = 3 V
VIC = 1 V
VID = –100 mV
IOL = 1 mA
Figure 71
400
200
100
00–2–4
600
700
800
–6 –8
500
300
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
VOL – Low-Level Output Voltage – mV
VOL
VID – Differential Input Voltage – V
VDD = 5 V
VIC = |VID /2|
I
OL = 5 mA
TA = 25°C
Figure 72
400
200
100
0
600
700
800
500
300
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
900
–75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature – °C
VOL – Low-Level Output Voltage – mV
VOL
VDD = 5 V
VIC = 0.5 V
VID = –1 V
IOL = 5 mA
Figure 73
0.5
0.4
0.2
0.1
0
0.9
0.3
0123456
0.7
0.6
0.8
1
78
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL – Low-Level Output Voltage – mV
VOL
IOL – Low-Level Output Current – mA
VIC = 1 V
VID = –1 V
TA = 25°C
VDD = 3 V
VDD = 5 V
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (LOW-BIAS MODE)
Figure 74
VDD – Supply Voltage – V
1000
800
200
0024 6
1400
1800
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
2000
8
600
1600
1200
400
TA = –40°C
TA = 25°C
RL = 1 MΩ
TA = 85°C
– Large-Signal Differential Voltage
AVD Amplification – V/mV
Figure 75
–75 TA – Free-Air Temperature – °C
0 25 50 75 100 125
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
RL = 1 MΩ
VDD = 5 V
VDD = 3 V
1000
800
200
0
1400
1800
2000
600
1600
1200
400
–50 –25
– Large-Signal Differential Voltage
AVD Amplification – V/mV
Figure 76
INPUT BIAS CURRENT AND INPUT
OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
IIB and IIO – Input Bias and Offset Currents – pA
IIB IIO
104
103
102
101
1
0.125 45 65 85 105 125
VDD = 3 V
VIC = 1 V
See Note A
IIB
IIO
35 55 75 95 115
NOTE A: The typical values of input bias current and input offset
current below 5 pA are determined mathematically.
Figure 77
COMMON-MODE INPUT VOLTAGE
POSITIVE LIMIT
vs
SUPPLY VOLTAGE
4
2
0
8
6
02468
V
DD – Supply Voltage – V
VIC – Common-Mode Input Voltage
IC
V
TA = 25°C
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (LOW-BIAS MODE)
Figure 78
IDD – Supply Current – uA
DD
IAµ
20
10
5
0
30
35
40
25
15
VDD – Supply Voltage – V
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
45
02468
V
IC = 1 V
VO = 1 V
No Load
TA = –40°C
TA = 25°C
TA = 85°C
Figure 79
15
10
5
0
20
25
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
30
TA – Free-Air Temperature – °C
–75 –50 –25 0 25 50 75 100 125
VIC = 1 V
VO = 1 V
No Load
VDD = 5 V
VDD = 3 V
IDD – Supply Current – uA
DD
IAµ
Figure 80
0.04
0.02
0.01
0
0.06
0.03
02468
0.05
SLEW RATE
vs
SUPPLY VOLTAGE
0.07
VDD – Supply Voltage – V
VIC = 1 V
VI(PP) = 1 V
AV = 1
RL = 1 MΩ
CL = 20 pF
TA = 25°C
SR – Slew Rate – V/us
sµV/
Figure 81
0.04
0.02
0.01
0
0.06
0.07
0.05
0.03
SLEW RATE
vs
FREE-AIR TEMPERATURE
–75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature – °C
VIC = 1 V
VI(PP) = 1 V
AV = 1
RL = 1 MΩ
CL = 20 pF
VDD = 5 V
VDD = 3 V
SR – Slew Rate – V/us
sµV/
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (LOW-BIAS MODE)
Figure 82
60
00246
Bias Select Current – nA
150
8
120
90
30
VDD – Supply Voltage – V
BIAS SELECT CURRENT
vs
SUPPLY VOLTAGE
TA = 25°C
VI(SEL) = VDD
Figure 83
3
2
1
0
4
f – Frequency – kHz
5
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
0.1 1 10 100
RL = 1 MΩ
TA = –40°C
VDD = 3 V
TA = 85°C
VDD = 5 V
TA = 25°C
– Maximum Peak-to-Peak Output Voltage – V
VO(PP)
Figure 84
B1 – Unity-Gain Bandwidth – kHz
80
50
35
20
110
125
140
95
65
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
–75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature – °C
B1
VI = 10 mV
RL = 1 MΩ
CL = 20 pF
VDD = 5 V
VDD = 3 V
Figure 85
70
60
40
30
20
110
50
0123456
90
80
100
120
78
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
B1 – Unity-Gain Bandwidth – MHz
B1
VI = 10 mV
RL = 1 MΩ
CL = 20 pF
TA = 25°C
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (LOW-BIAS MODE)
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
1 10 100 1 k 10 k 100 k
f – Frequency – Hz 1 M
Phase Shift
–60°
–30°
0°
30°
60°
90°
120°
150°
180°
107
106
105
104
103
102
101
0.1
VDD = 3 V
CL = 20 pF
RL = 1 MΩ
TA = 25°C
AVD
Phase Shift
1
– Large-Signal Differential Voltage Amplification
AVD
Figure 86
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
1 10 100 1 k 10 k 100 k 1 M
f – Frequency – Hz
Phase Shift
–60°
–30°
0°
30°
60°
90°
120°
150°
180°
106
105
104
103
102
101
1
AVD
Phase Shift
107
0.1
VDD = 5 V
CL = 20 pF
RL = 1 MΩ
TA = 25°C
– Large-Signal Differential Voltage Amplification
AVD
Figure 87
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (LOW-BIAS MODE)
Figure 88
02468
PHASE MARGIN
vs
SUPPLY VOLTAGE
VDD – Supply Voltage – V
VI = 10 mV
RL = 1 MΩ
CL = 20 pF
TA = 25°C
om – Phase Margin
φm
42°
40°
38°
36°
30°
34°
32°
Figure 89
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
–75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature – °C
VI = 10 mV
RL = 1 MΩ
CL = 20 pF
VDD = 3 V
VDD = 5 V
om – Phase Margin
φm
40°
38°
36°
30°
34°
32°
28°
26°
24°
22°
20°
Figure 90
om – Phase Margin
φm
40°
38°
36°
30°
34°
32°
28°
26°
24°
22°
20°0 102030405060708090100
PHASE MARGIN
vs
LOAD CAPACITANCE
CL – Load Capacitance – pF
VDD = 3 V
VI = 10 mV
RL = 1 MΩ
TA = 25°C
VDD = 5 V
Figure 91
0
f – Frequency – Hz
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
100
75
25
125
175
200
50
150
1 10 100 1000
VDD = 3 V, 5 V
RS = 20 Ω
TA = 25°C
Vn – Equivalent Input Noise Voltage – nV Hz
VnnV/ Hz
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLV2341 is optimized for single-supply operation, circuit configurations used for the various tests
often present some inconvenience since the input signal, in many cases, must be offset from ground. This
inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative
rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives
the same result.
–
+
–
+
VDD
VICLRL
VO
VDD+
VDD–
VIVO
CLRL
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
Figure 92. Unity-Gain Amplifier
–
+–
+
1/2 VDD
VDD
20 Ω
20 Ω
2 kΩ2 kΩ
VDD+
VDD–
VOV
O
20 Ω20 Ω
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
Figure 93. Noise-Test Circuits
–
+
–
+
10 kΩ
1/2 VDD
100 Ω
VO
VDD
VIVI100 Ω
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
10 kΩ
VDD+
VDD–
CLCL
VO
Figure 94. Gain-of-100 Inverting Amplifier
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLV2341 operational amplifier , attempts to measure the input bias
current can result in erroneous readings. The bias current at normal ambient temperature is typically less than
1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid
erroneous measurements:
•Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 95). Leakages that would otherwise flow to the inputs are shunted away.
•Compensate for the leakage of the test socket by actually performing an input bias current test (using a
picoammeter) with no device in the test socket. The actual input bias current can then be calculated by
subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
Many automatic testers as well as some bench-top operational amplifier testers use the servo-loop
technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires
that a device be inserted into the test socket to obtain a correct reading; therefore, an open-socket
reading is not feasible using this method.
V = VIC
85
14
Figure 95. Isolation Metal Around Device Inputs (P package)
low-level output voltage
To obtain low-level supply-voltage operation, some compromise is necessary in the input stage. This
compromise results in the device low-level output voltage being dependent on both the common-mode input
voltage level as well as the differential input voltage level. When attempting to correlate low-level output
readings with those quoted in the electrical specifications, these two conditions should be observed. If
conditions other than these are to be used, please refer to the T ypical Characteristics section of this data sheet.
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input of fset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. These measurements should be
performed at temperatures above freezing to minimize error.
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
–
+
TLE2426 VO
VIR1
R2
VDD
Figure 97. Inverting Amplifier With
Voltage Reference
V
O
+ǒ
VDD –V
I
2
Ǔ
R2
R1
)
VDD
2
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 92. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 96). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(d) f > BOM
(c) f = BOM
(b) BOM > f > 100 Hz(a) f = 100 Hz
Figure 96. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
APPLICATION INFORMATION
single-supply operation
While the TLV2341 performs well using dual-
power supplies (also called balanced or split
supplies), the design is optimized for single-
supply operation. This includes an input common-
mode voltage range that encompasses ground as
well as an output voltage range that pulls down to
ground. The supply voltage range extends down
to 2 V, thus allowing operation with supply levels
commonly available for TTL and HCMOS.
Many single-supply applications require that a
voltage be applied to one input to establish a
reference level that is above ground. This virtual
ground can be generated using two large
resistors, but a preferred technique is to use a
virtual-ground generator such as the TLE2426.
The TLE2426 supplies an accurate voltage equal
to VDD/2, while consuming very little power and is
suitable for supply voltages of greater than 4 V.
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
single-supply operation (continued)
The TLV2341 works well in conjunction with digital logic; however, when powering both linear devices and digital
logic from the same power supply, the following precautions are recommended:
•Power the linear devices from separate bypassed supply lines (see Figure 98); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
•Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, RC decoupling may be necessary in high-frequency
applications.
–
+Logic Logic Logic Power
Supply
–
+Logic Logic Logic Power
Supply
(a) COMMON-SUPPLY RAILS
(b) SEPARA TE-BYPASSED SUPPLY RAILS (preferred)
Figure 98. Common Versus Separate Supply Rails
input offset voltage nulling
The TLV2341 offers external input offset null control. Nulling of the input offset voltage can be achieved by
adjusting a 25-kΩ potentiometer connected between the offset null terminals with the wiper connected as shown
in Figure 99. The amount of nulling range varies with the bias selection. In the high-bias mode, the nulling range
allows the maximum offset voltage specified to be trimmed to zero. In low-bias and medium-bias modes, total
nulling may not be possible.
VDD
25 kΩ
N1 N2
–
+
25 kΩ
N1 N2
–
+
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
GND
Figure 99. Input Offset Voltage Null Circuit
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
bias selection
Bias selection is achieved by connecting the bias-select pin to one of the three voltage levels (see Figure 100).
For medium-bias applications, it is recommended that the bias-select pin be connected to the midpoint between
the supply rails. This is a simple procedure in split-supply applications, since this point is ground. In
single-supply applications, the medium-bias mode necessitates using a voltage divider as indicated. The use
of large-value resistors in the voltage divider reduces the current drain of the divider from the supply line.
However, large-value resistors used in conjunction with a large-value capacitor require significant time to charge
up to the supply midpoint after the supply is switched on. A voltage other than the midpoint may be used if it
is within the voltages specified in the following table.
BIAS MODE BIAS-SELECT VOLTAGE
(single supply)
Low VDD
Medium 1 V to VDD –1 V
High GND
Figure 100. Bias Selection for Single-Supply Applications
input characteristics
The TL V2341 is specified with a minimum and a maximum input voltage that, if exceeded at either input, could
cause the device to malfunction. Exceeding this specified range is a common problem, especially in
single-supply operation. The lower the range limit includes the negative rail, while the upper range limit is
specified at VDD –1 V at TA = 25°C and at VDD –1.2 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TL V2341 good input offset
voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices
is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in
the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization
problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with
time has been calculated to be typically 0.1 µV/month, including the first month of operation.
Because of the extremely high input impedance and resulting low bias-current requirements, the TLV2341 is
well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can
easily exceed bias-current requirements and cause a degradation in device performance. It is good practice
to include guard rings around inputs (similar to those of Figure 95 in the Parameter Measurement Information
section). These guards should be driven from a low-impedance source at the same voltage level as the
common-mode input (see Figure 101).
The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.
To BIAS SELECT
Low
High
Medium
1 MΩ
VDD
1 MΩ0.01 µF
–
+
Figure 102. Compensation for Input Capacitance
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input characteristics (continued)
–
+
–
+
–
+
(a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER
VOVIVOVO
VIVI
Figure 101. Guard-Ring Schemes
noise performance
The noise specifications in operational amplifiers circuits are greatly dependent on the current in the first-stage
differential amplifier . The low input bias-current requirements of the TLV2341 results in a very low noise current,
which is insignificant in most applications. This feature makes the device especially favorable over bipolar
devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise
currents.
feedback
Operational amplifier circuits nearly always
employ feedback, and since feedback is the first
prerequisite for oscillation, caution is appropriate.
Most oscillation problems result from driving
capacitive loads and ignoring stray input
capacitance. A small-value capacitor connected
in parallel with the feedback resistor is an effective
remedy (see Figure 102). The value of this
capacitor is optimized empirically.
electrostatic-discharge protection
The TLV2341 incorporates an internal electro-
static-discharge (ESD)-protection circuit that
prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care
should be exercised, however , when handling these devices as exposure to ESD may result in the degradation
of the device parametric performance. The protection circuit also causes the input bias currents to be
temperature dependent and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLV2341 inputs
and output are designed to withstand –100-mA surge currents without sustaining latch-up; however, techniques
should be used to reduce the chance of latch-up whenever possible. Internal protection diodes should not by
–
+VO
CL
VI
2.5 V
TA = 25°C
f = 1 kHz
VI(PP) = 1 V –2.5 V
–
+RP
+
VDD
*
VO
IF
)
IL
)
IP
IP = Pullup Current
Required by the
Operational Amplifier
(typically 500 µA)
VO
VDD
RP
IP
IF
ILRL
VI
R1 R2
Figure 103. Resistive Pullup to Increase VOH
Figure 104. Test Circuit for Output Characteristics
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
design be forward biased. Applied input and output voltage should not exceed the supply voltage by more that
300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients
should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close
to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
output characteristics
The output stage of the TLV2341 is designed to
sink and source relatively high amounts of current
(see Typical Characteristics). If the output is
subjected to a short-circuit condition, this
high-current capability can cause device damage
under certain conditions. Output current capability
increases with supply voltage.
Although the TLV2341 possesses excellent
high-level output voltage and current capability,
methods are available for boosting this capability
if needed. The simplest method involves the use
of a pullup resistor (RP) connected from the output
to the positive supply rail (see Figure 103). There
are two disadvantages to the use of this circuit.
First, the NMOS pulldown transistor N4 (see
equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves
like a linear resistor with an on resistance between
approximately 60 Ω and 180 Ω, depending on
how hard the operational amplifier input is driven.
With very low values of RP, a voltage offset from
0 V at the output occurs. Secondly, pullup resistor
RP acts as a drain load to N4 and the gain of the
operational amplifier is reduced at output voltage
levels where N5 is not supplying the output
current.
All operating characteristics of the TLV2341 are measured using a 20-pF load. The device drives higher
capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower
frequencies thereby causing ringing, peaking, or even oscillation (see Figures 105, 106 and 107). In many
cases, adding some compensation in the form of a series resistor in the feedback loop alleviates the problem.
TLV2341, TLV2341Y
LinCMOS PROGRAMMABLE LOW-VOLTAGE
OPERATIONAL AMPLIFIERS
SLOS110A – MA Y 1992 – REVISED AUGUST 1994
50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
output characteristics (continued)
(a) CL = 20 pF, RL = NO LOAD (b) CL = 130 pF, RL = NO LOAD (c) CL = 150 pF, RL = NO LOAD
Figure 105. Effect of Capacitive Loads in High-Bias Mode
(a) CL = 20 pF, RL = NO LOAD (b) CL = 170 pF, RL = NO LOAD (c) CL = 190 pF, RL = NO LOAD
Figure 106. Effect of Capacitive Loads in Medium-Bias Mode
(a) CL = 20 pF, RL = NO LOAD (b) CL = 260 pF, RL = NO LOAD (c) CL = 310 pF, RL = NO LOAD
Figure 107. Effect of Capacitive Loads in Low-Bias Mode
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV2341ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2341IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2341IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2341IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2341IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2341IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TLV2341IPWG4 ACTIVE TSSOP PW 8 TBD Call TI Call TI
TLV2341IPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI
TLV2341IPWRG4 ACTIVE TSSOP PW 8 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Mar-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2341IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2341IDR SOIC D 8 2500 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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