24'.+/+0#4;241&7%652'%+(+%#6+10 <5<. '0*#0%'&</+%41241%'5514 1(('45(#56'4':'%76+10 219'45#8'4/1&'.19'/+ ('#674'5 Code Compatible with ZiLOG Z80(R) CPU Two 16-Bit Counter/Timers Extended Instructions Two Enhanced UARTs (up to 512 Kbps) Two Chain-Linked DMA Channels Clock Speeds: 10, 20, 33 MHz Low Power-Down Modes Operating Range: 5V (3.3V@ 20 MHz) On-Chip Interrupt Controllers Operating Temperature Range: 0C to +70C Three On-Chip Wait-State Generators -40C to +85C Extended Temperature Range On-Chip Oscillator/Generator Three Packaging Styles - 68-Pin PLCC - 64-Pin DIP - 80-Pin QFP Expanded MMU Addressing (Up to 1 MB) Clocked Serial I/O Port )'0'4#.&'5%4+26+10 The enhanced Z8S180/Z8L180TM significantly improves on previous Z80180 models, while still providing full backward compatibility with existing ZiLOG Z80 devices. The Z8S180/Z8L180 now offers faster execution speeds, power-saving modes, and EMI noise reduction. This enhanced Z180TM design also incorporates additional feature enhancements to the ASCIs, DMAs, and 56#0&$; mode power consumption. With the addition of ESCC-like Baud Rate Generators (BRGs), the two ASCIs offer the flexibility and capability to transfer data asynchronously at rates of up to 512 Kbps. In addition, the ASCI receiver features a 4-byte first in/first out (FIFO) buffer which reduces the likelihood of overrun errors. The DMAs have been modified to allow for chain-linking of the two DMA channels when set to take their DMA requests from the same peripherals device. This feature allows for nonstop DMA operation between the two DMA channels. Not only does the Z8S180/Z8L180 consume less power during normal operations than the previous model, it offers &5</2 three modes intended to further reduce power consumption. Power consumption during 56#0&$; Mode is reduced to 10 A by stopping the external oscillators and internal clock. The 5.''2 mode reduces power by placing the CPU into a stopped state, consuming less current while the onchip I/O devices still operate. The 5;56'/5612 mode places both the CPU and the on-chip peripherals into a stopped mode, reducing power consumption even further. A new clock-doubler feature in the Z8S180/Z8L180 allows the internal clock speed to be twice the external clock speed. As a result, system cost is reduced by allowing the use of lower-cost, lower-frequency crystals. The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC, and 64-pin DIP packages. 0QVG All Signals with an overline are active Low. For example: B/W, in which WORD is active Low; or B/W, in which BYTE is active Low. <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #6176 6:5 4:5%65 $WU5VCVG%QPVTQN +06 +06 0/+ ' 56 855 4(5* )0& $75#%- )TQWPF $754'3 8&& 9#+6 8%% *#.6 2QYGT +143 &GXKEG /4'3 / 94 4& 4'5'6 %KTEWKV 6KOKPI )GPGTCVQT +PVGTTWRV %27 $KV 2TQITCOOCDNG 4GNQCF6KOGTU &/#%U &4'3 6'0& 6:# %NQEMGF 5GTKCN+1 2QTV #FFTGUU$WU $KV %-5 %QPPGEVKQP #U[PEJTQPQWU 5%+ %JCPPGN &CVC$WU $KV 2*+ ':6#. :6#. Power connections follow the conventional descriptions below: +06 )'0'4#.&'5%4+26+10 %QPVKPWGF #FFTGUU $WHHGT &CVC $WHHGT # # & & 4:# 465 %65 &%& 6:# #U[PEJTQPQWU 5%+ %JCPPGN //7 %-#&4'3 %-#6'0& 4:# 8&& 855 (KIWTG <5<.(WPEVKQPCN$NQEM&KCITCO 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 2+0+&'06+(+%#6+10 855 :6#. ':6#. 9#+6 $75#%$754'3 4'5'6 0/+ +06 +06 +06 56 # # # # # # # # # # # # # # # # # # #6176 8&& 1 64 <5 2KP&+2 32 33 2*+ 4& 94 / ' /4'3 +143 4(5* *#.6 6'0& &4'3 %-5 4:5%65 6:5 %-#6'0& 4:# 6:# %-#&4'3 4:# 6:# &%& %65 465 & & & & & & & & 855 (KIWTG <52KP&+22KP%QPHKIWTCVKQP &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 0/+ 4'5'6 $754'3 $75#%9#+6 ':6#. :6#. 8 8 2*+ 4& 94 / ' /4'3 +143 4(5* 2+0+&'06+(+%#6+10 %QPVKPWGF 55 55 +06 +06 +06 56 # # # # 855 # # # # # # # # <5<. 2KP2.%% # # # # # # #6 8 # 8 & & & & & & & 67 & 1 & 55 *#.6 6'0& &4'3 %-5 4:5%65 6:5 %-#6'0& 4:# 6'56 6:# %-#&4'3 4:# 6:# &%& %65 465 & (KIWTG <5<.2KP2.%%2KP%QPHKIWTCVKQP 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT 4(5* 0% 0% *#.6 6'0& &4'3 %-5 4:5%65 6:5 %-#6'0& 4:# 6'56 6:# 0% %-#&4'3 4:# 6:# &%& %65 465 & 0% 0% & ZiLOG +143 /4'3 ' / 94 4& 2*+ 855 855 :6#. 0% ':6#. 9#+6 $75#%$754'3 4'5'6 <5<. 2KP3(2 & & & & & & 855 # 8&& #6176 0% # # # # # 0/+ 0% 0% +06 +06 +06 56 # # # # 8 # 0% # # # # # # # 0% 0% # 55 (KIWTG <5<.2KP3(22KP%QPHKIWTCVKQP 6CDNG <5<.2KP+FGPVKHKECVKQP 2KP0WODGTCPF2CEMCIG6[RG 3(2 2.%% &+2 &GHCWNV (WPEVKQP 0/+ 5GEQPFCT[ (WPEVKQP %QPVTQN 0% 0% +06 +06 +06 56 # # # &5</2 # 855 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 2+0+&'06+(+%#6+10 %QPVKPWGF 6CDNG <5<.2KP+FGPVKHKECVKQP %QPVKPWGF 2KP0WODGTCPF2CEMCIG6[RG 3(2 2.%% &+2 &GHCWNV (WPEVKQP # # # # # # # # 0% 0% # # # # # # 0% # 8&& 855 & & & & & & 6176 $KVQT$KVQH6%4 # & 0% 0% 465 %65 &%& 6:# & 4:# %-# %QPVTQN 0% 5GEQPFCT[ (WPEVKQP &4'3 $KVQT$KVQH&/1&' 0% 6:# 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6CDNG <5<.2KP+FGPVKHKECVKQP %QPVKPWGF 2KP0WODGTCPF2CEMCIG6[RG &+2 &GHCWNV (WPEVKQP 3(2 2.%% 4:# %-# 6:5 4:5 5GEQPFCT[ (WPEVKQP %QPVTQN 6'56 %-5 &4'3 6'0& *#.6 0% 0% 4(5* +143 /4'3 ' / 94 4& 2*+ 855 6'0& %65 $KVQH%06.# $KVQH56#6 855 :6#. 0% ':6#. 9#+6 $75#%- $754'3 4'5'6 &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 2+0+&'06+(+%#6+10 %QPVKPWGF 6CDNG 2KP5VCVWU&WTKPI4'5'6$75#%-CPF5.''2/QFGU 2KP0WODGTCPF2CEMCIG6[RG 3(2 2.%% &+2 &GHCWNV (WPEVKQP 0/+ 5GEQPFCT[ (WPEVKQP 4'5'6 $75#%- 5.''2 +0 +0 +0 0% 0% +06 +0 +0 +0 +06 +0 +0 +0 +06 +0 +0 +0 56 *KIJ *KIJ *KIJ # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ 855 855 855 855 # 6 6 *KIJ 0% # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ 6 6 *KIJ 0% 0% # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ # 6 6 *KIJ 6176 0# 176 176 8&& 8&& 8&& 8&& # 6 6 *KIJ 2KP5VCVWU # 0% 855 855 855 855 & 6 6 6 & 6 6 6 & 6 6 6 & 6 6 6 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6CDNG 2KP5VCVWU&WTKPI4'5'6$75#%-CPF5.''2/QFGU %QPVKPWGF 2KP0WODGTCPF2CEMCIG6[RG 2KP5VCVWU 3(2 2.%% &+2 &GHCWNV (WPEVKQP 5GEQPFCT[ (WPEVKQP 4'5'6 $75#%- 5.''2 & 6 6 6 & 6 6 6 & 6 6 6 0% 0% & 6 6 6 465 *KIJ 176 *KIJ %65 +0 176 +0 &%& +0 +0 +0 6:# *KIJ 176 176 4:# +0 +0 +0 %-# 6 +1 +1 &4'3 0# +0 +0 *KIJ 176 176 +0 +0 +0 0% 6:# 6'56 4:# %-# 6 +1 +1 6'0& 0# *KIJ *KIJ 6:5 *KIJ 176 176 4:5 +0 +0 +0 %65 0# +0 +0 %-5 6 +1 +1 &4'3 +0 6 +0 6'0& *KIJ 176 *KIJ *#.6 *KIJ *KIJ .QY 4(5* *KIJ 176 *KIJ 0% 0% +143 *KIJ 6 *KIJ /4'3 *KIJ 6 *KIJ ' .QY 176 176 / *KIJ *KIJ *KIJ 94 *KIJ 6 *KIJ 4& *KIJ 6 *KIJ 2*+ 176 176 176 855 )0& )0& )0& 855 )0& )0& )0& :6#. 176 176 176 &5</2 0% 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 2+0+&'06+(+%#6+10 %QPVKPWGF 6CDNG 2KP5VCVWU&WTKPI4'5'6$75#%-CPF5.''2/QFGU %QPVKPWGF 2KP0WODGTCPF2CEMCIG6[RG 2KP5VCVWU 3(2 2.%% &+2 &GHCWNV (WPEVKQP 5GEQPFCT[ (WPEVKQP 4'5'6 $75#%- 5.''2 ':6#. +0 +0 +0 9#+6 +0 +0 +0 $75#%- *KIJ 176 176 $754'3 +0 +0 +0 4'5'6 +0 +0 +0 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 2+0&'5%4+26+105 # #Address Bus (Output, 3-state). # # form a 20-bit address bus. The Address Bus provides the address for memory data bus exchanges (up to 1 MB) and I/O data bus exchanges (up to 64 KB). The address bus enters a high-impedance state during reset and external bus acknowledge cycles. Address line # is multiplexed with the output of PRT channel 1 (6176, selected as address output on reset), and address line # is not available in DIP versions of the Z8S180. $75#%- . Bus Acknowledge (Output, active Low). $75#%- indicates that the requesting device, the MPU ad- dress and data bus, and some control signals enter their highimpedance state. $754'3 Bus Request (Input, active Low). This input is used by external devices (such as DMA controllers) to request access to the system bus. This request demands a higher priority than 0/+ and is always recognized at the end of the current machine cycle. This signal stops the CPU from executing further instructions, places addresses, data buses, and other control signals into the high-impedance state. %-#%-#Asynchronous Clock 0 and 1 (bidirection- al). When in output mode, these pins are the transmit and receive clock outputs from the ASCI baud rate generators. When in input mode, these pins serve as the external clock inputs for the ASCI baud rate generators. %-# is multiplexed with &4'3, and %-# is multiplexed with 6'0&. %-5Serial Clock (bidirectional). This line is the clock for the CSI/O channel. %65 %65. Clear to send 0 and 1 (Inputs, active Low). These lines are modem control signals for the ASCI channels. %65 is multiplexed with 4:5. & &Data Bus = (bidirectional, 3-state). & & constitute an 8-bit bidirectional data bus, used for the transfer of information to and from I/O and memory devices. The data bus enters the high-impedance state during reset and external bus acknowledge cycles. &%&. Data Carrier Detect 0 (Input, active Low); a programmable modem control signal for ASCI channel 0. &4'3&4'3. DMA Request 0 and 1 (Input, active Low). &4'3 is used to request a DMA transfer from one of the on-chip DMA channels. The DMA channels monitor these inputs to determine when an external device is ready for a 4'#& or 94+6' operation. These inputs can be programmed to be either level or edge sensed. &4'3 is multiplexed with %-#. &5</2 'Enable Clock (Output). This pin functions as a synchronous, machine-cycle clock output during bus transactions. ':6#.External Clock Crystal (Input). Crystal oscillator connections. An external clock can be input to the Z8S180/Z8L180 on this pin when a crystal is not used. This input is Schmitt triggered. *#.6. *#.6/5.''2 (Output, active Low). This output is asserted after the CPU executes either the *#.6 or 5.''2 instruction and is waiting for either a nonmaskable or a maskable interrupt before operation can resume. It is also used with the / and 56 signals to decode the status of the CPU machine cycle. +06. Maskable Interrupt Request 0 (Input, active Low). This signal is generated by external I/O devices. The CPU honors these requests at the end of the current instruction cycle as long as the 0/+ and $754'3 signals are inactive. The CPU acknowledges this interrupt request with an interrupt acknowledge cycle. During this cycle, both the / and +143 signals become active. +06+06. Maskable Interrupt Request 1 and 2 (Inputs, active Low). This signal is generated by external I/O devices. The CPU honors these requests at the end of the current instruction cycle as long as the 0/+, $754'3, and +06 signals are inactive. The CPU acknowledges these requests with an interrupt acknowledge cycle. Unlike the acknowledgment for +06, neither the / or +143 signals become active during this cycle. +143. I/O Request (Output, active Low, 3-state). +143 indicates that the address bus contains a valid I/O address for an +14'#& or +1 94+6' operation. +143 is also generated, along with /, during the acknowledgment of the +06 input signal to indicate that an interrupt response vector can be place onto the data bus. This signal is analogous to the +1' signal of the Z64180. /. Machine Cycle 1 (Output, active Low). Together with /4'3, / indicates that the current cycle is the opcodefetch cycle of instruction execution. Together with +143, / indicates that the current cycle is for interrupt acknowledgment. It is also used with the *#.6 and 56 signal to de- code the status of the CPU machine cycle. This signal is analogous to the .+4 signal of the Z64180. /4'3. Memory Request (Output, active Low, 3-state). /4'3 indicates that the address bus holds a valid address for a memory 4'#& or memory 94+6' operation. This signal is analogous to the /' signal of Z64180. 0/+. Nonmaskable Interrupt (Input, negative edge triggered). 0/+ demands a higher priority than +06 and is al- 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 2+0&'5%4+26+105 %QPVKPWGF ways recognized at the end of an instruction, regardless of the state of the interrupt-enable flip-flops. This signal forces CPU execution to continue at location 0066H. 2*+System Clock (Output). The output is used as a reference clock for the MPU and the external system. The frequency of this output may be one-half, equal to, or twice the crystal or input clock frequency. 4&Read (Output, active Low, 3-state). 4& indicates that the CPU wants to read data from either memory or an I/O device. The addressed I/O or memory device should use this signal to gate data onto the CPU data bus. 4(5* Refresh (Output, active Low). Together with /4'3, 4(5* indicates that the current CPU machine cycle and the contents of the address bus should be used for refresh of dynamic memories. The low-order 8 bits of the address bus (# #) contain the refresh address. This signal is analogous 6'0& 6'0& Transfer End 0 and 1 (Outputs, active Low). This output is asserted active during the most recent 94+6' cycle of a DMA operation. It is used to indicate the end of the block transfer. 6'0& is multiplexed with %-#. 6'56Test (Output, not in DIP version). This pin is for test and should be left open. 6176Timer Out (Output). 6176 is the output from PRT channel 1. This line is multiplexed with # of the address bus. 6:#6:#Transmit Data 0 and 1 (Outputs). These signals are the transmitted data from the ASCI channels. Transmitted data changes are with respect to the falling edge of the transmit clock. 6:5Clocked Serial Transmit Data (Output). This line is the transmitted data from the CSI/O channel. to the REF signal of the Z64180. 9#+6. Wait (Input, active Low). 9#+6 indicates to the 465 Request to Send 0 (Output, active Low); a program- MPU that the addressed memory or I/O devices are not ready for data transfer. This input is sampled on the falling edge of 6 (and subsequent 9#+6 states). If the input is sampled Low, then the additional 9#+6 states are inserted until the 9#+6 input is sampled High, at which time execution continues. mable MODEM control signal for ASCI channel 0. 4:#4:#Receive Data 0 and 1 (Input). These signals are the receive data for the ASCI channels. 4:5Clocked Serial Receive Data (Input). This line is the receive data for the CSI/O channel. RXS is multiplexed with the %65 signal for ASCI channel 1. 56Status (Output). This signal is used with the / and *#.6 output to decode the status of the CPU machine cycle. See Table 3. 6CDNG 5VCVWU5WOOCT[ 56 *#.6 / 1RGTCVKQP : %271RGTCVKQP UV1REQFG(GVEJ %271RGTCVKQP PF1REQFGCPFTF 1REQFG(GVEJ %271RGTCVKQP /%'ZEGRV1REQFG (GVEJ &/#1RGTCVKQP *#.6/QFG 5.''2/QFG +PENWFKPI5;56'/ 5612/QFG 94. 94+6' (Output, active Low, 3-state). 94 indicates that the CPU data bus holds valid data to be stored at the addressed I/O or memory location. :6#.Crystal Oscillator Connection (Input). This pin should be left open if an external clock is used instead of a crystal. The oscillator input is not a TTL level (see DC Characteristics). Several pins are used for different conditions, depending on the circumstance. Notes: :&QPQVECTG /%/CEJKPG%[ENG 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6CDNG /WNVKRNGZGF2KP&GUETKRVKQPU #6176 &WTKPI4'5'6VJKURKPKUKPKVKCNK\GFCU#+HGKVJGTVJG61%QTVJG61%DKVQHVJG6KOGT %QPVTQNTGIKUVGT 6%4 KUUGVVQ 1 VJG6176HWPEVKQPKUUGNGEVGF+H61%CPF61%CTGENGCTGF VQ0VJG#HWPEVKQPKUUGNGEVGF %-#&4'3 &WTKPI4'5'6VJKURKPKUKPKVKCNK\GFCU%-#+HGKVJGT&/QT5/KPVJG&/#/QFGTGIKUVGT &/1&' KUUGVVQ 1 VJG&4'3HWPEVKQPKUUGNGEVGF %-#6'0& &WTKPI4'5'6VJKURKPKUKPKVKCNK\GFCU%-#+HVJG%-#&DKVKP#5%+EQPVTQNTGIKUVGTEJ %06.# KUUGVVQ 1 VJG6'0&HWPEVKQPKUUGNGEVGF+HVJG%-#&DKVKUUGVVQ0VJG%-# HWPEVKQPKUUGNGEVGF 4:5%65 &WTKPI4'5'6VJKURKPKUKPKVKCNK\GFCU4:5+HVJG%65'DKVKPVJG#5%+UVCVWUTGIKUVGTEJ 56#6 KUUGVVQ 1 VJG%65HWPEVKQPKUUGNGEVGF+HVJG%65'DKVKUUGVVQ0VJG4:5 HWPEVKQPKUUGNGEVGF &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #4%*+6'%674' The Z180 combines a high-performance CPU core with a variety of system and I/O resources useful in a broad range of applications. The CPU core consists of five functional blocks: clock generator, bus state controller, Interrupt controller, memory management unit (MMU), and the central processing unit (CPU). The integrated I/O resources make up the remaining four functional blocks: direct memory access (DMA) control (2 channels), asynchronous serial communication interface (ASCI, 2 channels) programmable reload timers (PRT, 2 channels), and a clock serial I/O (CSI/O) channel. %NQEM)GPGTCVQTThis logic generates a system clock from an external crystal or clock input. The external clock is divided by 2 or 1 and provides the timing for both internal and external devices. $WU5VCVG%QPVTQNNGTThis logic performs all of the status and bus-control activity associated with the CPU and some on-chip peripherals. Also includes wait-state timing, reset cycles, DRAM refresh, and DMA bus exchanges. +PVGTTWRV%QPVTQNNGTThis logic monitors and prioritizes the variety of internal and external interrupts and traps to provide the correct responses from the CPU. To maintain compatibility with the Z80 CPU, three different interrupts modes are supported. /GOQT[/CPCIGOGPV7PKVThe MMU allows the user to map the memory used by the CPU (logically only 64KB) into the 1-MB addressing range supported by the Z8S180/Z8L180. The organization of the MMU object code maintains compatibility with the Z80 CPU, while offering access to an extended memory space. Accomplished by using an effective common-area/banked-area scheme. %GPVTCN2TQEGUUKPI7PKVThe CPU is microcoded to provide a core that is object-code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiplication. The core is modified to allow many of the instructions to execute in fewer clock cycles. &/#%QPVTQNNGTThe DMA controller provides highspeed transfers between memory and I/O devices. Transfer operations supported are memory-to-memory, memory to/from I/O, and I/O-to-I/O. Transfer modes supported are request, burst, and cycle steal. DMA transfers can access the full 1-MB address range with a block length up to 64 KB, and can cross over 64K boundaries. #U[PEJTQPQWU 5GTKCN %QOOWPKECVKQP +PVGTHCEG #5%+ The ASCI logic provides two individual full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. The ASCI channels can also support a multiprocessor communication format as well as break detection and generation 2TQITCOOCDNG4GNQCF6KOGTU 246 This logic consists of two separate channels, each containing a 16-bit counter (timer) and count reload register. The time base for the counters is derived from the system clock (divided by 20) before reaching the counter. PRT channel 1 provides an optional output to allow for waveform generation. 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 4GUGV 6KOGT&CVC 4GIKUVGT 6KOGT&CVC4GIKUVGT V 9TKVG * ((((* * ((((* * * * * * * * * * 4GNQCF 4GNQCF 6KOGT4GNQCF4GIKUVGT9TKVG * 6KOGT4GNQCF 4GIKUVGT * 9TKVGVQ6&' 6&'(NCI 6+((NCI 6KOGT&CVC4GIKUVGT4GCF 6KOGT%QPVTQN4GSWGUVQT4GCF (KIWTG 6KOGT+PKVKCNK\CVKQP%QWPV&QYPCPF4GNQCF6KOKPI 2*+ 6KOGT&CVC 6KOGT&CVC 4GI* 4GI* 6176 (KIWTG 6KOGT1WVRWV6KOKPI %NQEMGF5GTKCN+1 %5+1 The CSI/O channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple high-speed data connection to another microprocessor or microcomputer. 64&4 is used for both CSI/O transmission and reception. Thus, the system design must ensure that the constraints of half-duplex operation are met (Transmit and Receive operation cannot occur simultaneously). For example, if a CSI/O transmission is attempted while the CSI/O is receiving data, a CSI/O does not work. &5</2 0QVG 64&4 is not buffered. Performing a CSI/O transmit while the previous transmission is still in progress causes the data to be immediately updated and corrupts the transmit operation. Similarly, reading 64&4 while a transmit or receive is in progress should be avoided. 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #4%*+6'%674' %QPVKPWGF +PVGTPCN#FFTGUU&CVC$WU 2*+ 6:5 4:5 %5+16TCPUOKV4GEGKXG &CVC4GIKUVGT 64&4 $CWF4CVG )GPGTCVQT %-5 %5+1%QPVTQN4GIKUVGT %064 +PVGTTWRV4GSWGUV (KIWTG %5+1$NQEM&KCITCO 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 12'4#6+10/1&'5 <XGTUWU%QORCVKDKNKV[The Z8S180/Z8L180 is descended from two different "ancestor" processors, ZiLOG's original Z80 and the Hitachi 64180. The Operating Mode Control Register (OMCR), illustrated in Figure 8, can be programmed to select between certain Z80 and 64180 differences. /' /'PCDNG This bit controls the / output and is set to a 1 during 4'5'6. When /'1, the / output is asserted Low during opcode fetch cycles, Interrupt Acknowledge cycles, and the first machine cycle of an 0/+ acknowledge. On the Z8S180/Z8L180, this choice makes the processor fetch a 4'6+ instruction one time. When fetching a 4'6+ from a zero-wait-state memory location, the processor uses three clock bus cycles. These bus cycles are not fully Z80timing compatible. & & & 4GUGTXGF When /' 0, the processor does not drive / Low during the instruction fetch cycles. After fetching a 4'6+ instruction with normal timing, the processor goes back and refetches the instruction using fully Z80-compatible cycles that include driving / Low. This option may be required by some external Z80 peripherals to properly decode the 4'6+ instruction. Figure 9 and Table 5 show the 4'6+ sequence when /' is 0. +1% 49 /6' 9 /' 49 (KIWTG 1RGTCVKPI%QPVTQN4GIKUVGT 1/%4+1#FFTGUU'* 6 6 6 6 6 6 6+ 6+ 6+ 6 6 6 6+ 6 6 6 6+ 2*+ # # # & & 2% 2% '&* &* 2% '&* 2% &* / /4'3 4& 56 (KIWTG 4'6++PUVTWEVKQP5GSWGPEGYKVJ/' &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 12'4#6+10/1&'5 %QPVKPWGF 6CDNG 4'6+%QPVTQN5KIPCN5VCVGU /CEJKPG %[ENG 5VCVGU 6 6 6K 6K 6K 6 6K 6 6 6 6 6 6 6 6 6 #FFTGUU &CVC UV1REQFG PF1REQFG 0# 0# 0# UV1REQFG 0# PF1REQFG 52 52 '&* &* UVCVG UVCVG UVCVG '&* UVCVG &* &CVC &CVC 4& 94 /4'3 +143 /6' /6GORQTCT['PCDNG This bit controls the temporary assertion of the / signal. It is always read back as a 1 and is set to 1 during 4'5'6. When /' is set to0 to accommodate certain external Z80 peripheral(s), those same device(s) may require a pulse on / after programming certain of their registers to complete the function being programmed. 6 6 6 / / /' /' *#.6 56 For example, when a control word is written to the Z80 PIO to enable interrupts, no enable actually takes place until the PIO sees an active / signal. When /6' =1, there is no change in the operation of the / signal, and /' controls its function. When /6' =0, the / output is asserted during the next opcode fetch cycle regardless of the state programmed into the /' bit. This condition is only momentary (one time) and it is not necessary to preprogram a 1 to disable the function (see Figure 10). 6 6 6 2*+ 94 / 9TKVGKPVQ1/%4 1REQFG(GVEJ (KIWTG /6GORQTCT['PCDNG6KOKPI +1% +1%QORCVKDKNKV[ This bit controls the timing of the +143 and 4& signals. The bit is set to 1 by 4'5'6. When +1% =1, the +143 and 4& signals function the same as the Z64180 (Figure 11). 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6 6 69 6 2*+ +143 4& 94 (KIWTG +14GCFCPF9TKVG%[ENGUYKVJ+1% When +1% =0, the timing of the +143 and 4& signals match the timing of the Z80. The +143 and 4& signals go active as a result of the rising edge of T2. (Figure 12.) 6 6 69 6 2*+ +143 4& 94 (KIWTG +14GCFCPF9TKVG%[ENGUYKVJ+1% *#.6CPF.QY2QYGT1RGTCVKPI/QFGUT h e Z8S180/Z8L180 can operate in seven modes with respect to activity and power consumption: Normal Operation *#.6 Mode +15612 Mode 5.''2 Mode 5;56'/5612 Mode +&.' Mode 56#0&$; Mode (with or without 37+%- 4'%18 '4;) &5</2 0QTOCN1RGTCVKQPIn this state, the Z8S180/Z8L180 processor is fetching and running a program. All enabled functions and portions of the device are active, and the *#.6 pin is High. *#.6/QFGThis mode is entered by the *#.6 instruction. Thereafter, the Z8S180/Z8L180 processor continually fetches the following opcode but does not execute it and drives the *#.6, 56 and / pins all Low. The oscillator and 2*+ pin remain Active. Interrupts and bus granting to external Masters, and DRAM refresh can occur, and all onchip I/O devices continue to operate including the DMA channels. 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 12'4#6+10/1&'5 %QPVKPWGF The Z8S180/Z8L180 leaves *#.6 mode in response to: Low on 4'5'6 Interrupt from an enabled on-chip source External request on 0/+ In case of an interrupt, the return address is the instruction following the *#.6 instruction. The program can either branch back to the *#.6 instruction to wait for another interrupt or can examine the new state of the system/application and respond appropriately. Enabled external request on +06, +06, or +06 HALT Opcode Fetch Cycle T2 Interrupt Acknowledge Cycle HALT Mode T3 T1 T2 PHI INTi , NMI HALT Opcode Address + 1 A19-A 0 HALT Opcode Address HALT M1 MREQ RD Note: indicates an indefinite delay. (KIWTG *#.66KOKPI 5.''2/QFGThis mode is entered by keeping the +15612 an external request on 0/+, or an external request on +06, bit (ICR5) and bits 3 and 6 of the CPU Control Register (CCR3, CCR6) all zero and executing the 5.2 instruction. The oscillator and 2*+ output continue operating, but are blocked from the CPU core and DMA channels to reduce power consumption. DRAM refresh stops, but interrupts and granting to an external Master can occur. Except when the bus is granted to an external Master, A19-0 and all control signals except *#.6 are maintained High. *#.6 is Low. I/O operations continue as before the 5.2 instruction, except for the DMA channels. +06, or +06. The Z8S180/Z8L180 leaves 5.''2 mode in response to a Low on 4'5'6, an interrupt request from an on-chip source, If an interrupt source is individually disabled, it cannot bring the Z8S180/Z8L180 out of 5.''2 mode. If an interrupt source is individually enabled, and the +'( bit is 1 so that interrupts are globally enabled (by an EI instruction), the highest priority active interrupt occurs with the return address being the instruction after the 5.2 instruction. If an interrupt source is individually enabled, but the +'( bit is0 so that interrupts are globally disabled (by a DI instruction), the Z8S180/Z8L180 leaves 5.''2 mode by simply executing the following instruction(s). 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG This condition provides a technique for synchronization with high-speed external events without incurring the latency imposed by an interrupt-response sequence. Figure 14 depicts the timing for exiting 5.''2 mode due to an interrupt request. 5.2PF1REQFG (GVEJ%[ENG 6 6 0QVG The Z8S180/Z8L180 takes about 1.5 clock ticks to restart. 1REQFG(GVEJQT+PVGTTWRV #EMPQYNGFIG%[ENG 5.''2/QFG 6 6 65 65 6 6 6 2*+ +06K0/+ # # 5.2PF1REQFG#FFTGUU (((((* *#.6 / (KIWTG 5.''26KOKPI +15612/QFG+15612 mode is entered by setting the +15612 bit of the I/O Control Register (+%4) to 1. In this case, on-chip I/O (ASCI, CSI/O, PRT) stops operating. However, the CPU continues to operate. Recovery from +15612 mode is performed by resetting the +15612 bit in +%4 to 0. 5;56'/5612/QFG5;56'/5612 mode is the combination of 5.''2 and +15612 modes. 5;56'/ 5612 mode is entered by setting the +15612 bit in +%4 to 1 followed by execution of the 5.2 instruction. In this mode, onchip I/O and CPU stop operating, reducing power consumption, but the 2*+ output continues to operate. Recovery from 5;56'/5612 mode is the same as recovery from 5.''2 mode except that internal I/O sources (disabled by +15612) cannot generate a recovery interrupt. +&.'/QFGSoftware puts the Z8S180/Z8L180 into this mode by performing the following actions: Set the +15612 bit (+%4) to internal devices stop, but external interrupts can occur. Bus granting to external Masters can occur if the $4'56 bit in the CPU control Register (%%4) was set to 1 before +&.' mode was entered. The Z8S180/Z8L180 leaves +&.' mode in response to a Low on 4'5'6, an external interrupt request on 0/+, or an external interrupt request on +06, +06 or +06 that is enabled in the INT/TRAP Control Register. As previously described for 5.''2 mode, when the Z8S180/Z8L180 leaves +&.' mode due to an 0/+, or due to an enabled external interrupt request when the +'( flag is 1 due to an '+ instruction, the device starts by performing the interrupt with the return address of the instruction after the 5.2 instruction. If an external interrupt enables the INT/TRAP control register while the +'( bit is0, Z8S180/Z8L180 leaves +&.' mode; specifically, the processor restarts by executing the instructions following the 5.2 instruction. Figure 15 indicates the timing for exiting +&.' mode due to an interrupt request. Set %%4 to Set %%4 to 0QVG The Z8S180/Z8L180 takes about 9.5 clocks to restart. Execute the 5.2 instruction The oscillator keeps operating but its output is blocked to all circuitry including the 2*+ pin. DRAM refresh and all &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 12'4#6+10/1&'5 %QPVKPWGF 1REQFG(GVEJQT+PVGTTWRV #EMPQYNGFIG%[ENG +&.'/QFG 6 6 6 6 2*+ %[ENG&GNC[HTQO+06K#UUGTVGF 0/+ QT +06+06+06 # # (((((* *#.6 / (KIWTG <5<.+&.'/QFG'ZKV&WG6Q'ZVGTPCN+PVGTTWRV While the Z8S180/Z8L180 is in +&.' mode, it grants the bus to an external Master if the BREXT bit (CCR5) is 1. Figure 16 depicts the timing for this sequence. After the external Master negates the Bus Request, the Z8S180/Z8L180 disables the 2*+ clock and remains in +&.' mode. 0QVG A response to a bus request takes 8 clock cycles longer than in normal operation. 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG $WU4GNGCUG/QFG +&.'/QFG 6: +&.'/QFG 6: 2*+ %[ENG&GNC[WPVKN$75#%-#UUGTVGF $754'3 $75#%- # # (((((* *KIJ+ORGFCPEG *KIJ (((((* *#.6 / .QY (KIWTG $WU)TCPVKPIVQ'ZVGTPCN/CUVGTKP+&.'/QFG 56#0&$;/QFG 9KVJQT9KVJQWV37+%-4'%18'4; Software can put the Z8S180/Z8L180 into this mode by setting the +15612 bit (ICR5) to1, CCR6 to1, and executing the 5.2 instruction. This mode stops the on-chip oscillator and thus draws the least power of any mode, less than 10A. As with +&.' mode, the Z8S180/Z8L180 leaves 56#0&$; mode in response to a Low on 4'5'6, on 0/+, or a Low on +06-2 that is enabled by a 1 in the corresponding bit in the INT/TRAP Control Register. This action grants the bus to an external Master if the BREXT bit in the CPU Control Register (CCR5) is 1. The time required for all of these operations is greatly increased by the necessity for restarting the on-chip oscillator, and ensuring that it stabilizes to square-wave operation. When an external clock is connected to the EXTAL pin rather than a crystal to the XTAL and EXTAL pins and the external clock runs continuously, there is little necessity to use 56#0&$; mode because no time is required to restart the oscillator, and other modes restart faster. However, if external logic stops the clock during 56#0&$; mode (for example, by decoding *#.6 Low and / High for several clock cycles), then 56#0&$; mode can be useful to allow the external clock source to stabilize after it is re-enabled. &5</2 When external logic drives 4'5'6 Low to bring the device out of 56#0&$; mode, and a crystal is in use or an external clock source is stopped, the external logic must hold 4'5'6 Low until the on-chip oscillator or external clock source is restarted and stabilized. The clock-stability requirements of the Z8S180/Z8L180 are much less in the divide-by-two mode that is selected by a 4'5'6 sequence and controlled by the Clock Divide bit in the CPU Control Register (CCR7). As a result, software performs the following actions: 1. Sets CCR7 to0 for divide-by-two mode before an 5.2 instruction and 56#0&$; mode. 2. Delays setting CCR7 back to 1 for divide-by-one mode as long as possible to allow additional clock stabilization time after a 4'5'6, interrupt, or in-line RESTART after an 5.2 01 instruction. If CCR6 is set to 1 before the 5.2 instruction places the MPU in 56#0&$; mode, the value of the CCR3 bit determines the length of the delay before the oscillator restarts and stabilizes when it leaves 56#0&$; mode due to an ext e r n a l i n t e r r u p t r e q u e s t . Wh e n C C R 3 is 0 , t h e Z8S180/Z8L180 waits 217 (131,072) clock cycles. When CCR3 is 1, it waits 64 clock cycles. This state is called 37+%-4'%18'4; mode. The same delay applies to grant- 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG ing the bus to an external Master during 56#0&$; mode, when the $4':6 bit in the CPU Control Register (%%4) is 1. As described previously for 5.''2 and +&.' modes, when the MPU leaves 56#0&$; mode due to 0/+ Low or an enabled +06-+06 Low when the +'(, flag is 1 due to an IE instruction, it starts by performing the interrupt with the return address being that of the instruction following the 5.2 instruction. If the Z8S180/Z8L180 leaves 56#0&$; mode due to an external interrupt request that's enabled in the +0664#2 Control Register, but the +'(, bit is0 due to a &+ instruction, the processor restarts by executing the instruction(s) following the 5.2 instruction. If +06, or +06 or +06 goes inactive before the end of the clock stabilization delay, the Z8S180/Z8L180 stays in 56#0&$; mode. Figure 17 indicates the timing for leaving 56#0&$; mode due to an interrupt request. 0QVG The Z8S180/Z8L180 takes either 64 or 217 (131,072) clocks to restart, depending on the CCR3 bit. 1REQFG(GVEJQT+PVGTTWRV #EMPQYNGFIG%[ENG 56#0&$;/QFG 6 6 6 6 2*+ QT%[ENG&GNC[HTQO+06K#UUGTVGF 0/+ QT +06+06+06 # # (((((* *#.6 / (KIWTG <5<.56#0&$;/QFG'ZKV&WGVQ'ZVGTPCN+PVGTTWRV While the Z8S180/Z8L180 is in 56#0&$; mode, it grants the bus to an external Master if the $4':6 bit (%%4) is 1. Figure 18 indicates the timing of this sequence. The device takes 64 or 217 (131,072) clock cycles to grant the bus de- pending on the CCR3 bit. The latter (not the 37+%-4' %18'4;) case may be prohibitive for many demand-driven external Masters. If so, 37+%-4'%18'4; or +&.' mode can be used. 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 56#0&$;/QFG $WU4GNGCUG/QFG 56#0&$;/QFG 6: 6: 2*+ QT%[ENG&GNC[#HVGT$754'3#UUGTVGF $754'3 $75#%# # (((((* (((((* *#.6 .QY *KIJ / (KIWTG $WU)TCPVKPIVQ'ZVGTPCN/CUVGT&WTKPI56#0&$;/QFG &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 56#0&#4&6'56%10&+6+105 The following standard test conditions apply to DC Characteristics, unless otherwise noted. All voltages are referenced to VSS (0V). Positive current flows into the referenced pin. All AC parameters assume a load capacitance of 100 pF. Add a 10-ns delay for each 50-pF increase in load up to a maximum of 200 pF for the data bus and 100 pF for the address and control lines. AC timing measurements are referenced to VOL MAX or VOL MIN as indicated in Figures 20 through 30 (except for %.1%-, which is referenced to the 10% and 90% points). Ordering Information lists temperature ranges and product numbers. Find package drawings in Package Information. +1. 81.OCZ (TQO RKP 8 1*/KP %. R( +1* (KIWTG #%2CTCOGVGT6GUV%KTEWKV #$51.76'/#:+/7/4#6+0)5 +VGO 5[ODQN 5WRRN[8QNVCIG 8&& +PRWV8QNVCIG 8+0 8CNWG 7PKV 8EE 8 8 1RGTCVKPI6GORGTCVWTG 6124 u% 'ZVGPFGF6GORGTCVWTG 6':6 u% 5VQTCIG6GORGTCVWTG 656) u% 0QVG Permanent damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability. 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG &%%*#4#%6'4+56+%5 <5 6CDNG <5&%%JCTCEVGTKUVKEU 8&&8v8558 5[ODQN +VGO 8+* +PRWV*8QNVCIG 4'5'6':6#.0/+ 8+* +PRWV*8QNVCIG 'ZEGRV4'5'6':6#.0/+ 8+* +PRWV*8QNVCIG %-5%-#%-# 8+. +PRWV.8QNVCIG 4'5'6':6#.0/+ +PRWV.8QNVCIG 'ZEGRV4'5'6':6#.0/+ 1WVRWVU*8QNVCIG #NNQWVRWVU 8+. 81* 81. ++. +6. +&& 1WVRWVU.8QNVCIG #NNQWVRWVU +PRWV.GCMCIG %WTTGPV#NN+PRWVU 'ZEGRV:6#.':6#. 6JTGG5VCVG.GCMCIG %WTTGPV 2QYGT&KUUKRCVKQP 0QTOCN1RGTCVKQP 2QYGT&KUUKRCVKQP 5;56'/5612OQFG %2 2KP%CRCEKVCPEG %QPFKVKQP /KP 6[R /CZ 7PKV 8 8&& 8&& 8&& 8 8 8&& +1* z# +1* z# 8 8 8 8&& +1.O# 8 8+08&& z# 8+08&& z# O# (/*\ (/*\ 8+08H/*\ 6#u% R( 0QVG 8+*OKP8&& 88+.OCZ8 #NNQWVRWVVGTOKPCNUCTGCV01.1#& 8&&8 &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6CDNG <.&%%JCTCEVGTKUVKEU 8&&8v8558 5[ODQN +VGO 8+* +PRWV*8QNVCIG 4'5'6':6#.0/+ 8+* +PRWV*8QNVCIG 'ZEGRV4'5'6':6#.0/+ 8+. +PRWV.8QNVCIG 4'5'6':6#.0/+ +PRWV.8QNVCIG 'ZEGRV4'5'6':6#.0/+ 1WVRWVU*8QNVCIG #NNQWVRWVU 8+. 81* 81. ++. +6. +&& %2 %QPFKVKQP /KP 6[R /CZ 7PKV 8 8&& 8&& 8 8 8&& +1* z# +1* z# 8 8 8&& 8 1WVRWVU.8QNVCIG #NN1WVRWVU +PRWV.GCMCIG %WTTGPV#NN+PRWVU 'ZEGRV:6#.':6#. 6JTGG5VCVG.GCMCIG %WTTGPV 2QYGT&KUUKRCVKQP 0QTOCN1RGTCVKQP +1.O# 8 8+08&& z# 8+08&& z# (/*\ /*\ O# 2QYGT&KUUKRCVKQP 5;56'/5612OQFG (/*\ /*\ 2KP%CRCEKVCPEG 8+08H/*\ 6#u% R( 0QVG 8+*OKP8&& 88+.OCZ8 #NNQWVRWVVGTOKPCNUCTGCV01.1#& 8&&8 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #%%*#4#%6'4+56+%5 <5 6CDNG <5#%%JCTCEVGTKUVKEU 8&&8vQT8&&8v/*\%JCTCEVGTKUVKEU#RRN[1PN[VQ81RGTCVKQP <5 /*\ <5 /*\ 0WODGT 5[ODQN +VGO /KP /CZ /KP /CZ 7PKV V%;% %NQEM%[ENG6KOG &% &% PU V%*9 %NQEM * 2WNUG9KFVJ PU V%.9 %NQEM . 2WNUG9KFVJ PU V%( %NQEM(CNN6KOG PU V%4 %NQEM4KUG6KOG PU V#& 2*+4KUGVQ#FFTGUU8CNKF&GNC[ PU V#5 #FFTGUU8CNKFVQ/4'3(CNNQT+143(CNN V/'& 2*+(CNNVQ/4'3(CNN&GNC[ V4&& 2*+(CNNVQ4&(CNN&GNC[ +1% 2*+4KUGVQ4&4KUG&GNC[ +1% PU PU PU V/& 2*+4KUGVQ/(CNN&GNC[ V#* #FFTGUU*QNF6KOGHTQO /4'3+14'34&94*KIJ V/'& 2*+(CNNVQ/4'34KUG&GNC[ PU V4&& 2*+(CNNVQ4&4KUG&GNC[ PU V/& 2*+4KUGVQ/4KUG&GNC[ PU V&45 &CVC4GCF5GVWR6KOG V&4* &CVC4GCF*QNF6KOG V56& 2*+(CNNVQ56(CNN&GNC[ PU V56& 2*+(CNNVQ564KUG&GNC[ PU V95 9#+65GVWR6KOGVQ2*+(CNN PU V9* 9#+6*QNF6KOGHTQO2*+(CNN PU V9&< 2*+4KUGVQ&CVC(NQCV&GNC[ PU V94& 2*+4KUGVQ94(CNN&GNC[ PU V9&& 2*+(CNNVQ9TKVG&CVC&GNC[6KOG PU V9&5 9TKVG&CVC5GVWR6KOGVQ94(CNN V94& 2*+(CNNVQ944KUG&GNC[ V942 942WNUG9KFVJ /GOQT[9TKVG%[ENG C V9&* 9TKVG&CVC*QNF6KOGHTQO944KUG V+1& 2*+(CNNVQ+143(CNN&GNC[ PU PU PU 942WNUG9KFVJ +19TKVG%[ENG 2*+4KUGVQ+143(CNN&GNC[ PU PU PU PU PU PU +1% +1% PU V+1& 2*+(CNNVQ+1434KUG&GNC[ V+1& /(CNNVQ+143(CNN&GNC[ PU V+065 +065GVWR6KOGVQ2*+(CNN PU &5</2 24'.+/+0#4; PU <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #%%*#4#%6'4+56+%5 <5 %QPVKPWGF 6CDNG <5#%%JCTCEVGTKUVKEU %QPVKPWGF 8&&8vQT8&&8v/*\%JCTCEVGTKUVKEU#RRN[1PN[VQ81RGTCVKQP <5 /*\ <5 /*\ 0WODGT 5[ODQN +VGO /KP V+06* +06*QNF6KOGHTQO2*+(CNN PU V0/+9 0/+2WNUG9KFVJ PU V$45 $754'35GVWR6KOGVQ2*+(CNN PU V$4* $754'3*QNF6KOGHTQO2*+(CNN PU V$#& 2*+4KUGVQ$75#%-(CNN&GNC[ PU V$#& 2*+(CNNVQ$75#%-4KUG&GNC[ PU V$<& 2*+4KUGVQ$WU(NQCVKPI&GNC[6KOG PU V/'9* /4'32WNUG9KFVJ *KIJ PU V/'9. /4'32WNUG9KFVJ .QY PU V4(& 2*+4KUGVQ4(5*(CNN&GNC[ PU V4(& 2*+4KUGVQ4(5*4KUG&GNC[ PU V*#& 2*+4KUGVQ*#.6(CNN&GNC[ PU V*#& 2*+4KUGVQ*#.64KUG&GNC[ PU V&435 &4'35GVWR6KOGVQ2*+4KUG PU V&43* &4'3*QNF6KOGHTQO2*+4KUG PU V6'& 2*+(CNN VQ6'0&K(CNN &GNC[ PU V6'& 2*+(CNNVQ6'0&K4KUG &GNC[ PU V'& 2*+4KUG VQ'4KUG &GNC[ PU V'& 2*+(CNNQT4KUG VQ'(CNN &GNC[ PU 29'* '2WNUG9KFVJ *KIJ PU 29'. '2WNUG9KFVJ .QY PU V'T 'PCDNG4KUG6KOG PU V'H 'PCDNG(CNN6KOG PU V61& 2*+(CNN VQ6KOGT1WVRWV&GNC[ PU V56&+ %5+16TCPUOKV&CVC&GNC[6KOG +PVGTPCN %NQEM1RGTCVKQP VE[E V56&' %5+16TCPUOKV&CVC&GNC[6KOG 'ZVGTPCN %NQEM1RGTCVKQP V%;% V%;% PU V545+ %5+14GEGKXG&CVC5GVWR6KOG +PVGTPCN %NQEM1RGTCVKQP VE[E V54*+ %5+14GEGKXG&CVC*QNF6KOG +PVGTPCN %NQEM1RGTCVKQP VE[E V545' %5+14GEGKXG&CVC5GVWR6KOG 'ZVGTPCN %NQEM1RGTCVKQP VE[E V54*' %5+14GEGKXG&CVC*QNF6KOG 'ZVGTPCN %NQEM1RGTCVKQP VE[E V4'5 4'5'65GVWR6KOGVQ2*+(CNN PU 24'.+/+0#4; /CZ /KP /CZ 7PKV &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6CDNG <5#%%JCTCEVGTKUVKEU %QPVKPWGF 8&&8vQT8&&8v/*\%JCTCEVGTKUVKEU#RRN[1PN[VQ81RGTCVKQP <5 /*\ <5 /*\ 0WODGT 5[ODQN +VGO /KP V4'* 4'5'6*QNF6KOGHTQO2*+(CNN V15% 1UEKNNCVQT5VCDKNK\CVKQP6KOG V':4 /CZ /KP /CZ 7PKV PU PU 'ZVGTPCN%NQEM4KUG6KOG ':6#. PU V':( 'ZVGTPCN%NQEM(CNN6KOG ':6#. PU V44 4'5'64KUG6KOG OU V4( 4'5'6(CNN6KOG OU V+4 +PRWV4KUG6KOG GZEGRV':6#.4'5'6 PU V+( +PRWV(CNN6KOG GZEGRV':6#.4'5'6 PU &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6+/+0)&+#)4#/5 +19TKVG%[ENG +14GCF%[ENG 1REQFG(GVEJ%[ENG 6 2*+ 6 69 6 6 6 69 6 6 #&&4'55 9#+6 /4'3 +143 4& 94 / 56 &CVC+0 &CVC176 4'5'6 0QVG /GOQT[4GCF9TKVG%[ENGVKOKPIKUVJGUCOGCU+1 4GCF9TKVG%[ENGGZEGRVVJGTGCTGPQCWVQOCVKEYCKV UVCVGU 69 CPF/4'3KUCEVKXGKPUVGCFQH+143 (KIWTG %276KOKPI 1REQFG(GVEJ%[ENG/GOQT[4GCF%[ENG /GOQT[9TKVG%[ENG+19TKVG %[ENG +1 4GCF%[ENG 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 2*+ +06 0/+ / +143 &CVC+0 /4'3 4(5* $754'3 $75#% # & /4'34& 94+143 1WVRWV$WHHGT1HH *#.6 (KIWTG %276KOKPI +06#EMPQYNGFIG%[ENG4GHTGUJ%[ENG$754'.'#5'/QFG *#.6/QFG5.''2/QFG5;56'/5612/QFG &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6+/+0)&+#)4#/5 %QPVKPWGF +19TKVG%[ENG +14GCF%[ENG 6 6 6Y 6 6 6 6Y 6 2*+ #&&4'55 +143 4& 94 +14GCF%[ENG %276KOKPI +1% +19TKVG%[ENG (KIWTG %276KOKPI +1% +14GCF%[ENG+19TKVG%[ENG 6 %27QT&/#4GCF9TKVG%[ENG 1PN[&/#9TKVG%[ENGHQT6'0&K 6 69 6 6 2*+ &4'3 NGXGNUGPUG &4'3 GFIGUGPUG %27%[ENG 5VCTVU 6'0&K &/#%[ENG 5VCTVU 56 0QVGU 6&435CPF6&43*CTGURGEKHKGFHQTVJGTKUKPIGFIGQHVJGENQEMHQNNQYGFD[6 6&435CPF6&43*CTGURGEKHKGFHQTVJGTKUKPIGFIGQHVJGENQEM (KIWTG &/#%QPVTQN5KIPCNU 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6 6 69 69 6 2*+ ' /GOQT[4GCF9TKVG ' +14GCF ' +19TKVG & & (KIWTG '%NQEM6KOKPI /GOQT[4GCF9TKVG%[ENG+14GCF9TKVG%[ENG 2*+ ' $754'.'#5'OQFG 5.''2OQFG 5;56'/5612OQFG (KIWTG '%NQEM6KOKPI $754'.'#5'/QFG5.''2/QFG5;56'/5612/QFG 6 2*+ ' 'ZCORNG +14GCF 1REQFG(GVEJ ' +19TKVG 69 6 6 6 (KIWTG '%NQEM6KOKPI /KPKOWO6KOKPI'ZCORNGQH29'.CPF29'* &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6+/+0)&+#)4#/5 %QPVKPWGF 2*+ 6KOGT&CVC 4GI* #6176 (KIWTG 6KOGT1WVRWV6KOKPI 0GZV1REQFG(GVEJ 5.2+PUVTWEVKQP(GVEJ 6 6 65 65 6 6 6 2*+ +06K 0/+ # # /4'3/ 4& *#.6 (KIWTG 5.2'ZGEWVKQP%[ENG 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG %5+1%NQEM 6TCPUOKV&CVC +PVGTPCN%NQEM VE[E VE[E 6TCPUOKV&CVC 'ZVGTPCN%NQEM 4GEGKXG&CVC +PVGTPCN%NQEM VE[E VE[E 4GEGKXG&CVC 'ZVGTPCN%NQEM VE[E VE[E (KIWTG %5+14GEGKXG6TCPUOKV6KOKPI ':6#.8+. 8+* 8+. 8+* +PRWV4KUG6KOGCPF(CNN6KOG 'ZEGRV':6#.4'5'6 'ZVGTPCN%NQEM4KUG6KOG CPF(CNN6KOG (KIWTG 4KUG6KOGCPF(CNN6KOGU &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG %27%10641.4')+56'4 %27%QPVTQN4GIKUVGT %%4 This register controls the basic clock rate, certain aspects of Power-Down modes, and output drive/low-noise options (Figure 31). %27%QPVTQN4GIKUVGT %%4 & & & & & & & & .0#&&#6# 5VCPFCTF&TKXG &TKXGQP # #& & %NQEM&KXKFG :6#. :6#. 56#0&$;+&.''PCDNG 0Q56#0&$; +&.'#HVGT5.''2 56#0&$;#HVGT5.''2 56#0&$;#HVGT5.''2 %[ENG'ZKV 37+%-4'%18'4; .0%27%6. 5VCPFCTF&TKXG &TKXGQP%27 %QPVTQN5KIPCNU .0+1 5VCPFCTF&TKXG &TKXGQP )TQWR+15KIPCNU $4':6 +IPQTG$754'3 QP56#0&$;+&.' 56#0&$;+&.''ZKV QP$754'3 .02*+ 5VCPFCTF&TKXG &TKXGQP 2*+2KP (KIWTG %27%QPVTQN4GIKUVGT %%4 #FFTGUU(* $KVClock Divide Select. If this bit is0, as it is after a 4' 5'6, the Z8S180/Z8L180 divides the frequency on the :6#. pin(s) by two to obtain its Master clock 2*+. If this bit is programmed as1, the part uses the :6#. frequency as 2*+ without division. When D6 and D3 are both 1, setting +15612 (+%4) and executing a 5.2 instruction puts the part into 37+%-4' %18'4; 56#0&$; mode, in which the on-chip oscillator is stopped, and the part allows only 64 clock cycles for the oscillator to stabilize when it restarts. If an external oscillator is used in divide-by-one mode, the minimum pulse width requirement provided in the AC Characteristics must be satisfied. The latter section, *#.6 and .19 219'4 modes, describes the subject more fully. $KVUCPF56#0&$;/+&.' Control. When these bits are both0, a 5.2 instruction makes the Z8S180/Z8L180 enter 5.''2 or 5;56'/ 5612 mode, depending on the +15612 bit (ICR5). When D6 is0 and D3 is1, setting the +15612 bit (ICR5) and executing a 5.2 instruction puts the Z8S180/Z8L180 into +&.' mode in which the on-chip oscillator runs, but its output is blocked from the rest of the part, including 2*+ out. $KV $4':6T h i s b i t c o n t r o l s t h e a b i l i t y o f t h e Z8S180/Z8L180 to honor a bus request during 56#0&$; mode. If this bit is set to 1 and the part is in 56#0&$; mode, a $754'3 is honored after the clock stabilization timer is timed out. $KV.02*+This bit controls the drive capability on the 2*+ Clock output. If this bit is set to 1, the 2*+ Clock output is reduced to 33 percent of its drive capability. When D6 is 1 and D3 is0, setting +15612 (ICR5) and executing a 5.2 instruction puts the part into 56#0&$; mode, in which the on-chip oscillator is stopped and the part allows 217 (128K) clock cycles for the oscillator to stabilize when it restarts. 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG $KV.0+1This bit controls the drive capability of certain external I/O pins of the Z8S180/Z8L180. When this bit is set to 1, the output drive capability of the following pins is reduced to 33 percent of the original drive capability: $KV.0%27%6.This bit controls the drive capability of the CPU Control pins. When this bit is set to 1, the output drive capability of the following pins is reduced to 33 percent of the original drive capability: 465 6Z5 $75#%- 4& %-#6'0& %-#&4'3 94 / 6:# 6:# /4'3 +143 6'0&K %-5 4(5* *#.6 ' 6'56 56 $KV.0#&&#6#This bit controls the drive capability of the Address/Data bus output drivers. If this bit is set to 1, the output drive capability of the Address and Data bus outputs is reduced to 33 percent of its original drive capability. &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #5%+4')+56'4&'5%4+26+10 +PVGTPCN#FFTGUU&CVC$WU +PVGTTWRV4GSWGUV 6:# 4:# 465 %65 &%& #5%+6TCPUOKV&CVC4GIKUVGT %J6&4 #5%+6TCPUOKV&CVC4GIKUVGT %J6&4 #5%+6TCPUOKV5JKHV4GIKUVGT #5%+6TCPUOKV5JKHV4GIKUVGT #5%+4GEGKXG&CVC(+(1 %J4&4 #5%+4GEGKXG&CVC(+(1 %J4&4 #5%+4GEGKXG5JKHV4GIKUVGT %J454 #5%+4GEGKXG5JKHV4GIKUVGT %J454 #5%+%QPVTQN4GIKUVGT# %J%06.# #5%+ %QPVTQN #5%+%QPVTQN4GIKUVGT$ %J%06$ #5%+5VCVWU(+(1 %J #5%+5VCVWU(+(1 %J #5%+5VCVWU4GIKUVGT %J56#6 #5%+5VCVWU4GIKUVGT %J56#6 #5%+'ZVGPUKQP%QPVTQN4GI %J#5':6 #5%+'ZVGPUKQP%QPVTQN4GI %J#5':6 #5%+6KOG%QPUVCPV.QY %J#56%. #5%+6KOG%QPUVCPV.QY %J#56%. #5%+6KOG%QPUVCPV*KIJ %J#56%* #5%+6KOG%QPUVCPV*KIJ %J#56%* %-# 4:# #5%+%QPVTQN4GIKUVGT# %J%06.# #5%+%QPVTQN4GIKUVGT$ %J%06$ %-# 6:# %65 0QVG 0QV2TQITCO #EEGUUKDNG $CWF4CVG )GPGTCVQT 2*+ $CWF4CVG )GPGTCVQT (KIWTG #5%+$NQEM&KCITCO #5%+6TCPUOKV5JKHV4GIKUVGTW h e n t h e A S C I Transmit Shift Register (654) receives data from the ASCI Transmit Data Register (6&4), the data is shifted out to the 6:# pin. When transmission is completed, the next byte (if available) is automatically loaded from 6&4 into 654 and the next transmission starts. If no data is available for trans- mission, 654 idles by outputting a continuous High level. This register is not program-accessible #5%+6TCPUOKV&CVC4GIKUVGT 6&4+1CFFTGUU ** Data written to the ASCI Transmit Data Register is transferred to the 654 as soon as 654 is empty. Data can be written while 654 is shifting out the previous byte of data. Thus, the ASCI transmitter is double buffered. 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG Data can be written into and read from the ASCI Transmit Data Register. If data is read from the ASCI Transmit Data Register, the ASCI data transmit operation is not affected by this 4'#& operation. #5%+4GEGKXG5JKHV4GIKUVGT 454 This register receives data shifted in on the 4:# pin. When full, data is automatically transferred to the ASCI Receive Data Register (4&4) if it is empty. If 454 is not empty when the next incoming data byte is shifted in, an overrun error occurs. This register is not program accessible. #5%+4GEGKXG&CVC(+(1 4&4+1#FFTGUU ** The ASCI Receive Data Register is a read-only register. When a complete incoming data byte is assembled in 454, it is automatically transferred to the 4 character Receive Data First-In First-Out ((+(1) memory. The oldest character in the (+(1 (if any) can be read from the Receive Data Register (4&4). The next incoming data byte can be shifted into 454 while the (+(1 is full. Thus, the ASCI receiver is well buffered. #5%+56#675(+(1 This four-entry (+(1 contains Parity Error, Framing Error, Rx Overrun, and Break status bits associated with each char- acter in the receive data (+(1. The status of the oldest character (if any) can be read from the ASCI status registers. #5%+%*#00'.%10641.4')+56'4# #5%+%QPVTQN4GIKUVGT# %06.#+1#FFTGUU* $KV /2' 4' 6' 465 /2$4 '(4 /1& /1& /1& 49 49 49 49 49 49 49 49 #5%+%QPVTQN4GIKUVGT# %06.#+1#FFTGUU* $KV /2' 4' 6' %-#& /2$4 '(4 /1& /1& /1& 49 49 49 49 49 49 49 49 (KIWTG #5%+%JCPPGN%QPVTQN4GIKUVGT# /2'/WNVK2TQEGUUQT/QFG'PCDNG $KV T h e A S C I features a multiprocessor communication mode that utilizes an extra data bit for selective communication when a number of processors share a common serial bus. Multiprocessor data format is selected when the /2 bit in %06.$ is set to 1. If multiprocessor mode is not selected (/2 bit in %06.$), /2' has no effect. If multiprocessor mode is selected, /2' enables or disables the wake-up feature as follows. If /$' is set to 1, only received bytes in which the multiprocessor bit(/2$ ) can affect the 4&4( and error flags. Effectively, other bytes (with /2$) are ignored by the ASCI. If /2' is reset to0, all bytes, regardless of &5</2 the state of the /2$ data bit, affect the 4'&4 and error flags. /2' is cleared to0 during 4'5'6. 4'4GEGKXGT'PCDNG $KV When 4' is set to 1, the ASCI transmitter is enabled. When 6' is reset to0, the transmitter is disables and any transmit operation in progress is interrupted. However, the 6&4' flag is not reset and the previous contents of 6&4' are held. 6' is cleared to0 in +15612 mode during 4'5'6. 6'6TCPUOKVVGT'PCDNG $KV When 6' is set to 1, the ASCI receiver is enabled. When 6' is reset to0, the transmitter is disabled and any transmit operation in progress is interrupted. However, the 6&4' flag is not reset and the pre- 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #5%+%*#00'.%10641.4')+56'4# %QPVKPWGF vious contents of 6&4' are held. 6' is cleared to 0 in +15612 mode during 4'5'6. 465 4GSWGUV VQ 5GPF %JCPPGN $KV KP %06.# 1PN[ If bit 4 of the System Configuration Register is0, the 465/6:5 pin exhibits the 465 function. 465 allows the ASCI to control (start/stop) another communication devices transmission (for example, by connecting to that device's %65 input). 465 is essentially a 1-bit output port, having no side effects on other ASCI registers or flags. Bit 4 in %06.# is used. %-#&%-#6'0&RKP6'0& /1& 0QRCTKV[ 2CTKV[GPCDNGF /1& UVQRDKV UVQRDKVU The data formats available based on all combinations of /1&, /1&, and /1& are indicated in Table 9. 6CDNG &CVC(QTOCVU %-#& , %-#6'0&RKP%-# /1& /1& /1& &CVC(QTOCV These bits are cleared to0 on reset. /2$4'(4/WNVKRTQEGUUQT$KV4GEGKXG'TTQT(NCI4GUGV $KV When multiprocessor mode is enabled ( /2 in %06.$), /2$4, when read, contains the value of the /2$ bit for the most recent receive operation. When written to0, the '(4 function is selected to reset all error flags (1840, (', 2' and $4- in the #5':6 Register) to 0. /2$4/'(4 is undefined during 4'5'6. /1& #5%+ &CVC (QTOCV /QFG DKVU These bits program the ASCI data format as follows. /1& 5VCTV 5VCTV 5VCTV UVQR 5VCTV UVQR 5VCTV 5VCTV 5VCTV UVQR 5VCTV UVQR DKVFCVC UVQR DKVFCVC UVQR DKVFCVC RCTKV[ DKVFCVC RCTKV[ DKVFCVC UVQR DKVFCVC UVQR DKVFCVC RCTKV[ DKVFCVC RCTKV[ DKVFCVC DKVFCVC 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #5%+%*#00'.%10641.4')+56'4$ #5%+%QPVTQN4GIKUVGT$ %06.$+1#FFTGUU* #5%+%QPVTQN4GIKUVGT$ %06.$+1#FFTGUU* $KV /2$6 /2 %65 25 2'1 &4 55 55 55 49 49 49 49 49 49 49 49 (KIWTG #5%+%JCPPGN%QPVTQN4GIKUVGT$ /2$6/WNVKRTQEGUUQT$KV6TCPUOKV $KV When multiprocessor communication format is selected (/2 bit = ), /2$6 is used to specify the /2$ data bit for transmission. If /2$6 1, then /2$ is transmitted. If /2$6 0, then /2$0 is transmitted. The /2$6 state is undefined during and after 4'5'6. /2/WNVKRTQEGUUQT/QFG $KV When /2 is set to 1, the data format is configured for multiprocessor mode based on /1& (number of data bits) and /1& (number of stop bits) in %06.#. The format is as follows: 5VCTVDKV QTFCVCDKVU /2$DKV QTUVQRDKVU Multiprocessor (/2) format offers no provision for parity. If /2 0, the data format is based on /1&, /1& , /1&, and may include parity. The /2 bit is cleared to0 during 4'5'6. %6525%NGCTVQ5GPF2TGUECNG $KV W h e n r e a d , %6525 reflects the state of the external %65 input. If the %65 input pin is High, %6525 is read as 1. 0QVG When the %65 input pin is High, the 6&4' bit is inhibited (that is, held at ). For channel 1, the %65 input is multiplexed with 4:5 pin (Clocked Serial Receive Data). Thus, %6525 is only valid when read if the channel 1 %65' bit = 1 and the %65 input pin function is selected. The 4'#& data of %6525 is not affected by 4'5'6. If the 55 bits in this register are not , and the $4) mode bit in the #5':6 register is0, then writing to this bit sets the prescale (PS) control. Under those circumstances, a0 indicates a divide-by-10 prescale function while a 1 indicates divide-by-30. The bit resets to 0. &5</2 2'12CTKV['XGP1FF $KV 2'1 selects oven or odd parity. 2'1 does not affect the enabling/disabling of parity (/1& bit of %06.#). If 2'1 is cleared to0, even parity is selected. If 2'1 is set to 1, odd parity is selected. 2'1 is cleared to0 during 4'5'6. &4&KXKFG4CVKQ $KV If the : bit in the #5':6 register is0, this bit specifies the divider used to obtain baud rate from the data sampling clock. If &4 is reset to0, divideby-16 is used, while if &4 is set to 1, divide-by-64 is used. &4 is cleared to0 during 4'5'6. 555QWTEG5RGGF5GNGEV $KVU F i r s t , if these bits are , as they are after a 4'5'6, the %-# pin is used as a clock input, and is divided by 1, 16, or 64 depending on the &4 bit and the : bit in the #5':6 register. If these bits are not and the $4) mode bit is #5':6 is0, then these bits specify a power-of-two divider for the 2*+ clock as indicated in Table 10. Setting or leaving these bits as makes sense for a channel only when its %-# pin is selected for the %-# function. %-#1%-5 offers the %-#1 function when bit 4 of the System Configuration Register is 0. &%&/%-# offers the %-# function when bit0 of the Interrupt Edge register is 1. 6CDNG &KXKFG4CVKQ 55 55 55 &KXKFG4CVKQ / / / / / / / 'ZVGTPCN%NQEM 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #5%+56#6754')+56'4 Each ASCI channel status register (56#6) allows interrogation of ASCI communication, error and modem control signal status, and the enabling or disabling of ASCI interrupts. #5%+5VCVWU4GIKUVGT 56#6+1#FFTGUU* $KV 4&4( 1840 2' (' 4' &%& 6&4' 6+' 4 4 4 4 49 4 49 4 #5%+5VCVWU4GIKUVGT 56#6+1#FFTGUU* $KV 4&4( 1840 2' (' 4' 4 4 4 4 49 %65' 6&4' 49 4 6+' 49 (KIWTG #5%+5VCVWU4GIKUVGTU 4&4(4GEGKXG&CVC4GIKUVGT(WNN $KV 4&4( is set to 1 when an incoming data byte is loaded into an empty 4Z (+(1. If a framing or parity error occurs, 4&4( is still set and the receive data (which generated the error) is still loaded into the (+(1. 4&4( is cleared to0 by reading 4&4 and most recently received character in the (+(1 from +15612 mode, during 4'5'6 and for #5%+ if the &%& input is auto-enabled and is negated (High). 18401XGTTWP'TTQT $KV An overrun condition oc- curs if the receiver finishes assembling a character but the 4Z(+(1 is full so there is no room for the character. However, this status bit is not set until the most recent character received before the overrun becomes the oldest byte in the (+(1. This bit is cleared when software writes a 1 to the '(4 bit in the %06.# register. The bit may also be cleared by 4'5'6 in +15612 mode or #5%+ if the &%& pin is auto enabled and is negated (High). 0QVG When an overrun occurs, the receiver does not place the character in the shift register into the (+(1, nor any subsequent characters, until the most recent good character enters the top of the (+(1 so that 1840 is set. Software then writes a 1 to '(4 to clear it. 2'2CTKV['TTQT $KV A parity error is detected when parity checking is enabled.When the /1& bit in the %06.# register is 1, a character is assembled in which the parity does not match the 2'1 bit in the %06.$ register. However, this status bit is not set until or unless the error character becomes the oldest one in the 4Z (+(1. 2' is cleared when software writes a 1 to the '(4 bit in the %064.# register. 2' is also cleared by 4'5'6 in +15612 mode, or on #5%+, if the &%& pin is auto-enabled and is negated (High). ('(TCOKPI'TTQT $KV A framing error is detected when the stop bit of a character is sampled as 52#%'. However, this status bit is not set until/unless the error character becomes the oldest one in the 4Z(+(1. (' is cleared when software writes a 1 to the '(4 bit in the %06.# register. (' is also cleared by 4'5'6 in +15612 mode, or on #5%+, if the &%& pin is auto-enabled and is negated (High). 4'+4GEGKXG+PVGTTWRV'PCDNG $KV 4+' should be set to 1 to enable ASCI receive interrupt requests. When 4+' is 1, the Receiver requests an interrupt when a character is received and 4&4( is set, but only if neither DMA channel requires its request-routing field to be set to receive data from this ASCI. That is, if 5/ are and 5#4 are , or &+/ is 1 and +#4 are , then ASCI1 does not request an interrupt for 4&4(. If 4+' is 1, either ASCI requests an interrupt when 1840, 2' or (' is set, and 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #5%+ requests an interrupt when &%& goes High. 4+' is cleared to0 by 4'5'6. &%&&CVC%CTTKGT&GVGEV $KV56#6 This bit is set to 1 when the pin is High. It is cleared to0 on the first 4'#& of 56#6 following the pin's transition from High to Low and during 4'5'6. When bit 6 of the #5':6 register is 0 to select auto-enabling, and the pin is negated (High), the receiver is reset and its operation is inhibited. %65'%NGCT6Q5GPF $KV56#6 Channel 1 features an external %65 input, which is multiplexed with the receive data pin 45: for the CSI/O. Setting this bit to 1 selects the %65 function; clearing the bit to0 selects the 4:5 function. 6&4'6TCPUOKV&CVC4GIKUVGT'ORV[ $KV 6 & 4 ' 1 indicates that the 6&4 is empty and the next transmit data byte is written to 6&4. After the byte is written to 6&4, 6&4' is cleared to0 until the ASCI transfers the byte from 6&4 to the 654 and then 6&4' is again set to 1. 6&4' is set to 1 in +15612 mode and during 4'5'6. On ASCI0, if the %65 pin is auto-enabled in the #5':6 register and the pin is High, 6&4' is reset to 0. 6+'6TCPUOKV+PVGTTWRV'PCDNG $KV 6+' should be set to 1 to enable ASCI transmit interrupt requests. If 6+' 1, an interrupt is requested when 6&4' 1. 6+' is cleared to0 during 4'5'6. #5%+64#05/+6&#6#4')+56'45 Register addresses 06H and 07H hold the ASCI transmit data for channel 0 and channel 1, respectively. #5%+6TCPUOKV&CVC4GIKUVGTU%JCPPGN #5%+6TCPUOKV&CVC4GIKUVGTU%JCPPGN /PGOQPKE6&4 #FFTGUU* /PGOQPKE6&4 #FFTGUU* #5%+6TCPUOKV %JCPPGN (KIWTG #5%+4GIKUVGT #5%+6TCPUOKV %JCPPGN (KIWTG #5%+4GIKUVGT &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #5%+4'%'+8'4')+56'4 Register addresses 08H and 09H hold the ASCI receive data for channel 0 and channel 1, respectively. #5%+4GEGKXG4GIKUVGT%JCPPGN #5%+4GEGKXG4GIKUVGT%JCPPGN /PGOQPKE4&4 #FFTGUU* /PGOQPKE4&4 #FFTGUU* #5%+6TCPUOKV&CVC (KIWTG #5%+4GEGKXG4GIKUVGT%JCPPGN #5%+6TCPUOKV&CVC (KIWTG #5%+4GEGKXG4GIKUVGT%JCPPGN %5+1%10641.56#6754')+56'4 The CSI/O Control/Status Register (%064) is used to monitor CSI/O status, enable and disable the CSI/O, enable and $KV disable interrupt generation, and select the data clock speed and source. '( '+' 4' 6' AA 55 55 55 4 49 49 49 49 49 49 (KIWTG %5+1%QPVTQN4GIKUVGT %064+1#FFTGUU#* '('PF(NCI $KV '( is set to 1 by the CSI/O to indicate completion of an 8-bit data transmit or receive operation. If End Interrupt Enable('+') bit = 1 when '( is set to 1, a CPU interrupt request is generated. Program access of 64&4 only occurs if '( 1. The CSI/O clears '( to0 when 64&4 is read or written. '( is cleared to0 during 4'5'6 and +15612 mode. '+''PF+PVGTTWRV'PCDNG $KV '+' is set to 1 to generate a CPU interrupt request. The interrupt request is inhibited if '+' is reset to 0. '+' is cleared to0 during 4'5'6. 4'4GEGKXG'PCDNG $KV A CSI/O receive operation is started by setting 4' to 1. When 4' is set to 1, the data clock is enabled. In internal clock mode, the data clock is output from the %-5 pin. In external clock mode, the clock is input on the %-5 pin. In either case, data is shifted in on the 4:5 pin in synchronization with the (internal or external) data clock. After receiving 8 bits of data, the CSI/O automatically clears 4' to0, '( is set to 1, and an interrupt (if enabled by '+') is generated. 4' and 6' are never both set to 1 at the same time. 4' is cleared to0 during 4'5'6 and +15612 mode. 6'6TCPUOKV'PCDNG $KV A CSI/O transmit operation is started by setting 6' to 1. When 6' is set to 1, the data clock is enabled. When in internal clock mode, the data clock is output from the %-5 pin. In external clock mode, the clock is input on the %-5 pin. In either case, data is shifted out on the 6:5 pin synchronous with the (internal or external) data clock. After transmitting 8 bits of data, the CSI/O automatically clears 6' to0, sets '( to 1, and requests an interrupt if enabled by '+' 1. 6' and 4' are 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG never both set to 1 at the same time. 6' is cleared to0 during 4'5'6 and +15612 mode. 555RGGF5GNGEV $KVU 55 , 55 and 55 select the CSI/O transmit/receive clock source and speed. 55, 55 and 55 are all set to 1 during 4'5'6. 6KOGT&CVC4GIKUVGT%JCPPGN* /PGOQPKE6/&4* #FFTGUU&* Table 11 indicates CSI/O Baud Rate Selection. 6CDNG %5+1$CWF4CVG5GNGEVKQP 6KOGT&CVC 55 55 55 &KXKFG4CVKQ / / / / / / / 'ZVGTPCN%NQEM+PRWV .GUU6JCP/ After 4'5'6, the %-5 pin is configured as an external clock input (555555). Changing these values causes %-5 to become an output pin and the selected clock is output when transmit or receive operations are enabled. 6KOGT4GNQCF4GIKUVGT%JCPPGN.QY /PGOQPKE4.&4. #FFTGUU'* 6KOGT4GNQCF&CVC (KIWTG 6KOGT4GNQCF4GIKUVGT.QY 6KOGT4GNQCF4GIKUVGT%JCPPGN*KIJ %5+16TCPUOKV4GEGKXG&CVC4GIKUVGT /PGOQPKE4.&4* #FFTGUU(* /PGOQPKE64&4 #FFTGUU$* (KIWTG 6KOGT&CVC4GIKUVGT%JCPPGN*KIJ 6KOGT4GNQCF&CVC %5+164&CVC (KIWTG %5+16TCPUOKV4GEGKXG&CVC4GIKUVGT (KIWTG 6KOGT4GNQCF4GIKUVGT%JCPPGN*KIJ 6KOGT&CVC4GIKUVGT%JCPPGN.QY /PGOQPKE6/&4. #FFTGUU%* #5%+4GEGKXG&CVC (KIWTG 6KOGT4GIKUVGT%JCPPGN.QY &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 6+/'4%10641.4')+56'4 The Timer Control Register (6%4) monitors both channels (246246) 6/&4 status. It also controls the enabling $KV and disabling of down-counting and interrupts, and controls the output pin #6176 for 246. 6+( 6+( 6+' 6+' 61% 61% 6&' 6&' 4 4 49 49 49 49 49 49 (KIWTG 6KOGT%QPVTQN4GIKUVGT 6%4+1#FFTGUU* 6+(6KOGT+PVGTTWRV(NCI $KV When 6/&4 decrements to0, 6+( is set to 1. This condition generates an interrupt request if enabled by 6+' 1. 6+( is reset to0 when 6%4 is read and the higher or lower byte of 6/&4 is read. During 4'5'6, 6+( is cleared to 0. 6+(6KOGT+PVGTTWRV(NCI $KV When 6/&4 decrements to0, 6+( is set to 1. This condition generates an interrupt request if enabled by 6+' 1. 6+( is reset to0 when 6%4 is read and the higher or lower byte of 6/&4 is read. During 4'5'6, 6+( is cleared to 0. 6+'6KOGT+PVGTTWRV'PCDNG $KV When 6+' is set to 1, 6+( 1 generates a CPU interrupt request. When 6+' is reset to0, the interrupt request is inhibited. During 4'5'6, 6+' is cleared to 0. 61%6KOGT1WVRWV%QPVTQN $KVU 6 1 % and 61% control the output of 246 using the multiplexed #6176 pin as indicated in Table 12. During 4'5'6, 61% and 61% are cleared to 0. If bit 3 of the +#4$ register is 1, the 6176 function is selected. By programming 61% and 61%, the #6176 pin can be forced High, Low, or toggled when 6/&4 decrements to 0. 6CDNG 6KOGT1WVRWV%QPVTQN 61% 61% 1WVRWV +PJKDKVGF 6QIINGF 6JG#6176RKPKUPQV CHHGEVGFD[VJG246 +HDKVQH+#4$KUVJG #6176RKPKUVQIINGFQT UGV.QYQT*KIJCU KPFKECVGF 6&'6KOGT&QYP%QWPV'PCDNG $KVU 6 & ' and 6&' enable and disable down-counting for 6/&4 and 6/&4, respectively. When 6&'P (P ,) is set to 1, down-counting is stopped and 6/&4P is freely read or written. 6&' and 6&' are cleared to0 during 4'5'6 and 6/&4P does not decrement until 6&'P is set to . 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #5%+':6'05+10%10641.4')+56'4%*#00'.#0&%*#00'. The ASCI Extension Control Registers ( #5':6 and #5':6) control functions that have been added to the $KV #5%+'ZVGPUKQP%QPVTQN4GIKUVGT #5':6+1#FFTGUU* 4GUGTXGF $KV ASCIs in the Z8S180/Z8L180 family. All bits in this register reset to 0. &%& &KUCDNG %65 &KUCDNG : $4) /QFG $TGCM 'PCDNG $TGCM #5%+'ZVGPUKQP%QPVTQN4GIKUVGT #5':6+1#FFTGUU* 4GUGTXGF 4GUGTXGF 4GUGTXGF : $4) /QFG $TGCM 'PCDNG $TGCM 5GPF $TGCM 5GPF $TGCM (KIWTG #5%+'ZVGPUKQP%QPVTQN4GIKUVGTU%JCPPGNUCPF &%&&KUCDNG $KV#5%+1PN[ If this bit is 0, then the &%& pin auto-enables the ASCI0 receiver, such that when the pin is negated/High, the Receiver is held in a 4' 5'6 state. If this bit is 1, the state of the &%&-pin has no effect on receiver operation. In either state of this bit, software can read the state of the &%& pin in the 56#6 register, and the receiver interrupts on a rising edge of &%&. %65&KUCDNG $KV#5%+1PN[ If this bit is0, then the %65 pin auto-enables the #5%+1 transmitter, in that when the pin is negated/High, the 6&4' bit in the 56#6 register is forced to 0. If this bit is 1, the state of the %65 pin has no effect on the transmitter. Regardless of the state of this bit, software can read the state of the %65 pin the %06.$ register. : $KV If this bit is 1, the clock from the Baud Rate Generator or %-# pin is taken as a 1X-bit clock (sometimes called isochronous mode). In this mode, receive data on the 4:# pin must be synchronized to the clock on the %-# pin, regardless of whether %-# is an input or an output. If this bit is0, the clock from the Baud Rate Generator or %-# pin is divided by 16 or 64 per the &4 bit in the %06.$ reg- ister, to obtain the actual bit rate. In this mode, receive data on the 4:# pin is not required to be synchronized to a clock. divides 2*+ by 10 or 30, depending on the 25 bit in %06.$, and factored by a power of two (selected by the 55 bits), to obtain the clock that is presented to the transmitter and receiver and output on the %-# pin. If 55 are not , and this bit is 1, the Baud Rate Generator divides 2*+ by twice the sum of the 16-bit value (programmed into the Time Constant registers) and 2. This mode is identical to the operation of the baud rate generator in the '5%%. $TGCM'PCDNG $KV If this bit is 1, the receiver detects $4'#- conditions and report them in bit 1, and the transmitter sends $4'#-s under the control of bit 0. $TGCM&GVGEV $KV The receiver sets this read-only bit to 1 when an all-zero character with a Framing Error becomes the oldest character in the 4Z(+(1. The bit is cleared when software writes a0 to the '(4 bit in %06.# register, also by 4'5'6, by +15612 mode, and for #5%+, if the &%& pin is auto-enabled and is negated (High). 5GPF$TGCM $KV If this bit and bit 2 are both 1, the transmitter holds the 6:# pin Low to send a $4'#- condition. The duration of the $4'#- is under software control (one of the PRTs or CTCs can be used to time it). This bit resets to0, in which state 6:# carries the serial output of the transmitter. $4)/QFG $KV If the 55 bits in the %06.$ register are not , and this bit is0, the ASCI Baud Rate Generator &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #5%+':6'05+10%10641.4')+56'4%*#00'.#0&%*#00'. %QPVKPWGF 6KOGT&CVC4GIKUVGT%JCPPGN.QY 6KOGT4GNQCF4GIKUVGT%JCPPGN*KIJ /PGOQPKE6/&4. #FFTGUU* /PGOQPKE4.&4* #FFTGUU* 4GNQCF&CVC 6KOGT&CVC (KIWTG 6KOGT&CVC4GIKUVGT.QY (KIWTG 6KOGT4GNQCF4GIKUVGT%JCPPGN*KIJ 6KOGT&CVC4GIKUVGT%JCPPGN*KIJ (TGG4WPPKPI%QWPVGT 4GCF1PN[ /PGOQPKE6/&4* #FFTGUU* /PGOQPKE(4% #FFTGUU* %QWPVKPI&CVC 6KOGT&CVC (KIWTG 6KOGT&CVC4GIKUVGT*KIJ (KIWTG (TGG4WPPKPI%QWPVGT 6KOGT4GNQCF4GIKUVGT%JCPPGN.QY /PGOQPKE4.&4. #FFTGUU 4GNQCF&CVC (KIWTG 6KOGT4GNQCF%JCPPGN.QY 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG #5%+6+/'%1056#064')+56'45 If the 55 bits of the %06.$ register are not , and the $4) mode bit in the #5':6 register is 1, the #5%+ divides the 2*+ clock by two times the registers' 16-bit value, plus two. As a result, the clock is presented to the transmitter and receiver for division by 1, 16, or 64, and is output on the %-# pin. If the 55 bits in an ASCI %06.$ register are not 111, and the $4) mode bit in its Extension Control Register is 1, its new baud rate generator divides 2*+ for serial clocking, as follows: DKVUUGEQPFH2*+ 6% ZUCORNKPITCVG where 6% is the 16-bit value programmed into the ASCI Time Constant High and Low registers. If the ASCI multiplexed %-# pin is selected for the %-# function, it outputs the clock before the final division by the sampling rate, as follows: H%-#QWVH2*+ 6% Find the 6% value for a particular serial bit rate as follows: 6% H2*+ ZDKVUUGEQPFZUCORNKPITCVG #5%+6KOG%QPUVCPV4GIKUVGT.QY #56%.+1#FFTGUU#* #5%+6KOG%QPUVCPV4GIKUVGT.QY #56%.+1#FFTGUU%* $KV .5$KVUQH6KOG%QPUVCPV #5%+6KOG%QPUVCPV4GIKUVGT*KIJ #56%*+1#FFTGUU$* #5%+6KOG%QPUVCPV4GIKUVGT*KIJ #56%*+1#FFTGUU&* $KV /5$KVUQH6KOG%QPUVCPV (KIWTG #5%+6KOG%QPUVCPV4GIKUVGTU &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG %.1%-/7.6+2.+'44')+56'4 </27#FFTGUU'* 4'5'48'& .1901+5'%4;56#. :%.1%-/7.6+2.+'4 (KIWTG %NQEM/WNVKRNKGT4GIKUVGT $KV:%NQEM/WNVKRNKGT/QFGWhen this bit is set to 1, the programmer can double the internal clock speed from the speed of the external clock. This feature only operates effectively with frequencies of 10-16 MHz (20-32 MHz internal). When this bit is set to0, the Z8S180/Z8L180 device operates in normal mode. At power-up, this feature is disabled. $KV.QY0QKUG%T[UVCN1RVKQPSetting this bit to 1 enables the low-noise option for the ':6#. and :6#. pins. This option reduces the gain in addition to reducing the output drive capability to 30% of its original drive capability. The Low Noise Crystal Option is recommended in the use of crystals for PCMCIA applications, where the crystal may be driven too hard by the oscillator. Setting this bit to0 is selected for normal operation of the ':6#. and :6#. pins. The default for this bit is 0. 0QVG Operating restrictions for device operation are listed below. If a low-noise option is required, and normal device operation is required, use the clock multiplier feature. 6CDNG .QY0QKUG1RVKQP .QY0QKUG #&&4'DKV 0QTOCN #&&4'DKV /*\"8u% /*\"8u% /*\"8u% /*\"8u% 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG &/#5174%'#&&4'554')+56'4%*#00'. The DMA Source Address Register Channel 0 specifies the physical source address for channel 0 transfers. The register contains 20 bits and can specify up to 1024 KB memory addresses or up to 64-KB I/O addresses. Channel 0 source can be memory, I/O, or memory mapped I/O. For I/O, bits of this register identify the Request Handshake signal. &/#5QWTEG#FFTGUU4GIKUVGT%JCPPGN$ /PGOQPKE5#4$ #FFTGUU* &/#5QWTEG#FFTGUU4GIKUVGT%JCPPGN.QY /PGOQPKE5#4. #FFTGUU* &/#%JCPPGN#FFTGUU 4GUGTXGF (KIWTG &/#5QWTEG#FFTGUU4GIKUVGT$ &/#%JCPPGN#FFTGUU (KIWTG &/#5QWTEG#FFTGUU4GIKUVGT.QY &/#5QWTEG#FFTGUU4GIKUVGT%JCPPGN *KIJ /PGOQPKE5#4* #FFTGUU* If the source is in I/O space, bits of this register select the DMA request signal for DMA0, as follows: $KV # $KV # &/#6TCPUHGT4GSWGUV &4'3 GZVGTPCN 4&4( #5%+ 4&4( #5%+ 4GUGTXGF &/#%JCPPGN#FFTGUU (KIWTG &/#5QWTEG#FFTGUU4GIKUVGT*KIJ &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG &/#&'56+0#6+10#&&4'554')+56'4%*#00'. The DMA Destination Address Register Channel 0 specifies the physical destination address for channel 0 transfers. The register contains 20 bits and can specify up to 1024-KB memory addresses or up to 64-KB I/O addresses. Channel 0 destination can be memory, I/O, or memory mapped I/O. For I/O, the /5 bits of this register identify the Request Handshake signal for channel 0. &/#&GUVKPCVKQP#FFTGUU4GIKUVGT %JCPPGN $ /PGOQPKE&#4$ #FFTGUU* # # 4GUGTXGF &/#&GUVKPCVKQP#FFTGUU4GIKUVGT%JCPPGN .QY (KIWTG &/#&GUVKPCVKQP#FFTGUU4GIKUVGT%JCPPGN $ /PGOQPKE&#4. #FFTGUU* If the DMA destination is in I/O space, bits of this register select the DMA request signal for DMA0, as follows: (KIWTG &/#&GUVKPCVKQP#FFTGUU4GIKUVGT%JCPPGN .QY &/#&GUVKPCVKQP#FFTGUU4GIKUVGT%JCPPGN *KIJ /PGOQPKE&#4* #FFTGUU* $KV # $KV # &/#6TCPUHGT4GSWGUV &4'3 GZVGTPCN 6&4 #5%+ 6&4 #5%+ 0QV7UGF (KIWTG &/#&GUVKPCVKQP#FFTGUU4GIKUVGT%JCPPGN *KIJ 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG &/#$;6'%17064')+56'4%*#00'. The DMA Byte Count Register Channel 0 specifies the number of bytes to be transferred. This register contains 16 bits and may specify up to 64-KB transfers. When one byte is transferred, the register is decremented by one. If P bytes should be transferred, P must be stored before the DMA operation. &/#$[VG%QWPV4GIKUVGT%JCPPGN*KIJ 0QVG All DMA Count Register channels are undefined during 4'5'6. (KIWTG &/#$[VG%QWPV4GIKUVGT*KIJ &/#$[VG%QWPV4GIKUVGT%JCPPGN.QY /PGOQPKE$%4. #FFTGUU* (KIWTG &/#$[VG%QWPV4GIKUVGT.QY /PGOQPKE$%4* #FFTGUU* &/#$[VG%QWPV4GIKUVGT%JCPPGN.QY /PGOQPKE$%4. #FFTGUU'* (KIWTG &/#$[VG%QWPV4GIKUVGT.QY &/#$[VG%QWPV4GIKUVGT%JCPPGN*KIJ /PGOQPKE$%4* #FFTGUU(* (KIWTG &/#$[VG%QWPV4GIKUVGT*KIJ &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG &/#/'/14;#&&4'554')+56'4%*#00'. The DMA Memory Address Register Channel 1 specifies the physical memory address for channel 1 transfers. The address may be a destination or a source memory location. The register contains 20 bits and may specify up to 1024 KB memory addresses. &/#/GOQT[#FFTGUU4GIKUVGT%JCPPGN* /PGOQPKE/#4* #FFTGUU* &/#/GOQT[#FFTGUU4GIKUVGT%JCPPGN. (KIWTG &/#/GOQT[#FFTGUU4GIKUVGT %JCPPGN* /PGOQPKE/#4. #FFTGUU* &/#/GOQT[#FFTGUU4GIKUVGT%JCPPGN$ (KIWTG &/#/GOQT[#FFTGUU4GIKUVGT %JCPPGN. /PGOQPKE/#4$ #FFTGUU#* # # 4GUGTXGF (KIWTG &/#/GOQT[#FFTGUU4GIKUVGT %JCPPGN$ 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG &/#+1#&&4'554')+56'4 The DMA I/O Address Register specifies the I/O device for channel 1 transfers. This address may be a destination or source I/O device. +#4. and +#4* each contain 8 address bits. The most significant byte identifies the Request Handshake signal and controls the Alternating Channel feature. &/#+1#FFTGUU4GIKUVGT%JCPPGN.QY /PGOQPKE+#4. #FFTGUU$* (KIWTG &/#+1#FFTGUU4GIKUVGT%JCPPGN.QY &/#+1#FFTGUU4GIKUVGT%JCPPGN*KIJ /PGOQPKE+#4* #FFTGUU%* #NV'The #NV' bit should be set only when both DMA channels are programmed for the same I/O source or I/O destination. In this case, a channel end condition (byte count = 0) on channel 0 sets bit 6 (#NV%), which subsequently enables the channel 1 request and blocks the channel 0 request. Similarly, a channel end condition on channel 1 clears bit 6 (#NV%), which then enables the channel 0 request and blocks the channel 1 request. For external requests, the request from the device must be routed or connected to both the &4'3 and &4'3 pins. #NV%If bit (#NV') is0, the #NV% bit has no effect. When bit 7 (#NV') is 1 and the #NV% bit is0, the request signal selected by bits is not presented to channel 1; however, the channel 0 request operates normally. When #NV' is 1 and #NV% is 1, the request selected by 5#4 or &#4 is not presented to channel 0; however, the channel 1 request operates normally. The #NV% bit can be written by software to select which channel should operate first; however, this operation should be executed only when both channels are stopped (both &' and &' are ). 4GS5GNIf bit &+/ in the &%06. register is 1, indicating an I/O source, the following bits select which source handshake signal should control the transfer: (KIWTG &/#+1#FFTGUU4GIKUVGT%JCPPGN*KIJ 1VJGT &/#+1#FFTGUU4GIKUVGT%JCPPGN$ /PGOQPKE+#4$ #FFTGUU&* $KV #NV' #NV% 4GS5GN (KIWTG &/#+1#FFTGUU4GIKUVGT%JCPPGN$ &5</2 &4'3RKP #5%+4&4( #5%+4&4( 4GUGTXGFFQPQVRTQITCO If &+/ is0, indicating an I/O destination, the following bits select which destination handshake signal should control the transfer: 1VJGT 24'.+/+0#4; &4'3RKP #5%+6&4' #5%+6&4' 4GUGTXGFFQPQVRTQITCO <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG &/#56#6754')+56'4 The DMA Status Register (&56#6) is used to enable and disable DMA transfer and DMA termination interrupts. &56#6 also indicates DMA transfer status, Completed or In Progress. &/#5VCVWU4GIKUVGT /PGOQPKE&56#6 #FFTGUU* $KV &' &' &9' &9' &+' &+' &/' 49 49 9 9 49 49 4 (KIWTG &/#5VCVWU4GIKUVGT &56#6+1#FFTGUU* &'&/#'PCDNG%JCPPGN $KV When &' 1 and &/' 1, channel 1 DMA is enabled. When a DMA transfer terminates ($%4), &' is reset to0 by the DMAC. When &'0 and the DMA interrupt is enabled (&+' 1), a DMA interrupt request is made to the CPU. To perform a software 94+6' to &', &9' should be written with a0 during the same register 94+6' access. Writing &' to0 disables channel 1 DMA, but DMA is restartable. Writing &' to 1 enables channel 1 DMA and automatically sets DMA Main Enable (&/') to 1. &' is cleared to0 during 4'5'6. &'&/#'PCDNG%JCPPGN $KV When &' 1 and &/' 1, channel 0 DMA is enabled. When a DMA transfer terminates ($%4), &' is reset to0 by the DMAC. When &'0 and the DMA interrupt is enabled (&+' 1), a DMA interrupt request is made to the CPU. To perform a software 94+6' to &', &9' should be written with0 during the same register 94+6' access. Writing &' to0 disables channel 0 DMA. Writing &' to 1 enables channel 0 DMA and automatically sets DMA Main Enable (&/') to 1. &' is cleared to0 during 4'5'6. &9'&'$KV9TKVG'PCDNG $KV When performing any software 94+6' to &', this bit should be written with 0 during the same access. &9' always reads as . &+'&/#+PVGTTWRV'PCDNG%JCPPGN $KV W h e n &+' is set to 1, the termination channel 1 DMA transfer (indicated when &'0) causes a CPU interrupt request to be generated. When &+'0, the channel 0 DMA termination interrupt is disabled. &+' is cleared to0 during 4'5'6. &+'&/#+PVGTTWRV'PCDNG%JCPPGN $KV W h e n &+' is set to 1, the termination channel 0 of DMA transfer (indicated when &') causes a CPU interrupt request to be generated. When &+'0, the channel 0 DMA termination interrupt is disabled. &+' is cleared to0 during 4'5'6. &/'&/#/CKP'PCDNG $KV A DMA operation is only enabled when its &' bit (&' for channel0, &' for channel 1) and the &/'bit is set to . When 0/+ occurs, &/' is reset to0, thus disabling DMA activity during the 0/+ interrupt service routine. To restart DMA, &' and/or &' should be written with a 1 (even if the contents are already ). This condition automatically sets &/' to 1, allowing DMA operations to continue. 0QVG &/' cannot be directly written. The bit is cleared to 0 by 0/+ or indirectly set to 1 by setting &' and/or &' to 1. &/' is cleared to 0 during 4'5'6. &9'&'$KV9TKVG'PCDNG $KV When performing any software 94+6' to &', this bit should be written with 0 during the same access. &9' always reads as . 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG &/#/1&'4')+56'4 The DMA Mode Register (&/1&') is used to set the addressing and transfer mode for channel 0. &/#/QFG4GIKUVGT /PGOQPKE&/1&' #FFTGUU* $KV &/ &/ 5/ 5/ //1& 49 49 49 49 49 (KIWTG &/#/QFG4GIKUVGT &/1&'+1#FFTGUU* &/&/&GUVKPCVKQP/QFG%JCPPGN $KVU This mode specifies whether the destination for channel 0 transfers is memory or I/O, and whether the address should be incremented or decremented for each byte transferred. &/ and &/ are cleared to0 during 4'5'6. 5/5/5QWTEG/QFG%JCPPGN $KVU T h i s mode specifies whether the source for channel 0 transfers is memory or I/O, and whether the address should be incremented or decremented for each byte transferred. 6CDNG %JCPPGN5QWTEG 6CDNG %JCPPGN&GUVKPCVKQP &/ &/ /GOQT[+1 /GOQT[ +PETGOGPV&GETGOGPV /GOQT[ /GOQT[ /GOQT[ +1 HKZGF HKZGF &5</2 5/ 5/ /GOQT[+1 /GOQT[ +PETGOGPV&GETGOGPV /GOQT[ /GOQT[ /GOQT[ +1 HKZGF HKZGF 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG Table 16 indicates all DMA transfer mode combinations of &/, &/, 5/, and 5/. Because I/O to/from I/O transfers are not implemented, 12 combinations are available. 6CDNG 6TCPUHGT/QFG%QODKPCVKQPU &/ &/ 5/ 0QVG* Includes memory mapped I/O. 5/ 6TCPUHGT/QFG #FFTGUU+PETGOGPV&GETGOGPV /GOQT[/GOQT[ /GOQT[/GOQT[ /GOQT[ /GOQT[ +1/GOQT[ /GOQT[/GOQT[ /GOQT[/GOQT[ /GOQT[ /GOQT[ +1/GOQT[ /GOQT[/GOQT[ /GOQT[/GOQT[ 4GUGTXGF 4GUGTXGF /GOQT[+1 /GOQT[+1 4GUGTXGF 4GUGTXGF 5#4 &#4 5#4 &#4 5#4HKZGF&#4 5#4HKZGF&#4 5#4 &#4 5#4 &#4 5#4HKZGF&#4 5#4HKZGF&#4 5#4 &#4HKZGF 5#4 &#4HKZGF //1&/GOQT[/QFG%JCPPGN $KV When chan- nel 0 is configured for memory to/from memory transfers there is no Request Handshake signal to control the transfer timing. Instead, two automatic transfer timing modes are selectable: burst (//1&) and cycle steal (//1&). For burst memory to/from memory transfers, the DMAC takes control of the bus continuously until the DMA transfer 5#4 &#4HKZGF 5#4 &#4HKZGF completes (as indicated by the byte count register = ). In cycle steal mode, the CPU is provided a cycle for each DMA byte transfer cycle until the transfer is completed. For channel 0 DMA with I/O source or destination, the selected Request signal times the transfer ignoring //1&. //1& is cleared to0 during 4'5'6. 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG &/#9#+6%10641.4')+56'4 The DMA/WAIT Control Register (&%06.) controls the insertion of wait states into DMAC (and CPU) accesses of memory or I/O. Also, the register defines the Request signal for each channel as level or edge sense. &%06. also sets the DMA transfer mode for channel 1, which is limited to memory to/from I/O transfers. /9+ /9+ +9+ +9+ &/5 &/5 &+/ &+/ 49 49 49 49 49 49 49 49 $KV (KIWTG &/#9#+6%QPVTQN4GIKUVGT &%06.+1#FFTGUU* /9+/9+/GOQT[9CKV+PUGTVKQP $KVU T h i s bit specifies the number of wait states introduced into CPU or DMAC memory access cycles. /9+ and /9+ are set to 1 during 4'5'6. /9+ /9+ 9CKV5VCVG +9++9++19CKV+PUGTVKQP $KVU This bit specifies the number of wait states introduced into CPU or DMAC I/O access cycles. +9+ and +9+ are set to 1 during 4'5'6. +9+ +9+ 9CKV5VCVG 0QVG These wait states are added to the 3-clock I/O cycle that is used to access the on-chip I/O registers. It is equally valid to regard these as 0 to 3 wait states added to a 4clock external I/O cycle. &/5&/5&/#4GSWGUV5GPUG $KVU & / 5 and &/5 specify the DMA request sense for channel 0 and channel 1 respectively. When reset to0, the input is level sense. When set to 1, the input is edge sense. &/5 and &/5 are cleared to0 during 4'5'6. &5</2 &/5K 5GPUG 'FIG5GPUG .GXGN5GPUG Typically, for an input/source device, the associated &/5 bit should be programmed as0 for level sense. The device takes a relatively long time to update its Request signal after the DMA channel reads data (in the first of the two machine cycles involved in transferring a byte). An output/destination device takes much less time to update its Request signal after the DMA channel starts a 94+6' operation to it (the second machine cycle of the two cycles involved in transferring a byte). With zero-wait state I/O cycles, a device cannot update its request signal in the required time, so edge sensing must be used. A one-wait-state I/O cycle also does not provide sufficient time for updating, so edge sensing is again required. &+/ &+/ &/# %JCPPGN +1 CPF /GOQT[ /QFG $KVU Specifies the source/destination and address modifier for channel 1 memory to/from I/O transfer modes. &+/ and &+/ are cleared to0 during 4'5'6. 6CDNG %JCPPGN6TCPUHGT/QFG &+/ &/+ 6TCPUHGT/QFG 24'.+/+0#4; /GOQT[+1 /GOQT[+1 +1/GOQT[ +1/GOQT[ #FFTGUU +PETGOGPV&GETGOGPV /#4 +#4HKZGF /#4 +#4HKZGF +#4HKZGF/#4 +#4HKZGF/#4 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG +06'447268'%614.194')+56'4 Bits of the Interrupt Vector Low Register (+.) are used as bits of the synthesized interrupt vector during interrupts for the +06 and +06 pins and for the DMAs, ASCIs, PRTs, and CSI/O. These three bits are cleared to 0 during 4'5'6 (Figure 74). +PVGTTWRV8GEVQT.QY4GIKUVGT /PGOQPKE+. #FFTGUU* +. +. +. 49 49 49 $KV 2TQITCOOCDNG +PVGTTWRV5QWTEG&GRGPFGPV%QFG (KIWTG +PVGTTWRV8GEVQT.QY4GIKUVGT +.+1#FFTGUU* +0664#2%10641.4')+56'4 This register is used in handling 64#2 interrupts and to enable or disable Maskable Interrupt Level and the +06 and +06 pins. +0664#2%QPVTQN4GIKUVGT /PGOQPKEU+6% #FFTGUU* $KV 64#2 7(1 49 4 +6' +6' +6' 49 49 49 64#2 $KV This bit is set to 1 when an undefined opcode is fetched. 64#2 can be reset under program control by writing it with a ; however, 64#2 cannot be written with 1 under program control. 64#2 is reset to0 during 4'5'6. 7(17PFGHKPGF(GVEJ1DLGEV $KV When a 64#2 interrupt occurs, the contents of 7(1 allow the starting ad- dress of the undefined instruction to be determined. This interrupt is necessary because the 64#2 may occur on either the second or third byte of the opcode. 7(1 allows the stacked PC value to be correctly adjusted. If 7(10, the first opcode should be interpreted as the stacked 2%. If 7(1 1, the first opcode address is stacked 2%. 7(1 is Read-Only. +6'+PVGTTWRV'PCDNG $KVU + 6 ' and +6' enable and disable the external interrupt inputs +06 and +06, respectively. +6' enables and disables in- terrupts from: '5%% * Bidirectional Centronics controller %6%U * External interrupt input +06 A 1 in a bit enables the corresponding interrupt level while a0 disables it. A 4'5'6 sets +6' to 1 and clears +6' and +6' to 0. 64#2+PVGTTWRVThe Z8S180/Z8L180 generates a 64#2 sequence when an undefined opcode fetch occurs. This feature can be used to increase software reliability, implement an extended instruction set, or both. 64#2 may occur during opcode fetch cycles and also if an undefined opcode is fetched during the interrupt acknowledge cycle for +06 when Modeis used. When a 64#2 sequence occurs, the Z8S180/Z8L180: 1. Sets the 64#2 bit in the Interrupt 64#2/Control (+6%) register to 1. 2. Saves the current Program Counter (PC) value, reflecting the location of the undefined opcode, on the stack. 3. Resumes execution at logical address 0. 0QVG If logical address 0000H is mapped to physical address 00000H, the vector is the same as for 4'5'6. In this case, testing the 64#2 bit in +6% reveals whether the restart at physical address 00000H was caused by 4'5'6 or 64#2. 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG All 64#2U occur after fetching an undefined second opcode byte following one of the prefix opcodes (CBH, DDH, EDH, or FDH) or after fetching an undefined third opcode byte following one of the double-prefix opcodes (DDCBH or FDCBH). The state of the Undefined Fetch Object (7(1) bit in +6% allows 64#2 software to correctly adjust the stacked PC, depending on whether the second or third byte of the opcode generated the 64#2. If 7(10, the starting address of the invalid instruction is the stacked 2% . If 7(1 1, the starting address of the invalid instruction is equal to the stacked 2% . 4GUVCTV HTQO* PF1REQFG (GVEJ%[ENG 2*+ 6 6 6 # # # 1REQFG (GVEJ%[ENG 2%5VCEMKPI 662 6K 6K 6K 6K 6K 6 2% & & 6 6 6 6 6 52 52 2%* 2%. 6 6 6 * 7PFGHKPGF 1REQFG / /4'3 4& 94 (KIWTG 64#26KOKPI &5</2 PF1REQFG7PFGHKPGF 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 4GUVCTV (TQO* TF1REQFG (GVEJ%[ENG 2*+ # # # & & 6 6 6 2% /GOQT[ 4GCF%[ENG 6 6 662 6 +: F+; 1REQFG (GVEJ%[ENG 2%5VCEMKPI 6K 6K 6K 6K F 6 6 6 52 2%* 6 6 6 6 6 6 * 52 2%. 7PFGHKPGF 1REQFG / /4'3 4& 94 (KIWTG 64#26KOKPI TF1REQFG7PFGHKPGF 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 4'(4'5*%10641.4')+56'4 /PGOQPKE4%4 #FFTGUU* 4'('4GHTGUJ'PCDNG $KV 4'('0 disables the refresh controller, while 4'(' 1 enables refresh cycle insertion. 4'(' is set to 1 during 4'5'6. 4'(' %[E 4'(9 %[E 4GUGTXGF (KIWTG 4GHTGUJ%QPVTQN4GIKUVGT 4%4+1#FFTGUU* The Refresh Control Register(4%4) specifies the interval and length of refresh cycles, while enabling or disabling the refresh function. 4'(94GHTGUJ9CKV $KV 4'(9 0 causes the refresh cycle to be two clocks in duration. 4'(9 1 causes the refresh cycle to be three clocks in duration by adding a refresh wait cycle (649). 4'(9 is set to 1 during 4'5'6. %;%%[ENG+PVGTXCN $KV % ; % a n d % ; % specify the interval (in clock cycles) between refresh cycles. When dynamic RAM requires 128 refresh cycles every 2 ms (or 256 cycles in every 4 ms), the required refresh interval is less than or equal to 15.625 s. Thus, the underlined values indicate the best refresh interval depending on CPU clock frequency. %;% and %;% are cleared to0 during 4'5'6 (see Table 18). 6CDNG &4#/4GHTGUJ+PVGTXCNU 6KOG+PVGTXCN %;% %;% +PUGTVKQP+PVGTXCN 2*+/*\ 0QVG*calculated interval. UVCVGU UVCVGU UVCVGU UVCVGU zU zU zU zU 4GHTGUJ%QPVTQNCPF4GUGVAfter 4'5'6 , based on the initialized value of 4%4, refresh cycles occur with an interval of 10 clock cycles and be 3 clock cycles in duration. &[PCOKE4#/4GHTGUJ1RGTCVKQP 1. Refresh Cycle insertion is stopped when the CPU is in the following states: a. During 4'5'6 b. When the bus is released in response to $754'3 c. During 5.''2 mode d. During 9#+6 states 2. Refresh cycles are suppressed when the bus is released in response to $754'3. However, the refresh timer continues to operate. The time at which the first refresh cycle occurs after the Z8S180/Z8L180 reacquires the bus depends on the refresh timer. This cycle offers no timing relationship with the bus exchange. &5</2 /*\ /*\ /*\ /*\ zU zU zU zU zU zU zU zU zU zU zU zU zU zU zU zU 3. Refresh cycles are suppressed during 5.''2 mode. If a refresh cycle is requested during 5.''2 mode, the refresh cycle request is internally latched (until replaced with the next refresh request). The latched refresh cycle is inserted at the end of the first machine cycle after 5.''2 mode is exited. After this initial cycle, the time at which the next refresh cycle occurs depends on the refresh time and offers no relationship with the exit from 5.''2 mode. 4. The refresh address is incremented by one for each successful refresh cycle, not for each refresh. Thus, independent of the number of missed refresh requests, each refresh bus cycle uses a refresh address incremented by one from that of the previous refresh bus cycles. 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG //7%1//10$#5'4')+56'4 The Common Base Register (%$4) specifies the base address (on 4-KB boundaries) used to generate a 20-bit phys- ical address for Common Area 1 accesses. All bits of %$4 are reset to0 during 4'5'6. //7%QOOQP$CUG4GIKUVGT /PGOQPKE%$4 #FFTGUU* $KV %$ %$ %$ %$ %$ %$ %$ %$ 49 49 49 49 49 49 49 49 (KIWTG //7%QOOQP$CUG4GIKUVGT %$4+1#FFTGUU* //7$#0-$#5'4')+56'4 The Bank Base Register ($$4) specifies the base address (on 4-KB boundaries) used to generate a 20-bit physical ad- dress for Bank Area accesses. All bits of $$4 are reset to 0 during 4'5'6. //7$CPM$CUG4GIKUVGT /PGOQPKE$$4 #FFTGUU* $KV $$ $$ $$ $$ $$ $$ $$ $$ 49 49 49 49 49 49 49 49 (KIWTG //7$CPM$CUG4GIKUVGT $$4+1#FFTGUU* //7%1//10$#0-#4'#4')+56'4 The Common/Bank Area Register (%$#4) specifies boundaries within the Z8S180/Z8L180 64-KB logical address space for up to three areas; Common Area), Bank Area and Common Area 1. //7%QOOQP$CPM#TGC4GIKUVGT /PGOQPKE%$#4 #FFTGUU#* $KV %# %# %# %# $# $# $# $# 49 49 49 49 49 49 49 49 (KIWTG //7%QOOQP$CPM#TGC4GIKUVGT %$#4+1#FFTGUU#* 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG %# %#%# $KVU %# specifies the start (Low) address (on 4-KB boundaries) for Common Area 1. This condition also determines the most recent address of the Bank Area. All bits of %# are set to 1 during 4'5'6. $# $# $KVU $# specifies the start (Low) address (on 4-KB boundaries) for the Bank Area. This condition also determines the most recent address of Common Area 0. All bits of $# are set to 1 during 4'5'6. 12'4#6+10/1&'%10641.4')+56'4 The Z8S180/Z8L180 is descended from two different ancestor processors, ZiLOG's original Z80 and the Hitachi 64180. The Operating Mode Control Register (1/%4) can be programmed to select between certain differences between the Z80 and the 64180. /' /'PCDNG This bit controls the / output and is set to a 1 during reset. 1RGTCVKQP/QFG%QPVTQN4GIKUVGT On the Z8S180/Z8L180, this choice makes the processor fetch one 4'6+ instruction. When fetching a 4'6+ from zerowait-state memory, the processor uses three clock machine cycles that are not fully Z80-timing-compatible. /PGOQPKE1/%4 #FFTGUU'* When /' 1, the / output is asserted Low during the opcode fetch cycle, the +06 acknowledge cycle, and the first machine cycle of the 0/+ acknowledge. When /'0, the processor does not drive / Low during instruction fetch cycles. After fetching one 4'6+ instruction with normal timing, the processor returns and refetches the instruction using Z80-compatible cycles that drive / Low. This timing compatibility may be required by external Z80 peripherals to properly decode the 4'6+ instruction. & & & 4GUGTXGF +1% 49 /6' 9 /' 49 (KIWTG 1RGTCVKPI%QPVTQN4GIKUVGT 1/%4+1#FFTGUU'* T1 T2 T3 T1 T2 T3 TI TI TI T1 T2 T3 TI T1 T2 T3 TI 2*+ A0-A18 (A19) PC+1 PC EDH 4DH PC EDH PC+1 4DH D0-D7 M1 MREQ RD ST (KIWTG 4'6++PUVTWEVKQP5GSWGPEGYKVJ/' &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG +1%10641.4')+56'4 The I/O Control Register (+%4) allows relocation of the internal I/O addresses. +%4 also controls the enabling and disabling of +15612 mode (Figure 83). $KV +1# +1# +1562 49 49 49 (KIWTG +1%QPVTQN4GIKUVGT +%4+1#FFTGUU(* +1#+1#FFTGUU4GNQECVKQP $KVU + 1 # a n d +1# relocate internal I/O as indicated in Figure 84. 0QVG The high-order 8 bits of 16-bit internal I/O address are always 0. +1# and +1# are cleared to0during 4'5'6. ((* +1# +1# %* $(* +1# +1# * (* +1# +1# * (* +1# +1# * (KIWTG +1#FFTGUU4GNQECVKQP +1562+15612/QFG $KV +15612 mode is enabled when +1562 is set to 1. Normal I/O operation resumes when +1562 is reprogrammed or 4'5'6 to 0. 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 2#%-#)'+0(14/#6+10 (KIWTG 2KP&+22CEMCIG&KCITCO (KIWTG 2KP3(22CEMCIG&KCITCO &5</2 24'.+/+0#4; <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG (KIWTG 2KP2.%%2CEMCIG&KCITCO 24'.+/+0#4; &5</2 <5<. 'PJCPEGF</KETQRTQEGUUQT ZiLOG 14&'4+0)+0(14/#6+10 %QFGU 5RGGF 2CEMCIG 6GORGTCVWTG 'PXKTQPOGPVCN 'ZCORNG <5 2 5 % /*\ /*\ /*\ 22KP2NCUVKE&+2 82KP2.%% (2KP3(2 5u%VQ u% ' u%VQ u% %2NCUVKE5VCPFCTF For fast results, contact your local ZiLOG sales office for assistance in ordering the part(s) required. KUC<5/*\2KP&+2VQ %2NCUVKE5VCPFCTF(NQY 'PXKTQPOGPVCN(NQY 6GORGTCVWTG 2CEMCIG 5RGGF 2TQFWEV0WODGT <K.1)2TGHKZ 2TG%JCTCEVGTK\CVKQP2TQFWEV The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or non-conformance (c)2000 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. &5</2 with some aspects of the document may be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. ZiLOG, Inc. 910 East Hamilton Avenue, Suite 110 Campbell, CA 95008 Telephone (408) 558-8500 FAX (408) 558-8300 Internet: http://www.zilog.com 24'.+/+0#4;