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Code Compatible with ZiLOG Z80® CPU
Extended Instructions
Two Chain-Linked DMA Channels
Low Power-Down Modes
On-Chip Interrupt Controllers
Three On-Chip W ait-Sta te Generators
On-Chip Oscillator/Generator
Expanded MMU Addressing (Up to 1 MB)
Clocked Serial I/O Port
Two 16-Bit Counter /Ti me rs
Two Enhanced UARTs (up to 512 Kbps)
Clock Speeds: 10, 20, 33 MHz
Operating Range: 5V (3.3V@ 20 MHz)
Operating Temperature Range: 0°C to +70°C
–40°C to +85°C Extended Temperature Range
Three Packaging Styles
– 68-Pin PLCC
–64-Pin DIP
–80-Pin QFP
)'0'4#.&'5%4+26+10
The enhanced Z8S180/Z8L180™ significantly improves on
previous Z80180 models, while still providing full back-
ward compatibility with existing ZiLOG Z80 devices. The
Z8S180/Z8L180 now offers faster execution speeds, pow-
er-saving modes, and EMI noise reduction.
This enhanced Z180™ design also incorporates additional
feature enhancements to the ASCIs, DMAs, and 56#0&$;
mode power consumpti on. With t he additi on of ESCC-l ike
Baud Rate Generators (BRGs), the two ASCIs offer the flex-
ibility and capability to transfer data asynchronously at rates
of up to 512 Kbps. In addition, the ASCI receiver features
a 4-byte first in/first out (FIFO) buffer which reduces the
likelihood of overrun errors. The DMAs have been modified
to allow for chain-linking of the two DMA channels when
set to take their DMA requests from the same peripherals
device. This feature allows for nonstop DMA operation be-
tween the two DMA channels.
Not only does the Z8S180/Z8L180 consume less power dur-
ing normal operations than the previous model, it offers
three modes intended to further reduce power consumption.
Power consumpt ion during 56#0&$; Mode is reduc ed t o
10 µA by stopping the external oscillators and internal
clock. The 5.''2 mode reduces power by placing th e CPU
into a stopped state, consuming less current while the on-
chip I/O devices still operate. The 5;56'/5612 mode
places both the CPU and the on-chip peripherals into a
stopped mode, reducing power consumption even further.
A new clock-doubler feature in the Z8S180/Z8L180 allows
the internal clock speed to be twice the external clock speed.
As a result, system cost is reduced by allowing the use of
lower-cost, lower-frequency crystals.
The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC,
and 64-pin DIP packages.
0QVG All Signals with an overline are active Low. For exam-
ple: B/W, in which WORD is active Low; or B/W, in
which BYTE is active Low.
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Power connections follow the conventional descriptions be-
low: %QPPGEVKQP %KTEWKV &GXKEG
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&5</2 24'.+/+0#4;
2+0&'5%4+26+105
# #
Address Bus (Output, 3-state). # # form a
20-bit address bus. The Address Bus provides the address
for memory dat a bus exc hanges ( up to 1 MB) and I/O dat a
bus exchanges (up to 64 KB). The address bus enters a
high–impedance state during reset and external bus ac-
knowledge cycles. Address line # is multiplexed with the
output of PRT channel 1 (6
176
, selected as ad dress ou tpu t
on reset ), and addres s line # is not avail able in DIP ver -
sions of the Z8S180.
$75#%-. Bus Acknowledge (Output, active Low).
$75#%- indicates that the requesting device, the MPU ad-
dress and data bus, and some control signals enter their high-
impedance state.
$754'3Bus Request (Input, active Low). This input is
used by external devices (such as DMA controllers) to re-
quest access to the system bus. This request demands a high-
er p riori ty than 0/+ and is al ways r eco gnized at th e end o f
the curr ent mach ine cycl e. This signal stops t he CPU from
executing further instructions, places addresses, data buses,
and other control signals into the high-impedance state.
%-#%-#Asyn chronous Clock 0 a nd 1 (bidirection-
al). When in output mode, these pins are the transmit and
receiv e clock outputs f ro m the ASCI b aud r at e generators.
When i n inpu t mode, these pins serve as the exter nal c lock
inputs for the ASCI baud rate generators. %-# is mu lti-
plexed with &4'3, and %-# is multiplexed with 6'0&.
%-5Serial Cloc k (bidirection al). This line is the clock for
the CSI/O channel.
%65 %65. Clear to sen d 0 an d 1 (Inputs, act ive Low).
These lines are modem control signals for the ASCI chan-
nels. %65 is multip lexed wit h 4:5.
& &Data Bus = (bidirectional, 3-state). & & con-
stitute an 8-bit bidirectional data bus, used for the transfer
of information to and from I/O and memory devices. The
data bus enters the high-impedance state during reset and
external bus acknowledge cycles.
&%&. Data Carrier Detect 0 (Input, active Low); a pro-
grammable modem control signal for ASCI channel 0.
&4'3&4'3. DMA Request 0 and 1 (Input, active
Low). &4'3 is used to request a DMA transfer from one
of the on-chip DMA channels. The DMA channels monitor
these inputs to determine when an external device is ready
for a 4'#& or 94+6' operation. These inputs can be pro-
grammed to be eithe r level or edg e sens ed. &4'3 is mul -
tiplexed with %-#.
'Enable Clock (Ou tput). This pin functions as a sync hro-
nous, machine-cycle clock output during bus transactions.
':6#.External Clock Crystal (Input). Crystal oscillator
connections. An external clock can be input to the
Z8S180/Z8L180 on this pin when a crystal is not used. This
input is Schmitt triggered.
*#.6. *#.6/5.''2 (Output, active Low). This output is
assert ed af ter the CPU executes eit her the *#.6 or 5.''2
instruction and is waiting for either a nonmaskable or a
maska ble inte rrupt before o peratio n can res ume. I t is also
used with the / and 56 signals to d ecode the status of the
CPU machine cycle.
+06. Maskable Interrupt Request 0 (Input, active Low).
This signa l i s gen erated by external I/ O devi ces . The CPU
honors these requests at the end of the current instruction
cycle as l ong as the 0/+ and $754'3 signal s are inact ive.
The CPU acknowledges this interrupt request with an in-
terrup t ackn owledge cy cle. During thi s cycle , both th e /
and +143 signals become active.
+06+06. Maskable Interrupt Request 1 and 2 (Inputs,
active Low). This signal is generated by external I/O de-
vices. The CPU honor s these reques ts at the end of the cur -
rent instruction cycle as long as the 0/+, $754'3, and +06
signals are inactive. The CPU acknowledges these requests
with an interrupt acknowledge cycle. Unlike the acknowl-
edgment fo r +06, ne ither th e / or +143 signals bec ome
active during this cycle.
+143. I/O Request (Out put, acti ve Low, 3-sta te). +143 in -
dicate s that th e address bu s contains a valid I/O ad dress fo r
an +14'#& or +1 94+6' operation. +143 is also gener-
ated, along with /, during the acknowledgment of the
+06 input signal to indicate that an interrupt response vec-
tor ca n be p lace onto t he da ta bus. Th is s ignal is a nalogou s
to the +1' signal of the Z64180.
/. Machine Cycle 1 ( Output, active Low) . Together with
/4'3, / indicates that the current cycle is the opcode-
fetch cycle of instruction execution. Together with +143,
/ indicates that the current cycle is for interrupt acknowl-
edgment. It is also used wi th the *#.6 and 56 signal to de-
code the status of the CPU machine cycle. This signal is
analogous to the .+4 signal of the Z64180.
/4'3. Memory Request (Output, active Low, 3-state).
/4'3 indicates that the address bus holds a valid address
for a memory 4'#& or memory 94+6' operation. This sig-
nal is analogous to the /' signal of Z64180.
0/+. Nonmaskable Interrupt (Input, negative edge trig-
gered). 0/+ demands a higher priority than +06 and is al-
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
2+0&'5%4+26+105%QPVKPWGF
ways recognized at the end of an ins tr uct i on, regardless of
the state of the interrupt-enable flip-flops. This signal forces
CPU execution to continue at location 0066H.
2*+System Clock (O utput). The outp ut is used as a refer-
ence clock for the MPU and the external system. The fre-
quency of this output may be one-half, equal to, or twice
the crystal or input clock frequency.
4&Read (Output, active Low, 3-state). 4& indicates that
the C PU wan ts t o re ad d at a fr om ei th er me mo ry o r a n I/ O
device. The addressed I/O or memory device should use this
signal to gate data onto the CPU data bus.
4(5* Refresh (Output, active Low). Together with /4'3,
4(5* indicates that the current CPU machine cycle and the
contents of the address bus should be used for refresh of dy-
namic memories. The low-order 8 bits of the address bus
(# #) contain the refresh address. This signal is analogous
to the REF signal of the Z64180.
465 Request to Send 0 (Output, active Low); a program-
mable MODEM control signal for ASCI channel 0.
4:#4:#Receive Data 0 and 1 (Input). These signals
are the receive data for the ASCI channels.
4:5Clock ed Ser ial Re ceive Data ( Input) . This line is t he
receive data for the CSI/O channel. RXS is multiplexed with
the %65 signal for ASCI channel 1.
56Status (Output). This signal is used with the / and
*#.6 output to decode the status of the CPU machine cycle.
See Table 3.
6'0&6'0& Transfer End 0 and 1 (Outputs, active
Low). This ou tput is a sserted a ctive during the most recent
94+6' cycle of a DMA opera tion. It is use d to indica te the
end of the block transfer. 6'0& is multiplexed with %-#.
6'56Test (Output, not in DIP version). This pin is for test
and should be left open.
6
176
Timer Out (Output). 6
176
is the output from PRT
channel 1. This line i s multiplexed wi th # of the address
bus.
6:#6:#Transmit Data 0 and 1 (Outputs). These sig-
nals are the transmitted data from the ASCI channels. Trans-
mitted data changes are with respect to the falling edge of
the transmit clock .
6:5Clocked Serial Transmit Data (Output). This line is
the transmitted da ta from the CSI/O channel.
9#+6. Wait (Input, active Low). 9#+6 indicates to the
MPU that the addressed memory or I/O devices are not
ready fo r data t ransfer . This input is sampl ed on the f alling
edge of 6 (and subsequent 9#+6 states). If the input is
sampled Low, t hen the a dditi onal 9#+6 sta tes ar e inser ted
until the 9#+6 input is sampled High, at which time exe-
cution continues.
94. 94+6' (Output, active Low, 3-state). 94 indicates that
the CPU data bus holds valid data to be stored at the ad-
dressed I/O or memory location.
:6#.Crystal Oscillator Connection (Input). This pin
should be l eft op en if an exte rnal c lock is use d inste ad of a
crystal. The oscillator input is not a TTL level (see DC Char-
acteristics).
Several pins are used for different conditions, depending on
the circumstance.
6CDNG 5VCVWU5WOOCT[
56 *#.6 / 1RGTCVKQP
%271RGTCVKQPUV1REQFG(GVEJ
%271RGTCVKQPPF1REQFGCPFTF
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(GVEJ
:&/#1RGTCVKQP
*#.6/QFG
5.''2/QFG+PENWFKPI5;56'/
5612/QFG
Notes:
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'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
#4%*+6'%674'
The Z180 combines a high-performance CPU core with a
variet y of system and I/O re sources useful in a broa d range
of applications. The CPU core consists of five functional
blocks: clock g enerator, bus sta te control ler, Int errupt con-
troller, memory management unit (MMU), and the central
process ing unit (CPU). The int egr ated I/O resourc es make
up the remaining four functional blocks: direct memory ac-
cess (DMA) control (2 channels), asynchronous serial com-
munication interface (ASCI, 2 channels) programmable re-
load timers (PRT, 2 channels), and a clock serial I/O
(CSI/O) channel.
%NQEM)GPGTCVQTThis logic generates a system clock from
an exte rnal crystal or c loc k input. The ext er nal c loc k i s di-
vided by 2 or 1 and provides the timing for both internal
and external devices.
$WU5VCVG%QPVTQNNGTThis log ic pe rforms al l of the st atus
and bus-co ntrol activity asso ciated with the CPU and some
on-ch i p p er iph e rals . Al so i n cl ude s wa it-s ta te timing, res et
cycles, DRAM refresh, and DMA bus exchanges.
+PVGTTWRV%QPVTQNNGTThis logic monitors and prioritizes
the va riety o f intern al and externa l interr upts an d traps to
provide the correct responses from the CPU. To maintain
compatibili ty wit h the Z80 CPU , three different interrupts
modes are supported.
/GOQT[/CPCIGOGPV7PKVThe MMU allows the user to
map the memory used by the CPU (logically only 64KB)
into the 1-MB addressing range supported by the
Z8S180/Z8L180. The organization of the MMU object
code ma int ai ns com pa ti bil it y wi th the Z80 CPU, whi le of -
fering access to an extended memory space. Accompli shed
by using an effective common-area/banked-area scheme.
%GPVTCN2TQEGUUKPI7PKVThe CPU is microcoded to pro-
vide a core that is object-code compatible with the Z80
CPU. It also pr ovides a superse t of the Z80 instruct io n set,
including 8-bit multiplication. The core is modified to allow
many of the instructions to execute in fewer clock cycles.
&/#%QPVTQNNGTThe DMA controller provides high-
speed t ransfers b etween memory a nd I/O devic es. Transfe r
operations supported are memory-to-memory, memory
to/fro m I/ O, an d I /O- to- I/ O. Tr ansfer modes supported are
request, burst, and cycle steal. DMA transfers can access
the full 1-MB address range with a block length up to 64 KB,
and can cross over 64K boundaries.
#U[PEJTQPQWU5GTKCN%QOOWPKECVKQP+PVGTHCEG#5%+
The ASCI logic provides two individual full-duplex
UARTs. Each channel includes a prog rammable baud rate
generator and modem control signals. The ASCI channels
can also support a multiprocessor communication format as
well as break detection and generation
2TQITCOOCDNG4GNQCF6KOGTU246This logic consists
of two separate channels, each containing a 16-bit counter
(timer) and count reload register. The time base for the
counters is derived from the system clock (divided by 20)
before reaching the counter. PRT channel 1 provides an op-
tional output to allow for waveform generation.
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
%NQEMGF5GTKCN+1%5+1The CSI/O channel provides
a half-duplex serial transmitter and receiver. This channel
can be used for simple high-speed data connection to an-
other microprocessor or microcomputer. 64&4 is used for
both CSI/O transmission and reception. Thus, the system
design must ensure that the constraints of half-duplex op-
eration are met (Transmit and Receive operation cannot oc-
cur simul taneo usly). For exampl e, if a CSI/O t ransmis sion
is attempted while the CSI/O is receiving data, a CSI/O does
not work.
0QVG 64&4 is not buffered. Performing a CSI/O transmit
while the previous transmission is still in progress causes
the data to be immediately updated and corrupts the
transmit operation. Similarly, reading 64&4 while a
transmit or receive is in progress should be avoided.
(KIWTG 6KOGT+PKVKCNK\CVKQP%QWPV&QYPCPF4GNQCF6KOKPI
(KIWTG 6KOGT1WVRWV6KOKPI
((((* * * * * * * * * * *
6KOGT&CVC4GIKUVGT
9TKVG*
6KOGT&CVC
4GIKUVGT
6KOGT4GNQCF
4GIKUVGT
6&'(NCI
6+((NCI
4GUGV φφφφφφφφφ
Vφ
6KOGT4GNQCF4GIKUVGT9TKVG*
((((* *
4GNQCF 4GNQCF
9TKVGVQ6&'
6KOGT&CVC4GIKUVGT4GCF
6KOGT%QPVTQN4GSWGUVQT4GCF
6KOGT&CVC
4GI* 6KOGT&CVC
4GI*
6
176
2*+
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
#4%*+6'%674'%QPVKPWGF
(KIWTG %5+1$NQEM&KCITCO
+PVGTPCN#FFTGUU&CVC$WU
%5+16TCPUOKV4GEGKXG
&CVC4GIKUVGT
64&4
%5+1%QPVTQN4GIKUVGT
%064
$CWF4CVG
)GPGTCVQT
6:5
4:5
%-5
+PVGTTWRV4GSWGUV
2*+
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
12'4#6+10/1&'5
<XGTUWU%QORCVKDKNKV[The Z8S180/Z8L180
is descended from two different “ancestor” processors,
ZiLOG’s o ri ginal Z80 and t he Hitachi 64180. The Oper at -
ing M ode Co ntrol Re giste r (OMC R), illu strat ed in Fig ure
8, can be programmed to select between certain Z80 and
64180 differences.
/'/'PCDNGTh is bit c ontro ls th e / output and is
set to a 1 during 4'5'6.
When /'1, the / output i s asserted Low du ring op-
code fetch cycles, Interrupt Acknowledge cycles, and the
first machin e cycle of an 0/+ acknow ledge.
On the Z8S180/Z8L180, this choice makes the processor
fetch a 4'6+ instruction one time. When fetching a 4'6+
from a zero-wait-state memory location, the processor uses
three cl ock bus cycles . These bus cycle s are no t full y Z80-
timing compatible.
When /' 0, the processor does not drive / Low dur-
ing the instruction fetch cycles. After fetching a 4'6+ in-
struction with normal timing, the processor goes back and
refetches the instruction using fully Z80-compatible cycles
that in clu de driv ing / Low. Th is o ption may be require d
by some external Z80 peripherals to properly decode the
4'6+ instruction. Figure 9 and Table 5 show the 4'6+ se-
quence when /' is 0.
(KIWTG 1RGTCVKPI%QPVTQN4GIKUVGT
1/%4+1#FFTGUU'*
&
4GUGTXGF
& &
/'49
+1%49
/6'9
(KIWTG 4'6++PUVTWEVKQP5GSWGPEGYKVJ/'
6
6
6
6
6
6
6
+
6
+
6
+
6
6
6
6
6
6
6
+
6
+
#
#
#
&
&
2% 2% 2% 2%
'&* &* '&* &*
/4'3
4&
56
/
2*+
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
12'4#6+10/1&'5%QPVKPWGF
/6'/6GORQTCT['PCDNGThis b it cont rols t he tem -
pora ry asserti on of the / signal. It is alwa ys read back as
a 1 and is set to 1 during 4'5'6.
When /' is set to0 to accommodate certain external Z80
peripheral(s), those same devi ce (s) may require a pul se on
/ after programming certain of their registers to complete
the function being programmed.
For example, when a control word is written to the Z80 PIO
to enable interrupts, no enable actually takes place until the
PIO sees an active / signal. When /6' =1, there is no
change in the operation of the / signal, and /' controls
its function. When /6' =0, the / output is asserted dur-
ing the next opcode fe tch cycle r egar dl ess of the s ta te pro-
grammed into t he /' bit . This condition is o nly momen -
tary (one time) a nd it is no t neces sary to pr eprogr am a 1
to disable the function (see Figure 10).
+1%+1%QORCVKDKNKV[This bit controls the timing of the
+143 and 4& signals. The bit is set to 1 by 4'5'6.
When +1% =1, the +143 and 4& signals fu nction the same
as the Z64180 (Figure 11).
6CDNG 4'6+%QPVTQN5KIPCN5VCVGU
/CEJKPG
%[ENG 5VCVGU #FFTGUU &CVC 4& 94 /4'3 +143
/
/'
/
/'
*#.6
56
6
6 UV1REQFG '&*
6
6 PF1REQFG &*
6K 0# UVCVG
6K 0# UVCVG
6K 0# UVCVG
6
6 UV1REQFG '&*
6K 0# UVCVG
6
6 PF1REQFG &*
6
6 52 &CVC
6
6 52 &CVC
(KIWTG /6GORQTCT['PCDNG6KOKPI
6
6
6
6
6
6
94
/
1REQFG(GVEJ
9TKVGKPVQ1/%4
2*+
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
When +1% =0, the timing of the +143 and 4& signals match
the timing of the Z80. The +143 and 4& signals go active
as a result of the rising edge of T2. (Figure 12.)
*#.6CPF.QY2QYGT1RGTCVKPI/QFGUThe
Z8S180/Z8L180 can operate in seven modes with respect
to activity and power consumption:
Normal Operation
*#.6 Mode
+15612 Mode
5.''2 Mode
5;56'/5612 Mode
+&.' Mode
56#0&$;
Mode (with or without
37+%- 4'%18
'4;
)
0QTOCN1RGTCVKQPIn this state, the Z8S180/Z8L180 pro-
cessor is fetching and running a program. All enabled func-
tions and portions of the device are active, and the *#.6
pin is High.
*#.6/QFGThis mode is entered by the *#.6 instruc-
tion. Thereafter, the Z8S180/Z8L180 processor continually
fetches the following opcode but does not execute it and
drives the *#.6, 56 and / pins all Low. The oscillator
and 2*+ pin rema in Acti ve. Interr upts and bus g ranting to
external Masters, and DRAM refresh can occur, and all on-
chip I/O devices continue to operate including the DMA
channels.
(KIWTG +14GCFCPF9TKVG%[ENGUYKVJ+1%
6
6
6
9
6
2*+
+143
4&
94
(KIWTG +14GCFCPF9TKVG%[ENGUYKVJ+1%
6
6
6
9
6
2*+
+143
4&
94
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
12'4#6+10/1&'5%QPVKPWGF
The Z8S180/Z8L180 leaves *#.6 mode in response to:
Low on 4'5'6
Interrupt from an enabled on-chip source
External request on 0/+
Enabled ex te rn al request on +06, +06, or +06
In case of an interrupt, the return address is the instruction
following the *#.6 instruction. The program can either
branch ba ck to the *#.6 instruction to wait for another in-
terrup t or can examin e the new state of the system/ap plica-
tion and respond appropriately.
5.''2/QFGThis mode is entered by keeping the +15612
bit (ICR5) and bits 3 and 6 of the CPU Control Register
(CCR3, CCR6) a ll z er o a nd executing the 5.2 instruction.
The oscillator and 2*+ output continue operating, but are
blocked from the CPU core and DMA channels to reduce
power consumption. DRAM refresh stops, but interrupts
and gra nting t o an ext ernal Mast er can occur. Exc ept when
the bus is granted to an external Master, A19–0 and all con-
trol signals except *#.6 are maintained High. *#.6 is
Low. I/O operations continue as before the 5.2 instruction,
except for the DMA channels.
The Z8S180/Z8L180 leaves 5.''2 mode in response to a
Low on 4'5'6, an interrupt request from an on-chip source,
an e xternal r equest on 0/+, or an external request on +06,
+06, or +06.
If an interrupt source is individually disabled, it cannot bring
the Z8S180/Z8L180 out of 5.''2 mode. If an interrupt
source is indi vidual ly enabl ed, and the +'( bit is 1 so that
interrupts are globally enabled (by an EI instruction), the
highest priority active interrupt occurs with the return ad-
dress being the instruction after the 5.2 instruction. If an
interr upt source is individ ually enabled, but the +'( bit is0
so that interrupts are globally disabled (by a DI instruction),
the Z8S180/Z8L180 leaves 5.''2 mode by simply execut-
ing the following instruction(s).
(KIWTG *#.66KOKPI
INT , NMI
A –A
HALT
M1
MREQ
RD
Note:
PHI
T
19 0
i
HALT Opcode Fetch Cycle
HALT Opcode Address HALT Opcode Address + 1
HALT Mode Interrupt
Acknowledge Cycle
2T3T1T2
indicates an indefinite delay.
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
This condition provides a technique for synchronization
with high-speed external events without incurring the la-
tency imposed by an interrupt-response sequence. Figure 14
depicts the timing for e xi ti ng 5.''2 mode due to an inter-
rupt request.
0QVG The Z8S180/Z8L180 takes about 1.5 clock ticks to re-
start.
+15612/QFG+15612 mode is entered by setting the
+15612 bit of the I/O Control Register (+%4) to 1. In this
case, on-chip I/O (ASCI, CSI/O, PRT) stops operating.
However, the CPU continues to operate. Recovery from
+15612 mode is pe rf ormed b y r esett ing the +15612 bit in
+%4 to 0.
5;56'/5612/QFG5;56'/5612 mod e is the com-
bination of 5.''2 and +15612 modes. 5;56'/5612
mode is e ntere d by sett ing the +15612 bit in +%4 to 1 fol-
lowed by execution of the 5.2 instruction. In this mode, on-
chip I/O and CPU stop operating, reducing power consump-
tion, but the 2*+ output continues to operate. Recovery from
5;56'/5612 mode is the same as recovery f rom 5.''2
mode except that internal I/O sources (disabled by +15612)
cannot generate a recovery interrupt.
+&.'/QFGSoftware puts the Z8S180/Z8L180 into this
mode by performing the following actions:
Set the +15612 bit (+%4) to
Set %%4 to
Set %%4 to
Exec ute the 5.2 instruction
The oscillator keeps operating but its output is blocked to
all circuitry including the 2*+ pin. DRAM refresh and all
internal devices stop, but external interrupts can occur. Bus
gran tin g to e xter n al Ma st er s ca n o ccu r i f the $4'56 bit in
the CPU control Register (%%4) was set to 1 before +&.'
mode was entered.
The Z8S180/Z8L180 leaves +&.' mode in response to a
Low on 4'5'6, an external interrupt request on 0/+, or an
external interrupt request on +06, +06 or +06 that is en -
abled in the INT/TRAP Control Register. As previously de-
scribe d for 5.''2 mode, when th e Z8S180/Z8L180 le aves
+&.' mode due to an 0/+, or due to an e nabled ext ernal in-
terrupt request when the +'( flag is 1 due to an '+ instr uc-
tion, the device starts by performing the interrupt with the
return address of the instruction after the 5.2 instruction.
If an exte rnal in terrupt enables the INT/TRAP contr ol reg-
ister whi le the +'( bit is0, Z8S180/Z8L180 leaves +&.'
mode; specifically, the processor restarts by executing the
instructions following the 5.2 instruction.
Figure 15 indicates the timing for exiting +&.' mode due
to an interrupt request.
0QVG The Z8S180/Z8L180 takes about 9.5 clocks to restart.
(KIWTG 5.''26KOKPI
5.2PF1REQFG 5.''2/QFG
2*+
6
6
6
6
6
5
6
5
6
+06K0/+
#
#
*#.6
/
1REQFG(GVEJQT+PVGTTWRV
#EMPQYNGFIG%[ENG
5.2PF1REQFG#FFTGUU (((((*
(GVEJ%[ENG
6
6
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
12'4#6+10/1&'5%QPVKPWGF
While the Z8S180/Z8L180 is in +&.' mode, it grants the bus
to an external Master if the BREXT bit (CCR5) is 1. Fi gure
16 depicts the timing for this sequence.
0QVG A response to a bus request takes 8 clock cycles longer
than in normal operation.
After the external Master negates the Bus Request, the
Z8S180/Z8L180 disables the 2*+ clock and remains in +&.'
mode.
(KIWTG <5<.+&.'/QFG'ZKV&WG6Q'ZVGTPCN+PVGTTWRV
2*+
6
6
6
0/+
#
#
*#.6
/
1REQFG(GVEJQT+PVGTTWRV
#EMPQYNGFIG%[ENG
(((((*
+&.'/QFG
6
%[ENG&GNC[HTQO+06K#UUGTVGF
+06+06+06
QT
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
56#0&$;/QFG9KVJQT9KVJQWV37+%-4'%18'4;
Software can put the Z8S180/Z8L180 into this mode by set-
ting the +15612 bit (ICR5) to1, CCR6 to1, and executing
the 5.2 in structi on. This mode sto ps the on-chip os cillato r
and thus draws the least power of any mode, less than 10µA.
As with +&.' mode, the Z8S180/Z8L180 leaves 56#0&$;
mode in response to a Low on 4'5'6, on 0/+, or a Low
on +06–2 that is enabled by a 1 in the corr espondi ng bit
in the INT/ TRAP Cont rol Regi ster. This a cti on gra nts th e
bus to an external Master if the BREXT bit in the CPU Con-
trol Register (CCR5) is 1. The time required for all of these
operations is grea tl y increased by t he ne ces sity for res ta rt -
ing the on-chip oscillator, and ensuring that it stabilizes to
square-wave operation.
When an external clock is connected to the EXTAL pin rath-
er than a crysta l to the XTAL a nd EXTAL pins and the ex-
ternal clock runs continuously, there is little necessity to use
56#0&$; mode because no time is required to restart the
oscillator, and other modes restart faster. However, if ex-
ternal logic stops the clock during 56#0&$; mode (for ex-
ample, by decoding *#.6 Low and / High for several
clock cycl es), then 56#0&$; mode can be usef ul to allow
the external clock sou rce to stabilize after it is re-enabled.
When ex ternal log ic driv es 4'5'6 Low to brin g the devic e
out of 56#0&$; mode, and a crystal is in use or an external
clock source is stopped, the external logic must hold 4'5'6
Low until the on- chip o sci llator or ext ernal cloc k sourc e is
restarted and stabilized.
The clock-stability requirements of the Z8S180/Z8L180 are
much less in the divide-by-two mode that is selected by a
4'5'6 sequence and cont roll ed by the Clo ck Divide bit in
the CPU Control Register (CCR7). As a result, software per-
forms the following actions:
1. Sets CCR7 to0 for divide- by-two mode befor e an 5.2
instruction and 56#0&$; mode.
2. Delays setting CCR7 back to 1 for divide-by-one
mode as long as possible to allow additional clock
stabilization time after a 4'5'6, interrupt, or in-line
RESTART after an 5.2 01 instruction.
If CCR6 is set to 1 be for e the 5.2 instruction places the
MPU in 56#0&$; mode, the value of the CCR3 bit det er-
mines the length of the delay before the oscillator restarts
and stabilizes when it leaves 56#0&$; mode due to an ex-
ternal interrupt request. When CCR3 is0, the
Z8S180/Z8L180 waits 217 (131,072) clock cycles. When
CCR3 is1, it waits 64 clock cycles. This state is called
37+%-4'%18'4; mode. The same delay applies to grant-
(KIWTG $WU)TCPVKPIVQ'ZVGTPCN/CUVGTKP+&.'/QFG
2*+
6:
$754'3
#
#
*#.6
/
$WU4GNGCUG/QFG +&.'/QFG
(((((*
+&.'/QFG
%[ENG&GNC[WPVKN$75#%-#UUGTVGF
$75#%-
6:
*KIJ+ORGFCPEG
(((((*
*KIJ
.QY
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
ing the bus to an externa l M ast er during 56#0&$; mode,
when the $4':6 bit in the CPU Control Register (%%4)
is 1.
As d esc ri bed previo usl y for 5.''2 and +&.' modes, when
the MPU leaves 56#0&$; mode due to 0/+ Low or an en-
abled +06–+06 Low when the +'(, flag is 1 due to an
IE instruction, it starts by performing the interrupt with the
return address being that of the instruction following the
5.2 instruction. If the Z8S180/Z8L180 leaves 56#0&$;
mode due to an external interrupt request that's enabled in
the +0664#2 Cont rol Register, bu t the +'(, bi t i s0 due to
a &+ instr u ct io n, the processor re st arts by execut in g the in-
struction(s) following the 5.2 instruction. If +06, or +06
or +06 goes inact ive before the end of the clock stabi liza-
tion delay, the Z8S180/Z8L180 stays in 56#0&$; mode.
Figure 17 indicates the timing for leaving 56#0&$; mode
due to an interrupt req uest.
0QVG The Z8S180/Z8L180 takes either 64 or 217 (131,072)
clocks to restart, depending on the CCR3 bit.
While th e Z8S180/Z8L180 i s in 56#0&$; mode, it grants
the bu s to an external Mas ter if the $4':6 bit (%%4) is 1.
Figure 1 8 indicates the timing of this sequenc e. The device
takes 64 or 217 (131,072) clock cycles to grant the bus de-
pending on the CCR3 bit. The latter (not the 37+%-4'
%18'4;) case may be prohibitive for many demand-driven
exter n al Ma st er s. I f s o, 37+%-4'%18'4; or +&.' mode
can be used.
(KIWTG <5<.56#0&$;/QFG'ZKV&WGVQ'ZVGTPCN+PVGTTWRV
2*+
6
6
6
0/+
#
#
*#.6
/
1REQFG(GVEJQT+PVGTTWRV
#EMPQYNGFIG%[ENG
(((((*
56#0&$;/QFG
6
QT%[ENG&GNC[HTQO+06K#UUGTVGF
+06+06+06
QT
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
(KIWTG $WU)TCPVKPIVQ'ZVGTPCN/CUVGT&WTKPI56#0&$;/QFG
2*+
6: 6:
$754'3
#
#
*#.6
/
56#0&$;/QFG
$WU4GNGCUG/QFG
(((((*
56#0&$;/QFG
QT
%[ENG&GNC[#HVGT$754'3#UUGTVGF
$75#%-
(((((*
.QY
*KIJ
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
56#0&6'56%10&+6+105
The following standard test conditions apply to DC Char-
acteristics, un less ot herwise n oted. All volta ges are refer-
enced to VSS (0V). Positive current flows into the refer-
enced pin.
All AC parameters assume a load capacitance of 100 pF.
Add a 10-ns delay for each 50-pF increase in load up to a
maximum of 20 0 pF for the data bus and 100 pF for the ad-
dress and control lines. AC timing measurements are ref-
erenced to VOL MAX or VOL MIN as indicated in Fig ures 20
through 30 (except for %.1%-, which i s re fere n ced to the
10% and 90% points). Ordering Information list s tempe r-
ature ra nges and pr oduct numbe rs. Find pa ckage dr awings
in Package Information.
#$51.76'/#:+/7/4#6+0)5
0QVG Permanent damage may occur if maximum ratings are
exceeded. Normal operation should be under recom-
mended operating cond itions. If these cond itions ar e ex-
ceeded, it could affect reliability.
(KIWTG #%2CTCOGVGT6GUV%KTEWKV
+
1.
+
1*
(TQO
R(
%
.
8
1.
OCZ8
1*
/KP
RKP
+VGO 5[ODQN 8CNWG 7PKV
5WRRN[8QNVCIG 8
&&
` 8
+PRWV8QNVCIG 8
+0
`8
EE
8
1RGTCVKPI6GORGTCVWTG 6
124
` u%
'ZVGPFGF6GORGTCVWTG 6
':6
` u%
5VQTCIG6GORGTCVWTG 6
56)
` u%
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
&%%*#4#%6'4+56+%5 <5
6CDNG <5&%%JCTCEVGTKUVKEU
8
&&
8v8
55
8
5[ODQN +VGO %QPFKVKQP /KP 6[R /CZ 7PKV
8
+*
+PRWV*8QNVCIG
4'5'6':6#.0/+
8
&&
8
&&
8
8
+*
+PRWV*8QNVCIG
'ZEGRV4'5'6':6#.0/+
8
&&
8
8
+*
+PRWV*8QNVCIG
%-5%-#%-#
8
&&
8
8
+.
+PRWV.8QNVCIG
4'5'6':6#.0/+
8
8
+.
+PRWV.8QNVCIG
'ZEGRV4'5'6':6#.0/+
8
8
1*
1WVRWVU*8QNVCIG
#NNQWVRWVU
+
1*
z# 8
+
1*
z# 8
&&
8
1.
1WVRWVU.8QNVCIG
#NNQWVRWVU
+
1.
O# 8
+
+.
+PRWV.GCMCIG
%WTTGPV#NN+PRWVU
'ZEGRV:6#.':6#.
8
+0
`8
&&
z#
+
6.
6JTGG5VCVG.GCMCIG
%WTTGPV
8
+0
`8
&&
z#
+
&&
2QYGT&KUUKRCVKQP
0QTOCN1RGTCVKQP
(/*\ O#
2QYGT&KUUKRCVKQP
5;56'/5612OQFG
(/*\
%
2
2KP%CRCEKVCPEG 8
+0
8
H/*\
6
#
u%
R(
0QVG
8
+*OKP
8
&&
88
+.OCZ
8#NNQWVRWVVGTOKPCNUCTGCV01.1#&8
&&
8
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
6CDNG <.&%%JCTCEVGTKUVKEU
8
&&
8v8
55
8
5[ODQN +VGO %QPFKVKQP /KP 6[R /CZ 7PKV
8
+*
+PRWV*8QNVCIG
4'5'6':6#.0/+
8
&&
8
&&
8
8
+*
+PRWV*8QNVCIG
'ZEGRV4'5'6':6#.0/+
8
&&
8
8
+.
+PRWV.8QNVCIG
4'5'6':6#.0/+
8
8
+.
+PRWV.8QNVCIG
'ZEGRV4'5'6':6#.0/+
8
8
1*
1WVRWVU*8QNVCIG
#NNQWVRWVU
+
1*
z# 8
+
1*
z# 8
&&
8
8
1.
1WVRWVU.8QNVCIG
#NN1WVRWVU
+
1.
O# 8
+
+.
+PRWV.GCMCIG
%WTTGPV#NN+PRWVU
'ZEGRV:6#.':6#.
8
+0
`8
&&
z#
+
6.
6JTGG5VCVG.GCMCIG
%WTTGPV
8
+0
`8
&&
z#
+
&&
2QYGT&KUUKRCVKQP
0QTOCN1RGTCVKQP
(/*\ O#
/*\
2QYGT&KUUKRCVKQP
5;56'/5612OQFG
(/*\
/*\
%
2
2KP%CRCEKVCPEG 8
+0
8H/*\
6
#
u%
R(
0QVG
8
+*OKP
8
&&
88
+.OCZ
8#NNQWVRWVVGTOKPCNUCTGCV01.1#&8
&&
8
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
#%%*#4#%6'4+56+%5 <5
6CDNG <5#%%JCTCEVGTKUVKEU
8
&&
8vQT8
&&
8v/*\%JCTCEVGTKUVKEU#RRN[1PN[VQ81RGTCVKQP
0WODGT 5[ODQN +VGO
<5 /*\ <5 /*\
7PKV/KP /CZ /KP /CZ
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%;%
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2*+(CNNVQ/4'3(CNN&GNC[ PU
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4&&
2*+(CNNVQ4&(CNN&GNC[ +1% PU
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545+
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4'5
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8
&&
8vQT8
&&
8v/*\%JCTCEVGTKUVKEU#RRN[1PN[VQ81RGTCVKQP
0WODGT 5[ODQN +VGO
<5 /*\ <5 /*\
7PKV/KP /CZ /KP /CZ
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+(
+PRWV(CNN6KOGGZEGRV':6#.4'5'6 PU
6CDNG <5#%%JCTCEVGTKUVKEU %QPVKPWGF
8
&&
8vQT8
&&
8v/*\%JCTCEVGTKUVKEU#RRN[1PN[VQ81RGTCVKQP
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<5 /*\ <5 /*\
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9#+6
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94
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56
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4'5'6
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6
6
9
6
6
6
6
9
6
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0QVG/GOQT[4GCF9TKVG%[ENGVKOKPIKUVJGUCOGCU+1
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9
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6
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6
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6
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24'.+/+0#4; &5</2
%27%10641.4')+56'4
%27%QPVTQN4GIKUVGT%%4This register controls the
basic clock rate, certain aspects of Power-Down modes, and
output drive/low-noise options (Figure 31).
$KVClock Divide Select. If this bit is0, as it is after a 4'
5'6, the Z8S180/Z8L180 divides the frequency on the
:6#. pin(s) by two to obtain its Master clock 2*+. If this
bit is programmed as1, the part uses the :6#. frequency
as 2*+ without division.
If an ext ernal oscil lator is used in di vide- by-one mode, the
minimum pulse width requirement provided in the AC
Characteristics must be satisfied.
$KVUCPF56#0&$;/+&.' Control. When these bits
are both
0, a 5.2 instruction makes the Z8S180/Z8L180 en-
ter 5.''2 or 5;56'/5612 mode, depending on the
+15612 bit (ICR5).
When D6 is0 and D3 is1, setting the +15612 bit (ICR5)
and executing a 5.2 instruction puts the Z8S180/Z8L180
into +&.' mode in whi ch the on-chip osc illator runs, but its
output is blocked from the rest of the part, including 2*+ out.
When D6 is 1 and D3 is0, setting +15612 (ICR5) and
executing a 5.2 instruction puts the part into 56#0&$;
mode, in which the on-chip oscillator is stopped and the part
allows 217 (128K) clock cycles for the oscillator to stabilize
when it restarts.
When D6 and D3 are both 1, setting +15612 (+%4) and
executing a 5.2 instruction puts the part into 37+%-4'
%18'4; 56#0&$; mode, in which the on-chip oscillator
is stopp ed, and t he part allo ws only 64 clock c ycles for th e
oscillator to stabilize when it re starts.
The latter section, *#.6 and .19219'4 modes, de-
scribes the subject more fully.
$KV $4':6This bit controls the ability of the
Z8S180/Z8L180 to honor a bus request during 56#0&$;
mode. If this bi t is set to 1 and the part is in 56#0&$;
mode, a $754'3 is honored after the clock stabilization
timer is timed out.
$KV.02*+This bit controls the drive capability on the
2*+ Clock output. If this bit is set to 1, the 2*+ Clock output
is reduced to 33 p ercent of its drive capability.
(KIWTG %27%QPVTQN4GIKUVGT%%4#FFTGUU(*
&
.0#&#
& & & & & & &
%27%QPVTQN4GIKUVGT%%4
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:6#.
56#0&$;+&.''PCDNG
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56#0&$;+&.''ZKV
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&5</2 24'.+/+0#4;
$KV.0+1This bit controls the drive capability of certain
external I/O pins of the Z8S180/Z8L180. When this bit is
set to 1, the output drive capability of the following pins is
reduced to 33 percent of the original drive capability:
$KV.0%27%6.Thi s bit con t rols th e dr iv e cap a b ility of
the CPU Control pins. When this bit is set to 1, the out p ut
drive capability of the following pins is reduced to 33 per-
cent of the original drive capability:
$KV.0#&#This bit controls the drive capability of
the Address/Data bus output drivers. If this bit is set to 1,
the output drive capability of the Address and Data bus out-
puts is reduced to 33 percent of its original drive capability.
465 6Z5
%-#6'0& %-#&4'3
6:# 6:#
6'0&K %-5
$75#%- 4&
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56
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#5%+4')+56'4&'5%4+26+10
#5%+6TCPUOKV5JKHV4GIKUVGTWhen the ASCI
Transmit Shift Register (654) receives data from the ASCI
Transmit Data Register (6&4), the data i s shifted out to t he
6:# pin. When transmission is completed, the next byte (if
available) is automatically loaded from 6&4 into 654 and
the next transmission starts. If no data is available for trans-
mission, 654 idles by outputting a continuous High level.
This register is not program-accessible
#5%+6TCPUOKV&CVC4GIKUVGT6&4+1CFFTGUU
**Data written to the ASCI Transmit Data
Register is transferred to the 654 as soon as 654 is empt y.
Data can be written while 654 is shifting out th e previous
byte of data. Thus, the ASCI transmitter is double buffered.
(KIWTG #5%+$NQEM&KCITCO
+PVGTPCN#FFTGUU&CVC$WU
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%J6&4
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%J454
#5%+%QPVTQN4GIKUVGT#
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%J454
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%J
6:#
4:#
465
%65
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6:#
4:#
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$CWF4CVG
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$CWF4CVG
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%-#
%-#
2*+
0QVG0QV2TQITCO
+PVGTTWRV4GSWGUV
#EEGUUKDNG
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&5</2 24'.+/+0#4;
Data can be written int o an d read from th e ASCI Tra nsmi t
Data Regis ter. If data is read from the ASCI Transmit Data
Register, the ASCI data transmit operation is not affected
by this 4'#& operation.
#5%+4GEGKXG5JKHV4GIKUVGT454This register
receives data shifted in on the 4:# pin. When full, data is
automa tically tran sferred to the ASCI Receive Data Regis-
ter (4&4) if it i s empty. If 454 is not e mpty when the nex t
incoming data byte is shifted in, an overrun error occurs.
This register is not program accessible.
#5%+4GEGKXG&CVC(+(14&4+1#FFTGUU
**The ASCI Receive Data Register is a read-only
register. When a complete incoming data byte is assembled
in 454, it is automatically transferred to the 4 character Re-
ceive Data First-In First-Out ((+(1) memory. The oldest
charact er in the (+(1 (if any) can be read from the Receive
Data Register (4&4). The next incoming data byte can be
shif te d into 454 while the (+(1 is full. Thus, the ASCI re-
ceiver is well buffered.
#5%+56#675(+(1
This four -ent ry (+(1 contai ns Pari ty Err or, F raming Er ror,
Rx Overrun, and Break status bits associated with each char- acter i n the receive data (+(1. The status of the oldest char-
acter (if any) can be read from the ASCI status registers.
#5%+%*#00'.%10641.4')+56'4#
/2'/WNVK2TQEGUUQT/QFG'PCDNG$KVThe ASCI
features a multiprocessor communication mode that utilizes
an ex tra data bit for select ive co mmunication when a n um-
ber of pro ces sors sh are a common se rial bus. Mul tip roces -
sor d ata format is selecte d when the /2 bit in %06.$ is set
to 1. If multiprocessor mode is not selected (/2 bit in
%06.$), /2' has no effect. If multiprocessor mode
is select ed , /2' enables or disables the wake-up feature as
follows. If /$' is set to 1, only re ceived bytes in which the
multiprocessor bit(/2$ ) can affect the 4&4( and error
flags. Effectiv ely , ot her byt es (with /2$) are ignored
by the ASCI. If /2' is reset to0, all bytes, regardless of
the state of the /2$ data bit, affect the 4'&4 and error flags.
/2' is cleared to0 during 4'5'6.
4'4GEGKXGT'PCDNG$KVWhe n 4' is set to 1, the ASCI
transmitter is enabled. When 6' is reset to0, the transmitter
is disables and any transmit operation in progress is inter-
rupted. However, the 6&4' flag is not reset and the previous
contents of 6&4' are held. 6' is cleared to0 in +15612
mode during 4'5'6.
6'6TCPUOKVVGT'PCDNG$KVWhen 6' is set to 1, the
ASCI recei ver is enab led. Wh en 6' is reset to0, the trans-
mitter is disabl ed and any trans mit ope rat ion i n progr ess i s
interrupted. However, the 6&4' flag is not reset and the pre-
(KIWTG #5%+%JCPPGN%QPVTQN4GIKUVGT#
$KV
/2' 4'
49 49 49
6'
465 /2$4 /1& /1& /1&
49 49
#5%+%QPVTQN4GIKUVGT#%06.#+1#FFTGUU*
49 49 49
'(4
$KV
/2' 4'
49 49 49
6'
/1& /1& /1&
49 49
#5%+%QPVTQN4GIKUVGT#%06.#+1#FFTGUU*
49 49 49
/2$4
'(4%-#&
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
#5%+%*#00'.%10641.4')+56'4#%QPVKPWGF
vious contents of 6&4' are held. 6' is cleared to0 in
+15612 mode during 4'5'6.
465 4GSWGUV VQ 5GPF %JCPPGN $KV KP %06.#
1PN[If bit 4 of the System Configuration Register is0,
the 465/6:5 pin exhibits the 465 function. 465 allows
the ASCI to control (start/stop) another communication de-
vices transmission (for example, by connecting to that de-
vice’s %65 input). 465 is essentially a 1-bit output port,
having no side effects on other ASCI registers or flags.
Bit 4 in %06.# is used.
%-#&%-#6'0&RKP6'0&
%-#& , %-#6'0&RKP%-#
These bits are cleared to0 on re set.
/2$4'(4/WNVKRTQEGUUQT$KV4GEGKXG'TTQT(NCI4GUGV
$KVWhen multiprocessor mode is enabled (/2 in
%06.$), /2$4, when read, contains the value of the
/2$ bit for the most recent receive operation. When written
to0, the '(4 function is selected to reset all error flags
(1840, (', 2' and $4- in the #5':6 Register) to 0.
/2$4/'(4 is undefined during 4'5'6.
/1%+&CVC(QTOCV/QFGDKVU
These bits program the AS CI data format as follows.
/1&
→ DKVFCVC
→DKVFCVC
/1&
→0QRCTKV[
→2CTKV[GPCDNGF
/1&
→UVQRDKV
→UVQRDKVU
The data formats available based on all combinations of
/1&, /1&, and /1& are indicated in Table 9.
6CDNG &CVC(QTOCVU
/1& /1& /1& &CVC(QTOCV
5VCTVDKVFCVCUVQR
5VCTVDKVFCVCUVQR
5VCTVDKVFCVCRCTKV[
UVQR
5VCTVDKVFCVCRCTKV[
UVQR
5VCTVDKVFCVCUVQR
5VCTVDKVFCVCUVQR
5VCTVDKVFCVCRCTKV[
UVQR
5VCTVDKVFCVCRCTKV[
UVQR
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
#5%+%*#00'.%10641.4')+56'4$
/2$6/WNVKRTQEGUUQT$KV6TCPUOKV$KVWhen multi-
processor communication format is selected (/2 bit = ),
/2$6 is used to specify the /2$ data bit for tran smissi on.
If /2$6 1, then /2$ is tran smitte d. If /2$6
0, then /2$0 is tra ns mitte d. Th e /2$6 state is unde-
fined during and after 4'5'6.
/2/WNVKRTQEGUUQT/QFG$KVWhen /2 is set to 1,
the data format is configured for multiprocessor mode based
on /1& (number of data bits) and /1& (number of stop
bits) in %06.#. The format is as follows:
5VCTVDKVQTFCVCDKVU/2$DKVQTUVQRDKVU
Multiprocessor (/2) format offers no provision for
parity. If /20, the data format is based on /1&,
/1&, /1&, and may include parity. The /2 bit is
cle ared to0 during 4'5'6.
%6525%NGCTVQ5GPF2TGUECNG$KVWhen read,
%6525 reflects the state of the external %65 input. If the
%65 input pin is High, %6525 is read as 1.
0QVG When the %65 input pin is High, the 6&4' bit is inhib -
ited (that is, held at ).
For ch an ne l 1, the %65 input is multiplexed with 4:5 pin
(Clocked Serial Re ceive Data) . Thus, %6525 is o nly valid
when read if the channel 1 %65' bit = 1 and the %65
input pin function is selected. The 4'#& data of %6525
is not affected by 4'5'6.
If the 55 bits in this register are not , and the $4)
mode bit in the #5':6 regist er is 0, then writing to this bit
sets the prescale (PS) control. Under those circumstances,
a0 indicates a divide-by-10 prescale function while a 1
indicates divide-by-30. The bit resets to 0.
2'12CTKV['XGP1FF$KV2'1 selects oven or odd
parity. 2'1 does not affect the ena bling/di sabling of parity
(/1& bit of %06.#). If 2'1 is cl ear ed to0, even parity
is sel ected . If 2'1 is set to 1, odd parity is selected. 2'1 is
cleared to0 during 4'5'6.
&4&KXKFG4CVKQ$KVIf the : bit in the #5':6 reg-
ister is0, this bit specifies the divider used to obtain baud
rate from the data sampling clock. If &4 is reset to0, divide-
by-16 is used, while if &4 is set to 1, d ivi de- by- 64 is used.
&4 is cleared to0 during 4'5'6.
555QWTEG5RGGF5GNGEV$KVU First,
if these bits are , as they are after a 4'5'6, the %-#
pin is used as a clock input, and is divided by 1, 16, or 64
depending on the &4 bit and the : bit in the #5':6 reg-
ister.
If these bits are not and the $4) mode bit is #5':6
is0, then thes e bi ts specify a powe r- of- two divider fo r the
2*+ clock as indicated in Table 10.
Setting or leaving these bits as makes sense for a chan-
nel only when its %-# pin is selected for the %-# function.
%-#1%-5 offers the %-#1 function when bit 4 of the Sys-
tem Configuration Register is 0. &%&/%-# offers the
%-# function when bit
0 of the Interrupt Edge register is 1.
(KIWTG #5%+%JCPPGN%QPVTQN4GIKUVGT$
$KV
/2$6 /2
49 49 49
%65
2'1 &4 55 55 55
49 49
#5%+%QPVTQN4GIKUVGT$%06.$+1#FFTGUU*
49 49 49
#5%+%QPVTQN4GIKUVGT$%06.$+1#FFTGUU*
25
6CDNG &KXKFG4CVKQ
55 55 55 &KXKFG4CVKQ
÷
÷
÷
÷
÷
÷
÷
'ZVGTPCN%NQEM
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
#5%+56#6754')+56'4
Each ASCI channel status register (56#6) allows inter-
rogation of ASCI communication, error and modem control signal status, and the enabling or disabling of ASCI inter-
rupts.
4&4(4GEGKXG&CVC4GIKUVGT(WNN$KV4&4( is set to
1 when an incoming da ta byte is l oade d int o an e mp ty 4Z
(+(1. If a framing or parity error occurs, 4&4( is still set
and the receive data (which generated the error) is still load-
ed into the (+(1. 4&4( is cleared to0 by rea ding 4&4 and
most recently received character in the (+(1 from +15612
mode, during 4'5'6 and for #5%+ if th e &%& input is
auto-enabled and is negated (High).
18401XGTTWP'TTQT$KVAn overrun condition oc-
curs if the receiver finishes assembling a character but the
4Z(+(1 is full so there is no room for the character. How-
ever, this status bit is not set until the most recent character
receiv ed befor e the overr un becomes the oldes t byte in the
(+(1. Th is bi t is cl ea red wh e n s oft w are wr it es a 1 to the
'(4 bit in the %06.# r egist er. The bit ma y also be cle ared
by 4'5'6 in +15612 mode or #5%+ if the &%& pin is
auto enabled and is negated (High).
0QVG When an overrun occurs, the receiver does not place the
character in the shift register into the (+(1, nor any sub-
sequent characters, until the most recent good character
enters the top of the (+(1 so that 1840 is s et. Software
then writes a 1 to '(4 to clear it.
2'2CTKV['TTQT$KVA parity error is detected when
parity checking is enabled.When the /1& bit in the
%06.# register is 1, a c haracter is ass embled in whi ch th e
parity does not match the 2'1 bit in the %06.$ register.
However, this status bit is not set until or unless the error
character becomes the oldest one in the 4Z(+(1. 2' is
cleared when software writes a 1 to the '(4 bit in the
%064.# register. 2' is also cleared by 4'5'6 in +15612
mode, or on #5%+, if the &%& pin is auto-enab led an d is
negated (High).
('(TCOKPI'TTQT$KVA framing error is detected
when the stop bit of a character is sampled as 52#%'.
However, this status bit is not set until/unless the error char-
acter becomes the oldest one in the 4Z(+(1. (' is cl eared
when software writes a 1 to the '(4 bit in the %06.# reg-
ister. (' is also cleared by 4'5'6 in +15612 mode, or on
#5%+, if the &%& pin is auto-enabled and is negated
(High).
4'+4GEGKXG+PVGTTWRV'PCDNG$KV4+' should be set to
1 to enable ASCI receive interrupt requests. When 4+' is
1, the Receiver requests an interrupt when a character is re-
ceived and 4&4( is set, but only if neither DMA channel
requires its request-routing field to be set to receive data
from this ASCI. That is, if 5/ are and 5#4
are , or &+/ is 1 and +#4 are , then ASCI1
does not request an interrupt for 4&4(. If 4+' is 1, either
ASCI requests an interrupt when 1840, 2' or (' is set, and
(KIWTG #5%+5VCVWU4GIKUVGTU
$KV
4&4( 1840
4449
2'
(' 4' &%& 6&4' 6+'
44
#5%+5VCVWU4GIKUVGT56#6+1#FFTGUU*
4449
$KV
4&4( 1840
449
2'
(' 4' 6&4' 6+'
44
#5%+5VCVWU4GIKUVGT56#6+1#FFTGUU*
4449
%65'
49
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
#5%+ requests an inter rupt when &%& goes High. 4+' is
cle ared to0 by 4'5'6.
&%&&CVC%CTTKGT&GVGEV$KV56#6This bit is set
to 1 when the pin is High. It is cleared to0 on the first
4'#& of 56#6 following the pin’s transition from High
to Low and durin g 4'5'6. When bi t 6 of the #5':6 reg-
ister is0 to select auto-enabling, and the pin is negated
(High), th e receiver is reset and its opera tion is inhibited.
%65'%NGCT6Q5GPF$KV56#6Channel 1 fea-
tures an external %65 input, which is multiplexed with the
receive data pin 45: for the CSI/O. Setting this bit to 1
selects the %65 fu nc tio n; cl ea rin g th e bit to 0 selects the
4:5 function.
6&4'6TCPUOKV&CVC4GIKUVGT'ORV[$KV6&4'
1
indicates that the 6&4 is empty and the next transmit data
byte is written to 6&4. After the byte is written to 6&4,
6&4' is cleared to0 until the ASCI transfers the byte from
6&4 to the 654 and then 6&4' is again set to 1. 6&4' is
set to 1 in +15612 mode and during 4'5'6. On ASCI0,
if the %65 pin is auto-enabled in the #5':6 register and
the pin is High, 6&4' is reset to 0.
6+'6TCPUOKV+PVGTTWRV'PCDNG$KV6+' should be set
to 1 to enabl e ASCI t ra nsm it interrupt r eque st s. I f 6+'
1, an inte rrupt is request ed when 6&4' 1. 6+' is cleared
to0 during 4'5'6.
#5%+64#05/+6#4')+56'45
Register addresses 06H and 07H hold the ASCI transmit
data for channel 0 and channel 1, respectively.
#5%+6TCPUOKV&CVC4GIKUVGTU%JCPPGN
/PGOQPKE6&4
#FFTGUU*
#5%+6TCPUOKV&CVC4GIKUVGTU%JCPPGN
/PGOQPKE6&4
#FFTGUU*
(KIWTG #5%+4GIKUVGT
#5%+6TCPUOKV
%JCPPGN
(KIWTG #5%+4GIKUVGT
#5%+6TCPUOKV
%JCPPGN
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
#5%+4'%'+8'4')+56'4
Register addresses 08H and 09H hold the ASCI receive data
for channel 0 and channel 1, respectively.
#5%+4GEGKXG4GIKUVGT%JCPPGN
/PGOQPKE4&4
#FFTGUU*
#5%+4GEGKXG4GIKUVGT%JCPPGN
/PGOQPKE4&4
#FFTGUU*
%5+1%10641.56#6754')+56'4
The CSI/O Control/Status Register (%064) is used to mon-
itor CSI/O status, enable and disable the CSI/O, enable and disable interrupt generation, and select the data clock speed
and source.
'('PF(NCI$KV'( is set to 1 by the CSI/O to indicate
completion of an 8-bit data transmit or receive operation.
If End Interrupt Enable('+') bit = 1 when '( is set to 1,
a CPU interrupt request is generated. Program access of
64&4 only occurs if '( 1. The CSI/O clears '( to0 when
64&4 is read o r writte n. '( is cleared to0 during 4'5'6
and +15612 mode.
'+''PF+PVGTTWRV'PCDNG$KV'+' is se t to 1 to gen-
erate a CPU interrupt request. The interrupt request is in-
hibite d if '+' is reset to 0. '+' is cleared to0 during 4'5'6.
4'4GEGKXG'PCDNG$KVA CSI/ O rece ive op erati on is
started by setting 4' to 1. When 4' is set to 1, the data clock
is enab led. In inte rna l c loc k mode, the data cl oc k is output
from the %-5 pin. In external clock mode, the clock is input
on th e %-5 pin. In either case, data is shifted in on the 4:5
pin in synchronization with the (internal or external) data
clock. After receiving 8 bits of data, the CSI/O automati-
cally clears 4' to
0, '( is set to 1, and an interrupt (if enabled
by '+') is gen e rate d . 4' and 6' are neve r bot h set to
1 at the sa me tim e. 4' is cleared to0 during 4'5'6 and
+15612 mode.
6'6TCPUOKV'PCDNG$KVA CSI/O transmit operation
is started by setting 6' to 1. When 6' is set to 1, t he d ata
clock is enabled. When in internal clock mode, the data
clock is output from the %-5 pin. In external clock mode,
the clock is input on the %-5 pin. In either case, data is shift-
ed out o n the 6:5 pin synchronous with the (internal or ex-
ternal) data clock. After transmitting 8 bits of data, the
CSI/O automatically clears 6' to0, sets '( to 1, and re-
quests an interrupt if enabled by '+' 1. 6' and 4' are
(KIWTG #5%+4GEGKXG4GIKUVGT%JCPPGN
#5%+6TCPUOKV&CVC
(KIWTG #5%+4GEGKXG4GIKUVGT%JCPPGN
#5%+6TCPUOKV&CVC
(KIWTG %5+1%QPVTQN4GIKUVGT%064+1#FFTGUU#*
$KV
'( '+'
49 49 49
4'
6' AA 55 55 55
4 49 49 49
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
never both set to 1 at the same time. 6' is cleared to0
during 4'5'6 and +15612 mode.
555RGGF5GNGEV$KVU 55, 55
and 55 select the CSI/O transmit/receive clock source and
speed. 55, 55 and 55 are all set to 1 during 4'5'6.
Table 11 indicates CSI/O Baud Rate Selection.
After 4'5'6, the %-5 pin is configured as an external clock
input (555555). Changing these values causes
%-5 to become an output pin and the selected clock is output
when transmit or receive operations are enabled.
%5+16TCPUOKV4GEGKXG&CVC4GIKUVGT
/PGOQPKE64&4
#FFTGUU$*
6KOGT&CVC4GIKUVGT%JCPPGN.QY
/PGOQPKE6/&4.
#FFTGUU%*
6KOGT&CVC4GIKUVGT%JCPPGN*
/PGOQPKE6/&4*
#FFTGUU&*
6KOGT4GNQCF4GIKUVGT%JCPPGN.QY
/PGOQPKE4.&4.
#FFTGUU'*
6KOGT4GNQCF4GIKUVGT%JCPPGN*KIJ
/PGOQPKE4.&4*
#FFTGUU(*
6CDNG %5+1$CWF4CVG5GNGEVKQP
55 55 55 &KXKFG4CVKQ
÷
÷
÷
÷
÷
÷
÷
'ZVGTPCN%NQEM+PRWV
.GUU6JCP÷
(KIWTG %5+16TCPUOKV4GEGKXG&CVC4GIKUVGT
(KIWTG 6KOGT4GIKUVGT%JCPPGN.QY
%5+164&CVC
#5%+4GEGKXG&CVC
(KIWTG 6KOGT&CVC4GIKUVGT%JCPPGN*KIJ
(KIWTG 6KOGT4GNQCF4GIKUVGT.QY
(KIWTG 6KOGT4GNQCF4GIKUVGT%JCPPGN*KIJ
6KOGT&CVC
6KOGT4GNQCF&CVC
6KOGT4GNQCF&CVC
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
6+/'4%10641.4')+56'4
The Timer Con trol Regis ter ( 6%4) monitors both channels
(246246) 6/&4 status. It al so contro ls the enablin g and disabling of down-counting and interrupts, and controls
the output pin #6
176
for 246.
6+(6KOGT+PVGTTWRV(NCI$KVWhen 6/&4 dec-
remen ts to0, 6+( is set to 1. This condition generates an
interrupt request if enabled by 6+' 1. 6+( is reset to 0
when 6%4 is read and the higher or lower byte of 6/&4
is read. During 4'5'6, 6+( is cleared to 0.
6+(6KOGT+PVGTTWRV(NCI$KVWhen 6/&4 dec-
remen ts to0, 6+( is set to 1. This condition generates an
interrupt request if enabled by 6+' 1. 6+( is reset to 0
when 6%4 is read and the higher or lower byte of 6/&4
is read. During 4'5'6, 6+( is cleared to 0.
6+'6KOGT+PVGTTWRV'PCDNG$KVWhen 6+' is set
to 1, 6+( 1 generates a CPU interrupt request. Whe n
6+' is reset to0, the interrup t request is inh ibited. Duri ng
4'5'6, 6+' is cleared to 0.
61%6KOGT1WVRWV%QPVTQN$KVU61% and
61% control the output of 246 using the multiplexed
#6
176
pin as indicated in Table 12. During 4'5'6,
61% and 61% are clea red to 0. If bit 3 of the +#4$ reg-
ister i s 1, the 6
176
function is selected. By programming
61% and 61%, the #6
176
pin can be forced High,
Low, or toggled when 6/&4 decrements to 0.
6&'6KOGT&QYP%QWPV'PCDNG$KVU6&'
and 6&' enable and disable down-counting for 6/&4
and 6/&4, respectively. When 6&'P (P ,) is set to
1, down-counting is stopped and 6/&4P is freely read or
written. 6&' and 6&' are cleared to0 during 4'5'6 and
6/&4P does not decrement until 6&'P is set to .
(KIWTG 6KOGT%QPVTQN4GIKUVGT6%4+1#FFTGUU*
$KV
6+( 6+(
49 49 49
6+'
6+' 61% 6&' 6&'
4 4 49 49 49
61%
6CDNG 6KOGT1WVRWV%QPVTQN
61% 61% 1WVRWV
+PJKDKVGF 6JG#6
176
RKPKUPQV
CHHGEVGFD[VJG246
6QIINGF +HDKVQH+#4$KUVJG
#6
176
RKPKUVQIINGFQT
UGV.QYQT*KIJCU
KPFKECVGF
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
#5%+':6'05+10%10641.4')+56'4%*#00'.#0&%*#00'.
The ASCI Extension Control Registers (#5':6 and
#5':6) control functions that have been added to the ASCIs in the Z8S180/Z8L180 family. All bits in this
register reset to 0.
&%&&KUCDNG$KV#5%+1PN[If this bit is0, then
the &%& pin auto-enables the ASCI0 receiver, such that
when the pin i s negated/Hi gh, the Receiv er is held in a 4'
5'6 s tate. If th is bit is 1, the state of the &%&-pin has no
effect on recei ver operat ion. In ei ther s tate of this bi t, so ft-
ware can read the state of the &%& pin in t he 56#6 reg -
ister , and t he rece iver i nterr upt s on a ri sing edg e of &%&.
%65&KUCDNG$KV#5%+1PN[If this bit is
0, then the
%65 pin auto-enables the #5%+1 transmitter, in that when
the pin is negated/High, the 6&4' bit in the 56#6 register
is forced to 0. If this bit is 1, the state of the %65 pin has
no effect on the transmitter. Regardless of the state of this
bit, software can read the state of the %65 pin the %06.$
register.
:$KVIf this bit is 1, the clock from the Baud Rate
Generator or %-# pin is taken as a 1X-bit clock (sometimes
called isochronous mode). In this mode, receive data on the
4:# pin must be synchronized to the clock on the %-# pin,
regardless of whether %-# is an input or an output. If this
bit is0, the clock from the Baud Rate Generator or %-#
pin is div ided by 16 or 64 per t he &4 bit in the %06.$ reg-
ister, to obtain the actual bit rate. In this mode, receive data
on the 4:# pin is not required to be synchronized to a clock.
$4)/QFG$KVIf the 55 bits in the %06.$ register
are not , and this bit is0, the ASCI Baud Rate Generator
divides 2*+ by 10 or 30, depending on the 25 bit in %06.$,
and factored by a power of two (selected by the 55 bits),
to ob tai n th e cl ock that is prese nte d to the tran smit ter and
receive r and output o n the %-# pin. If 55 are not ,
and this bit is 1, the Baud Rate Generator divides 2*+ by
twice the sum of the 16-bit value (programmed into the
Time Constant registers) and 2. This mode is identical to
the operation of the baud rate generator in the '5%%.
$TGCM'PCDNG$KVIf this bit is 1, the receiver detects
$4'#- conditions and report them in bit 1, and the trans-
mitter sends $4'#-s under the control of bit 0.
$TGCM&GVGEV$KVThe receiver sets this read-only bit to
1 when an all-zero character with a Framing Error becomes
the o ldest charac ter in the 4Z(+(1. The bi t is cleared whe n
software writes a0 to the '(4 bit in %06.# regist er , a l so
by 4'5'6, by +15612 mode, and for #5%+, if the &%&
pin is auto-enabled and is negated (High).
5GPF$TGCM$KVIf this bit and bit 2 are both 1, the trans-
mitter hol ds t he 6:# pin Low to send a $4'#- con dit i on.
The duration of the $4'#- is under software control (one
of the PRTs or CTCs ca n be used to tim e it). This bit res ets
to0, in which state 6:# carries the serial output of the trans-
mitter.
(KIWTG #5%+'ZVGPUKQP%QPVTQN4GIKUVGTU%JCPPGNUCPF
$KV
&%&
: $4) $TGCM $TGCM 5GPF
#5%+'ZVGPUKQP%QPVTQN4GIKUVGT#5':6+1#FFTGUU*
%65 /QFG 'PCDNG $TGCM
$KV
: $4) $TGCM $TGCM 5GPF
/QFG 'PCDNG $TGCM
#5%+'ZVGPUKQP%QPVTQN4GIKUVGT#5':6+1#FFTGUU*
4GUGTXGF
4GUGTXGF
4GUGTXGF 4GUGTXGF
&KUCDNG &KUCDNG
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
#5%+':6'05+10%10641.4')+56'4%*#00'.#0&%*#00'.%QPVKPWGF
6KOGT&CVC4GIKUVGT%JCPPGN.QY
/PGOQPKE6/&4.
#FFTGUU*
6KOGT&CVC4GIKUVGT%JCPPGN*KIJ
/PGOQPKE6/&4*
#FFTGUU*
6KOGT4GNQCF4GIKUVGT%JCPPGN.QY
/PGOQPKE4.&4.
#FFTGUU
6KOGT4GNQCF4GIKUVGT%JCPPGN*KIJ
/PGOQPKE4.&4*
#FFTGUU*
(TGG4WPPKPI%QWPVGT4GCF1PN[
/PGOQPKE(4%
#FFTGUU*
(KIWTG 6KOGT&CVC4GIKUVGT.QY
(KIWTG 6KOGT&CVC4GIKUVGT*KIJ
(KIWTG 6KOGT4GNQCF%JCPPGN.QY
6KOGT&CVC
6KOGT&CVC
4GNQCF&CVC
(KIWTG 6KOGT4GNQCF4GIKUVGT%JCPPGN*KIJ
(KIWTG (TGG4WPPKPI%QWPVGT
4GNQCF&CVC
%QWPVKPI&CVC
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
#5%+6+/'%1056#064')+56'45
If the 55 bits of the %06.$ register are not , and
the $4) mode bit in the #5':6 register is 1, the #5%+ di -
vides the 2*+ clock by two times the registers’ 16-bit value,
plus two. As a result, the clock is presented to the transmitter
and receiver for division by 1, 16, or 64, and is output on
the %-# pin.
If the 55 bits in an ASCI %06.$ register are not 111,
and the $4) mode bit in its Extension Control Register is
1, its new baud rate generator divides 2*+ for serial clocking,
as follows:
DKVUUGEQPFH
2*+
6%ZUCORNKPITCVG
where 6% is the 16-bit value programmed into the ASCI
Time Const ant High and Low reg isters. If t he ASCI multi -
plexed %-# pin is selected for the %-# funct ion, it outputs
the clock before the final division by the sampling rate, as
follows:
H
%-#QWV
H
2*+
6%
Find the 6% value for a parti cular seri al bi t r ate a s foll ows:
6%H
2*+
ZDKVUUGEQPFZUCORNKPITCVG
(KIWTG #5%+6KOG%QPUVCPV4GIKUVGTU
$KV
$KV
#5%+6KOG%QPUVCPV4GIKUVGT.QY#56%.+1#FFTGUU#*
#5%+6KOG%QPUVCPV4GIKUVGT.QY#56%.+1#FFTGUU%*
#5%+6KOG%QPUVCPV4GIKUVGT*KIJ#56%*+1#FFTGUU$*
#5%+6KOG%QPUVCPV4GIKUVGT*KIJ#56%*+1#FFTGUU&*
.5$KVUQH6KOG%QPUVCPV
/5$KVUQH6KOG%QPUVCPV
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
%.1%-/7.6+2.+'44')+56'4
</27#FFTGUU'*
$KV:%NQEM/WNVKRNKGT/QFGWhen this bit is set to 1,
the programmer can double the internal clock speed from
the speed of the external clock. This feature only operates
effectively with frequencies of 10–16 MHz (20–32 MHz in-
ternal). When this bit is set to0, the Z8S180/Z8L180 device
operates in normal mode. At power-up, this feature is dis-
abled.
$KV.QY0QKUG%T[UVCN1RVKQPSetting this bit to 1 en-
ables the low-noise option for the ':6#. and :6#. pins.
This option reduces the gain in addition to reducing the out-
put drive capability to 30% of its original drive capability.
The Low Noise Cr ys tal Opt ion is recommended in the use
of crystals for PCMCIA applications, where the crystal may
be driven too hard by the oscillator. Setting this bit to0 is
selected for normal operation of the ':6#. and :6#. pins.
The d efault for thi s bit is 0.
0QVG Operating restrictions for device operation are listed be-
low. If a low-noise option is required, and normal device
operation is required, use the clock multiplier feature.
(KIWTG %NQEM/WNVKRNKGT4GIKUVGT
4'5'48'&
.1901+5'%4;56#.
:%.1%-/7.6+2.+'4
6CDNG .QY0QKUG1RVKQP
.QY0QKUG
#&&4'DKV
0QTOCN
#&&4'DKV
/*\"8u% /*\"8u%
/*\"8u% /*\"8u%
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
&/#5174%'#&&4'554')+56'4%*#00'.
The DMA Source Address Register Channel 0 specifies the
physical source address for channel 0 transfers. The register
contains 20 bits and can specify up to 1024 KB memory ad-
dresses or up to 64-KB I/O addresses. Channel 0 source can
be memory, I/O, or memory mapped I/O. For I/O, bits
of this register ide ntify the Request Handshake sig-
nal.
&/#5QWTEG#FFTGUU4GIKUVGT%JCPPGN.QY
/PGOQPKE5#4.
#FFTGUU*
&/#5QWTEG#FFTGUU4GIKUVGT%JCPPGN
*KIJ
/PGOQPKE5#4*
#FFTGUU*
&/#5QWTEG#FFTGUU4GIKUVGT%JCPPGN$
/PGOQPKE5#4$
#FFTGUU*
If the s ource i s in I/ O space , bits of t hi s regi ster selec t
the DMA request signal for DMA0, as follows:
(KIWTG &/#5QWTEG#FFTGUU4GIKUVGT.QY
(KIWTG &/#5QWTEG#FFTGUU4GIKUVGT*KIJ
&/#%JCPPGN#FFTGUU
&/#%JCPPGN#FFTGUU
(KIWTG &/#5QWTEG#FFTGUU4GIKUVGT$
$KV
#
$KV
# &/#6TCPUHGT4GSWGUV
&4'3GZVGTPCN
4&4(#5%+
4&4(#5%+
4GUGTXGF
&/#%JCPPGN#FFTGUU
4GUGTXGF
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
&/#&'56+0#6+10#&&4'554')+56'4%*#00'.
The DMA Destination Address Register Channel 0
specifies the physical destination address for channel 0
transfers. The register contains 20 bits and can specify up
to 1024-KB memory addresses or up to 64-KB I/O
addresses. Channel 0 destination can be memory, I/O, or
memory mapped I/O. For I/ O, the /5 bits of this register
identify the Request Handshake signal for channel 0.
&/#&GUVKPCVKQP#FFTGUU4GIKUVGT%JCPPGN
.QY
/PGOQPKE.
#FFTGUU*
&/#&GUVKPCVKQP#FFTGUU4GIKUVGT%JCPPGN
*KIJ
/PGOQPKE*
#FFTGUU*
&/#&GUVKPCVKQP#FFTGUU4GIKUVGT
%JCPPGN $
/PGOQPKE$
#FFTGUU*
If the DMA destination is in I/O space, bits of this reg-
ister se lect the DM A requ est s ign al f or DMA0, as foll ows:
(KIWTG &/#&GUVKPCVKQP#FFTGUU4GIKUVGT%JCPPGN
.QY
(KIWTG &/#&GUVKPCVKQP#FFTGUU4GIKUVGT%JCPPGN
*KIJ
(KIWTG &/#&GUVKPCVKQP#FFTGUU4GIKUVGT%JCPPGN
$
$KV
#
$KV
# &/#6TCPUHGT4GSWGUV
&4'3GZVGTPCN
6&4#5%+
6&4#5%+
0QV7UGF
# #
4GUGTXGF
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
&/#$;6'%17064')+56'4%*#00'.
The DMA Byte Count Register Channel 0 specifies the
number of bytes to be transferr ed. This register contains 16
bits and may specify up to 64-KB transfers. When one byte
is transferred, the register is decremented by one. If P bytes
should be transferred, P must be stored before the DMA op-
eration.
0QVG All DMA Count Register channels are undefined during
4'5'6.
&/#$[VG%QWPV4GIKUVGT%JCPPGN.QY
/PGOQPKE$%4.
#FFTGUU*
&/#$[VG%QWPV4GIKUVGT%JCPPGN*KIJ
/PGOQPKE$%4*
#FFTGUU*
&/#$[VG%QWPV4GIKUVGT%JCPPGN.QY
/PGOQPKE$%4.
#FFTGUU'*
&/#$[VG%QWPV4GIKUVGT%JCPPGN*KIJ
/PGOQPKE$%4*
#FFTGUU(*
(KIWTG &/#$[VG%QWPV4GIKUVGT.QY
(KIWTG &/#$[VG%QWPV4GIKUVGT*KIJ
(KIWTG &/#$[VG%QWPV4GIKUVGT.QY
(KIWTG &/#$[VG%QWPV4GIKUVGT*KIJ
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
&/#/'/14;#&&4'554')+56'4%*#00'.
The DMA Memory Address Register Channel 1 specifies
the physical memory address for channel 1 transfers. The
address may be a destinat io n or a sour ce memory loca tion.
The register contains 20 bits and may specify up to 1024 KB
memory addresses.
&/#/GOQT[#FFTGUU4GIKUVGT%JCPPGN.
/PGOQPKE/#4.
#FFTGUU*
&/#/GOQT[#FFTGUU4GIKUVGT%JCPPGN*
/PGOQPKE/#4*
#FFTGUU*
&/#/GOQT[#FFTGUU4GIKUVGT%JCPPGN$
/PGOQPKE/#4$
#FFTGUU#*
(KIWTG &/#/GOQT[#FFTGUU4GIKUVGT
%JCPPGN.
(KIWTG &/#/GOQT[#FFTGUU4GIKUVGT
%JCPPGN*
(KIWTG &/#/GOQT[#FFTGUU4GIKUVGT
%JCPPGN$
# #
4GUGTXGF
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
&/#+1#&&4'554')+56'4
The DMA I/O Address Register specifies the I/O device for
channel 1 transfers. This address may be a destination or
source I/O device. +#4. and +#4* each contain 8 address
bits. The most significant byte identifies the Request Hand-
shake signal and controls the Alternating Channel feature.
&/#+1#FFTGUU4GIKUVGT%JCPPGN.QY
/PGOQPKE+#4.
#FFTGUU$*
&/#+1#FFTGUU4GIKUVGT%JCPPGN*KIJ
/PGOQPKE+#4*
#FFTGUU%*
&/#+1#FFTGUU4GIKUVGT%JCPPGN$
/PGOQPKE+#4$
#FFTGUU&*
#NV'The #NV' bit should be set only when both DMA
channels are programmed for the same I/O source or I/O
destination. In this case, a channel end condition (byte count
= 0) on channel 0 sets bit 6 (#NV%), which subsequently
enables the channel 1 request and blocks the channel 0
request. Similarly, a channel end condition on channel 1
clears bit 6 (#NV%), which then enables the channel 0 request
and b locks the c hannel 1 req uest. For external r equests, th e
request from the device must be routed or connected to both
the &4'3 and &4'3 pins.
#NV%If bit (#NV') is0, the #NV% bit has no eff ect. When bi t
7 (#NV') is 1 and the #NV% bit is0, the request signal selected
by bits is not presented to channel 1; however, the chan-
nel 0 reques t operates normally. When #NV' is 1 and #NV%
is 1, the request selected by 5#4 or  is
not presen ted t o ch annel 0; ho wever, the channe l 1 r eq uest
operates normally. The #NV% bit can be written by soft ware
to select which channel should operate first; however, this
operati on shoul d be ex ecuted only when both ch anne ls ar e
stopped (both &' and &' are ).
4GS5GNIf bit &+/ in the &%06. register is 1, indicating
an I/O sourc e, the following bits se lect which sourc e hand-
shake signal should control the transfer:
If &+/ is0, indicating a n I/O d estination, the following
bits se le ct which desti natio n ha ndshake sig nal sho uld con -
trol the tran sfer:
(KIWTG &/#+1#FFTGUU4GIKUVGT%JCPPGN.QY
(KIWTG &/#+1#FFTGUU4GIKUVGT%JCPPGN*KIJ
(KIWTG &/#+1#FFTGUU4GIKUVGT%JCPPGN$
$KV
#NV' #NV%
4GS5GN
&4'3RKP
#5%+4&4(
#5%+4&4(
1VJGT 4GUGTXGFFQPQVRTQITCO
&4'3RKP
#5%+6&4'
#5%+6&4'
1VJGT 4GUGTXGFFQPQVRTQITCO
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
&/#56#6754')+56'4
The D MA Stat us Regi ster (&56#6) is used to enable and
disable DMA transfer and DMA termination interrupts. &56#6 also indicates DMA transfer status, Completed or
In Progress.
&/#5VCVWU4GIKUVGT
/PGOQPKE&56#6
#FFTGUU*
&'&/#'PCDNG%JCPPGN$KVWhen &' 1
and &/' 1, channel 1 DMA is enabled. When a DMA
transfer terminates ($%4), &' is reset to0 by the
DMAC. When &'0 and the DMA interrupt is enabl ed
(&+' 1), a DMA interrupt request is made to the CPU.
To perform a software 94+6' to &', &9' should be
written witha0 during the same register 94+6' access.
Writing &' to0 disables channel 1 DMA, but DMA is re-
starta b le . Wr it ing &' to 1 enables channel 1 DMA and
automatically sets DMA Main Enable (&/') to 1. &' is
cle ared to0 during 4'5'6.
&'&/#'PCDNG%JCPPGN$KVWhen &' 1
and &/' 1, channel 0 DMA is enabled. When a DMA
transfer terminates ($%4), &' is reset to0 by the
DMAC. When &'0 and the DMA i nterrupt is enabled
(&+' 1), a DMA interrupt request is made to the CPU.
To perform a software 94+6' to &', &9' should be
written with
0 during the same register 94+6' access. Writ-
ing &' to0 disables channel 0 DMA. Writing &' to 1
enables channel 0 DMA and automatically sets DMA Main
Enable (&/') to 1. &' is cleared to0 during 4'5'6.
&9'&'$KV9TKVG'PCDNG$KVWhen performing
any software 94+6' to &', this bit should be written with
0 during the same access. &9' always reads as .
&9'&'$KV9TKVG'PCDNG$KVWhen performing
any software 94+6' to &', this bit should be written with
0 during the same access. &9' always reads as .
&+'&/#+PVGTTWRV'PCDNG%JCPPGN$KVWhen
&+' is set to 1, the termination channel 1 DMA transfer
(indic ate d when &'0) causes a CPU interrupt request
to be ge ner at ed. When &+'0, the channel 0 DMA ter-
mination interrupt is disabled. &+' is cleared to0 during
4'5'6.
&+'&/#+PVGTTWRV'PCDNG%JCPPGN$KVWhen
&+' is set to 1, the termination channel 0 of DMA transfer
(indic ate d when &') caus es a CPU in terru pt req uest
to be ge ner at ed. Whe n &+'0, the channel 0 DMA ter-
mination interrupt is disabled. &+' is cleared to0 during
4'5'6.
&/'&/#/CKP'PCDNG$KVA DMA operation is
only enabled when its &' bit (&' fo r ch an ne l0, &' for
channel 1) and the &/'bit is set to .
When 0/+ occu rs, &/' is reset to0, thus disa bl ing DMA
activi ty during th e 0/+ interrupt service routine. To restart
DMA, &' and/or &' should be written with a 1 (even
if the conten ts are a lready ). This c ondition a utomaticall y
sets &/' to 1, allowing DMA operations to continue.
0QVG &/' cannot be directly written. The bit is cleared to 0
by 0/+ or indirectly set to 1 by setting &' and/or &'
to 1. &/' is cleared to 0 during 4'5'6.
(KIWTG &/#5VCVWU4GIKUVGT&56#6+1#FFTGUU*
$KV
&' &' &9'
49 49 9
&9' &+' &+' &/'
949 49 4
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
&/#/1&'4')+56'4
The DMA Mode Register (&/1&') is u sed t o se t the ad-
dressing and transfer mode for channel 0.
&/#/QFG4GIKUVGT
/PGOQPKE&/1&'
#FFTGUU*
&/&/&GUVKPCVKQP/QFG%JCPPGN$KVU
This
mode specifies whether the destination for channel 0 transfers
is memo ry or I/O, and w hether the a ddress should be incr e-
men ted or decremen ted for each byte transferred.
&/
and
&/
are cleared to
0
during
4'5'6
.
5/5/5QWTEG/QFG%JCPPGN$KVUThis
mode specifies whether the source for channel 0 transfers
is memory or I/O, and whether the address should be incre-
mented or decremented for each byte transferred.
(KIWTG &/#/QFG4GIKUVGT&/1&'+1#FFTGUU*
$KV
&/ &/
49 49
5/ 5/ //1&
49 49 49
6CDNG %JCPPGN&GUVKPCVKQP
&/ &/ /GOQT[+1
/GOQT[
+PETGOGPV&GETGOGPV
/GOQT[
/GOQT[
/GOQT[ HKZGF
+1 HKZGF
6CDNG %JCPPGN5QWTEG
5/ 5/ /GOQT[+1
/GOQT[
+PETGOGPV&GETGOGPV
/GOQT[
/GOQT[
/GOQT[ HKZGF
+1 HKZGF
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
Table 16 indicates all DMA transfer mode combinations of
&/, &/, 5/, and 5/. Because I/O to/from I/O trans-
fers are not implemented, 12 combinations are available.
//1&/GOQT[/QFG%JCPPGN$KVWhen chan-
nel 0 is configured for memory to/from memory transfers
there is no Request Handshake signal to control the transfer
timing. Instead, two automatic transfer timing modes are se-
lectable: burst (//1&) and cycle steal (//1&).
For burst memory to/from memory transfers, the DMAC
takes control of the bus continuously until the DMA transfer
completes (as indicated by the byte count register = ). In
cycle steal mode, the CPU is provided a cycle for each DMA
byte transfer cycle until the transfer is completed.
For channe l 0 DMA wit h I/O sou rce or desti nation , the se -
lected Request signal times the transfer ignoring //1&.
//1& is cleared to0 during 4'5'6.
6CDNG 6TCPUHGT/QFG%QODKPCVKQPU
&/ &/ 5/ 5/ 6TCPUHGT/QFG #FFTGUU+PETGOGPV&GETGOGPV
/GOQT[→/GOQT[ 5#4
/GOQT[→/GOQT[ 5#4 
/GOQT[→/GOQT[ 5#4HKZGF
+1→/GOQT[ 5#4HKZGF
/GOQT[→/GOQT[ 5#4
/GOQT[→/GOQT[ 5#4 
/GOQT[→/GOQT[ 5#4HKZGF
+1→/GOQT[ 5#4HKZGF
/GOQT[→/GOQT[ 5#4HKZGF
/GOQT[→/GOQT[ 5#4 HKZGF
4GUGTXGF
4GUGTXGF
/GOQT[→+1 5#4HKZGF
/GOQT[→+1 5#4 HKZGF
4GUGTXGF
4GUGTXGF
0QVG* Includes memory mapped I/O.
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
&/#9#+6%10641.4')+56'4
The DMA/WAIT Control Register (&%06.) controls the
insert io n of wait st ates in to DMAC (a nd CPU) acces ses of
memory or I/O. Also, the register defines the Request signal
for each channel as level or edge sense. &%06. also sets
the D MA tra n sfe r mo de fo r ch a nne l 1 , wh ic h is l imi ted to
memory to/from I/O transfers.
/9+/9+/GOQT[9CKV+PUGTVKQP$KVU This
bit specifies the number of wait states introduced into CPU
or DMAC memory ac cess cycles . /9+ and /9+ are set
to 1 during 4'5'6.
+9++9++19CKV+PUGTVKQP$KVU
This bit speci-
fies the number of wait states introduced into CPU or DMAC
I/O access cycles.
+9+
and
+9+
are set to
1
during
4'5'6
.
0QVG These wait states are added to the 3-clock I/O cycle that
is used to access the on-chip I/O registers. It is equally
valid to regard these as 0 to 3 wait states added to a 4-
clock external I/O cycle.
&/5&/5&/#4GSWGUV5GPUG$KVU &/5
and &/5 specify the DMA request sense for channel 0 and
channel 1 respectively. When reset to0, th e inp ut is level
sense. When set to 1, the input is edge sense. &/5 and
&/5 are cleared to0 during 4'5'6.
Typically, for an input/source device, the associated &/5
bit shoul d be progr ammed as 0 for level se nse. The devic e
takes a relatively long time to update its Request signal after
the DMA channel reads data (in the first of the two machine
cycles involved in transferring a byte).
An output/destination device takes much less time to update
its Request signal after the DMA channel starts a 94+6'
opera tion to it (the second mac hine cycle of the two cyc les
involved in transferring a byte). With zero-wait state I/O cy-
cles, a device cannot update its request signal in the required
time, so edge sensing must be used.
A one-wa it-s tate I/O cyc le als o do es not p rov ide suf fici ent
time for updating, so edge sensing is again required.
&+/ &+/ &/# %JCPPGN +1 CPF /GOQT[ /QFG
$KVU Specifies the source/destination and address
modifier for channel 1 memory to/from I/O transfer modes.
&+/ and &+/ are cleared to0 during 4'5'6.
(KIWTG &/#9#+6%QPVTQN4GIKUVGT&%06.+1#FFTGUU*
$KV
/9+ +9+
49 49
&/5 &/5 &+/
49 49 49
/9+ +9+ &+/
49 49 49
/9+ /9+ 9CKV5VCVG
+9+ +9+ 9CKV5VCVG
&/5K 5GPUG
'FIG5GPUG
.GXGN5GPUG
6CDNG %JCPPGN6TCPUHGT/QFG
&+/ &/+ 6TCPUHGT/QFG
#FFTGUU
+PETGOGPV&GETGOGPV
/GOQT[→+1 /#4+#4HKZGF
/GOQT[→+1 /#4 +#4HKZGF
+1→/GOQT[ +#4HKZGF/#4
+1→/GOQT[ +#4HKZGF/#4
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
+06'447268'%614.194')+56'4
Bits of the Interrupt Vector Low Register (+
.
) are us ed
as bits of the synthes ized interrupt vector during inter-
rupts for the +06 and +06 pins and for the DMAs, ASCIs,
PRTs, and CSI/O. These three bits are cleared to0 during
4'5'6 (Figure 74).
+PVGTTWRV8GEVQT.QY4GIKUVGT
/PGOQPKE+.
#FFTGUU*
+0664#2%10641.4')+56'4
This reg ister is used in handling 64#2 i nterrupts and t o en-
able or disable Maskable Interrupt Leveland the +06
and +06 pins.
+0664#2%QPVTQN4GIKUVGT
/PGOQPKEU+6%
#FFTGUU*
64#2$KVThis bit is set to 1 when an undefined op-
code is fetched. 64#2 can be reset under program control
by writing it with a ; however, 64#2 cannot be written with
1 under program control. 64#2 is reset to0 during 4'5'6.
7(17PFGHKPGF(GVEJ1DLGEV$KVWhen a 64#2 in-
terrupt occurs, the contents of 7(1 allow the starting ad-
dress of the undefined instruction to be determined. This in-
terrup t is ne cessar y bec aus e the 64#2 may occur on either
the second or third byte of the opcode. 7(1 allows the
stacked PC value to be correctly adjusted. If 7(10, the
first opcode should be interpreted as the stacked 2%. If
7(1 1, th e firs t opcode addr ess is sta cked 2%. 7(1 is
Read-Only.
+6'+PVGTTWRV'PCDNG$KVU +6'
and +6' enable and disable the external interrupt inputs
+06 and +06, respectivel y. +6' enables and disables in-
terrupts from:
'5%% • Bidirectional Centronics controller
%6%U • External interrupt input +06
A 1 in a bit enables the corresponding interrupt level while
a0 disables it. A 4'5'6 sets +6' to 1 and clea rs +6'
and +6' to 0.
64#2+PVGTTWRVThe Z8S180/Z8L180 generates a 64#2
sequence when an undefined opcode fetch occurs. This fea-
ture can be used to increase software reliability, implement
an extended instruction set, or both. 64#2 may occur during
opcode fetch cycles and also if an undefined opcode is
fetched during the interrupt acknowledge cycle for +06
when Modeis used.
When a 64#2 sequence occurs, the Z8S180/Z8L180:
1. Sets the 64#2 bit in the Interrupt 64#2/Control (+6%)
register to 1.
2. Saves the current Program Counter (PC) value,
reflec ting th e loca tion of the undefi ned opcode, on the
stack.
3. Resumes execution at logical address 0.
0QVG If lo gica l ad dress 0000H is mapped to physical address
00000H, the vector is the same as for 4'5'6. In this
case, testing the 64#2 bi t in +6% reveals whether the re-
start at physical address 00000H was caused by 4'5'6
or 64#2.
(KIWTG +PVGTTWRV8GEVQT.QY4GIKUVGT+.+1#FFTGUU*
$KV
+. +.
+PVGTTWRV5QWTEG&GRGPFGPV%QFG
+.
49 49 49
2TQITCOOCDNG
$KV
64#2 7(1
49 49 49
+6' +6' +6'
49 4
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
All 64#2U occur after fetching an undefined second opcode
byte following one of the prefix opcodes (CBH, DDH, EDH,
or FDH) or after fetching an undefined third opcode byte
following one of the double-prefix opcodes (DDCBH or
FDCBH).
The state of the Undefined Fetch Object (7(1) bit in +6%
allow s 64#2 software to correctly adjust the stacked PC, de-
pending o n whether the second or third byte of the opcode
generated the 64#2. If 7(10, the starting address of
the invalid instruction is the stacked 2% . If 7(1 1, the
starting address of the invalid instruction is equal to the
stacked 2% .
(KIWTG 64#26KOKPI
PF
1REQFG7PFGHKPGF
6
6
6
6
62
6
K
6
K
6
K
6
K
6
K
6
6
6
6
6
6
6
6
#
#
#
2*+
&
&
2% *
52
7PFGHKPGF
/4'3
/
4&
94
6
52
1REQFG
2%
*
2%
.
PF1REQFG
(GVEJ%[ENG
2%5VCEMKPI
1REQFG
(GVEJ%[ENG
4GUVCTV
HTQO*
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
(KIWTG 64#26KOKPI
TF
1REQFG7PFGHKPGF
6
6
6
6
6
6
62
6
6
K
6
K
6
6
6
6
6
6
6
6
#
#
#
2*+
&
&
2% *
52
7PFGHKPGF
/4'3
/
4&
94
6
52
1REQFG
2%
*
2%
.
TF1REQFG
(GVEJ%[ENG 2%5VCEMKPI
1REQFG
(GVEJ%[ENG
4GUVCTV
/GOQT[
+:F+;F
6
K
6
K
4GCF%[ENG
(TQO*
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
4'(4'5*%10641.4')+56'4
/PGOQPKE4%4
#FFTGUU*
The Refresh Control Register(4%4) specifies the interval
and length of refresh cycles, while enabling or disabling the
refresh function.
4'('4GHTGUJ'PCDNG$KV4'('0 disables the re-
fresh controller, while 4'(' 1 enables refresh cycle in-
sertio n. 4'(' is set to 1 during 4'5'6.
4'(94GHTGUJ9CKV$KV4'(9 0 causes the re-
fresh cycle to be two clocks in duration. 4'(9 1 causes
the refr es h cycle t o be thre e clock s in durati on by addin g a
refres h wait cycle (649). 4'(9 is set to 1 during 4'5'6.
%;%%[ENG+PVGTXCN$KV%;% and %;%
specify the interval (in clock cycles) between refresh cycles.
When dynamic RAM requires 128 refresh cycles every 2
ms (or 256 cycles in every 4 ms), the required refresh in-
terval is less than or equal to 15.625 µs. Thus, the underlined
values indica te the best ref resh int erval d ependin g on CPU
clock frequency. %;% and %;% are cleared to0 during
4'5'6 (see Table 18).
4GHTGUJ%QPVTQNCPF4GUGVAfter 4'5'6, based on the
initialized value of 4%4, refresh cycles occur with an inter-
val of 10 clock cycles and be 3 clock cycles in duration.
&[PCOKE4#/4GHTGUJ1RGTCVKQP
1. Refresh Cy cle ins erti on is st opped whe n the CPU is i n
the following st ates:
a. During 4'5'6
b. When the bus is released in response to $754'3
c. During 5.''2 mode
d. During 9#+6 states
2. Refr esh cycles a re suppresse d when the bus is rele ased
in response to $754'3. However, the refresh timer
continues to operate. The time at which the first
refresh cycle occurs after the Z8S180/Z8L180
reacquires the bus depends on the refresh timer. This
cycle offers no timing relationship with the bus
exchange.
3. Refresh cycles are suppressed during 5.''2 mode. If
a refresh cycle is requested during 5.''2 mode, the
refresh cycle request is internally latched (until
replaced with the next refresh request). The latched
refres h cycle is ins er ted at the end of th e fi rst machine
cycle after 5.''2 mode is exited. After this initial
cycle, the time at which the next refresh cycle occurs
depends on the re fresh time and offers no relationship
with the exit from 5.''2 mode.
4. The refresh address is incremented by one for each
successful refresh cycle, not for each refresh. Thus,
independent of th e n umber of missed re fresh reque st s,
each refresh bus cycle uses a refresh address
incremented by one from that of the previous refresh
bus cycles.
(KIWTG 4GHTGUJ%QPVTQN4GIKUVGT
4%4+1#FFTGUU*
4GUGTXGF
%[E
%[E
4'(9
4'('
6CDNG &4#/4GHTGUJ+PVGTXCNU
6KOG+PVGTXCN
%;% %;% +PUGTVKQP+PVGTXCN 2*+/*\ /*\ /*\ /*\ /*\
UVCVGU zU zU zU zU zU
UVCVGU zU zU zU zU zU
UVCVGU zU zU zU zU zU
UVCVGU zU zU zU zU zU
0QVG*calculated interval.
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
//7%1//10$#5'4')+56'4
The Common Base Register (%$4) specifies the base ad-
dress (on 4-KB boundaries) used to generate a 20-bit phys- ical address for Common Area 1 accesses. All bits of %$4
are reset to0 during 4'5'6.
//7%QOOQP$CUG4GIKUVGT
/PGOQPKE%$4
#FFTGUU*
//7$#0-$#5'4')+56'4
The Bank Base Register ($$4) specifies the base address
(on 4-KB boundaries) used to generate a 20-bit physical ad- dress for Bank Area accesses. All bits of $$4 are reset to
0 during 4'5'6.
//7$CPM$CUG4GIKUVGT
/PGOQPKE$$4
#FFTGUU*
//7%1//10$#0-#4'#4')+56'4
The Common/Bank Area Register (%$#4) specifies bound-
aries within the Z8S180/Z8L180 64-KB logical address space for up to three areas; Common Area), Bank Area and
Common Area 1.
//7%QOOQP$CPM#TGC4GIKUVGT
/PGOQPKE%$#4
#FFTGUU#*
(KIWTG //7%QOOQP$CUG4GIKUVGT%$4+1#FFTGUU*
$KV
%$ %$
49
%$
%$ %$ %$ %$
49
%$
49
494949
49
49
(KIWTG //7$CPM$CUG4GIKUVGT$$4+1#FFTGUU*
$KV
$$ $$
49
$$
$$ $$ $$ $$
49
$$
49
494949
49
49
(KIWTG //7%QOOQP$CPM#TGC4GIKUVGT%$#4+1#FFTGUU#*
$KV
%# %#
49
%#
%# $# $# $#
49
$#
49
494949
49
49
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
%# %#%#$KVU %# specifies the start (Low) ad-
dress (on 4-KB boundari es) for Common Area 1. This con-
dition a lso determines t he most recent address of the Bank
Area. All bits of %# are set to 1 during 4'5'6.
$# $#$KVU $# specifies the start (Low) address
(on 4-KB boundaries) for the Bank Area. This condition
also determines the most recent address of Common Area
0. All bits of $# are set to 1 during 4'5'6.
12'4#6+10/1&'%10641.4')+56'4
The Z8S180/Z8L180 is descended from two different an-
cestor processors, ZiLOG’s original Z80 and the Hitachi
64180. The Operating Mode Control Register (1/%4) can
be programmed to select between certain differences be-
tween the Z80 and the 64180.
1RGTCVKQP/QFG%QPVTQN4GIKUVGT
/PGOQPKE1/%4
#FFTGUU'*
/'/'PCDNGTh is bit c ontro ls th e / output and is
set to a 1 during reset.
When /' 1, the / output is ass erted Low during the
opcode fetch cycle, the +06 acknowledge cycle, and the
first machin e cycle of the 0/+ acknowledge.
On the Z8S180/Z8L180, this choice makes the processor
fetch one 4'6+ instruction. When fetching a 4'6+ from zero-
wait-state memory, the processor uses three clock machine
cycles that are not fully Z80-timing-compatible.
When /'0, the processor does not drive / Low dur-
ing instruction fetch cycles. After fetching one 4'6+ instruc-
tion with normal timing, the processor returns and refetches
the in st ruc ti on using Z80-compat ible cycles tha t dr iv e /
Low. This timing compatibility may be required by external
Z80 peripherals to properly decode the 4'6+ instruction.
(KIWTG 1RGTCVKPI%QPVTQN4GIKUVGT
1/%4+1#FFTGUU'*
&
4GUGTXGF
& &
+1%49
/6'9
/'49
(KIWTG 4'6++PUVTWEVKQP5GSWGPEGYKVJ/'
T1T2T3T1T2T3TITITIT1T2T3T1T2T3
TITI
A0–A18 (A19)
2*+
D0–D7
PC PC+1 PC PC+1
EDH 4DH EDH 4DH
MREQ
M1
RD
ST
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
+1%10641.4')+56'4
The I/O Control Register (+%4) allows relocation of the in-
ternal I/O addresses. +%4 also controls the enabling and dis-
abling of +15612 mode (Figure 83).
+1#+1#FFTGUU4GNQECVKQP$KVU+1# and
+1# relocate internal I/O as indicated in Figure 84. 0QVG
The high-order 8 bits of 16-bit internal I/O address are al-
ways
0.
+1#
and
+1#
are cleared to
0
during
4'5'6
.
+1562+15612/QFG$KV+15612 mode is enabled
when +1562 is set to 1. Normal I/O operation resumes when
+1562 is reprogrammed or 4'5'6 to 0.
(KIWTG +1%QPVTQN4GIKUVGT+%4+1#FFTGUU(*
+1# +1# +1562
$KV
49 49 49
(KIWTG +1#FFTGUU4GNQECVKQP
+1# +1#
+1# +1#
+1# +1#
+1# +1#
((*
%*
$(*
*
(*
*
(*
*
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
2#%-#)'+0(14/#6+10
(KIWTG 2KP&+22CEMCIG&KCITCO
(KIWTG 2KP3(22CEMCIG&KCITCO
<5<.
'PJCPEGF</KETQRTQEGUUQT ZiLOG
24'.+/+0#4; &5</2
(KIWTG 2KP2.%%2CEMCIG&KCITCO
<5<.
ZiLOG 'PJCPEGF</KETQRTQEGUUQT
&5</2 24'.+/+0#4;
14&'4+0)+0(14/#6+10
For fast results, contact your local ZiLOG sales office for
assistance in ordering the part(s) required.
2TG%JCTCEVGTK\CVKQP2TQFWEV
The product represented by this document is newly introduced
and ZiLOG has not completed the full characterization of the
product. The document states what ZiLOG knows about this
product at this time, but ad ditional featur es or non -con for mance
with some aspects of the document may be found, either by
ZiLOG or its customers in the course of further application and
characterization work. In addition, ZiLOG cautions that delivery
may be uncertain at times, due to start-up yield issues.
©2000 by ZiLOG, Inc. All rights reserved. Information in this
publication concerning the devices, applications, or technology
described is intended to suggest possible uses and may be
superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY
FOR OR PROVIDE A REPRESENTATION OF AC CURA CY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES
NOT ASSUME LIABILITY FOR INTELLECTUAL
PROPERTY INFRINGEMENT RELATED IN ANY
MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE.
Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of
life support systems is n ot authorized. No licenses are con veyed,
implicitly or o therwis e, by thi s docum ent und er any in tellectual
property rights.
ZiLOG, Inc.
910 East Hamilton Avenue, Suite 110
Campbell, CA 95008
Telephone (408) 558-8500
FAX (408) 558-8300
Internet: http://www.zilog.com
%QFGU
5RGGF /*\
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82KP2.%%
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' u%VQu%
'PXKTQPOGPVCN %2NCUVKE5VCPFCTF
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<5 2 5 % KUC<5/*\2KP&+2VQ%2NCUVKE5VCPFCTF(NQY
'PXKTQPOGPVCN(NQY
6GORGTCVWTG
2CEMCIG
5RGGF
2TQFWEV0WODGT
<K.1)2TGHKZ
