ie FE EI INTEL CORP (UP/PRPHLS) ede D M 442b175 0075078 6 . 8 | PRELIMINARY intel 2 MCS-51 T-#9-+19-07 8-BIT CONTROL-ORIENTED MICROCOMPUTERS 8031/8051 : 8031AH/8051AH 8032AH/8052AH 8751H/8751H-8 High Performance HMOS Process = Boolean Processor Internal Timers/Event Counters m Bit-Addressable RAM 2-Level Interrupt Priority Structure m Programmable Full Duplex Serial 32 1/0 Lines (Four 8-Bit Ports) Channel 64K Program Memory Space . m 111 instructions (64 Single-Cycle) Security Feature Protects EPROM Parts 64K Data Memory Space Against Software Piracy The MCS-51 products are optimized for control applications. Byte-processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc- tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit manipulation and testing in control and logic systems that require Boolean processing. The 8051 is the original member of the MCS-51 family. The 8051AH is identical to the 8051, but it is fabricated with HMOS II technology. The 8751H is an EPROM version of the 8051AH; that is, the on-chip Program Memory can be electrically programmed, and can be erased by exposure to ultraviolet light. it is fully compatible with its predecessor, the 8751-8, but incorporates two new features: a Program Memory Security bit that can be used to protect the EPROM against unauthorized read-out, and a programmable baud rate modification bit (SMOD). The 8751 H-8 is identical to the 8751H but only operates up to 8 MHz. The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is fabricated with HMOS II technology. The 8052AH enhancements are listed in the table below. Also refer to this table for the ROM, ROMless, and EPROM versions of each product. Internal Memory Timers/ Device Program Data Event Counters interrupts 8052AH 8K x 8 ROM 256 x 8 RAM 3 x 16-Bit 6 8051AH 4K x8 ROM 128 x8 RAM 2x 16-Bit 5 8051 4K x8 ROM 128 x8 RAM 2x 16-Bit 5 8032AH none 256 x 8 RAM 3x 16-Bit 6 8031AH none 128 x 8 RAM 2x 16-Bit 5 8031 none 128 x 8 RAM 2x 16-Bit 5 8751H 4K x 8 EPROM 128 x 8 RAM 2x 16-Bit 5 8751H-8 4K x 8 EPROM 128 x 8 RAM 2x 16-Bit 5 . October 1988 7-44 Order Number: 270048-004INTEL CORP (UP/PRPHLS) cOE D MMW 4426175 0079079 T me intel Mcse-51 PRELIMINARY T-49-19-07 g fl: ORIVERS 3 FC Tuo 7 INCRERENTER iP INTERRUPT, PORT ANC TIMER BLOCKS 2) F Sl Vo SE LLL PLO? P3.0-PL7 270048-1 Figure 1. MCS-51 Block Diagram a Port 0: Port 0 is an 8-bit open drain bidirectional I/O PACKAGES - port. As an output port each pin can sink 8 LS TTL Part Prefix Package Type inputs. 8051AH/ P 40-Pin Plastic DIP 8031AH D 40-Pin CERDIP Port 0 pins that have 1s written to them float, and in . N 44-Pin PLCC that state can be used as high-impedance inputs. S052AH/ P 40-Pin Plastic DIP Port 0 is also the multiplexed low-order address and 8032AH D 40-Pin CERDIP . N 44-Pin PLCC data bus during accesses to external Program and - Data Memory. In this application it uses strong inter- 8751H/ D 40-Pin GERDIP nal pullups when emitting 1s and can source and 8751H-8 _R 44-Pin LCC sink 8 LS TTL inputs. Port 0 also receives the code bytes during program- PIN DESCRIPTIONS ming of the EPROM parts, and outputs the code bytes during program verification of the ROM and Vec: Supply voltage. EPROM parts. External pullups are required during program verification. : Vgs: Circuit ground. 7-45 Te f fe b 'ea \ i i i awe et, INTEL CORP (UP/PRPHLS) 206 D mm 4426175 0079080 b @ intel wes-54 PRELIMINARY 6052/8032 ONLY 7 | 12 Proc XY 0B vee a. 8898 Tex Put Cl2 391 P0.0 ADO DEX EE eee P1213 383 Po.1 AO1 CORNER sede? 8322 P1306 377) Po.2 AD2 Sonat P1405 36 [2 P0.3 AD3 Ha iy] i ee P1s C16 35 (7) P0.4 ADA P15 [o> tH] P0.4 (AD4) P16 C7 3413 P05 ADS P16 [e} 34] PO.5 (ADS) P1.7Cl8 335 Po0.6 ADS P17 [33 {321 Po.6 (AD6) ast C19 32|5) P0.7 A07 AST fi63 {8 ] PO? (AD7) AXD P3.0 C] 10 317 EAVpp* (AXD) P2.0 [473 3] EA/Vpp* TXO P3.1 ow 307 ALE/PROG* a tay Ne INTO P9.2 C12 28 F) PSEN (1X0) P3.1 1353 C3] ALE/PROG" INTi P3.3 C113 28 (5) P27 Ais Unto) P32 Hi cul BEEN 10 P3.4 C18 272 p2.6a1s 33 a7 (INTE) P33 [537 ii] P2.7 (A18) 11 P35 Cts 26 (7) p25 A139 sea sas wt (To) P34 [333 38] P26 (A14) WR P3.6 Cl 16 25(7) P24 A12 2) P38 {31 * RO P37 C17 246 P23 att 8 yey eng tp Pes A) XTAL2 Cl 18 23173 P2.2 ato : 4 ra aa XTALI Ch19 - 22D p2.4 ag enyn poss = Ves 20 217 P2.0 as gaaaf2aagas gakk g2e28 BE Slee Pin (DIP) 970048-8 Pad (LCC, PLCC) *EPROM only Figure 2. MCS-51 Connections Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/ source 4 LS TTL inputs. Port 1 pins that have 1s written to them are pulled high by the internal pull- ups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (Ij_ on the data sheet) be- cause of the internal pullups. Port 1 also receives the low-order address bytes during programming of the EPROM parts and during program verification of the ROM and EPROM parts. In the 8032AH and 8052AH, Port 1 pins P1.0 and P1.1 also serve the T2 and T2EX functions, respec- tively. Port 2: Port 2 is an 8-bit bidirectional [/O port with internal pullups. The Port 2 output buffers can sink/ source 4 LS TTL inputs. Port 2 pins that have ts written to them are pulled high by the internal, pull- ups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lj_ on the data sheet) be- cause of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullups when emitting 1s. Dur- ing accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits dur- ing programming of the EPROM parts and during program verification of the ROM and EPROM parts. Port 3: Port 3 is an 8-bit bidirectional 1/O port with internal pullups, The Port 3 output buffers can sink/ source 4 LS TTL inputs. Port 3 pins that have 1s written to ther are pulled high by the internal pull- ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lj, on the data sheet) be- cause of the pullups. Port 3 also serves the functions of various special features of the MCS-51 Family, as listed below: Port Pin Alternative Function P3.0 | RXD (serial input port) P3.1 | TXD (serial output port) P3.2 | INTO (external interrupt 0) P3.3 | INT (external interrupt 1) P3.4 {| TO (Timer 0 external input) P3.5 | Ti (Timer 1 external input): P3.6 | WR (external data memory write strobe) P3.7 | RD (external data memory read strobe) 7-46__ ee ede D mm 48eb175 CO79I081 & ast mtr \Bigy> INTEL Corp (UP/PRPHLS) intel MCS-51 PRELIMINARY RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the de- vice. ALE/PROG:; Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during programming of the EPROM parts. In normal operation ALE is emitted at a constant rate of the oscillator frequency, and may be used for external timing or clocking purposes. Note, how- ever, that one ALE pulse is skipped during each ac- cess to external Data Memory. PSEN: Program Store Enable is the read strobe to external Program Memory. When the device is executing code from external Program Memory, PSEN is activated twice each ma- chine cycle, except that two PSEN activations are skipped during each access to external Data Memo- ty. EA/Vpp: External Access enable EA must be strapped to Vgg in order to enable any MCS-51 de- vice to fetch code from external Program _memory locations starting at COOOH up to FFFFH. EA must be strapped to Vcc for internal program execution. Note, however, that if the Security Bit in the EPROM devices is programmed, the device will not fetch code from any location in external Program Memory. This pin also receives the 21V programming supply voltage (VPP) during programming of the EPROM Parts, ar [ XTAL2 Cc van a ~ c1 XTALI vss i - 270048-4 G1, C2 = 30 pF 10 pF for Crystals - = 40 pF 10 pF for Ceramic Resonators Figure 3. Oscillator Connections T-49-19-07 XTAL1: Input to the inverting oscillator amplifier. XTAL2: Output from the inverting oscillator amplifi- er. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respec- tively, of an inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in Figure 3. Either a quartz crystal or ceramic resonator may be used. More detailed information concerning the use of the on-chip oscillator is available in Appii- cation Note AP-155, Oscillators for Microcontrol- lers. ' To drive the device from an external clock source, XTAL1 should be grounded, while XTAL2 is driven, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the Data Sheet must be observed. EXTERNAL - OSCILLATOR +4._ x TaL2 SIGNAL XTAL1 vSs => 270048-5 Figure 4. External Drive Configuration DESIGN CONSIDERATIONS If an 8751BH or 8752BH may replace an 8751H ina. future design, the user should carefully compare both data sheets for DC or AC Characteristic differ- ences. Note that the Vixy and | specifications for the EA pin differ significantly between the devices. Exposure to light when the EPROM device is in op- eration may cause logic errors. For this reason, it is suggested that an opaque label be placed over the window when the die is exposed to ambient light. _INTEL CORP (UP/PRPHLS) intel eOE PD MM 4426175 00759082 T MCS-51 PRELIMINARY ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias ...... 0C fo 70C Storage Temperature .......... 65C to + 150C Voltage on EA/Vpp Pin to Vgg ... 0.5V to +21.5V Vaitage on Any Other Pin to Vgg ....0.5V to +7V ~ 7249-19-07 *Notice: Stresses above those listed under Abso- lute Maximum Ratings" may cause permanent dam- _ age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Ex- posure to absolute maximum rating conditions for Power Dissipation... 2... sccees eens er eee LEW extended periods may affect device reliability. D.C. CHARACTERISTICS Ta = 0C to 70C; Veo = 5V +10%; Vag = OV 7 Symbol Parameter Min Max Units | Test Conditions Vit Input Low Voltage (Except EA Pin of -0.5 0.8 V , 8751H & 8751H-8) ; . Vina Input Low Voltage to EA Pin of 0 0.7 V 8751H & 8751H-8 ; Vin Input High Voltage (Except XTAL2, - 2.0 {Voc t+ 0.8] V RST) Vind Input High Voltage to XTAL2, RST 2.5 |Voo + 0.5} V. | XTAL1 = Vss VoL Output Low Voltage (Ports 1, 2, 3)* 0.45 Vo |lot = 1.6 mA Vou Output Low Voltage (Port 0, ALE, PSEN)* . 8751H, 8751H-8 0.60 Vo [lop = 3.2mA 0.45 V_ [lon = 2.4 mA All Others . 0.45 Vo ilot = 3.2mA Vou Output High Voltage (Ports 1, 2,3, ALE, PSEN) | 2.4 V [low = 80 pA VoHi Output High Voltage (Port 0 in 2.4 Vo ilon = 400 pA External Bus Mode) Ihe Logical 0 Input Current (Ports 1, 2, 3, RST) 8032AH, 8052AH ~800 | pA | Vin = 0.45V All Others 500 pA | Vin = 0.45V tha Logical 0 Input Current to EA Pin of 15 mA | Vin = 0.45V ~ 8751H & 8751H-8 Only . lite Logical 0 Input Current (XTAL2) 3.2 mA | Vin = 0.45V thy Input Leakage Current (Port 0) 8751H & 8751H-8 +100 pA 10.45 < Vin < Voo All Others +10 pA |0.45 < Vin < Voc lH Logical 1 Input Current to EA Pin of 500 pA | Vin = 2.4V 8751H & 8751H-8 : lad Input Current to RST to Activate Reset 500 BA 1 Vin < Voc 1.5V) loc Power Supply Current: 8031/8051 . 160 mA 8031AH/8051AH 125 mA | All Outputs 8032AH/8052AH 175 mA | Disconnected; 8751H/8751H-8 250 mA_| EA = Vcc. Clo Pin Capacitance | 10 pF | Test freq = 1 MHz *NOTE: Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo_s of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 7-48 ce ES SC TR edINTEL CORP (UP/PRPHLS) intel MCS-51 20E D mm 48ecbirs 0073063 1 PRELIMINARY T-49-19~07 A.C. CHARACTERISTICS Ta = 0C to +70C; Voc = 5V 10%; Vgg = OV; Load Capacitance for Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max 1/TCLCL | Oscillator Frequency : 3.5 12.0 MHz TLHLL ALE Pulse Width 127 2TCLCL40 ns TAVLL Address Valid to ALE Low 43 TGLCL40 ns TLLAX Address Hold after ALE Low 48. TCLCL35 ns TLLIV ALE Low to Valid Instr In 8751H 183 4TCLCL 150 ns All Others 233 4TCLCL 100 ns TLLPL ALE Low to PSEN Low 58 TCLCL25 ns TPLPH PSEN Pulse Width 8751H 190 3TCLCL60 ns All Others 215 8TCLCL-35 ns TPLIV PSEN Low to Valid Instr In , 8751H 100 S8TCLCL- 150 ns All Others 125 8TCLCL 125 ns TPXIX Input Instr Hold after PSEN 0 0 ns TPXIZ Input Instr Float after PSEN 63 , TCLOL20 ns TPXAV PSEN to Address Valid 75 TCLCL-8 ns TAVIV Address to Valid Instr In 8751H 267 5TCLCL150 } ns |__ All Others 302 5TCLCL-115 ns TPLAZ PSEN Low to Address Float 20 20 ns TRLRH | RD Pulse Width 400 6TCLCL 100 ns TWLWH_ | WR Pulse Width 400 6TCLGL 100 ns TRLDV RD Low to Valid Data In 252 5TCLCL 165 ns" TRHDX | Data Hold after RD O 0 ns TRHDZ_ | Data Float after AD 97 2TCLCL70 | ns TLLDV - ALE Low to Valid Data In 517 8TCLCL 150 ns TAVDV Address to Valid Data In 585 9TCLCL 165 ns TLLWL | ALE Low to RD or WR Low 200 300 38TCLCL50 | 3TCLCL+50 ns TAVWL_ | Address to RD or WR Low 203 ATCLCL- 130 ns TQVWX | Data Valid to WR Transition 8751H 13 TCLCL70 ns All Others 23 TCLCL60 ns TQVWH_| Data Valid to WR High 433 7TCLGL 150 ns TWHQX_ | Data Hold after WR 33 TCLCL50 ns TRLAZ RD Low to Address Float 20 20 ns TWHLH_ | RD or WR High to ALE High 8751H - 33 133 TCLCL50 TGLCL + 50 ns All Others 43 123 TCLGCL40 TCLCL + 40 ns NOTE; *This table does not include the 8751-8 A.C, characteristics (see next page).TURNS TSS ae my REET | WEEE. INTEL CORP (UP/PRPHLS) intel 2e0E OD MM 4426175 0079084 3 MCS-51 This Table is only for the 8751H-8 PRELIMINARY (T-49-19-07. A.C. CHARACTERISTICS Ta = 0C to + 70C; Voc = 5V 10%; Vsg = OV; Load Capacitance for Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF Symbol Parameter 8 MHz Oscillator Variable Oscillator Units Min Max Min Max 1/TCLCL | Oscillator Frequency 3.5 8.0 - MHz TLHLL =| ALE Pulse Width 210 2TCLCL40 ns TAVLL | Address Valid to ALE Low 85 TCLCL40 ns TLLAX Address Hold after ALE Low 90 TCLCL35 ns TLUV | ALE Low to Valid Instr In 350 4TCLCL150 | ns TLLPL ALE Low to PSEN Low 100 TCLCL25 ns TPLPH | PSEN Pulse Width 315 3TCLCL60 ns TPLIV PSEN Low to Valid Instr In 225 3TCLCL150 | ns TPXIX Input Instr Hold after PSEN 0 0 ns TPXIZ Input Instr Float after PSEN 105 TCLCOL--20 ns TPXAV | PSEN to Address Valid 117 TCLCL8 ns TAVIV | Address to Valid Instr In 475 5TCLCL150 | ns TPLAZ PSEN Low to Address Float 20 20 ns TRLRH | RD Pulse Width 650 6TCLCL100 ns TWLWH | WR Pulse Width 650 6TCLCL100 ns TRLDV =| AD Low to Valid Data In 460 STCLCL165-| ns TRHDX | Data Hold after RD 0 0 ns TRHDZ | Data Float after RD 180 2TCLCL70 | ns TLLDV | ALELow to Valid Data In 850 8TCLCL150 | ns TAVDV_ | Address to Valid Data In 960 9TCLCL165 | ns TLLWL =| ALE Low to RD or WR Low 325 425 | 3TCLCL50 | 3TCLCL+50 ns TAVWL_ | Address to RD or WR Low 370 4TCLCL130 ns TQVWX | Data Valid to WR Transition 55 TCLCL70 ns TQVWH_ | Data Valid to WR High 725 7TCLCL150 ns TWHQX | Data Hold after WR 75 TCLCL-50 ns TRLAZ RD Low to Address Float 20 20 ns TWHLH | RD or WR High to ALE High 75 175 | TCLCL50 | TCLCL+50 ns 7-50oe REE SOR WAT INTEL CORP (UP/PRPHLS) intel ede D M@ 4826175 0079085 5 MCS-51 PRELIMINARY EXTERNAL PROGRAM MEMORY READ CYCLE PORT 2 TLHLL TAVLL R 7-49-19-07 _- A8-A1S 270048-6 7-51INTEL CORP (UP/PRPHLS) 2e0 D MM 4426175 0079086 7 intel | Mcs-51 PRELIMINARY _T-49-19- EXTERNAL DATA MEMORY READ CYCLE 49-19-07 AQ-AT FROM RIOR DATAIN TAVWL TAVDY P2.0-P2.7 OR A8-A15 FROM OPH . AS-A15 FROM PCH 270048-7 EXTERNAL DATA MEMORY WRITE CYCLE TLHLL TWHLH 4 L - ALE / \ / rea _/ \ y | TLLWL # TWLWH yp wa Ve >| TOVWX TWHOX TLLAX , we : TAVLL be TOVWH Y A0-A7 A0-A7 INSTR PORTO FROM RIOR ou DATA OUT / FROM PCL IN < TAVWL PORT 2 x P2.0-P2.7 OR A8-A1S FROM DPH x A6-A15 FROM PCH 1 270048-8 7-62INTEL CORP (UP/PRPHLS) edge D = UB2b175 0079047 7 = intel : Mcse-51 PRELIMINARY A AIRE SEE IEE NIRS, LACS EN T-49-19-07 SERIAL PORT TIMINGSHIFT REGISTER MODE - : Test Conditions: Ta = 0C to 70C; VCG = 5V 10%; VSS = OV: Load Capacitance = 80 oF Symbol Parameter 12 MHz Oscillator Varlable Oscillator Units Min Max Min Max TXLXL | Serial Port Clock Cycle Time 1.0 12TCLCL ps TQVXH | Output Data Setup to Clock Rising} 700 10TCLCL 133 : ns Edge TXHQX | Output Data Hold after Clock 60 2TCLCL117 > ns Rising Edge : : TXHDX | Input Data Hold after Clock Rising 0 0 ns Edge TXHDV | Clock Rising Edge to Input Data . 700 1OTCLCL133; ns Valid . SHIFT REGISTER TIMING WAVEFORMS mmc foe foe Pot Poe foe Fe fe Pe Pt LAL -e mn >} rece LiTLlS wi ULF Li LSP LSP LS fe rove] Jae tenor | outrarout VF TFK TFT TFT FO | Jf i Wott To saue rwov +>| [e-rn0 wooo =), GD C=), GD C=) GDC), GDC), GD CD GD CDC an SUGAR 270048-9 7-53000 ee INTEL CORP (UP/PRPHLS) COE D Mt YSebh7s 0079088 0 m@ intl = Mese-51 PRELIMINARY . T-49-19-07 EXTERNAL CLOCK DRIVE - ~ - Symbol Parameter. : Min Max Units 1/TGLCL Oscillator Frequency (except 8751H-8) 3.5 12 =: MHz 8751H-8 - . 3.6 - 8 MHz TGHCX High Time 20 ons TCLCX Low Time 20 ons TCLCH Rise Time 20 ns TGHCL Fall Time 20 - ns-. EXTERNAL CLOCK DRIVE WAVEFORM Ht TCHCX >} ToLCH] ~| je rere as 25 / 25 \ f \ 08 0.8 p+ TCLEX . ~ TeLeL > 270048-10 A.C. TESTING INPUT, OUTPUT WAVEFORM a 2.0 2.0 > TEST POWTS < aus oe oe 270048-11 AC. Testing: Inputs are driven at 2.4V for a Logic 1" and 0.45V for a Logic "0". Timing measurements are made at 2.0V fora | Logic 1" and 0.8V for a Logic O". 7-54INTEL CORP (UP/PRPHLS) 20EF D @@ 4426175 0079089 2 _ VW i: \ H - he ry ae intel Mc5e-51 PRELIMINARY T-49-19-07 EPROM CHARACTERISTICS . - Table 3. EPROM Programming Modes Mode RST PSEN ALE EA P2.7 P2.6 P2.5 P2.4 Program 1 0 o* VPP 1 0 X X Inhibit 1 0 1 4 1 0 X X Verity 1 9 1 1 0 0 x x Security Set 1 0 o* VPP 1 1 X X NOTE: {"" = logic high for that pin O" = logic low for that pin X" = don't care Programming the EPROM To be programmed, the part must be running with a 4 to 6 MHz oscillator. (The reason the oscillator needs to be running is that the internal bus is being used to transfer address and program data to appro- priate internal registers.) The address of an EPROM location to be programmed is applied to Port 1 and pins P2.0-P2.3 of Port 2, while the code byte to be programmed into that location is applied to Port_0. The other Port 2 pins, and RST, PSEN, and EA should be held at the Program levels indicated in Table 3. ALE is pulsed low for 50 ms to program the code byte into the addressed EPROM location. The setup is shown in Figure 5. Normally EA is held at a logic high until just before ALE is to be pulsed. Then EA is raised to +21V, ALE Is pulsed, and then EA is returned to a logic high. Waveforms and detailed timing specifications are shown in later sections of this data sheet. +5V ve J PL PO KK PGM DATA P2.0- P23 751K Xw] p24 = DON'T GARE ~~) P25 ALE ALE PROG va >] e265 50 ms PULSE TO GND Viti e4 2.7 XTAL2 EA be EAvep lz re To TALI RAST e VI H vss PSEN rl] 270048-12 Figure 5, Programming Configuration VPP" = +21V +0,5V - *ALE is pulsed tow for 50 ms, Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level of 21.5V for any amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The VPP source should be well regulated and free of glitches. Program Verification If the Security Bit has not been programmed, the on- chip Program Memory can be read out for verifica- tion purposes, if desired, either during or after the programming operation. The address of the Program Memory location to be read is applied to Port 1 and pins P2.0-P2.3. The other pins should be held at the Verify levels indicated in Table 3. The contents of the addressed location will come out on Port 0. Ex- ternal pullups are required on Port 0 for this opera- tion. The setup, which is shown in Figure 6, is the same as for programming the EPROM except that pin P2.7 is held at a logic low, or may be used as an active- low read strobe. +5V J vec A0-a? PA PGM aoa. po EN, bara O000HOFFFH P20- + use 10K AG-AN YN 523 PULLUPS) 875tH xmd P2. X = "DON'T CARE" p24 Xel p25 ALE oe VL} P26 P b ENABLE ] 2.7 EA XTAL2 Lk 4-02 + RST Vint XTALI res mah Figure 6. Program Verification 270048-13INTEL CORP (UP/PRPHLS) intel MCS-51 eOE PD MM 4426175 0079090 9 PRELIMINARY EPROM Security The security feature consists of a locking bit which when programmed denies electrical access by any external means to the on-chip Program Memory. The bit is programmed as shown in Figure 7. The setup and procedure are the same as for normal _ EPROM programming, except that P2.6 is held ata logic high. Port 0, Port 1, and pins P2.0-P2.3 may be in any state. The other pins should be held at the Security levels indicated in Table 3. Once the Security Bit has been programmed, it can be cleared only by full erasure of the Program Mem- ory. While it is programmed, the internal Program Memory can not be read out, the device can not be further programmed, and it can not execute out of external program memory. Erasing the EPROM, thus clearing the Security Bit, restores the device's full functionality. It can then be reprogrammed. Erasure Characteristics Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have wavelengths in this _ range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadver- tent erasure. If an application subjects the device to this type of exposure, itis suggested that an opaque ~ label be placed over the window. T-49-19-07 + X = DON'T CARE" Nv - vec J =< rT) wk _ 20- P23 a75tH } P P24 ALE [-* ALE/PROG P25 50 ms PULSE TO GND ge! eT P26 . P27 EA [-+ EAvep XTAL2 < = 5 SteSL RST -e VIH1 HO x XTALt re Figure 7. Programming the Security Bit PSEN 270048-14 The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrat- ed dose of at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 pW/cm? rating for 20 to 30 minutes, at a distance of about 1 inch, should be sufficient. : : Erasure leaves the array in an all 1s state. EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Ta = 21C to 27C; VCC = 5V 10%; VSS = OV Symbol Parameter Min Max Units VPP. Programming Supply Voltage 20.5 21,5 Vv IPP Programming Supply Current 30 mA ~ 4/TCLOL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold after PROG - 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold after PROG 48TCLCL TEHSH P2.7 (ENABLE) High to VPP 48TCLCL ; . TSHGL VPP Setup to PROG Low 10 Bs TGHSL VPP Hold after PROG 10 ; MS TGLGH PROG Width 45 55 ms TAVQV Address to Data Valid 48TCLCL TELQV ENABLE Low to Data Valid 48TCLCL TEHQZ Data Float after ENABLE 0 48TCLCL 7-56INTEL CORP (UP/PRPHLS) eOE p MM 48ecbi?s 0079091 0 intel Mcse51 PRELIMINARY EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION oO P1.0-F1.7 b_ . \ P2.0-P23 4 ADDRESS y ADDRESS pt TAVOV / y PORTO : DATA IN y DATA OUT TOVGL P] TGHOX . TAVGL _ >] TGHAX ALE/PROG mm : ' TSHGL TGLGH GHSL 21V + SV Ex/ver TTL HIGH / AIL HIGH TTL HIGH TTL HIGH TEHSH + TELQY i] TEHOZ P27 (ENABLE) f 270048~15 For programming conditions see Figure 5. For verification conditions see Figure 6. DATA SHEET REVISION SUMMARY The following are the key differences between this and the -003 version of this data sheet: 1. Introduction was expanded to include product descriptions, 2. Package table was added. 3. Design Considerations added. 4. Test Conditions for hL4 and lj specitications added to the DC Characteristics. 5. Data Sheet Revision Summary added. 7-57 soa als toy PE AK