www.irf.com 1
9/15/03
IRF3704ZCS
IRF3704ZCL
HEXFET® Power MOSFET
Notes through are on page 11
Applications
Benefits
lLow RDS(on) at 4.5V VGS
lUltra-Low Gate Impedance
lFully Characterized Avalanche Voltage
and Current
lHigh Frequency Synchronous Buck
Converters for Computer Processor Power
PD - 94782
D2Pak
IRF3704ZCS TO-262
IRF3704ZCL
VDSS RDS(on) max Qg
20V 7.9m:8.7nC
Absolute Maximum Ratings
Parameter Units
VDS Drain-to-Source Voltage V
VGS Gate-to-Source Voltage
ID @ TC = 25°C Continuous Drai n Current, VGS @ 10V A
ID @ TC = 100°C Continuous Drai n Current, VGS @ 10V
IDM Pulsed Drai n Current
c
PD @TC = 25°C Maximum Power Dissipation W
PD @TC = 100°C Maximum Power Dissipation
Linear Derating Fac t or W/°C
TJ Operating Junction and °C
TSTG Storage Temperat ure Range
Soldering Temperat ure, for 10 sec onds
Thermal Resistance Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 2.65 °C/W
RθJA Junct i on-to-Ambient (P CB Mount)
f
––– 40
57
0.38
28
Max.
67
g
47
g
260
± 20
20
300 (1.6mm f rom case)
-55 to + 175
IRF3704ZCS/L
2www.irf.com
S
D
G
Static @ TJ = 25°C ( unl ess otherwise specif i ed)
Parameter Min. Typ. Max. Units
BVDSS Drain-to-S ource Breakdown Vol tage 20 ––– ––– V
∆ΒVDSS
/
∆TJ Break down V ol tage Temp. Coefficient ––– 0.014 ––– V/°C
RDS(on) Static Drai n-t o -S ource On-Resis t ance ––– 6.3 7.9 mΩ
––– 8.9 11.1
VGS(th) Gate Threshol d V ol tage 1.65 2. 1 2.55 V
∆VGS(th)
/
∆TJ Gate Threshold Voltage Coeff i cient ––– -5.6 ––– mV/°C
IDSS Drain-to-S ource Leakage Current ––– ––– 1.0 µA
––– ––– 150
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leak age ––– ––– -100
gfs Forward Transconductance 48 ––– ––– S
QgTotal Gate Charge ––– 8.7 13
Qgs1 Pre-Vth Gate-t o-Source Charge ––– 2.9 –––
Qgs2 Post-Vth Gate-to-Source Charge ––– 1.1 ––– nC
Qgd Gate-to-Drain Charge ––– 2.3 –––
Qgodr Gate Charge Overdriv e ––– 2.4 ––– See Fig. 16
Qsw Switc h Charge (Q gs2 + Qgd)––– 3.4 –––
Qoss Output Charge ––– 5.6 ––– nC
td(on) Turn-On Delay Time ––– 8.9 –––
trRise Time ––– 38 –––
td(off) Turn-Off Del ay Ti m e ––– 11 ––– ns
tfFall Time ––– 4.2 –––
Ciss Input Capacit ance ––– 1220 –––
Coss Output Capacit ance ––– 390 ––– pF
Crss Reverse Transfer Capacitance ––– 190 –––
Avalanche Characterist i cs
Parameter Units
EAS Single Pul se Avalanche Energy
d
mJ
IAR Avalanche Current
c
A
EAR Repetitive Avalanche Energy
c
mJ
Diode Characterist i cs
Parameter Min. Typ. Max. Units
ISContinuous S ource Current ––– ––– 67
g
(Body Diode) A
ISM Pulsed S ource Current ––– ––– 260
(Body Diode)
c
VSD Diode Forward Voltage ––– ––– 1.0 V
trr Reverse Rec overy Time ––– 11 17 ns
Qrr Reverse Rec overy Charge ––– 2.3 3.5 nC
MOSFET symbol
VGS = 4.5V, I D = 17A
e
–––
VGS = 4.5V
Typ.
–––
–––
ID = 17A
VGS = 0V
VDS = 10V
TJ = 25°C, IF = 17A, V DD = 10V
di/dt = 100A/µs
e
TJ = 25°C, IS = 17A, V GS = 0V
e
showing the
integral rev erse
p-n juncti on di ode.
VDS = VGS, ID = 250µA
VDS = 16V, VGS = 0V
VDS = 16V, VGS = 0V, TJ = 125°C
Clamped Induc tive Load
VDS = 10V, I D = 17A
VDS = 10V, VGS = 0V
VDD = 10V, VGS = 4. 5V
e
ID = 17A
VDS = 10V
Conditions
VGS = 0V, ID = 250µA
Reference t o 25° C, ID = 1mA
VGS = 10V, ID = 21A
e
VGS = 20V
VGS = -20V
Conditions
5.7
Max.
36
17
ƒ = 1.0MHz
IRF3704ZCS/L
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Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1 110
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
60µs PULSE WIDTH
Tj = 25°C
3.0V
VGS
TOP 10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM 3.0V
0.1 110
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
60µs PULSE WIDTH
Tj = 175°C
3.0V
VGS
TOP 10V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM 3.0V
3.0 4.0 5.0 6.0 7.0 8.0
VGS, Gate-to-Source Voltage (V)
10.0
100.0
1000.0
ID, Drain-to-Source Current (Α)
VDS = 10V
60µs PULSE WIDTH
TJ = 25°C
TJ = 175°C
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 42A
VGS = 10V
IRF3704ZCS/L
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 5 10 15 20 25
QG Total Gate Charge (nC)
0
2
4
6
8
10
12
VGS, Gate-to-Source Voltage (V)
VDS= 16V
VDS= 10V
ID= 17A
0.0 0.5 1.0 1.5 2.0
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0 1 10 100
VDS , Drain-toSource Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN T H IS AREA
LIM ITED BY RDS(on)
100µsec
IRF3704ZCS/L
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature Fig 10. Threshold Voltage vs. Temperature
25 50 75 100 125 150 175
TC , Case Tem perature (°C)
0
10
20
30
40
50
60
70
ID , Drain Current (A)
LIMITED BY PACKAGE
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
0.6
1.0
1.4
1.8
2.2
2.6
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1E-006 1E-005 0.0001 0.001 0.01
t1 , Rectangular Pulse Durati on (sec)
0.001
0.01
0.1
1
10
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGL E PU LSE
( THERM AL R ESPO N SE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τi (sec)
0.920 0.000139
0.194 0.000602
0.538 0.001567
τJ
τJ
τ1
τ1τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
τ
τC
Ci= τi/Ri
Ci= τi/Ri
IRF3704ZCS/L
6www.irf.com
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
VGS
VDS
90%
10%
td(on) td(off)
trtf
VGS
Pulse Width < 1µ s
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
25 50 75 100 125 150 175
Starting TJ, Junct i on Tem perat ure (° C)
0
20
40
60
80
100
120
140
EAS, Single Pulse Avalanche Energy (mJ)
ID
TOP 5.6A
8.5A
BOTTOM 17A
IRF3704ZCS/L
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Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRF3704ZCS/L
8www.irf.com
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms 2×Rds(on)
()
+I×Qgd
ig
×Vin ×f
+I×Qgs2
ig
×Vin ×f
+Qg×Vg×f
()
+Qoss
2×Vin ×f
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
+Qrr ×Vin ×f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and of f there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
IRF3704ZCS/L
www.irf.com 9
D2Pak Part Marking Information
F530S
THIS IS AN IRF530S WITH
LOT CODE 8024
AS S E MB L E D ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
ASSEMBLY
LOT CODE
INT E RNAT IONAL
RECT IFIER
LOGO
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
DAT E CODE
IN THE ASSEMBLY LINE "L"
AS S E MB L E D ON WW 02, 2000
THIS IS AN IRF530S WITH
LOT CODE 8024 INT E RNAT IONAL
LOGO
RECTIFIER
LOT CODE
PART NUMBER
F530S
For GB Production
IRF3704ZCS/L
10 www.irf.com
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXA
MPLE:THIS IS A
N IRL3103L
LO
T C
O
DE 1789
A
SSEMBLY
PA
RT NUM
BER
DA
TE C
O
DE
W
EEK 19
LINE C
LOT C
O
DE
YEA
R 7 = 1997
A
SSEMBLED ON W
W 19, 1997
IN THE A
SSEMBLY LINE "C
"LO
G
O
REC
TIFIER
INTERNA
TIO
NA
L
IGBT
1- GATE
2- COLLEC-
TOR
IRF3704ZCS/L
www.irf.com 11
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/03
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.25mH, RG = 25Ω,
IAS = 17A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 42A.
D2Pak Tape & Reel Information
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECT IO N
10.90 (.429)
10.70 (.421) 16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1 .0 79 )
23.90 (. 94 1)
60.00 (2.362)
MIN.
30.40 (1 .197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.