SAR ADC
Control
Logic
Config
Register
I/O
Clock
Generator
SAR ADC
SAR ADC
SAR ADC
SAR ADC
SAR ADC
SAR ADC
SAR ADC
StringDAC 2.5/3V
Reference
CH_A0
CH_A1
CH_B0
CH_B1
CH_C0
CH_C1
CH_D0
CH_D1
REFIO
Parallel
orSerial
DataBus
Control
Signal
Bus
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
12-, 14-, 16-Bit, Eight-Channel, Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTERS
Check for Samples: ADS8528,ADS8548,ADS8568
1FEATURES DESCRIPTION
The ADS8528/48/68 contain eight low-power, 12-,
2•Family of 12-, 14-, 16-Bit, Pin- and 14-, or 16-bit, successive approximation register
Software-Compatible ADCs (SAR)-based analog-to-digital converters (ADCs) with
•Maximum Data Rate Per Channel: true bipolar inputs. These channels are grouped in
–ADS8528: 650kSPS (PAR) or four pairs, thus allowing simultaneous high-speed
signal acquisition of up to 650kSPS.
480kSPS (SER)
–ADS8548: 600kSPS (PAR) or The devices support selectable parallel or serial
450kSPS (SER) interface with daisy-chain capability. The
programmable reference allows handling of analog
–ADS8568: 510kSPS (PAR) or input signals with amplitudes up to ±12V.
400kSPS (SER) The ADS8528/48/68 family supports an auto-sleep
•Excellent AC Performance: mode for minimum power dissipation and is available
–Signal-to-Noise Ratio: in both QFN-64 and LQFP-64 packages. The entire
ADS8528: 73.9dB family is specified over a temperature range of –40°C
ADS8548: 85dB to +125°C.
ADS8568: 91.5dB
–Total Harmonic Distortion:
ADS8528: –89dB
ADS8548: –91dB
ADS8568: –94dB
•Programmable and Buffered Internal
Reference: 0.5V to 2.5V or 0.5V to 3.0V
Supports Input Voltage Ranges of Up to ±12V
•Selectable Parallel or Serial Interface
•Scalable Low-Power Operation Using
Auto-Sleep Mode: Only 32mW at 10kSPS
•Fully Specified Over the Extended Industrial
Temperature Range
APPLICATIONS
•Protection Relays
•Power Quality Measurement
•Multi-Axis Motor Control
•Programmable Logic Controllers
•Industrial Data Acquisition
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FAMILY/ORDERING INFORMATION(1)
MAXIMUM DATA RATE:
RESOLUTION PAR/SER SNR THD
PRODUCT (Bits) (kSPS/ch) (dB, typ) (dB, typ)
ADS8528 12 650/480 73.9 –89
ADS8548 14 600/450 85 –91
ADS8568 16 510/400 91.5 –94
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. VALUE UNIT
HVDD to AGND –0.3 to 18 V
HVSS to AGND –18 to 0.3 V
Supply voltage AVDD to AGND –0.3 to 6 V
DVDD to DGND –0.3 to 6 V
Analog input voltage HVSS –0.3 to HVDD + 0.3 V
Reference input voltage with respect to AGND AGND –0.3 to AVDD + 0.3 V
Digital input voltage with respect to DGND DGND –0.3 to DVDD + 0.3 V
Ground voltage difference AGND to DGND ±0.3 V
Input current to all pins except supply ±10 mA
Maximum virtual junction temperature, TJ+150 °C
Human body model (HBM) ±2500 V
JEDEC standard 22, test method A114-C.01, all pins
ESD ratings Charged device model (CDM) ±500 V
JEDEC standard 22, test method C101, all pins
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION ADS8528/48/68
THERMAL METRIC(1) RGC PM UNITS
64 PINS 64 PINS
θJA Junction-to-ambient thermal resistance 22 48.5
θJCtop Junction-to-case (top) thermal resistance 9.0 9.4
θJB Junction-to-board thermal resistance 3.6 21.9 °C/W
ψJT Junction-to-top characterization parameter 0.1 0.3
ψJB Junction-to-board characterization parameter 2.9 21.4
θJCbot Junction-to-case (bottom) thermal resistance 0.3 n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2Copyright ©2011, Texas Instruments Incorporated
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
ELECTRICAL CHARACTERISTICS: ADS8528
All minimum/maximum specifications are at TA=–40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal),
VIN =±10V, and fDATA = max, unless otherwise noted. Typical values are at TA= +25°C, HVDD = 15V, HVSS = –15V,
AVDD = 5V, and DVDD = 3.3V. ADS8528
PARAMETER CONDITIONS MIN TYP MAX UNIT
SAMPLING DYNAMICS
Conversion time Internal conversion clock 1.33 μs
Serial interface, all four SDOx active 480 kSPS
Throughput rate fDATA Parallel interface 650 kSPS
DC ACCURACY
Resolution 12 Bits
No missing codes 12 Bits
Integral linearity error(1) INL –0.75 ±0.2 0.75 LSB
Differential linearity error DNL –0.5 ±0.2 0.5 LSB
Offset error –1.5 ±0.5 1.5 mV
Offset error matching –0.65 0.65 mV
Offset error drift ±3.5 μV/°C
Gain error Referenced to voltage at REFIO –0.5 ±0.25 0.5 %
Between channels of any pair –0.2 0.2 %
Gain error matching Between any two channels –0.4 0.4 %
Gain error drift Referenced to voltage at REFIO ±6 ppm/°C
AC ACCURACY
Signal-to-noise ratio SNR At fIN = 10kHz 73 73.9 dB
Signal-to-noise ratio + distortion SINAD At fIN = 10kHz 73 73.8 dB
Total harmonic distortion(2) THD At fIN = 10kHz –89 –84 dB
Spurious-free dynamic range SFDR At fIN = 10kHz 84 92 dB
Channel-to-channel isolation At fIN = 10kHz 120 dB
In 4VREF mode 48 MHz
–3dB small-signal bandwidth BW In 2VREF mode 24 MHz
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as the number of LSBs or percentage of the specified full-scale range.
(2) Calculated on the first nine harmonics of the input frequency.
Copyright ©2011, Texas Instruments Incorporated 3
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ELECTRICAL CHARACTERISTICS: ADS8548
All minimum/maximum specifications are at TA=–40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal),
VIN =±10V, and fDATA = max, unless otherwise noted. Typical values are at TA= +25°C, HVDD = 15V, HVSS = –15V,
AVDD = 5V, and DVDD = 3.3V. ADS8548
PARAMETER CONDITIONS MIN TYP MAX UNIT
SAMPLING DYNAMICS
Conversion time Internal conversion clock 1.45 μs
Serial interface, all four SDOx active 450 kSPS
Throughput rate fDATA Parallel interface 600 kSPS
DC ACCURACY
Resolution 14 Bits
No missing codes 14 Bits
Integral linearity error(1) INL –1±0.5 1 LSB
Differential linearity error DNL –1±0.25 1 LSB
Offset error –1.5 ±0.5 1.5 mV
Offset error matching –0.65 0.65 mV
Offset error drift ±3.5 μV/°C
Gain error Referenced to voltage at REFIO –0.5 ±0.25 0.5 %
Between channels of any pair –0.2 0.2 %
Gain error matching Between any two channels –0.4 0.4 %
Gain error drift Referenced to voltage at REFIO ±6 ppm/°C
AC ACCURACY
Signal-to-noise ratio SNR At fIN = 10kHz 84 85 dB
Signal-to-noise ratio + distortion SINAD At fIN = 10kHz 83 84 dB
Total harmonic distortion(2) THD At fIN = 10kHz –91 –86 dB
Spurious-free dynamic range SFDR At fIN = 10kHz 86 92 dB
Channel-to-channel isolation At fIN = 10kHz 120 dB
In 4VREF mode 48 MHz
–3dB small-signal bandwidth BW In 2VREF mode 24 MHz
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as the number of LSBs or percentage of the specified full-scale range.
(2) Calculated on the first nine harmonics of the input frequency.
4Copyright ©2011, Texas Instruments Incorporated
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ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
ELECTRICAL CHARACTERISTICS: ADS8568
All minimum/maximum specifications are at TA=–40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal),
VIN =±10V, and fDATA = max, unless otherwise noted. Typical values are at TA= +25°C, HVDD = 15V, HVSS = –15V,
AVDD = 5V, and DVDD = 3.3V. ADS8568
PARAMETER CONDITIONS MIN TYP MAX UNIT
SAMPLING DYNAMICS
Conversion time Internal conversion clock 1.7 μs
Serial interface, all four SDOx active 400 kSPS
Throughput rate fDATA Parallel interface 510 kSPS
DC ACCURACY
Resolution 16 Bits
No missing codes 16 Bits
At TA=–40°C to +85°C, QFN package (RGC) –3±1.5 3 LSB
At TA=–40°C to +125°C, QFN package (RGC) –4±1.5 4 LSB
Integral linearity error(1) INL At TA=–40°C to +85°C, LQFP package (PM) –4±1.5 4 LSB
At TA=–40°C to +125°C, LQFP package (PM) –4.5 ±1.5 4.5 LSB
At TA=–40°C to +85°C–1±0.75 1.75 LSB
Differential linearity error DNL At TA=–40°C to +125°C–1±0.75 2 LSB
Offset error –1.5 ±0.5 1.5 mV
Offset error matching –0.65 0.65 mV
Offset error drift ±3.5 μV/°C
Gain error Referenced to voltage at REFIO –0.5 ±0.25 0.5 %
Between channels of any pair –0.2 0.2 %
Gain error matching Between any two channels –0.4 0.4 %
Gain error drift Referenced to voltage at REFIO ±6 ppm/°C
AC ACCURACY
At fIN = 10kHz, TA=–40°C to +85°C 90 91.5 dB
Signal-to-noise ratio SNR At fIN = 10kHz, TA=–40°C to +125°C 89 91.5 dB
At fIN = 10kHz, TA=–40°C to +85°C 87 90 dB
Signal-to-noise ratio + distortion SINAD At fIN = 10kHz, TA=–40°C to +125°C 86.5 90 dB
At fIN = 10kHz, TA=–40°C to +85°C–94 –90 dB
Total harmonic distortion(2) THD At fIN = 10kHz, TA=–40°C to +125°C–94 –89.5 dB
At fIN = 10kHz, TA=–40°C to +85°C 90 95 dB
Spurious-free dynamic range SFDR At fIN = 10kHz, TA=–40°C to +125°C 89.5 95 dB
Channel-to-channel isolation At fIN = 10kHz 120 dB
In 4VREF mode 48 MHz
–3dB small-signal bandwidth BW In 2VREF mode 24 MHz
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as the number of LSBs or percentage of the specified full-scale range.
(2) Calculated on the first nine harmonics of the input frequency.
Copyright ©2011, Texas Instruments Incorporated 5
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
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ELECTRICAL CHARACTERISTICS: GENERAL
All minimum/maximum specifications are at TA=–40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal),
VIN =±10V, and fDATA = max, unless otherwise noted. Typical values are at TA= +25°C, HVDD = 15V, HVSS = –15V,
AVDD = 5V, and DVDD = 3.3V. ADS8528, ADS8548, ADS8568
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
RANGE pin/RANGE bit = 0 –4VREF 4VREF V
Bipolar full-scale range CHXX RANGE pin/RANGE bit = 1 –2VREF 2VREF V
Input range = ±4VREF 10 pF
Input capacitance Input range = ±2VREF 20 pF
Input leakage current No ongoing conversion –1 1 μA
Aperture delay 5 ns
Aperture delay matching Common CONVST for all channels 100 ps
Aperture jitter 50 ps
Power-supply rejection ratio PSRR At output code FFFFh, related to HVDD and HVSS –78 dB
REFERENCE VOLTAGE OUTPUT (REFOUT)
2.5V operation, REFDAC = 3FFh 2.485 2.5 2.515 V
2.5V operation, REFDAC = 3FFh at +25°C 2.496 2.5 2.504 V
Reference voltage VREF 3.0V operation, REFDAC = 3FFh 2.985 3.0 3.015 V
3.0V operation, REFDAC = 3FFh at +25°C 2.995 3.0 3.005 V
Reference voltage drift dVREF/dT ±10 ppm/°C
Power-supply rejection ratio PSRR At output code FFFFh, related to AVDD –77 dB
Output current IREFOUT DC current –2 2 mA
Short-circuit current(1) IREFSC 50 mA
Turn-on settling time tREFON 10 ms
At REF_xP/N pins 4.7 10 μF
External load capacitance At REFIO pin 100 470 nF
Tuning range REFDAC Internal reference output voltage range 0.2 VREF VREF V
REFDAC resolution 10 Bits
REFDAC differential nonlinearity DNLDAC –1±0.1 1 LSB
REFDAC integral nonlinearity INLDAC –2±0.1 2 LSB
REFDAC offset error VOSDAC VREF = 0.5V (DAC = 0CDh) –4±0.65 4 LSB
REFERENCE VOLTAGE INPUT (REFIN)
Reference input voltage VREFIN 0.5 2.5 3.025 V
Input resistance 100 MΩ
Input capacitance 5 pF
Reference input current 1 μA
(1) Reference output current is not limited internally.
6Copyright ©2011, Texas Instruments Incorporated
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
ELECTRICAL CHARACTERISTICS: GENERAL (continued)
All minimum/maximum specifications are at TA=–40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal),
VIN =±10V, and fDATA = max, unless otherwise noted. Typical values are at TA= +25°C, HVDD = 15V, HVSS = –15V,
AVDD = 5V, and DVDD = 3.3V. ADS8528, ADS8548, ADS8568
PARAMETER CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS(2)
Logic family CMOS with Schmitt-Trigger
High-level input voltage 0.7 DVDD DVDD + 0.3 V
Low-level input voltage DGND –0.3 0.3 DVDD V
Input current VI= DVDD to DGND –50 50 nA
Input capacitance 5 pF
DIGITAL OUTPUTS(2)
Output capacitance 5 pF
Load capacitance 30 pF
High-impedance-state output current –50 50 nA
Logic family CMOS
High-level output voltage VOH IOH = 100μA DVDD –0.6 V
IOH =–100μA DGND +
Low-level output voltage VOL V
0.4
POWER-SUPPLY REQUIREMENTS
Analog supply voltage AVDD 4.5 5.0 5.5 V
Buffer I/O supply voltage DVDD 2.7 3.3 5.5 V
Input positive supply voltage HVDD 5.0 15.0 16.5 V
Input negative supply voltage HVSS –16.5 –15.0 –5.0 V
ADS8528, fDATA = maximum 37.9 50.1 mA
ADS8548, fDATA = maximum 37.3 49.3 mA
ADS8568, fDATA = maximum 36.6 48.4 mA
fDATA = 250kSPS, auto-sleep mode 20.3 30.0 mA
fDATA = 200kSPS, auto-sleep mode 17 mA
Analog supply current IAVDD fDATA = 10kSPS, normal operation 30 mA
fDATA = 10kSPS, auto-sleep mode 4.6 mA
Auto-sleep mode, no ongoing conversion, 7.0 mA
internal conversion clock
Power-down mode 0.03 mA
fDATA = maximum 0.5 2.0 mA
fDATA = 250kSPS 0.5 1.4 mA
fDATA = 200kSPS 0.5 mA
Buffer I/O supply current IDVDD fDATA = 10kSPS 0.4 mA
Auto-sleep mode, no ongoing conversion, 0.35 mA
internal conversion clock
Power-down mode 0.01 mA
ADS8528, fDATA = maximum 3.0 4.2 mA
ADS8548, fDATA = maximum 2.8 3.9 mA
ADS8568, fDATA = maximum 2.3 3.2 mA
fDATA = 250kSPS 1.8 2.4 mA
Input positive supply current IHVDD fDATA = 200kSPS 1.5 mA
fDATA = 10kSPS 0.4 mA
Auto-sleep mode, no ongoing conversion, 0.45 mA
internal conversion clock
Power-down mode 0.01 mA
(2) Specified by design.
Copyright ©2011, Texas Instruments Incorporated 7
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ELECTRICAL CHARACTERISTICS: GENERAL (continued)
All minimum/maximum specifications are at TA=–40°C to +125°C, specified supply voltage range, VREF = 2.5V (internal),
VIN =±10V, and fDATA = max, unless otherwise noted. Typical values are at TA= +25°C, HVDD = 15V, HVSS = –15V,
AVDD = 5V, and DVDD = 3.3V. ADS8528, ADS8548, ADS8568
PARAMETER CONDITIONS MIN TYP MAX UNIT
POWER-SUPPLY REQUIREMENTS (continued)
ADS8528, fDATA = maximum 3.4 4.5 mA
ADS8548, fDATA = maximum 3.3 4.4 mA
ADS8568, fDATA = maximum 2.7 3.6 mA
fDATA = 250kSPS 2.1 2.6 mA
Input negative supply current IHVSS fDATA = 200kSPS 1.7 mA
fDATA = 10kSPS 0.4 mA
Auto-sleep mode, no ongoing conversion, 0.35 mA
internal conversion clock
Power-down mode 0.01 mA
ADS8528, fDATA = maximum 287.1 430.1 mW
ADS8548, fDATA = maximum 279.7 419.1 mW
ADS8568, fDATA = maximum 259.7 389.4 mW
fDATA = 250kSPS, auto-sleep mode 161.7 255.2 mW
fDATA = 200kSPS, auto-sleep mode 151.2 mW
Power dissipation(3)
fDATA = 10kSPS, normal operation 163.3 mW
fDATA = 10kSPS, auto-sleep mode 36.3 mW
Auto-sleep mode, no ongoing conversion, 53.6 mW
internal conversion clock
Power-down mode 0.6 mW
Operating ambient temperature TA–40 25 +125 °C
range
(3) Maximum power dissipation values are specified with HVDD = 15V and HVSS = –15V.
8Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8528 ADS8548 ADS8568
tDCVB
tBUFS
tDMSB
tHDO
tDTRI
tFSCV
tCVL
tSUDI tHDI
Don’tCare
132
tPDDO
CH_x1
LSB
CH_x1
D1
CH_x1
D2
CH_x1
D3
D31 D0
D1D2
D3
tSCVX
CH_x0
MSB
Don’tCare
CONVST_x
BUSY
(C27=C26=0)
FS
SCLK
SDO_x
XCLK
(C29=1)
SDIor
DCIN_x
tCONV tACQ
tXCLK
tSCLK
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
PARAMETER MEASUREMENT INFORMATION
TIMING CHARACTERISTICS
Figure 1. Serial Operation Timing Diagram (All Four SDO_x Active)
Copyright ©2011, Texas Instruments Incorporated 9
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PARAMETER MEASUREMENT INFORMATION (continued)
Table 1. Serial Interface Timing Requirements(1)(2)
ADS8528, ADS8548, ADS8568
TEST
PARAMETER CONDITION MIN TYP MAX UNIT
CONVST_x high to XCLK rising edge
tSCVX CLKSEL = 1 6 ns
setup time ADS8528 66.67 ns
tXCLK External conversion clock period ADS8548 72.46 ns
ADS8568 85.11 ns
ADS8528 1 15.0 MHz
External conversion clock frequency ADS8548 1 13.8 MHz
ADS8568 1 11.75 MHz
External conversion clock duty cycle 40 60 %
tCVL CONVST_x low time 20 ns
tACQ Acquisition time 280 ns
19 20 tCCLK or tXCLK
ADS8528, 1.33 μs
CLKSEL = 0
tCONV Conversion time ADS8548, 1.45 μs
CLKSEL = 0
ADS8568, 1.7 μs
CLKSEL = 0
tDCVB CONVST_x high to BUSY high delay 25 ns
tBUFS BUSY low to FS low time 0 ns
ADS8528 0 ns
Bus access finished to next conversion
tFSCV ADS8548 20 ns
start time ADS8568 40 ns
tSCLK Serial clock period 0.022 10 μs
Serial clock frequency 0.1 45 MHz
Serial clock duty cycle 40 60 %
tDMSB FS low to MSB valid delay 12 ns
tHDO Output data to SCLK falling edge hold time 5 ns
SCLK falling edge to new data valid
tPDDO 17 ns
propagation delay
tDTRI FS high to SDO_x three-state delay 10 ns
tSUDI Input data to SCLK falling edge setup time 3 ns
tHDI Input data to SCLK falling edge hold time 5 ns
(1) Over recommended operating free-air temperature range TA, AVDD = 5V, and DVDD = 2.7V to 5.5V, unless otherwise noted.
(2) All input signals are specified with tR= tF= 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2.
10 Copyright ©2011, Texas Instruments Incorporated
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CONVST_x
BUSY
(C27=C26=0)
CS
DB[15:0]
tDCVB
tCONV
tBUCS tCSCV
tCVL
RD
tCSRD
CH
A0
CH
A1
CH
B0
CH
B1
CH
C0
CH
C1
tRDCS
tPDDO
tRDL
tHDO
tRDH
CH
D0
CH
D1
tDTRI
tACQ
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
Figure 2. Parallel Read Access Timing Diagram
Table 2. Parallel Interface Timing Requirements (Read Access)(1)(2)
ADS8528, ADS8548, ADS8568
TEST
PARAMETER CONDITION MIN TYP MAX UNIT
tCVL CONVST_x low time 20 ns
tACQ Acquisition time 280 ns
19 20 tCCLK or tXCLK
ADS8528, 1.33 µs
CLKSEL = 0
tCONV Conversion time ADS8548, 1.45 µs
CLKSEL = 0
ADS8568, 1.7 µs
CLKSEL = 0
tDCVB CONVST_x high to BUSY high delay 25 ns
tBUCS BUSY low to CS low time 0 ns
ADS8528 0 ns
Bus access finished to next conversion
tCSCV ADS8548 20 ns
start time(3) ADS8568 40 ns
tCSRD CS low to RD low time 0 ns
tRDCS RD high to CS high time 0 ns
tRDL RD pulse width 20 ns
tRDH Minimum time between two read accesses 2 ns
RD or CS falling edge to data valid propagation
tPDDO 15 ns
delay
tHDO Output data to RD or CS rising edge hold time 5 ns
tDTRI CS high to DB[15:0] three-state delay 10 ns
(1) Over recommended operating free-air temperature range TA, AVDD = 5V, and DVDD = 2.7V to 5.5V, unless otherwise noted.
(2) All input signals are specified with tR= tF= 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2.
(3) Refer to CS signal or RD, whichever occurs first.
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CS
DB[15:0]
WR
tCSWR
tHDI
tWRL
tSUDI
C
[31:16]
tWRCS
tWRH
C
[15:0]
R =200
SER WR =130
SW W
R =200W
SER R =130
SW W
C =5pF
PAR
C =20pF
S
C =20pF
S
CH_XX
AGND
Inputrange: 2VREF±
VDC
R =200
SER WR =130
SW W
R =200W
SER R =130
SW W
C =5pF
PAR
C =10pF
S
C =10pF
S
CH_XX
AGND
Inputrange: 4VREF±
VDC
ADS8528
ADS8548
ADS8568
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Figure 3. Parallel Write Access Timing Diagram
Table 3. Parallel Interface Timing Requirements (Write Access)(1)(2)
ADS8528, ADS8548, ADS8568
PARAMETER MIN TYP MAX UNIT
tCSWR CS low to WR low time 0 ns
tWRL WR low pulse width 15 ns
tWRH Minimum time between two write accesses 10 ns
tWRCS WR high to CS high time 0 ns
tSUDI Output data to WR rising edge setup time 5 ns
tHDI Data output to WR rising edge hold time 5 ns
(1) Over recommended ambient temperature range TA, AVDD = 5V, and DVDD = 2.7V to 5.5V, unless otherwise noted.
(2) All input signals are specified with tR= tF= 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2.
EQUIVALENT CIRCUITS
Figure 4. Equivalent Input Circuits
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Product Folder Link(s): ADS8528 ADS8548 ADS8568
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
HVDD
CH_A1
REFAN
AVDD
AGND
REFAP
CH_A0
/SW
CONVST_D
CONVST_C
CONVST_B
CONVST_A
ASLEEP
BUSY/INT
RANGE/XCLK
DB0/DCIN_D
HW
HVSS
CH_D1
REFDN
AVDD
AGND
REFDP
CH_D0
/SER
RESET
REFEN/
/
AVDD
AGND
DB15/SDO_D
STBY
RD
CS
PAR
WR
FS
CH_C0
REFCP
AGND
AVDD
REFCN
CH_C1
AGND
AVDD
REFIO
REFN
CH_B1
REFBN
AVDD
AGND
REFBP
CH_B0
DB14/SDO_C
DB13/SDO_B
DB12/SDO_A
DB11/
DB10/SCLK
DB9/SDI
DB8/DCEN
DGND
DVDD
DB7
DB6/SEL_B
DB5/SEL_CD
DB4
DB3/DCIN_A
DB2/DCIN_B
DB1/DCIN_C
REFBUFEN
7.3-mmx7.3-mm
ExposedThermalPad
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
PIN CONFIGURATIONS
RGC PACKAGE
QFN-64
(TOP VIEW)
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48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
HVDD
CH_A1
REFAN
AVDD
AGND
REFAP
CH_A0
/SW
CONVST_D
CONVST_C
CONVST_B
CONVST_A
ASLEEP
BUSY/INT
RANGE/XCLK
DB0/DCIN_D
HW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HVSS
CH_D1
REFDN
AVDD
AGND
REFDP
CH_D0
/SER
RESET
REFEN/
/
AVDD
AGND
DB15/SDO_D
STBY
RD
CS
PAR
WR
FS
CH_C0
REFCP
AGND
AVDD
REFCN
CH_C1
AGND
AVDD
REFIO
REFN
CH_B1
REFBN
AVDD
AGND
REFBP
CH_B0
DB14/SDO_C
DB13/SDO_B
DB12/SDO_A
DB11/
DB10/SCLK
DB9/SDI
DB8/DCEN
DGND
DVDD
DB7
DB6/SEL_B
DB5/SEL_CD
DB4
DB3/DCIN_A
DB2/DCIN_B
DB1/DCIN_C
REFBUFEN
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
www.ti.com
PM PACKAGE
LQFP-64
(TOP VIEW)
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
PIN DESCRIPTIONS
DESCRIPTION
PIN # NAME TYPE(1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1)
Negative supply voltage for the analog inputs.
1 HVSS P Decouple according to the Power Supply section.
Analog input of channel D1.
The input voltage range is controlled by the RANGE pin in hardware mode or by the Configuration Register
2 CH_D1 AI (CONFIG) bit C19 (RANGE_D) in software mode.
This pin can be powered down using CONFIG bit C18 (PD_D) in software mode.
Decoupling capacitor input for reference of channel pair D.
3 REFDN AI Connect to the decoupling capacitor and AGND according to the Power Supply section.
4, 14, Analog power supply.
45, 52, AVDD P Decouple according to the Power Supply section.
57, 61
5, 15,
44, 51, AGND P Analog ground; connect to the analog ground plane.
58, 62
Decoupling capacitor input for the channel pair D reference.
6 REFDP AI Connect to the decoupling capacitor according to the Power Supply section.
Analog input of channel D0.
7 CH_D0 AI The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C19 (RANGE_D) in
software mode. This pin can be powered down using CONFIG bit C18 (PD_D) in software mode.
Interface mode selection input.
8 PAR/SER DI When low, the parallel interface is selected. When high, the serial interface is enabled.
Hardware mode (HW/SW = 0): standby mode input.
When low, the entire device is powered down (including the internal conversion clock source and reference).
When high, the device operates in normal mode.
9 STBY DI Software mode (HW/SW = 1): connect to DGND or DVDD.
The standby mode can be activated using CONFIG bit C25 (STBY).
Reset input, active high.
10 RESET DI This pin aborts any ongoing conversions and resets the internal Configuration Register (CONFIG) to 000003FFh.
A valid reset pulse should be at least 50 ns long.
Hardware mode (HW/SW = 0): internal reference Hardware mode (HW/SW = 0): internal reference
enable input. enable input.
When high, the internal reference is enabled (the When high, the internal reference is enabled (the
reference buffers are also enabled). reference buffers are also enabled).
When low, the internal reference is disabled and an When low, the internal reference is disabled and an
11 REFEN/WR DI/DI external reference is applied at REFIO. external reference is applied at REFIO.
Software mode (HW/SW = 1): write input. Software mode (HW/SW = 1): connect to DGND or
The parallel data input is enabled when CS and WR are DVDD. The internal reference is enabled by CONFIG bit
low. The internal reference is enabled by CONFIG bit C15 (REFEN).
C15 (REFEN).
Read data input.
12 RD DI/DI When low, the parallel data output is enabled (if CS = 0). Must be connected to DGND.
When high, the data output is disabled.
Chip select input. Frame synchronization.
13 CS/FS DI/DI When low, the parallel interface is enabled. When high, The FS falling edge controls the frame transfer.
the interface is disabled.
When SEL_CD = 1, this pin is the data output for
Data bit 15 (MSB) input/output.
16 DB15/SDO_D DIO/DO channel pair D.
Output is sign extension for the ADS8528/48. When SEL_CD = 0, this pin should be tied to DGND.
When SEL_CD = 1, this pin is the data output for
Data bit 14 input/output.
17 DB14/SDO_C DIO/DO channel pair C.
Output is sign extension for the ADS8528/48. When SEL_CD = 0, this pin should be tied to DGND.
When SEL_B = 1, this pin is the data output for channel
Data bit 13 input/output. pair B. When SEL_B = 0, this pin should be tied to
18 DB13/SDO_B DIO/DO Output is sign extension for the ADS8528 and MSB for DGND. When SEL_CD = 0, data from channel pair D
the ADS8548. are also available on this output.
Data output for channel pair A.
When SEL_CD = 0, data from channel pair C are also
Data bit 12 input/output.
19 DB12/SDO_A DIO/DO available on this output.
Output is sign extension for the ADS8528. When SEL_CD = 0 and SEL_B = 0, SDO_A acts as
single data output for all eight channels.
(1) AI = analog input; AIO = analog input/output; DI = digital input; DO = digital output; DIO = digital input/output; and P = power supply.
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PIN DESCRIPTIONS (continued)
DESCRIPTION
PIN # NAME TYPE(1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1)
Hardware mode (HW/SW = 0): reference buffer
enable input.
When low, all internal reference buffers are enabled
(mandatory if internal reference is used).
DB11/REFBUFE Data bit 11 input/output. When high, all reference buffers are disabled.
20 DIO/DI
N Output is MSB for the ADS8528. Software mode (HW/SW = 1): connect to
DGND or DVDD.
The internal reference buffers are controlled by bit C14
(REFBUFEN) in the Configuration Register (CONFIG).
21 DB10/SCLK DIO/DI Data bit 10 input/output Serial interface clock input.
Hardware mode (HW/SW = 0): connect to DGND.
22 DB9/SDI DIO/DI Data bit 9 input/output Software mode (HW/SW = 1): serial data input.
Daisy-chain enable input.
When high, DB[3:0] serve as daisy-chain inputs
23 DB8/DCEN DIO/DI Data bit 8 input/output DCIN_[A:D].
If daisy-chain mode is not used, connect to DGND.
24 DGND P Buffer I/O ground, connect to digital ground plane
Buffer I/O supply, connect to digital supply.
25 DVDD P Decouple according to the Power Supply section.
26 DB7 DIO Data bit 7 input/output Must be connected to DGND
Select SDO_B input.
When low, SDO_B is disabled and data from all eight
channels are only available through SDO_A.
27 DB6/SEL_B DIO/DI Data bit 6 input/output When high and SEL_CD = 0, data from channel pairs B
and D are available on SDO_B. When SEL_CD = 1,
data from channel pair B are available on SDO_B.
Select SDO_C and SDO_D input.
When high, data from channel pair C are available on
SDO_C while data from channel pair D are available on
SDO_D. When low and SEL_B = 1, data from channel
28 DB5/SEL_CD DIO/DI Data bit 5 input/output pairs A and C are available on SDO_A while data from
channel pairs B and D are available on SDO_B. When
low and SEL_B = 0, data from all eight channels are
avaiable on SDO_A.
29 DB4 DIO Data bit 4 input/output Connect to DGND
When DCEN = 1, this pin is the daisy-chain data input
30 DB3/DCIN_A DIO/DI Data bit 3 input/output for SDO_A of the previous device in the chain. When
DCEN = 0, connect to DGND.
When DCEN = 1 and SEL_B = 1, this pin is the
31 DB2/DCIN_B DIO/DI Data bit 2 input/output daisy-chain data input for SDO_B of the previous device
in the chain. When DCEN = 0, connect to DGND.
When DCEN = 1 and SEL_CD = 1, this pin is the
daisy-chain data input for SDO_C of the previous
32 DB1/DCIN_C DIO/DI Data bit 1 input/output device in the chain.
When DCEN = 0, connect to DGND.
When DCEN = 1 and SEL_CD = 1, this pin is the
daisy-chain data input for SDO_D of the previous
33 DB0/DCIN_D DIO/DI Data bit 0 (LSB) input/output device in the chain.
When DCEN = 0, connect to DGND.
Hardware mode (HW/SW = 0): analog input voltage range select input.
When low, the analog input voltage range is ±4VREF. When high, the analog input voltage range is ±2VREF.
34 RANGE/XCLK DI/DI/DO Sofware mode (HW/SW = 1): this pin is an external conversion clock input if CONFIG bit C29 = 1 (CLKSEL); or an
internal conversion clock output if CONFIG bit C28 = 1 (CLKOUT_EN).
If this pin is not used, connect to DGND.
When CONFIG bit C27 = 0 (BUSY/INT) this pin is a converter busy status output.
This pin transitions high when a conversion has been started and transitions low for a single conversion clock cycle
(tCCLK) whenever a channel pair conversion is completed and stays low when the conversion of the last channel pair
has completed.
35 BUSY/INT DO When bit C27 = 1 (BUSY/INT in CONFIG), this pin is an interrupt output. This pin transitions high after a conversion
has been completed and remains high until the next read access. This mode can only be used if all eight channels
are sampled simultaneously (all CONVST_x tied together). The polarity of the BUSY/INT output can be changed
using bit C26 (BUSY L/H) in the Configuration Register.
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
PIN DESCRIPTIONS (continued)
DESCRIPTION
PIN # NAME TYPE(1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1)
Auto-sleep enable input.
When low, the device operates in normal mode.
36 ASLEEP DI When high, the device works in auto-sleep mode where the hold mode and the actual conversion is activated 6
conversion clock (tCCLK) cycles after issuing a conversion start using a CONVST_x. This mode is recommended to
save power if the device runs at a lower data rate; see the Reset and Power-Down Modes section for more details.
Conversion start of channel pair A.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0].
37 CONVST_A DI This signal resets the internal channel state machine that causes the data output to start with conversion results of
channel A0 with the next read access.
Conversion start of channel pair B.
38 CONVST_B DI The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0].
Conversion start of channel pair C.
39 CONVST_C DI The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0].
Conversion start of channel pair D.
40 CONVST_D DI The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_D[1:0].
Mode selection input.
When low, the hardware mode is selected and the device functions according to the settings of the external pins.
41 HW/SW DI When high, the software mode is selected in which the device is configured by writing to the Configuration Register
(CONFIG).
Analog input of channel A0; channel A is the master channel pair that is always active.
The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C24 (RANGE_A) in
42 CH_A0 AI software mode. In cases where channel pairs of the device are used at different data rates, channel pair A should
always run at the highest data rate.
Decoupling capacitor input for reference of channel pair A.
43 REFAP AI Connect to the decoupling capacitor according to the Power Supply section.
Decoupling capacitor input for reference of channel pair A.
46 REFAN AI Connect to the decoupling capacitor and AGND according to the Power Supply section.
Analog input of channel A1; channel A is the master channel pair that is always active.
The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C24 (RANGE_A) in
47 CH_A1 AI software mode. In cases where channel pairs of the device are used at different data rates, channel pair A should
always run at the highest data rate.
Positive supply voltage for the analog inputs.
48 HVDD P Decouple according to the Power Supply section.
Analog input of channel B0.
49 CH_B0 AI The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C23 (RANGE_B) in
software mode.
Decoupling capacitor input for reference of channel pair B.
50 REFBP AI Connect to the decoupling capacitor according to the Power Supply section.
Decoupling capacitor input for reference of channel pair B.
53 REFBN AI Connect to the decoupling capacitor and AGND according to the Power Supply section.
Analog input of channel B1.
54 CH_B1 AI The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C23 (RANGE_B) in
software mode.
Negative reference input/output pin.
55 REFN AI Connect to a decoupling capacitor and AGND according to the Power Supply section.
Reference voltage input/output.
The internal reference is enabled by the REFEN/WR pin in hardware mode or by CONFIG bit C15 (REFEN) in
56 REFIO AIO software mode. The output value is controlled by the internal DAC (CONFIG bits C[9:0]).
Connect to a decoupling capacitor according to the Power Supply section.
Analog input of channel C1.
59 CH_C1 AI The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C21 (RANGE_C) in
software mode.
Decoupling capacitor input for reference of channel pair C.
60 REFCN AI Connect to the decoupling capacitor and AGND according to the Power Supply section.
Decoupling capacitor input for reference of channel pair C.
63 REFCP AI Connect to the decoupling capacitor according to the Power Supply section.
Analog input of channel C0.
64 CH_C0 AI The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C21 (RANGE_C) in
software mode.
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DVDD
HVSS AVDDHVDD
CH_A0
CONVST_A
AGND
REFAP
REFIO
CH_A1
AGND
CH_B0
CONVST_B
AGND
REFBP
CH_B1
AGND
CH_C0
CONVST_C
AGND
REFCP
CH_C1
AGND
CH_D0
AGND
CH_D1
AGND
String
DAC
2.5
VREF
SAR
ADC
SAR
ADC
CONVST_D
REFDP
SAR
ADC
SAR
ADC
SAR
ADC
SAR
ADC
SAR
ADC
SAR
ADC
Clock
Generator
Control
Logic
Config
Register
I/O
BUSY/INT
RANGE/XCLK
STBY
RESET
REFEN/WR
HW/SW
CS/FS
RD
DB[15:0]
ASLEEP
PAR/SER
SCLK
AGND DGND
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
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FUNCTIONAL BLOCK DIAGRAM
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS
Graphs are valid for all devices of the family, at TA= +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V,
VREF = 2.5V (internal), VIN =±10V, and fDATA = maximum, unless otherwise noted.
INL vs CODE DNL vs CODE
(ADS8528) (ADS8528)
Figure 5. Figure 6.
INL vs CODE INL vs CODE
(ADS8548 ±10VIN Range) (ADS8548 ±5VIN Range)
Figure 7. Figure 8.
DNL vs CODE DNL vs CODE
(ADS8548 ±10VIN Range) (ADS8548 ±5VIN Range)
Figure 9. Figure 10.
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ADS8568
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TYPICAL CHARACTERISTICS (continued)
Graphs are valid for all devices of the family, at TA= +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V,
VREF = 2.5V (internal), VIN =±10V, and fDATA = maximum, unless otherwise noted.
INL vs CODE INL vs CODE
(ADS8568 ±10VIN Range) (ADS8568 ±5VIN Range)
Figure 11. Figure 12.
DNL vs CODE DNL vs CODE
(ADS8568 ±10VIN Range) (ADS8568 ±5VIN Range)
Figure 13. Figure 14.
OFFSET ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE
Figure 15. Figure 16.
20 Copyright ©2011, Texas Instruments Incorporated
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0 8 46 0 0
7389
8947
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS (continued)
Graphs are valid for all devices of the family, at TA= +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V,
VREF = 2.5V (internal), VIN =±10V, and fDATA = maximum, unless otherwise noted.
PSRR vs SUPPLY NOISE FREQUENCY CONVERSION TIME vs TEMPERATURE
Figure 17. Figure 18.
CODE HISTOGRAM
(ADS8568, 16390 Hits) SNR vs TEMPERATURE
Figure 19. Figure 20.
SINAD vs TEMPERATURE THD vs TEMPERATURE
Figure 21. Figure 22.
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TYPICAL CHARACTERISTICS (continued)
Graphs are valid for all devices of the family, at TA= +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V,
VREF = 2.5V (internal), VIN =±10V, and fDATA = maximum, unless otherwise noted. FREQUENCY SPECTRUM
SFDR vs TEMPERATURE (ADS8568, 2048-Point FFT, fIN = 10kHz, ±10VIN Range)
Figure 23. Figure 24.
FREQUENCY SPECTRUM CHANNEL-TO-CHANNEL ISOLATION vs
(ADS8568, 2048-Point FFT, fIN = 10kHz, ±5VIN Range) INPUT NOISE FREQUENCY
Figure 25. Figure 26.
INTERNAL REFERENCE VOLTAGE vs INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
ANALOG SUPPLY VOLTAGE (2.5V Mode) (2.5V Mode)
Figure 27. Figure 28.
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS (continued)
Graphs are valid for all devices of the family, at TA= +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V,
VREF = 2.5V (internal), VIN =±10V, and fDATA = maximum, unless otherwise noted.
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
(3.0V Mode) ADS8568 ANALOG SUPPLY CURRENT vs TEMPERATURE
Figure 29. Figure 30.
ADS8568 ANALOG SUPPLY CURRENT vs DATA RATE BUFFER I/O SUPPLY CURRENT vs TEMPERATURE
Figure 31. Figure 32.
ADS8568 INPUT SUPPLY CURRENT vs INPUT SUPPLY
ADS8568 INPUT SUPPLY CURRENT vs TEMPERATURE VOLTAGE
Figure 33. Figure 34.
Copyright ©2011, Texas Instruments Incorporated 23
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ADS8568
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TYPICAL CHARACTERISTICS (continued)
Graphs are valid for all devices of the family, at TA= +25°C, HVDD = 15V, HVSS = –15V, AVDD = 5V, and DVDD = 3.3V,
VREF = 2.5V (internal), VIN =±10V, and fDATA = maximum, unless otherwise noted.
ADS8568 INPUT SUPPLY CURRENT vs DATA RATE
Figure 35.
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f =
3dB
ln(2)(n+1)
2 tpACQ
ADS8528
ADS8548
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
GENERAL DESCRIPTION
The ADS8528/48/68 series includes eight 12-, 14-, and 16-bit analog-to-digital converters (ADCs), respectively,
that operate based on the successive approximation register (SAR) architecture. This architecture is designed on
the charge redistribution principle, which inherently includes a sample-and-hold function. The eight analog inputs
are grouped into four channel pairs. These channel pairs can be sampled and converted simultaneously,
preserving the relative phase information of the signals of each pair. Separate conversion start signals allow
simultaneous sampling on each channel pair of four, six, or eight channels. These devices accept single-ended,
bipolar analog input signals in the selectable ranges of ±4VREF or ±2VREF with an absolute value of up to
±12V; see the Analog Inputs section.
The devices offer an internal 2.5V or 3V reference source followed by a 10-bit digital-to-analog converter (DAC)
that allows the reference voltage VREF to be adjusted in 2.44mV or 2.93mV steps, respectively.
The ADS8528/48/68 also offer a selectable parallel or serial interface that can be used in hardware or software
mode; see the Device Configuration section for details. The Analog and Digital sections describe the functionality
and control of the device in detail.
ANALOG
This section addresses the analog input circuit, the ADCs and control signals, and the reference design of the
device.
Analog Inputs
The inputs and the converters are of single-ended bipolar type. The absolute voltage range can be selected
using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the Configuration (CONFIG)
Register to either ±4VREF or ±2VREF. With the internal reference set to 2.5V (VREF bit C13 = 0 in the CONFIG
Register), the input voltage range can be ±10V or ±5V. With the internal reference source set to 3V (CONFIG bit
C13 = 1), an input voltage range of ±12V or ±6V can be configured. The logic state of the RANGE pin is latched
with the falling edge of BUSY (if CONFIG bit C26 = 0).
The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source
impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the
sampling period (tACQ). The source of the analog input voltage must be able to charge the input capacitance of
10pF in ±4VREF mode or of 20pF in ±2VREF mode to a 12-, 14-, or 16-bit accuracy level within the acquisition
time; see Figure 4. During the conversion period, there is no further input current flow and the input impedance is
greater than 1MΩ. To ensure a defined start condition, the sampling capacitors of the ADS8528/48/68 are
pre-charged to a fixed internal voltage before switching into sampling mode.
To maintain the linearity of the converter, the inputs should always remain within the specified range shown in
the Electrical Characteristics table. The minimum –3dB bandwidth of the driving operational amplifier can be
calculated using Equation 1:
(1)
where:
n = 12, 14, or 16; nis the resolution of the ADS8528/48/68
With a minimum acquisition time of tACQ = 280ns, the required minimum bandwidth of the driving amplifier is
5.2MHz for the ADS8528, 6.0MHz for the ADS8548, or 6.7MHz for the ADS8568. The required bandwidth can be
lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill
the bandwidth requirement shown in Equation 1.
Copyright ©2011, Texas Instruments Incorporated 25
Product Folder Link(s): ADS8528 ADS8548 ADS8568
R <
SOURCE
tACQ
C ln(2)(n+1)
S
-(R +R )
SER SW
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
www.ti.com
A driving operational amplifier may not be required, if the impedance of the signal source (RSOURCE) fulfills the
requirement of Equation 2:
(2)
where:
n = 12, 14, or 16; nis the resolution of the ADC,
CS= 10pF is the sample capacitor value in VIN =±4VREF mode,
RSER = 200Ωis the input resistor value,
and RSW = 130Ωis the switch resistance value.
With a minimum acquisition time of tACQ = 280ns, the maximum source impedance should be less than 2.7kΩfor
the ADS8528, 2.3kΩfor the ADS8548, and 2.0kΩfor the ADS8568 in ±4VREF mode, or less than 1.2kΩfor the
ADS8528, 1.0kΩfor the ADS8548, and 0.8kΩfor the ADS8568 in ±2VREF mode. The source impedance can be
higher if the application allows longer acquisition time.
Analog-to-Digital Converter (ADC)
The device includes eight ADCs that operate with either an internal or an external conversion clock.
Conversion Clock
The device uses either an internally-generated (CCLK) or an external (XCLK) conversion clock signal (in
software mode only). In default mode, the device generates an internal clock. In this case, a complete conversion
including the pre-charging of the sample capacitors takes 19 to 20 clock cycles, depending on the setup time of
the incoming CONVST_x signal with relation to the rising edge of the CCLK.
When CLKSEL bit is set high (CONFIG bit C29), an external conversion clock can be applied on pin 34. A
complete conversion process requires 19 clock cycles in this case if the tSCVX timing requirement is fulfilled. The
external clock can remain low between conversions.
If the application requires lowest power dissipation at low data rates, it is recommended to use the auto-sleep
mode, activated using pin 36 (ASLEEP). In this case, a conversion cycle takes up to 26 clock cycles (see the
Reset and Power-Down Modes section for more details).
26 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8528 ADS8548 ADS8568
CONVST_A,C
BUSY
(C27=C26=0)
CS
DB[15:0]
RD
CH
A0
CH
A1
CONVST_B
DB[15:0]
CONVST_A,C,D
RD
CONVST_B,D
CH
B0
CH
B1
CH
C0
CH
C1
CH
D0
CH
D1
OldData OldData
OldData OldData
CH
A0
CH
A1
CH
B0
CH
B1
CH
C0
CH
C1
CH
D0
CH
D1
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
CONVST_x
The analog inputs of each channel pair (CH_x0/1) are held with the rising edge of the corresponding CONVST_x
signal. The conversion automatically starts with the next rising edge of the conversion clock. CONVST_A is a
master conversion start that resets the internal state machine and causes the data output to start with the result
of channel A0. In cases where channel pairs of the device are used at different data rates, CONVST_A should
always be the one used at the highest frequency.
A conversion start must not be issued during an ongoing conversion on the corresponding channel pair. It is
allowed to initiate conversions on the other input pairs, however.
If a parallel interface is used, the content of the output port depends on which CONVST_x signals have been
issued. Figure 36 shows examples of different scenarios with all channel pairs active.
Figure 36. Data Output versus CONVST_x (All Channels Active)
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Product Folder Link(s): ADS8528 ADS8548 ADS8568
CONVST_x
BUSY
(C27=C26=0)
PAR =
SER=
RD
FS
INT
(C27=1,C26=0)
tCONV
V =
REF
Range (Code+1)´
1024
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
www.ti.com
BUSY/INT
The BUSY signal indicates if a conversion is in progress. It goes high with a rising edge of any CONVST_x
signal and goes low when the output data of the last channel pair are available in the respective output register.
The readout of the data can be initiated immediately after the falling edge of BUSY.
In contrary, the INT signal goes high when a new conversion result has been loaded in the output register (this is
when the conversion has been completed) and remains high until the next read access, as shown in Figure 37.
The polarity of the BUSY/INT signal can be changed using CONFIG bit C26. The mode of pin 35 can be
controlled using CONFIG bit C27.
Figure 37. BUSY versus INT Behavior of Pin 35
Reference
The ADS8528/48/68 provides an internal, low-drift, 2.5V reference source. To increase the input voltage range,
the reference voltage can be switched to 3V mode using the VREF bit (CONFIG bit C13). The reference feeds a
10-bit string-DAC controlled by bits REFDAC[9:0] in the Configuration (CONFIG) Register. The buffered DAC
output is connected to the REFIO pin. In this way, the voltage at this pin is programmable in 2.44mV (2.92mV in
3V mode) steps and adjustable to the applications needs without additional external components. The actual
output voltage can be calculated using Equation 3:
(3)
where:
Range = the chosen maximum reference voltage output range (2.5V or 3V),
Code = the decimal value of the DAC register content.
Table 4 lists some examples of internal reference DAC settings with a reference range set to 2.5V. However, to
ensure proper performance, the DAC output voltage should not be programmed below 0.5V.
The buffered output of the DAC should be decoupled with a 100nF capacitor (minimum); for best performance, a
470nF capacitor is recommended. If the internal reference is placed into power-down (default), an external
reference voltage can drive the REFIO pin.
Table 4. DAC Settings Examples (2.5V Operation)
VREFOUT DECIMAL CODE BINARY CODE HEXADECIMAL CODE
0.5 V 204 00 1100 1100 CCh
1.25 V 511 01 1111 1111 1FFh
2.5 V 1023 11 1111 1111 3FFh
28 Copyright ©2011, Texas Instruments Incorporated
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f =
3dB
ln(2)
2 tpCONV
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
The voltage at the REFIO pin is buffered with four internal amplifiers, one for each ADC pair. The output of each
buffer must be decoupled with a 10µF capacitor between the pin pairs 3 and 6, 43 and 46, 50 and 53, and 60
and 63. The 10µF capacitors are available as ceramic 0805-SMD components and in X5R quality.
The internal reference buffers can be powered down to decrease the power dissipation of the device. In this
case, external reference drivers can be connected to the REFAP, REFBP, REFCP, and REFDP pins. With 10µF
decoupling capacitors, the minimum required bandwidth can be calculated using Equation 4:
(4)
With the minimum tCONV of 1.33µs, the external reference buffers require a minimum bandwidth of 83kHz.
DIGITAL
This section describes the digital control and the timing of the device in detail.
Device Configuration
Depending on the desired mode of operation, the ADS8528/48/68 can be configured using the external pins
and/or the Configuration Register (CONFIG), as shown in Table 5.
Table 5. ADS8528/48/68 Configuration Settings
INTERFACE MODE HARDWARE MODE (HW/SW = 0) SOFTWARE MODE (HW/SW = 1)
Configuration using pins and (optionally) Configuration Configuration using Configuration Register bits C[31:0]
Parallel (PAR/SER = 0) Register bits C30, C29, C[27:26], C22, C20, C18, C14, only; status of pins 9, 11, 20, and 34 are disregarded
C13, and C[9:0] (if C29 = C28 = 0)
Configuration using pins and (optionally) Configuration Configuration using Configuration Register bits C[31:0]
Serial (PAR/SER = 1) Register bits C30, C29, C[27:26], C22, C20, C18, C13, only; status of pins 9, 11, 20, and 34 are disregarded
and C[9:0] (if C29 = C28 = 0)
Hardware Mode
With the HW/SW input (pin 41) set low, the device functions are controlled via the pins and, optionally,
Configuration Register bits C30, C29, C[27:26], C22, C20, C18, C14 (in parallel interface mode only), C13, and
C[9:0].
It is possible to generally use the part in hardware mode but to switch it into software mode to initialize or adjust
the Configuration Register settings (for example, the internal reference DAC) and back to hardware mode
thereafter.
Software Mode
When the HW/SW input is set high, the device operates in software mode with functionality set only by the
Configuration Register bits (corresponding pin settings are ignored).
If parallel interface is used, an update of all Configuration Register settings is performed by issuing two 16-bit
write accesses on pins DB[15:0] (to avoid loosing data, the entire sequence must be finished before starting a
new conversion). CS should be held low during these two accesses. To enable the actual update of the register
settings, the first bit (C31) must be set to '1' during the access.
Copyright ©2011, Texas Instruments Incorporated 29
Product Folder Link(s): ADS8528 ADS8548 ADS8568
RESET
(orPowerUp)
BUSY
(C20=C21=0)
WR
DB[15:0] C
[31:16]
PAR/SER=0
CS
C
[15:0]
InitializationData Update
C
[31:16]
C
[15:0]
FS
SDI C[31:0]
InitializationData C[31:0]
PAR/SER=1
NoContentUpdate
ContentUpdate
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
www.ti.com
If the serial interface is used, the update of the register contents can be performed continuously (combined
read/write access). Optionally, to reduce the data transfer on the SDI line and the electromagnetic interference
(EMI) of the system, the SDI input can be pulled low when a register update is not required. Figure 38 illustrates
the different Configuration Register update options.
Figure 38. Configuration Register Update Options
30 Copyright ©2011, Texas Instruments Incorporated
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ADS8548
ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
Configuration (CONFIG) Register
The Configuration Register settings can only be changed in software mode and are not affected when switching
to hardware mode thereafter. The register values are independent from input pin settings. Changes are active
with the second rising edge of WR in parallel interface mode or with the 32nd SCLK falling edge of the access in
which the register content has been updated in serial mode. The CONFIG content is defined in Table 6.
Table 6. CONFIG: Configuration Register (Default: 000003FFh)
31 30 29 28 27 26 25 24
WRITE_EN READ_EN CLKSEL CLKOUT BUSY/INT BUSY POL STBY RANGE_A
23 22 21 20 19 18 17 16
RANGE_B PD_B RANGE_C PD_C RANGE_D PD_D Don't care Don't care
15 14 13 12 11 10 9 8
REFEN REFBUF VREF Don't care Don't care Don't care D9 D8
76543210
D7 D6 D5 D4 D3 D2 D1 D0
Bit 31 WRITE_EN: Register update enable
This bit is not active in hardware mode.
0 = Register content update disabled (default)
1 = Register content update enabled
Bit 30 READ_EN: Register read-out access enable
This bit is not active in hardware mode.
0 = Normal operation (conversion results available on SDO_A)
1 = Configuration Register contents output on SDO_A with next two accesses
(READ_EN automatically resets to '0' thereafter)
Bit 29 CLKSEL: Conversion clock selector
This bit is active in hardware mode.
0 = Normal operation with internal conversion clock; mandatory in hardware mode (default)
1 = External conversion clock applied through pin 34 (XCLK) is used (conversion takes 19
clock cycles)
Bit 28 CLKOUT: Internal conversion clock output enable
This bit is not active in hardware mode.
0 = Normal operation (default)
1 = Internal conversion clock is available at pin 34
Bit 27 BUSY/INT: Busy/interrupt selector
This bit is active in hardware mode.
0 = BUSY/INT pin in BUSY mode (default)
1 = BUSY/INT pin in interrupt mode (INT); can only be used if all eight channels are
sampled simultaneously (all CONVST_x tied together)
Bit 26 BUSY POL: BUSY/INT polarity selector
This bit is active in hardware mode.
0 = BUSY/INT active high (default)
1 = BUSY/INT active low
Bit 25 STBY: Power-down enable
This bit is not active in hardware mode.
0 = Normal operation (default)
1 = Entire device is powered down (including the internal clock and reference)
Copyright ©2011, Texas Instruments Incorporated 31
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Bit 24 RANGE_A: Input voltage range selector for channel pair A
This bit is not active in hardware mode.
0 = Input voltage range: 4VREF (default)
1 = Input voltage range: 2VREF
Bit 23 RANGE_B: Input voltage range selector for channel pair B
This bit is not active in hardware mode.
0 = Input voltage range: 4VREF (default)
1 = Input voltage range: 2VREF
Bit 22 PD_B: Power-down enable for channel pair B
This bit is active in hardware mode.
0 = Normal operation (default)
1 = Channel pair B is powered down
Bit 21 RANGE_C: Input voltage range selector for channel pair C
This bit is not active in hardware mode.
0 = Input voltage range: 4VREF (default)
1 = Input voltage range: 2VREF
Bit 20 PD_C: Power-down enable for channel pair C
This bit is active in hardware mode.
0 = Normal operation (default)
1 = Channel pair C is powered down
Bit 19 RANGE_D: Input voltage range selector for channel pair D
This bit is not active in hardware mode.
0 = Input voltage range: 4VREF (default)
1 = Input voltage range: 2VREF
Bit 18 PD_D: Power-down enable for channel pair D
This bit is active in hardware mode.
0 = Normal operation (default)
1 = Channel pair D is powered down
Bits[17:16] Not used (default = 0)
Bit 15 REF_EN: Internal reference enable
This bit is not active in hardware mode.
0 = Internal reference source disabled (default)
1 = Internal reference source enabled
Bit 14 REFBUF: Internal reference buffers disable
This bit is active in hardware mode if the parallel interface is used.
0 = Internal reference buffers enabled (default)
1 = Internal reference buffers disabled
Bit 13 VREF: Internal reference voltage selector
This bit is active in hardware mode.
0 = Internal reference voltage set to 2.5V (default)
1 = Internal reference voltage set to 3.0V
Bits[12:10] Not used (default = 0)
Bits[9:0] D[9:0]: REFDAC setting bits
These bits are active in hardware mode.
These bits correspond to the settings of the internal reference DACs (compare to the
Reference section). Bit D9 is the MSB of the DAC. Default value is 3FFh (2.5V, nom).
32 Copyright ©2011, Texas Instruments Incorporated
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BUSY
(C20=C21=0)
FS
SDO_A
CHA0
FS
SDO_A
SDO_B
SEL_B=SEL_C/D=0
SEL_B=1,SEL_C/D=0
CHA1 CHC0 CHC1
CHB0 CHB1 CHD0 CHD1
CHA0 CHA1 CHB0 CHB1 CHC0 CHC1 CHD0 CHD1
64SCLKs
128SCLKs
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
Parallel Interface
To use the device with the parallel interface, the PAR/SER pin should be held low. The maximum achievable
data throughput rate is 650kSPS for the ADS8528, 600kSPS for the ADS8548, and 510kSPS for the ADS8568 in
this case.
Access to the ADS8528/48/68 is controlled as illustrated in Figure 2 and Figure 3.
Serial Interface
The serial interface mode is selected by setting the PAR/SER pin high. In this case, each data transfer starts with
the falling edge of the frame synchronization input (FS). The conversion results are presented on the serial data
output pins SDO_A (always active), SDO_B, SDO_C, and SDO_D, depending on the selections made using the
SEL_xx pins. Starting with the most significant bit (MSB), the output data are changed with the falling edge of
SCLK. Output data of the ADS8528 and ADS8548 maintain the LSB-aligned 16-bit format with leading bits
containing the extended sign (see also Table 7). Serial data input SDI are latched with the falling edge of SCLK.
The serial interface can be used with one, two, or four output ports. Port SDO_B can be enabled using pin 27
(SEL_B) while ports SDO_C and SDO_D are enabled using pin 28 (SEL_CD). If all four serial data output ports
are selected, the data can be read with either two 16-bit data transfers or with a single 32-bit data transfer. The
data of channels CH_x0 are available first, followed by data from channels CH_x1. The maximum achievable
data throughput rate is 480kSPS for the ADS8528, 450kSPS for the ADS8548, and 400kSPS for the ADS8568 in
this case.
If the application allows a data transfer using two ports only, the SDO_A and SDO_B outputs are used. The
device outputs data from channel CH_A0 followed by CH_A1, CH_C0, and CH_C1 on SDO_A, while data from
channel CH_B0 followed by CH_B1, CH_D0, and CH_D1 occur on SDO_B. In this case, a data transfer of four
16-bit words, two 32-bit words, or one continuous 64-bit word is supported. The maximum achievable data
throughput rate is 360kSPS for the ADS8528, 345kSPS for the ADS8548, and 315kSPS for the ADS8568 in this
case.
The output SDO_A is always active and exclusively used if only one serial data port is used in the application.
The data are available in the following order: CH_A0, CH_A1, CH_B0, CH_B1, CH_C0, CH_C1, CH_D0, and
CH_D1. Data can be read using eight 16-bit transfers, four 32-bit transfers, two 64-bit transfers, or a single
128-bit transfer. The maximum achievable data throughput rate is 235kSPS for the ADS8528, 230kSPS for the
ADS8548 and 215kSPS for the ADS8568 in this case. Figure 1 and Figure 39 show all possible scenarios in
more detail.
Figure 39. Data Output with One or Two Active SDOs (All Input Channels Active and Converted)
Copyright ©2011, Texas Instruments Incorporated 33
Product Folder Link(s): ADS8528 ADS8548 ADS8568
CONVST
BUSY
(C27=C26=0)
FS
SDO_x#3 Don’tCare 16-BitDataCHx0
ADS85x8#3
ADS85x8
#1
CONVST_A/B/C/D
FS
SCLK
SDO_A
SDO_B
SDO_C
SDO_D
ADS85x8
#2
ADS85x8
#3
DCIN_A
DCIN_B
DCIN_C
DCIN_D
CONVST_A/B/C/D
FS
SCLK
CONVST_A/B/C/D
FS
SCLK
CONVST
FS
SCLK
16-BitData
ADS85x8#3
CHx1 16-BitData
ADS85x8#2
CHx0 16-BitData
ADS85x8#2
CHx1 16-BitData
ADS85x8#1
CHx0 16-BitData
ADS85x8#1
CHx1
DCIN_A
DCIN_B
DCIN_C
DCIN_D
To
Processing
Unit
DCEN DCEN
DVDD
DGND
DCEN
DVDD
SDO_A
SDO_B
SDO_C
SDO_D
SDO_A
SDO_B
SDO_C
SDO_D
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
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Daisy-Chain Mode
The serial interface of the ADS8528/48/68 supports a daisy-chain feature that allows cascading of multiple
devices to minimize the board space requirements and simplify routing of the data and control lines. In this case,
pins DB3/DCIN_A, DB2/DCIN_B, DB1/DCIN_C, and DB0/DCIN_D are used as serial data inputs for channels A,
B, C, and D, respectively. Figure 40 shows an example of a daisy-chain connection of three devices sharing a
common CONVST line to allow simultaneous sampling of 24 analog channels along with the corresponding
timing diagram.
To activate the daisy-chain mode, the DCEN pin must be pulled high. However, the DCEN of the first device in
the chain must remain low.
In applications in which not all channel pairs are used, it is recommended to declare the part with disabled
channel pair(s) to be the first in the daisy-chain.
Figure 40. Example of Daisy-Chaining Three Devices
34 Copyright ©2011, Texas Instruments Incorporated
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
Output Data Format
The data output format of the ADS8528/48/68 is binary twos complement, as shown in Table 7. For the
ADS8528/48 (which deliver 12-bit or 14-bit conversion results, respectively), the leading bits of either the 16-bit
frame (serial interface) or the output pins (DB[15:12] for the ADS8528 or DB[15:14] for the ADS8548 in parallel
mode) deliver a sign extension.
Table 7. Output Data Format
BINARY CODE HEXADECIMAL CODE
DESCRIPTION INPUT VOLTAGE VALUE ADS8528 ADSS8548 ADS8568
0000 0111 1111 1111 0001 1111 1111 1111 0111 1111 1111 1111
Positive full-scale +4VREF or +2VREF 07FFh 1FFFh 7FFFh
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Midscale +0.5LSB VREF/(2 ×resolution) 0000h 0000h 0000h
1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
Midscale –0.5LSB –VREF/(2 ×resolution) FFFFh FFFFh FFFFh
1111 1000 0000 0000 1110 0000 0000 0000 1000 0000 0000 0000
Negative full-scale –4VREF or –2VREF F800h E000h 8000h
Reset and Power-Down Modes
The device supports two reset mechanisms: a power-on reset (POR) and a pin-controlled reset (RESET) that
can be issued using pin 10. Both, the POR and RESET act as a master reset that causes any ongoing
conversion to be interrupted, the Configuration Register content to be set to the default value, and all channels to
be switched into the sample mode.
When the device is powered up, the POR sets the device in default mode when AVDD reaches 1.2V. In normal
operation, glitches on the AVDD supply below this threshold trigger a device reset.
The entire device, except for the digital interface, can be powered down by pulling the STBY pin low (pin 9). As
the digital interface section remains active, data can be retrieved while in stand-by mode. To power the part on
again, the STBY pin must be brought high. The device is ready to start a new conversion after the 10ms required
to activate and settle the internal circuitry. This user-controlled approach can be used in applications that require
lower data throughput rates at lowest power dissipation. The content of CONFIG is not changed during stand-by
mode and it is not required to perform a reset after returning to normal operation.
Copyright ©2011, Texas Instruments Incorporated 35
Product Folder Link(s): ADS8528 ADS8548 ADS8568
CONVST_A/B/D
BUSY
(C27=C26=0)
DB[15:0]
RD
CH
A0
CH
A1
CONVST_B
DB[15:0]
CONVST_A/D
RD
CH
B0
CH
B1
CH
D0
CH
D1
CH
A0
CH
A1
OldData
SameData(Reread)
OldData OldData(Reread)
CH
A0
CH
A1
CH
B0
CH
B1
CH
D0
CH
D1
CH
A0
CH
A1
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
www.ti.com
While the standby mode impacts the entire device, each device channel pair (except channel pair A, which as
the master channel pair, is always active) can also be individually switched off by setting the Configuration
Register bits C22, C20, and C18 (PD_x). If a certain channel pair is powered-down in this manner, the output
register is disabled as shown in Figure 41. When reactivated, the relevant channel pair requires 10ms to fully
settle before starting a new conversion.
(1) Channel pair C disabled (PD_C = 1), CS = 0.
NOTE: Boxed areas indicate the minimum required frame to acquire all new conversion results. The read access might be interrupted,
thereafter.
Figure 41. Example of Data Output Order with Channel Pair C Powered Down(1)
36 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8528 ADS8548 ADS8568
CONVST_x
ADC CH_x ACQ CONV Power-Down ACQ
ASLEEP
BUSY
CONV Power-Down
6tCCLK
ADS8528
ADS8548
ADS8568
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SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
The auto-sleep mode is enabled by pulling pin 36 (ASLEEP) high. If the auto-sleep mode is enabled, the
ADS8528/48/68 automatically reduce the current requirement to 7mA (IAVDD) after finishing a conversion; thus,
the end of conversion actually activates this power-down mode. Triggering a new conversion by applying a
positive CONVST_x edge puts the device back into normal operation, starts the acquisition of the analog input,
and automatically starts a new conversion 6 to 7 conversion clock cycles later, as shown in Figure 42. Therefore,
a complete conversion process takes 25 to 26 conversion clock cycles; thus, the maximum throughput rate in
auto-sleep mode is reduced to a maximum of 400kSPS for the ADS8528, 375kSPS for the ADS8548, and
330kSPS for the ADS8568 in serial interface mode. In parallel mode, the maximum data rates are 510kSPS for
the ADS8528, 470kSPS for the ADS8548 and 400kSPS for the ADS8568. If enabled, the internal reference
remains active during auto-sleep mode. Table 8 compares the analog current requirements of the device in
different modes.
Figure 42. Auto-Sleep Power-Down Mode
Table 8. Maximum Analog Current (IAVDD) Demand of the ADS85x8
NORMAL POWER-UP POWER-UP
ANALOG OPERATION
OPERATIONA ENABLED/DIS ACTIVATED TO NORMAL TO NEXT
CURRENT TO RESUMED BY
L MODE ABLED BY BY OPERATION CONVERSION
(IAVDD) POWER- DELAY START TIME
DOWN DELAY
12.5mA/ch pair Power on
Normal at maximum CONVST_x ————
operation Power off
data rate ASLEEP = 1 Each end of At falling edge
Auto-sleep 1.75mA/ch pair CONVST_x Immediate 7 ×tCCLK max
conversion of BUSY
ASLEEP = 0
HW/SW = 1 Immediate after
Power-down of 16µA PD_x = 1 PD_x = 0 completing
Immediate 10ms
channel pair X (channel pair X) (CONFIG bit) (CONFIG bit) CONFIG
HW/SW = 0 update
Power on
Power-down 30µA STBY = 0 Immediate STBY = 1 Immediate 10ms
(entire device) Power off
Copyright ©2011, Texas Instruments Incorporated 37
Product Folder Link(s): ADS8528 ADS8548 ADS8568
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
www.ti.com
APPLICATION INFORMATION
TYPICAL APPLICATION EXAMPLE
An example of a typical application of the ADS8528/48/68 is illustrated in Figure 43. In this case, the device is
used to simultaneously sample and convert the voltages and currents on three phases and the neutral line. In
this example, the BUSY signal is not used by the controller while the SW generates the required signals in timely
manner. TI’sOPA2211 is used as an input driver, supporting bandwidth that allows running the device at the
maximum data rate. However, because relatively low data rates are generally used in this type of applications,
the auto-sleep mode is activated in this example (ASLEEP is high) to minimize the current demand on the AVDD
and HVDD/HVSS power supplies. Further, the input drivers may not be necessary if the signal source fulfills the
requirements as defined by Equation 2. For example, at 10kSPS, the external drivers are not necessary if the
source impedance remains below 830kΩin ±4VREF mode or 415kΩin ±2VREF mode.
While the actual values of the resistors and capacitors depend on the bandwidth and performance requirements
of the application, for a data rate of 10kSPS, it is recommended to use a filter capacitor CFvalue of 1nF and a
series resistor RFof 10kΩ.
In applications supporting only single supply (for example, 5V), it is recommended to use the TPS65130 to
generate the bipolar supplies required by the ADC.
GROUNDING
All ground pins should be connected to a clean ground reference. This connection should be kept as short as
possible to minimize the inductance of these paths. It is recommended to use vias connecting the pads directly to
the corresponding ground plane. In designs without ground planes, the ground trace should be kept as wide and
as short as possible to reduce inductance. Avoid connections that are too close to the grounding point of a
microcontroller or digital signal processor.
Depending on the circuit density on the board, placement of the analog and digital components, and the related
current loops, a single solid ground plane for the entire printed circuit board (PCB) or dedicated analog and
digital ground areas may be used. In case of separated ground areas, ensure a low-impedance connection
between the analog and digital ground of the ADC by placing a bridge underneath (or next to) the ADC.
Otherwise, even short undershoots on the digital interface with a value of lower than –300mV lead to the
conduction of ESD diodes, causing current to flow through the substrate and either degrading the analog
performance or even damaging the part. It is recommended to use a common ground plane underneath the
device as a local ground reference for all xGND pins; see Figure 44. During PCB layout, care should be taken to
avoid any return currents crossing sensitive analog areas or signals.
38 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8528 ADS8548 ADS8568
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
6x
0.1 Fm
10 Fm
AGND HVSS
DGND
HVDD
DVDD
1 Fm
0.1 Fm
0.1 Fm
10 Fm
10 Fm
DGND
DVDD
HVSS
HVDD
AGND
ADS85x8
OPA2211
L1Current
Signal
L1Voltage
Signal
HVDD
HVSS
RF
RF
CF
CF
AGND
AGND
R2
R1
AGND
R2
R1
OPA2211
L2Current
Signal
L2Voltage
Signal
HVDD
HVSS
RF
RF
CF
CF
AGND
AGND
AGND
R2
R1
OPA2211
L3Current
Signal
L3Voltage
Signal
HVDD
HVSS
RF
RF
CF
CF
AGND
AGND
AGND
R2
R1
OPA2211
NCurrent
Signal
NVoltage
Signal
HVDD
HVSS
RF
RF
CF
CF
AGND
AGND
AGND
R2
R1
0.47 Fm
AGND
10 Fm
AGND
10 Fm
10 Fm
AGND
10 Fm
REFN
REFIO
REFBP
REFAN
REFAP
REFBN
REFDP
REFCN
REFCP
REFDN
CH_D0
CH_D1
CH_C0
CH_C1
CH_B0
CH_B1
CH_A0
CH_A1
CONVST_A
CONVST_B
CONVST_C
CONVST_D
RESET
CS
RD
DB[15:0]
STBY
ASLEEP
REF /WR
EN
HW/SW
PAR/SER
RANGE
Host
Controller
DGND
DVDD
ADS85x8
ADS8528
ADS8548
ADS8568
www.ti.com
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
Figure 43. Three-Phase + N Current/Voltage Measurement Application Based on the ADS85x8
Copyright ©2011, Texas Instruments Incorporated 39
Product Folder Link(s): ADS8528 ADS8548 ADS8568
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
www.ti.com
POWER SUPPLY
The ADS8528/48/68 require four separate supplies: an analog supply for the ADC (AVDD), the buffer I/O supply
for the digital interface (DVDD), and the high-voltage supplies driving the analog input circuitry (HVDD and
HVSS). Generally, there are no specific requirements with regard to the power sequencing of the device.
However, when HVDD is supplied before AVDD, the internal electrostatic discharge (ESD) structure conducts,
increasing the IHVDD beyond the specified value, until the AVDD is applied.
The AVDD supply provides power to the internal circuitry of the ADC. If run at maximum data rate, the IAVDD is
too high to allow use of a passive filter between the digital board supply of the application and the AVDD pins. A
linear regulator is recommended to generate the analog supply voltage. Each AVDD pin should be decoupled to
AGND with a 100nF ceramic capacitor. In addition, a single 10µF capacitor should be placed close to the device
but without compromising the placement of the smaller capacitors. Optionally, each supply pin can be decoupled
using a 1µF ceramic capacitor without the requirement for the additional 10µF capacitor.
The DVDD supply is only used to drive the digital I/O buffers and allows seamless interface with most
state-of-the-art processors and controllers. As a result of the low IDVDD value, a 10Ωseries resistor can be used
on the DVDD pin to reduce the noise energy from the external digital circuitry influencing the performance of the
device. A bypass ceramic capacitor of 1µF (or alternatively, a pair of 100nF and 10µF capacitors) should be
placed between pins 24 and 25.
The high-voltage supplies (HVSS and HVDD) are connected to the analog inputs. These supplies are not
required to be of symmetrical nature with regard to AGND. Noise and glitches on these supplies directly couple
into the input signals. Place a 100nF ceramic decoupling capacitor, located as close to the device as possible,
between each of pins 1, 48, and AGND. An additional 10µF capacitor is used that should be placed close to the
device but without compromising the placement of the smaller capacitors.
Figure 44 shows a layout recommendation for the ADS8528/48/68 along with the proper decoupling and
reference capacitors placement and connections. The layout recommendation takes into account the actual size
of the components used.
40 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8528 ADS8548 ADS8568
TopView
REFIO
REFBN
AGND
REFN
REFCP
AGND
REFCN
CH_C0
CH_C1
AVDD
CH_B0
REFBP
CH_B1
AGND
AVDD
AVDD
RF
RF
10 Fm
CF
ToHVDD
TtoHVSS
LEGEND
TopLayer;CopperPourandTraces
LowerLayer;AGNDArea
LowerLayer;DGNDArea
Via
CF
10 Fm
10 Fm10 Fm
10 Fm
10 Fm
RF
CF
RF
RF
RF
CFCFCF
0.1 Fm
0.47 Fm
0.1 Fm
RF
CF
RF
CF
REFAN
CH_A1
HVDD
AVDD
AGND
REFAP
CH_A0
41
40
39
38
37
36
35
34
33
17 18 19 20 23 29
26
27
DVDD
30
31
32
28
21 22
DGND
HVSS
CH_D1
REFDN
AVDD
CH_D0
8
REFDP
AGND
9
10
11
12
AGND
16
AVDD
13
ADS8528
ADS8548
ADS8568
www.ti.com
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
(1) All AVDD/DVDD decoupling capacitors are placed on the bottom layer underneath the device power-supply pins and are connected by
vias. All 100nF ceramic capacitors are placed as close as possible to the device while the 10µF capacitors are also close but without
compromising the placement of the smaller capacitors.
Figure 44. Layout Recommendation
Copyright ©2011, Texas Instruments Incorporated 41
Product Folder Link(s): ADS8528 ADS8548 ADS8568
ADS8528
ADS8548
ADS8568
SBAS543A –AUGUST 2011–REVISED OCTOBER 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2011) to Revision A Page
•Deleted INL column from Family/Ordering Information table ............................................................................................... 2
•Changed DC Accuracy, INL parameter in ADS8568 Electical Chatacteristics table ............................................................ 5
42 Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): ADS8528 ADS8548 ADS8568
PACKAGE OPTION ADDENDUM
www.ti.com 16-Nov-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS8528SPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8528SPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8528SRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8528SRGCT ACTIVE VQFN RGC 64 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8548SPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8548SPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8548SRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8548SRGCT ACTIVE VQFN RGC 64 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8568SPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8568SPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8568SRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS8568SRGCT ACTIVE VQFN RGC 64 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Nov-2011
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS8528SPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
ADS8528SRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
ADS8528SRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
ADS8548SPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
ADS8548SRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
ADS8548SRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
ADS8568SPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
ADS8568SRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
ADS8568SRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS8528SPMR LQFP PM 64 1000 367.0 367.0 45.0
ADS8528SRGCR VQFN RGC 64 2000 367.0 367.0 38.0
ADS8528SRGCT VQFN RGC 64 250 210.0 185.0 35.0
ADS8548SPMR LQFP PM 64 1000 367.0 367.0 45.0
ADS8548SRGCR VQFN RGC 64 2000 367.0 367.0 38.0
ADS8548SRGCT VQFN RGC 64 250 210.0 185.0 35.0
ADS8568SPMR LQFP PM 64 1000 367.0 367.0 45.0
ADS8568SRGCR VQFN RGC 64 2000 367.0 367.0 38.0
ADS8568SRGCT VQFN RGC 64 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PM (S-PQFP-G64) PLASTIC QUAD FLATPACK
4040152/C 11/96
32
17 0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
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