High Accuracy, Low IQ, anyCAP(R) Adjustable Low Dropout Regulator ADP3334 FEATURES High Accuracy over Line and Load: 0.9% @ 25C, 1.8% over Temperature 500 mA Current Capability Ultralow Dropout Voltage Requires Only CO = 1.0 F for Stability anyCAP = Stable with Any Type of Capacitor (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: < 1.0 A (Typ) 2.6 V to 11 V Supply Range 1.5 V to 10 V Output Range -40C to +85C Ambient Temperature Range FUNCTIONAL BLOCK DIAGRAM Q1 IN OUT ADP3334 THERMAL PROTECTION CC FB gm DRIVER SD BAND GAP REF GND APPLICATIONS Cellular Phones TFT LCD Modules Camcorders, Cameras Networking Systems, DSL/Cable Modems Cable Set-Top Boxes DSP Supplies Personal Digital Assistants GENERAL DESCRIPTION The ADP3334 is available in three different package options: The ADP3334 is a member of the ADP333x family of precision low dropout anyCAP voltage regulators. The ADP3334 operates with an input voltage range of 2.6 V to 11 V and delivers a continuous load current up to 500 mA. The novel anyCAP architecture requires only a very small 1 F output capacitor for stability, and the LDO is insensitive to the capacitor's equivalent series resistance (ESR). This makes the ADP3334 stable with any capacitor, including ceramic (MLCC) types for space restricted applications. 1. Excellent thermal capability, space saving 3 mm 3 mm LFCSP. The ADP3334 achieves exceptional accuracy of 0.9% at room temperature and 1.8% over temperature, line, and load. The dropout voltage of the ADP3334 is only 200 mV (typical) at 500 mA. This device also includes a safety current limit, thermal overload protection, and a shutdown feature. In shutdown mode, the ground current is reduced to less than 1 A. The ADP3334 has low quiescent current of 90 A (typical) in light load situations. 2. Popular low profile MSOP-8. 3. Traditional thermal enhanced SOIC-8. ADP3334 VIN IN OUT IN OUT VOUT R1 CIN 1F FB SD GND CNR COUT 1F R2 OFF ON Figure 1. Typical Application Circuit REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. ADP3334-SPECIFICATIONS1, 2, 3 (V IN = 6.0 V, CIN = COUT = 1.0 F, TA = -40C to +85C, unless otherwise noted.) Parameter Symbol Conditions Min OUTPUT Voltage Accuracy4 VOUT VIN = VOUT(NOM) + 0.4 V to 11 V IL = 0.1 mA to 500 mA TA = 25C VIN = VOUT(NOM) + 0.4 V to 11 V IL = 0.1 mA to 500 mA TA = 85C VIN = VOUT(NOM) + 0.4 V to 11 V IL = 0.1 mA to 500 mA TJ = 150C VIN = VOUT(NOM) + 0.4 V to 11 V IL = 0.1 mA TA = 25C IL = 0.1 mA to 500 mA TA = 25C VOUT = 98% of VOUT(NOM) IL = 500 mA IL = 300 mA IL = 100 mA IL = 1 mA VIN = VOUT(NOM) + 1 V f = 10 Hz-100 kHz, CL = 10 F IL = 500 mA, CNR = 10 nF f = 10 Hz-100 kHz, CL = 10 F IL = 500 mA, CNR = 0 nF Line Regulation4 Load Regulation Dropout Voltage Peak Load Current Output Noise GROUND CURRENT5 In Regulation VDROP ILDPK VNOISE IGND In Dropout IGND In Shutdown IGNDSD SHUTDOWN Threshold Voltage SD Input Current Output Current in Shutdown VTHSD ISD IOSD Max Unit -0.9 +0.9 % -1.8 +1.8 % -2.3 +2.3 % 0.04 mV/V 0.04 mV/mA 200 140 60 10 800 27 400 250 140 45 IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) - 100 mV IL = 0.1 mA SD = 6 V, VIN = 11 V LDO OFF LDO ON 0 SD 5 V SD = 2 V, VIN = 11 V Typ mV mV mV mV mA V rms V rms 4.5 2.6 0.5 90 150 10 6 1.5 130 450 mA mA mA A A 0.9 3 A 1.2 0.01 0.4 3 5 V V A A 2.0 NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. 2 Ambient temperature of 85C corresponds to a junction temperature of 125C under pulsed full load test conditions. 3 Application stable with no load. 4 VIN = 2.6 V to 11 V for V OUT(NOM) 2.2 V. 5 Ground current includes current through external resistors. Specifications subject to change without notice. -2- REV. B ADP3334 ABSOLUTE MAXIMUM RATSINGS* PIN FUNCTION DESCRIPTIONS Input Supply Voltage . . . . . . . . . . . . . . . . . . . -0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . -0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . . -40C to +85C Operating Junction Temperature Range . . . -40C to +150C Storage Temperature Range . . . . . . . . . . . . -65C to +150C JA 2-Layer SOIC-8 . . . . . . . . . . . . . . . . . . . . . . . . 122.3C/W JA 4-Layer SOIC-8 . . . . . . . . . . . . . . . . . . . . . . . . . 86.6C/W JA 2-Layer LFCSP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 62C/W JA 4-Layer LFCSP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 48C/W JA 2-Layer MSOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . 220C/W JA 4-Layer MSOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . 158C/W Lead Temperature Range (Soldering 6 sec) . . . . . . . . . . 300C Mnemonic Function GND SD Ground Pin. Shutdown Control. Pulling this pin low turns on the regulator. Regulator Input. IN *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. OUT Output. Bypass to ground with a 1.0 F or larger capacitor. FB Feedback Input. FB should be connected to an external resistor divider that sets the output voltage. NC No Connection. PIN CONFIGURATIONS OUT 1 OUT 2 FB 3 8 IN OUT 1 8 IN GND 1 8 NC ADP3334ARM 7 IN 7 IN SD 2 ADP3334AR 7 FB TOP VIEW (Not to Scale) OUT 2 6 SD FB 3 6 SD IN 3 TOP VIEW (Not to Scale) 6 OUT 5 GND NC 4 5 GND IN 4 5 OUT NC 4 NC = NO CONNECT ADP3334ACP TOP VIEW* NC = NO CONNECT *PINS UNDERSIDE NC = NO CONNECT ORDERING GUIDE Model Package Output Description ADP3334AR ADJ ADP3334ACP ADJ ADP3334ARM ADJ Package Option Standard Small Outline RN-8 Package (SOIC-8) Lead Frame Chip CP-8 Scale Package (LFCSP) 3 mm 3 mm Body, 8-Lead MSOP Package RM-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3334 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B -3- Brand LLA LLA ADP3334-Typical Performance Characteristics 2.202 IL = 0 2.200 OUTPUT VOLTAGE - V 2.200 2.199 150mA 2.198 2.197 300mA 2.196 2.195 500mA 4 6 8 INPUT VOLTAGE - V 2.199 10 2.197 2.196 2.195 0 100 200 300 OUTPUT LOAD - mA 500 IL = 500mA 0.2 0.1 500mA 0 -0.1 GROUND CURRENT - mA OUTPUT CHANGE - % 0.3 1.0 500mA -0.2 -50 -25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE - C 500 TPC 4. Ground Current vs. Load Current 10 12 VIN = 6V VOUT = 2.2V 6 5 300mA 4 3 2 100mA 1 50mA 0 0 -50 -25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE - C 0 400 4 6 8 INPUT VOLTAGE - V 7 300mA 2.0 2 8 0.4 3.0 0 TPC 3. Ground Current vs. Supply Voltage 0mA 4.0 GROUND CURRENT - mA 400 0.5 200 300 100 OUTPUT LOAD - mA 40 TPC 2. Output Voltage vs. Load Current VIN = 6V VOUT = 2.2V IL = 0 60 20 0 5.0 0 80 2.193 12 VOUT = 2.2V 100 2.198 TPC 1. Line Regulation Output Voltage vs. Supply Voltage 0 IL = 100A 120 2.194 2.194 2 140 VOUT = 2.2V VIN = 6V GROUND CURRENT - A 2.201 OUTPUT VOLTAGE - V 2.201 VOUT = 2.2V TPC 6. Ground Current vs. Junction Temperature TPC 5. Output Voltage Variation % vs. Junction Temperature 200 150 100 VOUT = 2.2V SD = GND RL = 4.4 3.0 2.5 3 2 COUT = 1F 2.0 1 1.5 0 1.0 4 VIN - V INPUT/OUTPUT VOLTAGE - V DROPOUT VOLTAGE - mV VOUT = 2.2V VOUT - V 250 0.5 COUT = 10F 2 VOUT = 2.2V SD = GND RL = 4.4 0 0 50 1 0 0 200 300 100 OUTPUT LOAD - mA 400 TPC 7. Dropout Voltage vs. Output Current 2 3 TIME - s 4 200 400 600 TIME - s 800 500 TPC 8. Power-Up/Power-Down -4- TPC 9. Power-Up Response REV. B ADP3334 VOUT = 2.2V RL = 4.4 CL = 1F 2.180 2.170 3.000 40 80 140 TIME - s VOUT = 2.2V RL = 4.4 CL = 10F 2.170 3.500 3.000 180 40 2.3 2.2 2.2 2.1 400 VIN = 6V VOUT = 2.2V CL = 1F 200 0 200 180 0 2.1 400 600 TIME - s FULL SHORT 800m SHORT 0 200 400 600 TIME - s VIN = 4V 1 0 200 800 TPC 13. Load Transient Response 400 600 TIME - s 2 1F 10F 10F 1 1F 0 200 TPC 14. Short Circuit Current -30 -40 100 120 CL = 1F IL = 50A -50 -60 -70 IL = 500mA WITHOUT NOISE REDUCTION 100 IL = 500mA WITH NOISE REDUCTION 80 IL = 0mA WITHOUT NOISE REDUCTION 60 40 CL = 10F IL = 50A -80 100 1k 10k 100k FREQUENCY - Hz 1M 10M TPC 16. Power Supply Ripple Rejection REV. B 800 10 VOUT = 2.2V IL = 1mA CL = 10F CNR = 10nF CL = 10F CNR = 0 1 CL = 1F CNR = 0 0.1 CL = 1F CNR = 10nF 0.01 20 -90 10 400 600 TIME - s TPC 15. Turn Off/On Response VOUT = 2.0V CNR = 10nF 140 RMS NOISE - V CL = 1F IL = 500mA CL = 10F IL = 500mA 0 VOLTAGE NOISE SPECTRAL DENSITY - V/ Hz VOUT = 2.2V VIN = 6V VOUT = 2.2V RL = 4.4 2 800 160 -20 VSD - V VOUT = 2.2V VIN = 6V CL = 10F 200 800 TPC 12. Load Transient Response 2 400 IOUT - A IOUT - mA 2.3 2.2 3 RIPPLE REJECTION - dB 80 140 TIME - s TPC 11. Line Transient Response VOUT - V TPC 10. Line Transient Response VOUT - V 2.190 2.180 VIN - V VIN - V 3.500 2.200 IOUT - mA 2.190 2.210 VOUT - V 2.200 VOUT - V VOUT - V VOUT - V 2.210 0 0 IL = 0mA WITH NOISE REDUCTION 10 20 30 CL - F 40 TPC 17. RMS Noise vs. CL (10 Hz to 100 kHz) -5- 50 0.001 10 100 1k 10k 100k FREQUENCY - Hz TPC 18. Output Noise Density 1M ADP3334 superior line noise rejection and very high regulator gain, which lead to excellent line and load regulation. An impressive 1.8% accuracy is guaranteed over line, load, and temperature. THEORY OF OPERATION The new anyCAP LDO ADP3334 uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider consisting of R1 and R2 that is varied to provide the available output voltage option. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier. Additional features of the circuit include current limit and thermal shutdown. APPLICATION INFORMATION Output Capacitor OUTPUT INPUT Q1 NONINVERTING WIDEBAND DRIVER ATTENUATION (VBANDG AP / VOUT) COMPENSATION CAPACITOR R3 D1 PTAT FB VOS gm PTAT CURRENT R4 ADP3334 As with any micropower device, output transient response is a function of the output capacitance. The ADP3334 is stable with a wide range of capacitor values, types, and ESR (anyCAP). A capacitor as low as 1 F is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. The ADP3334 is stable with extremely low ESR capacitors (ESR 0), such as multilayer ceramic capacitors (MLCC) or OSCON. Note that the effective capacitance of some capacitor types may fall below the minimum over the operating temperature range or with the application of a dc voltage. R1 CLOAD (a) RLOAD R2 GND Input Bypass Capacitor Figure 2. Functional Block Diagram An input bypass capacitor is not strictly required but is advisable in any application involving long input wires or high source impedance. Connecting a 1 F capacitor from IN to ground reduces the circuit's sensitivity to PC board layout. If a larger value output capacitor is used, then a larger value input capacitor is also recommended. A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that equilibrium produces a large, temperature-proportional input, "offset voltage" that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary diode voltage to form a "virtual band gap" voltage, implicit in the network although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design. Noise Reduction Capacitor A noise reduction capacitor (CNR) can be placed between the output and the feedback pin to further reduce the noise by 6 dB to 10 dB (TPC 18). Low leakage capacitors in the 100 pF to 1 nF range provide the best performance. Since the feedback pin (FB) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible, and long PC board traces are not recommended. The R1, R2 divider is chosen in the same ratio as the band gap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values can be chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider, thus avoiding the error resulting from base current loading in conventional circuits. When adding a noise reduction capacitor, maintain a minimum load current of 1 mA when not in shutdown. It is important to note that as CNR increases, the turn-on time will be delayed. With CNR values of 1 nF, this delay may be on the order of several milliseconds. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type, and ESR of the load capacitance. ADP3334 VIN Most LDOs place very strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value, required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. With the ADP3334 anyCAP LDO, this is no longer true. It can be used with virtually any good quality capacitor, with no constraint on the minimum ESR. This innovative design allows the circuit to be stable with just a small 1 mF capacitor on the output. Additional advantages of the pole-splitting scheme include IN OUT IN OUT VOUT R1 CIN 1F FB SD GND CNR COUT 1F R2 OFF ON Figure 3. Typical Application Circuit Output Voltage The ADP3334 has an adjustable output voltage that can be set by an external resistor divider. The output voltage will be divided by R1 and R2 and then fed back to the FB pin. -6- REV. B ADP3334 To have the lowest possible sensitivity of the output voltage to temperature variations, it is important that the value of the parallel resistance of R1 and R2 be kept as close as possible to 50 kW. 3.0 2.5 VFB = VOUT E R2 A E R1 + R2 OUTPUT ERROR - % R1 R2 (1) = 50 kW R1 + R2 Also, for the best accuracy over temperature, the feedback voltage should be set for 1.178 V: (2) 0 R2 (1% Resistor) (k) 1.5 1.8 2.2 2.7 3.3 5.0 10.0 63.4 76.8 93.1 115.0 140.0 210.0 422.0 232.0 147.0 107.0 88.7 78.7 64.9 56.2 6 VOUT = 3.274 V (5) So worst-case error will occur when R1 has a -1% tolerance and R2 has a +1% tolerance. Recalculating the output voltage, the parallel resistance and error are: E 138.6 VOUT = 1.178 V A + 1 E 79.5 VOUT = 3.232 V (6) E 3.232 Resistor Divider Error = A - 1 100% = - 2.1% E 3.3 R1 R2 138.6 79.5 = = 50.51 kW R1 + R2 138.6 + 79.5 E 50.51 Error = A - 1 100% = 1.02% E 50 RPARALLEL = Using standard 1% values, as shown in Table I, will sacrifice some output voltage accuracy. To estimate the overall output voltage accuracy, it is necessary to take into account all sources of error. The accuracy given in the specifications table does not take into account the error introduced by the feedback resistor divider ratio or the error introduced by the parallel combination of the feedback resistors. RPARALLEL (7) So, from the graph in Figure 4, the output voltage error is estimated to be an additional 0.25%. The error budget is 1.8% (the initial output voltage accuracy over temperature), plus 2.1% (resistor divider error), plus 0.25% (parallel resistance error) for a worst-case total of 4.15%. The error in the parallel combination of the feedback resistors causes the reference to have a wider variation over temperature. To estimate the variation, calculate the worst-case error from 50 kW, and then use the graph in Figure 4 to estimate the additional change in the output voltage over the operating temperature range. Thermal Overload Protection The ADP3334 is protected against damage from excessive power dissipation by its thermal overload protection circuit, which limits the die temperature to a maximum of 165C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165C, the output current is reduced until the die temperature has dropped to a safe level. The output current is restored when the die temperature is reduced. For example: VIN = 5 V VOUT = 3.3 V R1 = 140 kW, 1% R2 = 78.7 kW, 1% REV. B 5 E R1 VOUT = 1.178 V A + 1 E R2 Table I. Feedback Resistor Selection R1 (1% Resistor) (k) 3 4 Rp ERROR - % The actual output voltage can be calculated using the following equation. (4) VOUT (V) 2 Figure 4. Output Voltage Error vs. Parallel Resistance Error (3) 50 kW E VFB A1 - V E OUT 1.0 0 Combining the above equations and solving for R1 and R2 gives the following formulas: R2 = 1.5 0.5 where VOUT is the desired output voltage and VFB is the virtual band gap voltage. Note that VFB does not actually appear at the FB pin due to loading by the internal PTAT current. EV R1 = 50 kW A OUT V E FB 2.0 -7- ADP3334 Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 150C. As an example, the patented thermal coastline lead frame design of the ADP3334 uniformly minimizes the value of the dominant portion of the thermal resistance. It ensures that heat is conducted away by all pins of the package. This yields a very low 86.6C/W thermal resistance for the SOIC-8 package, without any special board layout requirements, relying only on the normal traces connected to the leads. This yields a 15% improvement in heat dissipation capability as compared to a standard SOIC-8 package. The thermal resistance can be decreased by an additional 10% by attaching a few square centimeters of copper area to the IN or OUT pins of the ADP3334 package. Calculating Junction Temperature Device power dissipation is calculated as follows: PD = (VIN - VOUT ) I LOAD + (VIN ) IGND (8) where ILOAD and IGND are load current and ground current, VIN and VOUT are input and output voltages, respectively. Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V and VOUT = 2.8 V, device power dissipation is: PD = (5 - 2.8) 400 mA + 5.0 (4 mA) = 900 mW It is not recommended to use solder mask or silkscreen on the PCB traces adjacent to the ADP3334's pins since it will increase the junction-to-ambient thermal resistance of the package. (9) As an example, the proprietary package used in the ADP3334 has a thermal resistance of 86.6C/W, significantly lower than a standard SOIC-8 package. Assuming a 4-layer board, the junction temperature rise above ambient temperature will be approximately equal to: DTJA = 0.900W 86.6C / W = 77.9C 2x VIAS, 0.250 35m PLATING 0.73 0.30 (10) 1.80 0.90 To limit the maximum junction temperature to 150C, maximum allowable ambient temperature will be: TAMAX = 150C - 77.9C / W = 72.1C 2.36 0.50 (11) The maximum power dissipation versus ambient temperature for each package is shown in Figure 5. 1.40 1.90 3.36 3.5 Figure 6. 3 mm x 3 mm LFCSP Pad Pattern (Dimensions shown in millimeters) 48C/W LFCSP POWER DISSIPATION - W 3.0 LFCSP Layout Considerations 2.5 The LFCSP package has an exposed die paddle on the bottom, which efficiently conducts heat to the PCB. In order to achieve the optimum performance from the LFCSP package, special consideration must be given to the layout of the PCB. Use the following layout guidelines for the LFCSP package. 62C/W LFCSP 2.0 86C/W SOIC 1.5 122C/W SOIC 1.0 0.5 1. The pad pattern is given in Figure 6. The pad dimension should be followed closely for reliable solder joints while maintaining reasonable clearances to prevent solder bridging. 158C/W MSOP 220C/W MSOP 0 -20 0 20 40 60 AMBIENT TEMPERATURE - C 2. The thermal pad of the LFCSP package provides a low thermal impedance path (approximately 20C/W) to the PCB. Therefore the PCB must be properly designed to effectively conduct the heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal path to the inner or bottom layers. See Figure 5 for the recommended via pattern. Note that the via diameter is small to prevent the solder from flowing through the via and leaving voids in the thermal pad solder joint. 80 Figure 5. Power Derating Curve Printed Circuit Board Layout Consideration All surface-mount packages rely on the traces of the PC board to conduct heat away from the package. In standard packages, the dominant component of the heat resistance path is the plastic between the die attach pad and the individual leads. In typical thermally enhanced packages, one or more of the leads are fused to the die attach pad, significantly decreasing this component. To make the improvement meaningful, however, a significant copper area on the PCB must be attached to these fused pins. Note that the thermal pad is attached to the die substrate, so the thermal planes that the vias attach the package to must be electrically isolated or connected to VIN. Do NOT connect the thermal pad to ground. -8- REV. B ADP3334 3. The solder mask opening should be about 120 microns (4.7 mils) larger than the pad size resulting in a minimum 60 micron (2.4 mils) clearance between the pad and the solder mask. Use the following general guidelines when designing printed circuit boards. 4. The paste mask opening is typically designed to match the pad size used on the peripheral pads of the LFCSP package. This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. 2. Keep the input capacitor as close as possible to the input and ground pins. 1. Keep the output capacitor as close as possible to the output and ground pins. 3. PC board traces with larger cross sectional areas will remove more heat from the ADP3334. For optimum heat transfer, specify thick copper and use wide traces. The paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the size of the thermal pad, eliminating voids may not be possible. 4. Use additional copper layers or planes to reduce the thermal resistance. When connecting to other layers, use multiple vias if possible. 5. The recommended paste mask stencil thickness is 0.125 mm. A laser cut stainless steel stencil with trapezoidal walls should be used. Shutdown Mode Applying a TTL high signal to the shutdown (SD) pin or the input pin will turn the output off. Pulling SD down to 0.4 V or below or tying it to ground will turn the output on. In shutdown mode, quiescent current is reduced to much less than 1 A. A "No Clean" Type 3 solder paste should be used for mounting the LFCSP package. Also, a nitrogen purge during the reflow process is recommended. 6. The package manufacturer recommends that the reflow temperature should not exceed 220C and the time above liquidus is less than 75 seconds. The preheat ramp should be 3C/second or lower. The actual temperature profile depends on the board density and must determined by the assembly house as to what works best. REV. B -9- ADP3334 OUTLINE DIMENSIONS 8-Lead Mini Small Outline Package [MSOP] (RM-8) 8-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-8) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) 3.00 BSC 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 8 5 1 4 5 4.90 BSC 3.00 BSC 6.20 (0.2440) 5.80 (0.2284) 1 4 PIN 1 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE 0.50 (0.0196) 45 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 0.65 BSC 1.10 MAX 0.15 0.00 8 0.25 (0.0098) 0 1.27 (0.0500) 0.41 (0.0160) 0.19 (0.0075) 0.51 (0.0201) 0.33 (0.0130) 0.38 0.22 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 0.23 0.08 8 0 0.80 0.40 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA 8-Lead Frame Chip Scale Package [LFCSP] 3 mm 3 mm Body (CP-8) Dimensions shown in millimeters 3.00 BSC SQ 0.60 0.42 0.24 0.60 MAX PIN 1 INDICATOR 0.45 PIN 1 INDICATOR 2 TOP VIEW 2.75 BSC SQ 0.50 BSC 0.90 MAX 0.85 NOM 0.05 MAX 0.01 NOM 0.30 0.23 0.18 BOTTOM VIEW 1.50 REF 1.89 1.74 1.59 0.25 MIN 0.80 MAX 0.65 NOM 12 MAX SEATING PLANE 1 1.60 1.45 1.30 0.20 REF DIMENSIONS SHOWN ARE IN MILLIMETERS -10- REV. B ADP3334 Revision History Location Page 3/03--Data Sheet changed from REV. A to REV. B. Edits to Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Added text to Output Voltage section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Added Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edits to Calculating Junction Temperature section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Renumbered Figures 5 and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1/03--Data Sheet changed from REV. 0 to REV. A. Added 8-Lead LFCSP and 8-Lead MSOP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Edits to product title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Removed pin numbers from Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Added pinouts to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Added text to Calculating Junction Temperature section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Added LFCSP Layout Considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Added Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Updated 8-Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 REV. B -11- -12- C02610-0-3/03(B)