REV. B
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ADP3334
High Accuracy, Low I
Q
, anyCAP
®
Adjustable Low Dropout Regulator
FEATURES
High Accuracy over Line and Load: 0.9% @ 25C,
1.8% over Temperature
500 mA Current Capability
Ultralow Dropout Voltage
Requires Only CO = 1.0 F for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: < 1.0 A (Typ)
2.6 V to 11 V Supply Range
1.5 V to 10 V Output Range
–40C to +85C Ambient Temperature Range
APPLICATIONS
Cellular Phones
TFT LCD Modules
Camcorders, Cameras
Networking Systems, DSL/Cable Modems
Cable Set-Top Boxes
DSP Supplies
Personal Digital Assistants
GENERAL DESCRIPTION
The ADP3334 is a member of the ADP333x family of precision
low dropout anyCAP voltage regulators. The ADP3334 operates
with an input voltage range of 2.6 V to 11 V and delivers a
continuous load current up to 500 mA. The novel anyCAP
architecture requires only a very small 1 µF output capacitor for
stability, and the LDO is insensitive to the capacitor’s equivalent
series resistance (ESR). This makes the ADP3334 stable with any
capacitor, including ceramic (MLCC) types for space restricted
applications.
The ADP3334 achieves exceptional accuracy of ±0.9% at room
temperature and ±1.8% over temperature, line, and load. The
dropout voltage of the ADP3334 is only 200 mV (typical) at
500 mA. This device also includes a safety current limit, ther-
mal overload protection, and a shutdown feature. In shutdown
mode, the ground current is reduced to less than 1 µA. The
ADP3334 has low quiescent current of 90 µA (typical) in light
load situations.
FUNCTIONAL BLOCK DIAGRAM
THERMAL
PROTECTION CC
IN
ADP3334
OUT
GND
Q1
BAND GAP
REF
DRIVER
gm
FB
SD
The ADP3334 is available in three different package options:
1. Excellent thermal capability, space saving 3 mm ⫻ 3 mm LFCSP.
2. Popular low profile MSOP-8.
3. Traditional thermal enhanced SOIC-8.
CNR
ADP3334
OUT
VIN IN
GND
VOUT
ON
OFF
IN
OUT
R1
R2
SD
CIN
1FFB
COUT
1F
Figure 1. Typical Application Circuit
REV. B–2–
ADP3334–SPECIFICATIONS
1, 2, 3
(VIN = 6.0 V, CIN = COUT = 1.0 F, TA = –40C to +85C, unless otherwise noted.)
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT
Voltage Accuracy
4
V
OUT
V
IN
= V
OUT(NOM)
+ 0.4 V to 11 V –0.9 +0.9 %
I
L
= 0.1 mA to 500 mA
T
A
= 25°C
V
IN
= V
OUT(NOM)
+ 0.4 V to 11 V –1.8 +1.8 %
I
L
= 0.1 mA to 500 mA
T
A
= 85°C
V
IN
= V
OUT(NOM)
+ 0.4 V to 11 V –2.3 +2.3 %
I
L
= 0.1 mA to 500 mA
T
J
= 150°C
Line Regulation
4
V
IN
= V
OUT(NOM)
+ 0.4 V to 11 V 0.04 mV/V
I
L
= 0.1 mA
T
A
= 25°C
Load Regulation I
L
= 0.1 mA to 500 mA 0.04 mV/mA
T
A
= 25°C
Dropout Voltage V
DROP
V
OUT
= 98% of V
OUT(NOM)
I
L
= 500 mA 200 400 mV
I
L
= 300 mA 140 250 mV
I
L
= 100 mA 60 140 mV
I
L
= 1 mA 10 mV
Peak Load Current I
LDPK
V
IN
= V
OUT(NOM)
+ 1 V 800 mA
Output Noise V
NOISE
f = 10 Hz–100 kHz, C
L
= 10 µF 27 µV rms
I
L
= 500 mA, C
NR
= 10 nF
f = 10 Hz–100 kHz, C
L
= 10 µF 45 µV rms
I
L
= 500 mA, C
NR
= 0 nF
GROUND CURRENT
5
In Regulation I
GND
I
L
= 500 mA 4.5 10 mA
I
L
= 300 mA 2.6 6 mA
I
L
= 50 mA 0.5 1.5 mA
I
L
= 0.1 mA 90 130 µA
In Dropout I
GND
V
IN
= V
OUT(NOM)
– 100 mV 150 450 µA
I
L
= 0.1 mA
In Shutdown I
GNDSD
SD = 6 V, V
IN
= 11 V 0.9 3 µA
SHUTDOWN
Threshold Voltage V
THSD
LDO OFF 2.0 V
LDO ON 0.4 V
SD Input Current I
SD
0 £ SD £ 5 V 1.2 3 µA
Output Current in Shutdown I
OSD
SD = 2 V, V
IN
= 11 V 0.01 5 µA
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2
Ambient temperature of 85°C corresponds to a junction temperature of 125°C under pulsed full load test conditions.
3
Application stable with no load.
4
V
IN
= 2.6 V to 11 V for V
OUT(NOM)
£ 2.2 V.
5
Ground current includes current through external resistors.
Specifications subject to change without notice.
REV. B
ADP3334
–3–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3334 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATSINGS*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . –40°C to +85°C
Operating Junction Temperature Range . . . –40°C to +150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
JA
2-Layer SOIC-8 . . . . . . . . . . . . . . . . . . . . . . . . 122.3°C/W
JA
4-Layer SOIC-8 . . . . . . . . . . . . . . . . . . . . . . . . . 86.6°C/W
JA
2-Layer LFCSP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W
JA
4-Layer LFCSP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
JA
2-Layer MSOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
JA
4-Layer MSOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
Lead Temperature Range (Soldering 6 sec) . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only. Functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATIONS
ORDERING GUIDE
Package Package
Model Output Description Option Brand
ADP3334AR ADJ Standard Small Outline RN-8
Package (SOIC-8)
ADP3334ACP ADJ Lead Frame Chip CP-8 LLA
Scale Package (LFCSP)
3 mm ⫻ 3 mm Body, 8-Lead
ADP3334ARM ADJ MSOP Package RM-8 LLA
PIN FUNCTION DESCRIPTIONS
Mnemonic Function
GND Ground Pin.
SD Shutdown Control. Pulling this pin low
turns on the regulator.
IN Regulator Input.
OUT Output. Bypass to ground with a 1.0 µF or
larger capacitor.
FB Feedback Input. FB should be connected to
an external resistor divider that sets the
output voltage.
NC No Connection.
8
7
6
5
1
2
3
4
OUT
OUT
FB
NC
IN
IN
SD
GND
TOP VIEW
(Not to Scale)
ADP3334ARM
NC = NO CONNECT
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
GND
SD
IN
IN
NC
FB
OUT
OUT
ADP3334AR
NC = NO CONNECT
TOP VIEW*
ADP3334ACP
*PINS UNDERSIDE
NC = NO CONNECT
1
2
3
4
IN
IN
SD
GND
OUT
OUT
FB
NC
8
7
6
5
REV. B–4–
ADP3334–Typical Performance Characteristics
INPUT VOLTAGE – V
GROUND CURRENT – A
140
60
0012
24 6810
120
100
40
20
80
V
OUT
= 2.2V
I
L
= 100A
I
L
= 0
TPC 3. Ground Current vs.
Supply Voltage
JUNCTION TEMPERATURE – C
GROUND CURRENT – mA
8
6
–50 125
–25 0 25 50 75 100
7
150
5
3
4
1
2
0
300mA
0
100mA
I
L
= 500mA
50mA
V
IN
= 6V
V
OUT
= 2.2V
TPC 6. Ground Current vs.
Junction Temperature
TIME – s
200 400 600 800
3
2
1
0
4
2
0
V
IN
– V V
OUT
– V
V
OUT
= 2.2V
SD = GND
R
L
= 4.4
C
OUT
= 10F
C
OUT
= 1F
TPC 9. Power-Up Response
INPUT VOLTAGE – V
OUTPUT VOLTAGE – V
2.202
2.201
2.194
24 12
6810
2.198
2.197
2.196
2.195
2.200
2.199
I
L
= 0
V
OUT
= 2.2V
500mA
150mA
300mA
TPC 1. Line Regulation Output
Voltage vs. Supply Voltage
OUTPUT LOAD – mA
GROUND CURRENT – mA
5.0
00 100 500
200 300 400
2.0
1.0
4.0
3.0
V
IN
= 6V
V
OUT
= 2.2V
TPC 4. Ground Current vs.
Load Current
OUTPUT LOAD – mA
DROPOUT VOLTAGE – mV
250
200
00 100 500
200 300 400
150
100
50
V
OUT
= 2.2V
TPC 7. Dropout Voltage vs.
Output Current
OUTPUT LOAD – mA
OUTPUT VOLTAGE – V
2.201
2.200
2.193
0 100 500
200 300 400
2.197
2.196
2.195
2.194
2.199
2.198
VOUT = 2.2V
VIN = 6V
TPC 2. Output Voltage vs.
Load Current
JUNCTION TEMPERATURE – C
OUTPUT CHANGE – %
0.5
–50 125
–25 0 25 50 75 100
0.3
0.4
150
0
0.1
0.2
–0.1
–0.2
500mA
300mA
0
500mA
0mA
TPC 5. Output Voltage Variation %
vs. Junction Temperature
TIME – s
1234
3.0
2.5
2.0
1.5
1.0
0.5
0
INPUT/OUTPUT VOLTAGE – V
VOUT = 2.2V
SD = GND
RL = 4.4
TPC 8. Power-Up/Power-Down
REV. B
ADP3334
–5–
V
OUT
= 2.2V
R
L
= 4.4
C
L
= 1F
TIME – s
3.000
3.500
2.170
2.180
2.190
2.200
2.210
40 80 140 180
V
IN
– V V
OUT
– V
TPC 10. Line Transient Response
V
OUT
= 2.2V
V
IN
= 6V
C
L
= 10F
TIME – s
0
200
400
2.1
2.2
2.3
200 400 600 800
I
OUT
– mA V
OUT
– V
TPC 13. Load Transient Response
FREQUENCY – Hz
RIPPLE REJECTION – dB
10 100 1k 10k 100k 1M 10M
–20
–30
–40
–50
–60
–70
–80
–90
C
L
= 1F
I
L
= 500mA
C
L
= 1F
I
L
= 50A
C
L
= 10F
I
L
= 500mA
C
L
= 10F
I
L
= 50A
V
OUT
= 2.2V
TPC 16. Power Supply Ripple
Rejection
V
OUT
= 2.2V
R
L
= 4.4
C
L
= 10F
TIME – s
3.000
3.500
2.170
2.180
2.190
2.200
2.210
40 80 140 180
V
IN
– V V
OUT
– V
TPC 11. Line Transient Response
TIME – s
0
1
2
0
2.2
200 400 600 800
V
IN
= 4V
800m
SHORT
FULL SHORT
3
I
OUT
– A V
OUT
– V
TPC 14. Short Circuit Current
120
160
05010 20 30 40
100
80
60
140
C
L
– F
RMS NOISE – V
40
20
0
V
OUT
= 2.0V
C
NR
= 10nF
I
L
= 0mA WITH NOISE REDUCTION
I
L
= 0mA WITHOUT
NOISE REDUCTION
I
L
= 500mA WITHOUT
NOISE REDUCTION
I
L
= 500mA WITH
NOISE REDUCTION
TPC 17. RMS Noise vs. C
L
(10 Hz to 100 kHz)
VIN = 6V
VOUT = 2.2V
CL = 1F
TIME – s
200 400 600 800
0
200
400
2.1
2.2
2.3
IOUT – mA VOUT – V
TPC 12. Load Transient Response
TIME – s
0
0
2
1
2
200 400 600 800
VSD – V VOUT – V
1F
1F
10F
10F
VIN = 6V
VOUT = 2.2V
RL = 4.4
TPC 15. Turn Off/On Response
FREQUENCY – Hz
VOLTAGE NOISE SPECTRAL
DENSITY – V/ Hz
100
10 100 1M1k 10k 100k
10
1
0.1
0.01
0.001
VOUT = 2.2V
IL = 1mA
CL = 1F
CNR = 0
CL = 10F
CNR = 0
CL = 1F
CNR = 10nF
CL = 10F
CNR = 10nF
TPC 18. Output Noise Density
REV. B–6–
ADP3334
THEORY OF OPERATION
The new anyCAP
LDO ADP3334 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 that is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
PTAT
V
OS
NONINVERTING
WIDEBAND
DRIVER
INPUT
Q1
ADP3334
COMPENSATION
CAPACITOR
ATTENUATION
(V
BANDGAP
/V
OUT
)R1
D1
R2
R3
R4
OUTPUT
PTAT
CURRENT
(a)
C
LOAD
R
LOAD
FB
GND
g
m
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium pro-
duces a large, temperature-proportional input, “offset voltage”
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complementary
diode voltage to form a “virtual band gap” voltage, implicit in
the network although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control
the loop with only one amplifier. This technique also improves
the noise characteristics of the amplifier by providing more
flexibility on the trade-off of noise sources that leads to a low
noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider, thus avoiding the error resulting from
base current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. More-
over, the ESR value, required to keep conventional LDOs stable,
changes depending on load and temperature. These ESR limita-
tions make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
With the ADP3334 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no con-
straint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 mF capacitor on the out-
put. Additional advantages of the pole-splitting scheme include
superior line noise rejection and very high regulator gain, which
lead to excellent line and load regulation. An impressive ±1.8%
accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit and ther-
mal shutdown.
APPLICATION INFORMATION
Output Capacitor
As with any micropower device, output transient response is a
function of the output capacitance. The ADP3334 is stable with
a wide range of capacitor values, types, and ESR (anyCAP).
A capacitor as low as 1 µF is all that is needed for stability;
larger capacitors can be used if high output current surges are
anticipated. The ADP3334 is stable with extremely low ESR
capacitors (ESR ⬇0), such as multilayer ceramic capacitors
(MLCC) or OSCON. Note that the effective capacitance of some
capacitor types may fall below the minimum over the operating
temperature range or with the application of a dc voltage.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance. Connecting a 1 µF capacitor from IN to ground
reduces the circuit’s sensitivity to PC board layout. If a larger
value output capacitor is used, then a larger value input capaci-
tor is also recommended.
Noise Reduction Capacitor
A noise reduction capacitor (C
NR
) can be placed between the
output and the feedback pin to further reduce the noise by
6dB to 10 dB (TPC 18). Low leakage capacitors in the 100 pF
to 1 nF range provide the best performance. Since the feedback
pin (FB) is internally connected to a high impedance node, any
connection to this node should be carefully done to avoid noise
pickup from external sources. The pad connected to this pin
should be as small as possible, and long PC board traces are not
recommended.
When adding a noise reduction capacitor, maintain a mini-
mum load current of 1 mA when not in shutdown.
It is important to note that as C
NR
increases, the turn-on time
will be delayed. With C
NR
values of 1 nF, this delay may be
on the order of several milliseconds.
C
NR
ADP3334
OUT
V
IN
IN
GND
V
OUT
ON
OFF
IN
OUT
R1
R2
SD
C
IN
1FFB
C
OUT
1F
Figure 3. Typical Application Circuit
Output Voltage
The ADP3334 has an adjustable output voltage that can be set
by an external resistor divider. The output voltage will be divided
by R1 and R2 and then fed back to the FB pin.
REV. B
ADP3334
–7–
To have the lowest possible sensitivity of the output voltage to
temperature variations, it is important that the value of the parallel
resistance of R1 and R2 be kept as close as possible to 50 kW.
RR
RR
k
12
12
50
¥
+=W
(1)
Also, for the best accuracy over temperature, the feedback volt-
age should be set for 1.178 V:
VV R
RR
FB OUT
=¥
+
Ê
Ë
Áˆ
¯
˜
2
12
(2)
where V
OUT
is the desired output voltage and V
FB
is the virtual
band gap voltage. Note that V
FB
does not actually appear at the
FB pin due to loading by the internal PTAT current.
Combining the above equations and solving for R1 and R2 gives
the following formulas:
Rk
V
V
OUT
FB
150=¥
Ê
Ë
Áˆ
¯
˜
W
(3)
Rk
V
V
FB
OUT
250
1
=
-
Ê
Ë
Áˆ
¯
˜
W
(4)
Table I. Feedback Resistor Selection
V
OUT
(V)R1 (1% Resistor) (k)R2 (1% Resistor) (k)
1.5 63.4 232.0
1.8 76.8 147.0
2.2 93.1 107.0
2.7 115.0 88.7
3.3 140.0 78.7
5.0 210.0 64.9
10.0 422.0 56.2
Using standard 1% values, as shown in Table I, will sacrifice
some output voltage accuracy. To estimate the overall output
voltage accuracy, it is necessary to take into account all sources
of error. The accuracy given in the specifications table does not
take into account the error introduced by the feedback resistor
divider ratio or the error introduced by the parallel combination
of the feedback resistors.
The error in the parallel combination of the feedback resistors
causes the reference to have a wider variation over temperature.
To estimate the variation, calculate the worst-case error from
50 kW, and then use the graph in Figure 4 to estimate the
additional change in the output voltage over the operating
temperature range.
For example:
V
IN
= 5 V
V
OUT
= 3.3 V
R1 = 140 kW, 1%
R2 = 78.7 kW, 1%
Rp ERROR – %
OUTPUT ERROR – %
3.0
2.5
2.0
1.5
1.0
0.5
0
023456
Figure 4. Output Voltage Error vs.
Parallel Resistance Error
The actual output voltage can be calculated using the following
equation.
V.V
R
R
V.V
OUT
OUT
=¥+
Ê
Ë
Áˆ
¯
˜
=
1 178 1
21
3 274
(5)
So worst-case error will occur when R1 has a –1% tolerance and
R2 has a +1% tolerance. Recalculating the output voltage, the
parallel resistance and error are:
V.V .
.
V.V
Resistor Divider Error .
.
OUT
OUT
=¥+
Ê
Ë
Áˆ
¯
˜
=
=-
Ê
Ë
Áˆ
¯
˜¥=-
1 178 138 6
79 5 1
3 232
3 232
33 1 100 2 1%.%
(6)
RRR
RR
..
.. . k
R Error .
PARALLEL
PARALLEL
=¥
+=¥
+=
=-
Ê
Ë
Áˆ
¯
˜¥=
12
12
138 6 79 5
138 6 79 5 50 51
50 51
50 1100 1 02
W
%.%
(7)
So, from the graph in Figure 4, the output voltage error is
estimated to be an additional 0.25%. The error budget is
1.8% (the initial output voltage accuracy over temperature),
plus 2.1% (resistor divider error), plus 0.25% (parallel resis-
tance error) for a worst-case total of 4.15%.
Thermal Overload Protection
The ADP3334 is protected against damage from excessive power
dissipation by its thermal overload protection circuit, which limits
the die temperature to a maximum of 165°C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165°C, the output
current is reduced until the die temperature has dropped to a safe
level. The output current is restored when the die temperature
is reduced.
REV. B–8–
ADP3334
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150°C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
PVV I VI
DINOUT LOAD IN GND
=-
()
+
()
(8)
where I
LOAD
and I
GND
are load current and ground current, V
IN
and V
OUT
are input and output voltages, respectively.
Assuming I
LOAD
= 400 mA, I
GND
= 4 mA, V
IN
= 5.0 V and
V
OUT
= 2.8 V, device power dissipation is:
PmAmAmW
D
=-
()
+
()
=528400 5 0 4 900..
(9)
As an example, the proprietary package used in the ADP3334
has a thermal resistance of 86.6°C/W, significantly lower than
a standard SOIC-8 package. Assuming a 4-layer board, the
junction temperature rise above ambient temperature will be
approximately equal to:
DT=. W CW C
A
J
0 900 86 6 77 9¥∞=∞./ .
(10)
To limit the maximum junction temperature to 150°C, maxi-
mum allowable ambient temperature will be:
TC/WC
AMAX =∞-∞=∞150 77 9 72 1C..
(11)
The maximum power dissipation versus ambient temperature
for each package is shown in Figure 5.
AMBIENT TEMPERATURE – C
3.5
–20 0 20 406080
POWER DISSIPATION – W
2.5
1.5
1.0
0.5
0
3.0
2.0
158C/W MSOP
220C/W MSOP
122C/W SOIC
86C/W SOIC
62C/W LFCSP
48C/W LFCSP
Figure 5. Power Derating Curve
Printed Circuit Board Layout Consideration
All surface-mount packages rely on the traces of the PC board
to conduct heat away from the package.
In standard packages, the dominant component of the heat
resistance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages, one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement mean-
ingful, however, a significant copper area on the PCB must be
attached to these fused pins.
As an example, the patented thermal coastline lead frame design
of the ADP3334 uniformly minimizes the value of the dominant
portion of the thermal resistance. It ensures that heat is con-
ducted away by all pins of the package. This yields a very low
86.6°C/W thermal resistance for the SOIC-8 package, without
any special board layout requirements, relying only on the normal
traces connected to the leads. This yields a 15% improvement in
heat dissipation capability as compared to a standard SOIC-8
package. The thermal resistance can be decreased by an addi-
tional 10% by attaching a few square centimeters of copper area
to the IN or OUT pins of the ADP3334 package.
It is not recommended to use solder mask or silkscreen on the
PCB traces adjacent to the ADP3334’s pins since it will increase
the junction-to-ambient thermal resistance of the package.
0.50
2x VIAS, 0.250
35µm PLATING
3.36
0.90
1.80
2.36
1.90
1.40
0.30
0.73
Figure 6. 3 mm x 3 mm LFCSP Pad Pattern
(Dimensions shown in millimeters)
LFCSP Layout Considerations
The LFCSP package has an exposed die paddle on the bottom,
which efficiently conducts heat to the PCB. In order to achieve
the optimum performance from the LFCSP package, special
consideration must be given to the layout of the PCB. Use the
following layout guidelines for the LFCSP package.
1. The pad pattern is given in Figure 6. The pad dimension
should be followed closely for reliable solder joints while
maintaining reasonable clearances to prevent solder bridging.
2. The thermal pad of the LFCSP package provides a low ther-
mal impedance path (approximately 20°C/W) to the PCB.
Therefore the PCB must be properly designed to effectively
conduct the heat away from the package. This is achieved by
adding thermal vias to the PCB, which provide a thermal
path to the inner or bottom layers. See Figure 5 for the rec-
ommended via pattern. Note that the via diameter is small to
prevent the solder from flowing through the via and leaving
voids in the thermal pad solder joint.
Note that the thermal pad is attached to the die substrate, so
the thermal planes that the vias attach the package to must
be electrically isolated or connected to V
IN
. Do NOT con-
nect the thermal pad to ground.
REV. B
ADP3334
–9–
3. The solder mask opening should be about 120 microns
(4.7 mils) larger than the pad size resulting in a minimum
60 micron (2.4 mils) clearance between the pad and the
solder mask.
4. The paste mask opening is typically designed to match the
pad size used on the peripheral pads of the LFCSP package.
This should provide a reliable solder joint as long as the
stencil thickness is about 0.125 mm.
The paste mask for the thermal pad needs to be designed for
the maximum coverage to effectively remove the heat from the
package. However, due to the presence of thermal vias and the
size of the thermal pad, eliminating voids may not be possible.
5. The recommended paste mask stencil thickness is 0.125 mm.
A laser cut stainless steel stencil with trapezoidal walls should
be used.
A “No Clean” Type 3 solder paste should be used for mount-
ing the LFCSP package. Also, a nitrogen purge during the
reflow process is recommended.
6. The package manufacturer recommends that the reflow
temperature should not exceed 220°C and the time above
liquidus is less than 75 seconds. The preheat ramp should be
3°C/second or lower. The actual temperature profile depends
on the board density and must determined by the assembly
house as to what works best.
Use the following general guidelines when designing printed
circuit boards.
1. Keep the output capacitor as close as possible to the out-
put and ground pins.
2. Keep the input capacitor as close as possible to the input
and ground pins.
3. PC board traces with larger cross sectional areas will remove
more heat from the ADP3334. For optimum heat transfer,
specify thick copper and use wide traces.
4. Use additional copper layers or planes to reduce the
thermal resistance. When connecting to other layers, use
multiple vias if possible.
Shutdown Mode
Applying a TTL high signal to the shutdown (SD) pin or the
input pin will turn the output off. Pulling SD down to 0.4 V or
below or tying it to ground will turn the output on. In shutdown
mode, quiescent current is reduced to much less than 1 µA.
REV. B–10–
ADP3334
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
Dimensions shown in millimeters and (inches)
0.25 (0.0098)
0.19 (0.0075)
1.27 (0.0500)
0.41 (0.0160)
0.50 (0.0196)
0.25 (0.0099) 45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
85
41
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.33 (0.0130)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
OUTLINE DIMENSIONS
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
0.23
0.08
0.80
0.40
8
0
85
4
1
4.90
BSC
PIN 1
0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COMPLIANT TO JEDEC STANDARDS MO-187AA
COPLANARITY
0.10
8-Lead Frame Chip Scale Package [LFCSP]
3 mm 3 mm Body
(CP-8)
Dimensions shown in millimeters
1
BOTTOM
VIEW
0.50
BSC
0.60 MAX PIN 1 INDICATOR
1.50
REF
0.60
0.42
0.24
0.25
MIN
0.45
2.75
BSC SQ
TOP
VIEW
12 MAX 0.80 MAX
0.65 NOM
SEATING
PLANE
PIN 1
INDICATOR
0.90 MAX
0.85 NOM
0.30
0.23
0.18
0.05 MAX
0.01 NOM
0.20 REF
1.89
1.74
1.59
2
1.60
1.45
1.30
3.00
BSC SQ
DIMENSIONS SHOWN ARE IN MILLIMETERS
REV. B
ADP3334
–11–
Revision History
Location Page
3/03—Data Sheet changed from REV. A to REV. B.
Edits to Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Added text to Output Voltage section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Added Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edits to Calculating Junction Temperature section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Renumbered Figures 5 and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1/03—Data Sheet changed from REV. 0 to REV. A.
Added 8-Lead LFCSP and 8-Lead MSOP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Edits to product title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Removed pin numbers from Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Added pinouts to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Added text to Calculating Junction Temperature section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Added LFCSP Layout Considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Added Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Updated 8-Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
C02610–0–3/03(B)
–12–
