74LCX16240MTDX - Fairchild Semiconductor Corporation

Februa ry 199 4

Revised May 2005

74LCX16240 Low Voltage 16-Bit Inver ting Buffer/Line Driver with 5V Tolera nt Inputs and Outputs

74LCX16240

Low Voltage 16-Bit Inverting Buffer/Line Dri ver

with 5V Tolerant Inputs and Outputs

General Descript ion

The LCX16240 contains sixteen inverting buffers with

3-STATE outputs designed to be employed as a memory

and address driver, clock driver, or bus-oriented transmit-

ter/receiver. The device is nibble controlled. Each nibble

has separate 3- S TATE control inpu ts which can be sh orted

together for full 16-bit operation.

The LCX16240 is designed for low voltage (2.5V or 3.3V)

VCC applicat ions w ith capacity of interfa cing to a 5V sig nal

environment.

The LCX16240 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■5V tolerant inputs and outputs

■2.3V to 3.6V VCC specifications provided

■4.5 ns tPD max (VCC

3.3V), 20

A ICC max

■Power down high impedance inputs and outputs

■Supports live insertion/withdrawal (Note 1)

■

24 mA output drive (VCC

3.0V)

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human body model

2000V

Machine model

200V

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to VCC throug h a pu ll-up res istor: the m inimu m value o r the

resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Devices also available in Tape and R eel. Specify by ap pending th e s uffix let t er “X” to the or dering code.

Connection Diagram Logic Symbol

Pin Descriptions

GTO

is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74LCX16240MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-1 18, 0.300" Wide

74LCX16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Pin Names Description

OEnOutput Enable Inputs (Active LOW)

I0–I15 Inputs

O0–O15 Outputs

■Implements proprietary noise/EMI reduction circuitry

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74LCX16240

Truth Tables

HIGH Voltage Level

LOW Voltage Level

Immaterial

High Impeda nc e

Functional Description

The LCX16240 contains sixteen inverting buffers with

3-STATE standard outputs. The device is nibble (4 bits)

cont rolled with each nib bl e f unct i onin g ide nti ca ll y, but i nde -

pendent of the other. The control pins may be shorted

together to obtain full 16-bit operation. The 3-STATE out-

puts are controlled by an Output Enable (OEn) input for

each nibble. When OEn is LOW, the outputs are in 2-state

mode. When OEn is HIGH, the outputs are in the high

impeda nce mode, b ut this does not interf ere with e ntering

new data into the inputs.

Logic Diagram

Inputs Outputs Inputs Outputs

OE1I0–I3O0–O3OE3I8–I11 O8–O11

LLH LLH

LHL LHL

HXZ HZZ

Inputs Outputs Inputs Outputs

OE2I4–I7O4–O7OE4I12–I15 O12–O15

LLH LLH

LHL LHL

HXZ HZZ

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74LCX16240

Absolute Maximum Ratings(Note 2)

Recommended Operating Conditions (Note 4)

Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be op erated

at these limits. The para metric value s defined in the Elec trical Cha racteristic s tables are n ot guarantee d at the A bsolute Ma ximum R atings . The “Recom-

mended Operating Conditions” table will define th e c onditions for actual devic e operation.

Note 3: IO Absolu te Maximu m Rating must be observed.

Note 4: Unused input s m ust be he ld H I GH or LOW. They may not f loat.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage



0.5 to



7.0 V

VIDC Input Voltage



0.5 to



7.0 V

VODC Output Volta ge



0.5 to



7.0 Output in 3-STATE V



0.5 to VCC



0.5 Output in HIGH or LOW State (Note 3)

IIK DC Input Diode Current



50 VI



GND mA

IOK DC Output Diode Current



50 VO



GND mA



50 VO

VCC

IODC Output Source/Sink Current

50 mA

ICC DC Supply Current per Supply Pin

100 mA

IGND DC Ground Current per Ground Pin

100 mA

TSTG Storage Temperature



65 to



150

Symbol Parameter Min Max Units

VCC Supply Voltage Operating 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Voltage 05.5V

VOOutput Voltage HIGH or LOW State 0 VCC V

3-STATE 0 5.5

IOH/IOL Output Curr en t VCC

3.0V



3.6V

24 mAVCC

2.7V



3.0V

VCC

2.3V



2.7V

TAFree-Air Operating Temperature



40 85

V Input Edge Rate, VIN

0.8V–2.0V, VCC

3.0V 0 10 ns/V

Symbol Parameter Conditions VCC TA



C to



CUnits

(V) Min Max

VIH HIGH Level Input Voltage 2.3



2.7 1.7 V

2.7



3.6 2.0

VIL LOW Level Input Voltage 2.3



2.7 0.7 V

2.7



3.6 0.8

VOH HIGH Level Output Voltage IOH



100

A2.3



3.6 VCC



0.2

IOH



8 mA 2.3 1.8

IOH



12 mA 2.7 2.2

IOH



18 mA 3.0 2.4

IOH



24 mA 3.0 2.2

VOL LOW Level Output Voltage IOL

100

A2.3



3.6 0.2

IOL

8 mA 2.3 0.6

IOL

12 mA 2.7 0.4

IOL

16 mA 3.0 0.4

IOL

24 mA 3.0 0.55

IIInput Leakage Current 0

5.5V 2.3



3.6

5.0

IOZ 3-STATE Output Leakage 0

5.5V 2.3



3.6

5.0

VIH or VIL

IOFF Power-Off Leakage Current VI or VO

5.5V 0 10

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74LCX16240

DC Electrical Characteristics (Continued)

Note 5: Outputs disabled or 3-STATE only.

AC Electrical Characteristics

Note 6: Skew is de fi ned as th e absolut e value of the difference betw een the actual propaga t ion delay f or any t w o separat e outpu ts of t he same device. The

specif ic ation ap plies to an y o ut puts switch ing in the same direction, eit her HIGH-t o-LOW (tOSHL) or LOW-to-H I GH (t OSLH).

Dynamic Switching Characteristics

Capacitance

Symbol Parameter Conditions VCC TA



C to



CUnits

(V) Min Max

ICC Quiescent Supply Current VI

VCC or GND 2.3



3.6 20

3.6V

VI, VO

5.5V (Note 5) 2.3



3.6

ICC Increase in ICC per Input VIH

VCC



0.6V 2.3



3.6 500

Symbol Parameter



C to



C, RL

500

Units

VCC

3.3V

0.3V VCC

2.7V VCC

2.5

0.2V

50 pF CL

30 pF

Min Max Min Max Min Max

tPHL Propagation Delay 1.0 4.5 1.0 5.3 1.0 5.4 ns

tPLH Data to Output 1.0 4.5 1.0 5.3 1.0 5.4

tPZL Output Enable Time 1.0 5.4 1.0 6.0 1.0 7.0 ns

tPZH 1.05.41.06.01.07.0

tPLZ Output Disable Time 1.0 5.3 1.0 5.4 1.0 6.4 ns

tPHZ 1.05.31.05.41.06.4

tOSHL Output to Output Skew (Note 6) 1.0 ns

tOSLH 1.0

Symbol Parameter Conditions VCC TA

CUnit

(V) Typical

VOLP Quiet Output Dynamic Peak VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3 0.8 V

30pF, VIH

2.5V, VIL

0V 2.5 0.6

VOLV Quiet Output Dynamic Valley VOL CL

50 pF, VIH

3.3V, VIL

0V 3.3



0.8 V

30pF, VIH

2.5V, VIL

0V 2.5



0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC

Open, VI

0V or VCC 7pF

COUT Output Capacitance VCC

3.3V, VI

0V or VCC 8pF

CPD Power Dissipation Capacitance VCC

3.3V, VI

0V or VCC, f

10 MHz 20 pF

5 www.fairchildsemi.com

74LCX16240

AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Dela y. Pulse Width and trec Waveforms

3-STATE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Reco very Time for Logic

trise and tfall

FIGURE 2. Waveforms

(Input Characteristics; f =1MHz, tr = tf = 3ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC

3.3

0.3V

VCC x 2 at VCC

2.5

0.2V

tPZH,tPHZ GND

Symbol VCC

3.3V

0.3V 2.7V 2.5V

0.2V

Vmi 1.5V 1.5V VCC/2

Vmo 1.5V 1.5V VCC/2

VxVOL



0.3V VOL



0.3V VOL



0.15V

VyVOH



0.3V VOH



0.3V VOH



0.15V

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74LCX16240

Schematic Diagram Generic for LCX Family

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74LCX16240

Physical Dimensions inches (millimeters) unless otherwise noted

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

Package Number MS48A

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74LCX16240 Low Voltage 16-Bit Inverting Buffer /Line Driver with 5V Tolerant Inputs and Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.