This is information on a product in full production.
July 2014 DocID025378 Rev 3 1/34
L6984
36 V 400 mA synchronous step-down switching regulator
Datasheet - production data
Features
400 mA DC output current
4.5 V to 36 V operating input voltage
Synchronous rectification
Low consumption mode or low noise mode
100 µA IQ at light load (LCM VOUT = 3.3 V)
13 µA IQ-SHTDWN
Adjustable fSW (250 kHz - 600 kHz)
Output voltage adjustable from 0.9 V
No resistor divider required for 3.3 V VOUT
VBIAS maximizes efficiency at light load
350 mA valley current limit
Constant on-time control scheme
PGOOD open collector
Thermal shutdown
Application
Automotive systems (LCM)
Battery powered applications (LCM)
Car audio and low noise applications (LNM)
Sensors (LNM)
E- metering
Description
The L6984 is a step-down monolithic switching
regulator able to deliver up to 400 mA DC. The
output voltage adjustability ranges from 0.9 V. The
fixed 3.3 V VOUT requires no external resistor
divider. The “Low Consumption Mode” (LCM) is
designed for applications active during car
parking, so it maximizes the efficiency at light load
with controlled output voltage ripple. The “Low
Noise Mode” (LNM) makes the switching
frequency almost constant over the load current
range, serving low noise application specification
like car audio/sensors. The PGOOD open
collector output can implement output voltage
sequencing during the power-up phase. The
synchronous rectification, designed for high
efficiency at medium - heavy load, and the high
switching frequency capability make the size of
the application compact. Pulse-by-pulse current
sensing on low-side power element implements
an effective constant current protection.
Figure 1. Application schematic
VDFPN10 3 x 3 x 1.0 mm
VFDFPN10 4 x 4 x 1.0 mm
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Contents L6984
2/34 DocID025378 Rev 3
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Leading network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Light load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2 Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.1 LCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.2 LNM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.1 Output voltage ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.2 COUT specification and loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DocID025378 Rev 3 3/34
L6984 Contents
34
5 Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin settings L6984
4/34 DocID025378 Rev 3
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
1.2 Pin description
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Table 1. Pin description
No. Pin Description
1 PGOOD The open collector output is driven low when the FB voltage is below the VPGD L threshold
(see Table 5).
2 FB Inverting input of the error amplifier
3 TON A resistor connected between this pin and VIN sets the switching frequency.
4EN
Enable pin. A logical active high signal enables the device. Connect this pin to VIN if not
used.
5 GND Power GND
6 LX Switching node
7 VIN DC input voltage
8VCC
Embedded regulator output that supplies the main switching controller.
Connect an external 1 F capacitor for proper operation.
An integrated LDO regulates VCC = 3.3 V if VBIAS voltage is < 2.4 V.
VCC is connected to VBIAS through a MOSFET switch if VBIAS > 3.2 V and the embedded
LDO is disabled to increase the light load efficiency.
9 VBIAS
Typically connected to the regulated output voltage. An external voltage reference can be
used to supply the analog circuitry to increase the efficiency at light load. Connect to GND if
not used.
10 LNM Connect to VCC for low noise mode (LNM) / to GND for low consumption mode (LCM)
operation.
DocID025378 Rev 3 5/34
L6984 Pin settings
34
1.3 Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device.
These are stress ratings only and operation of the device at these or any other conditions
above those indicated in Table 5 of this specification is not implied.
Exposure to absolute maximum rating conditions may affect device reliability.
Table 2. Absolute maximum ratings
1.4 Thermal data
Table 3. Thermal data
Symbol Description Min. Max. Unit
VIN
see Table 1
-0.3 40
V
EN
-0.3 VIN + 0.3LX
TON
VCC -0.3 6
VBIAS
PGOOD
-0.3 VCC + 0.3FB
LNM
TJOperating temperature range -40 150
°C
TSTG Storage temperature range -55 to 150
TLEAD
Lead temperature (soldering
10 sec.) 260
IHS, ILS
High-side RMS switch current 420
mA
Low-side RMS switch current 500
Symbol Parameter Value Unit
Rth JA
Thermal resistance junction ambient
(device soldered on the STMicroelectronics®
evaluation board)
50 C/W
Pin settings L6984
6/34 DocID025378 Rev 3
1.5 ESD protection
Table 4. ESD protection
Symbol Test condition Value Unit
ESD
HBM 2 KV
MM 200 V
CDM 500 V
DocID025378 Rev 3 7/34
L6984 Electrical characteristics
34
2 Electrical characteristics
TJ = 25 °C, VIN = VEN = 12 V, VBIAS = 3.3 V unless otherwise specified.
Table 5. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
VIN Operating input voltage range 4.5 36
V
VIN_UVLO UVLO thresholds
rising edge VCC regulator
VBIAS = GND 3.1 3.8 4.5
falling edge VCC regulator
VBIAS = GND 2.9 3.6 4.3
VOUT
Fixed output voltage valley
regulation FB = VCC, no load 3.23 3.3 3.37
VFB
Adjustable output voltage
valley regulation No load, VBIAS = 3.3 V 0.88 0.9 0.92
RDSON HS High-side RDSON ISW = 0.1 A 0.9 1.3 1.7
RDSON LS Low-side RDSON ISW = 0.1 A 0.6 1.0 1.4
Current limit and zero crossing comparator
IVY Valley current limit 350 400 470
mA
IZCD Zero crossing current threshold (1) 12 27 46
VCC regulator
VCC VCC voltage VFB = 1 V, VBIAS = GND 3 3.8 4.6
V
VBIAS
VBIAS falling threshold 2.4 2.6 2.8
VBIAS rising threshold 2.6 2.9 3.2
Power consumption
ISHTDWN Shutdown current from VIN EN = GND 3 13 22 A
Electrical characteristics L6984
8/34 DocID025378 Rev 3
IQ OPVIN Quiescent current from VIN
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
(2)
11 26 41
A
LCM - NO SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = GND
(2) 90 160 230
LNM - SWO
VREF < VFB < VOVP
VBIAS = 3.3 V
11 26 42
LNM - NO SWO
VREF < VFB < VOVP
VBIAS = GND
200 320 440
IQ OPVBIAS Quiescent current from VBIAS
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
(2) 80 150 200
LNM - SWO
VREF < VFB < VOVP
VBIAS = 3.3 V
180 300 390
Enable
EN
EN thresholds
Device inhibited 1.1
V
Device enabled 2.6
EN hysteresis (3) 650 mV
Overvoltage protection
VOVP Overvoltage trip (VOVP/VREF) Rising edge 18 23 28 %
PGOOD
VPGD L Power good LOW threshold
VFB rising edge
(PGOOD high impedance)
(3) 90
%
VFB falling edge
(PGOOD low impedance) 84 88 92
VPGD H Power good HIGH threshold
Internal FB rising edge
(PGOOD low impedance)
VFB = VCC
118 123 128
Internal FB falling edge
(PGOOD high impedance)
VFB = VCC
(3) 100
VPGOOD PGOOD open collector output
VIN > VIN_UVLO_H,
VFB=GND
4 mA sinking load
0.6 V
2.9 < VIN < VIN_UVLO_H
100 A sinking load 0.6 V
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
DocID025378 Rev 3 9/34
L6984 Electrical characteristics
34
Thermal shutdown
TSHDWN Thermal shutdown temperature (3) 150 C
THYS Thermal shutdown hysteresis (3) 20 C
1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
2. LCM enables SLEEP mode (part of the internal circuitry is disabled) at light load.
3. Not tested in production.
Table 5. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Device description L6984
10/34 DocID025378 Rev 3
3 Device description
The L6984 device is based on a “Constant On-Time” (COT) control scheme with frequency
feed-forward correction over the VIN range. As a consequence the device features fast load
transient response, almost constant switching frequency operation over the input voltage
range and simple stability control.
The switching frequency can be adjusted in the 250 kHz - 600 kHz range.
The LNM (low noise mode) implements constant PWM control to minimize the voltage ripple
over the load range, the LCM (low consumption mode) pulse skipping technique to increase
the efficiency at the light load.
No external resistor divider is required to regulate fixed 3.3 V output voltage, connecting FB
to the VCC pin and VBIAS to the regulated output voltage (see Figure 1 on page 1). An
external voltage divider implements the output voltage adjustability.
The switchover capability of the internal regulator derives a portion of the quiescent current
from an external voltage source (VBIAS pin is typically connected to the regulated output
voltage) to maximize the efficiency at the light load.
The device main internal blocks are shown in the block diagram in Figure 5:
The bandgap reference voltage
The on-time controller
A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the
embedded power elements
The SMPS controller block
The soft-start block to ramp the current limitation
The switchover capability of the internal regulator to supply a portion of the quiescent
current when the VBIAS pin is connected to an external output voltage
The current limitation circuit to implement the constant current protection, sensing
pulse-by-pulse low-side switch current.
A circuit to implement the thermal protection function
LNM pin strapping sets the LNM/LCM mode
The PG (“Power Good”) open collector output
The thermal protection circuitry.
DocID025378 Rev 3 11/34
L6984 Device description
34
Figure 3. L6984 block diagram
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Device description L6984
12/34 DocID025378 Rev 3
3.1 Output voltage adjustment
No external resistor divider is required to regulate fixed 3.3 V output voltage, connecting FB
to the VCC pin and VBIAS to the regulated output voltage (see Figure 1 on page 1). An
external voltage divider otherwise implements the output voltage adjustability.
Figure 4. Internal voltage divider for 3.3 V output voltage
The error amplifier reference voltage is 0.9 V typical.
The output voltage is adjusted accordingly with the following formula (see Figure 5):
Equation 1
Leading network
The small signal contribution of a simple voltage divider is:
Equation 2
A small signal capacitor in parallel to the upper resistor (see C3 in Figure 5) of the voltage
divider implements a leading network (fzero < fpole) that can improve the dynamic regulation
for boundary application conditions (high fSW / high duty cycle conversion) or a not
optimized board layout.
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VOUT 0.9 1 R3
R2
-------+
=
GDIV s R2
R2R3
+
--------------------=
DocID025378 Rev 3 13/34
L6984 Device description
34
Figure 5. L6984 application circuit
Laplace transformer of the leading network:
Equation 3
where:
Equation 4
The R2, R3 compose the voltage divider. CR3 is calculated as (see Section 4.3.2: COUT
specification and loop stability on page 26 for COUT selection):
Equation 5
3.2 Control loop
The L6984 device is based on a constant on-time control loop with frequency feed-forward
correction over the input range. As a consequence the on-time generator compensates the
input voltage variations in order to keep the switching frequency almost constant over the
input voltage range.
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GDIV s R2
R2R3
+
-------------------- 1sR
3CR3
+
1s
R2R3
R2R3
+
-------------------- CR3
+
-----------------------------------------------------------=
fZ
1
2R3CR3
-------------------------------------- =
fP
1
2R2R3
R2R3
+
-------------------- CR3
---------------------------------------------------=
fZfP
CR3 28 10 3–VOUT COUT
R3
----------------------------------=
Device description L6984
14/34 DocID025378 Rev 3
A standard COT loop requires a high ESR output capacitor to generate a proper PWM
signal. The L6984 device supports output ceramic capacitors with negligible ESR.
The controller generates a TON duration switching pulse as soon as the voltage ripple drops
below the valley voltage threshold. The L6984 on-time is calculated as:
Equation 6
where RTON represents the external resistor connected between VIN, TON pins and CTON
the overall contribution given by the integrated capacitor and the parasitic capacitor of the
board trace at the pin 3.
CTON value for the L6984 soldered on the STM evaluation board is 7.5 pF typical, anyway it
depends on the parasitic capacitance connected at the pin 3 (TON) that changes over the
different board layouts. If the final application requires precise TON adjustment, a further
fine tune for RTON value may be required accordingly with the designed board layout. This is
simply done adjusting the RTON value to get the desired TON value with direct scope
measurement.
The L6984 internal circuitry compensates the TOFF time variation over the input voltage
range to keep the switching frequency almost constant.
The almost constant switching frequency depends on the output current and it can be
calculated as:
Equation 7
where DREAL is the real duty cycle accounting conduction losses:
Equation 8
RON_HS and RON_LS represent the RDSON value of the embedded power elements (see
Table 5 on page 7) and DCR the equivalent series resistor of the selected inductor.
The L6984 small signal loop compensates the internal losses, that depends on the output
current value, adjusting the TOFF time so the switching frequency.
Finally from Equation 6 and Equation 7:
Equation 9
where fSW is the desired switching frequency at a certain load current level.
TON
0.9 RTON CTON
VIN
----------------------------------------------- 0.9 RTON 7.5pF
VIN
------------------------------------------------==
fSW IOUT
DREAL IOUT
TON
----------------------------------=
DREAL IOUT
VOUT RON_LS DCR+IOUT
+
VIN RON_LS RON_HS
–IOUT
+
------------------------------------------------------------------------------------=
RTON
1
0.9
--------VIN DREAL IOUT
*
fSW CTON
------------------------------------------------=
DocID025378 Rev 3 15/34
L6984 Device description
34
Figure 6 shows the estimated fSW variation over the load range assuming the typical
RDSON of the power elements, DCR = 420 m (see Section 5 on page 27 for details of the
selected inductor for the reference application board.) and RTON = 1 Meg.
Figure 6. fSW variation over the load range
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Device description L6984
16/34 DocID025378 Rev 3
3.3 Soft-start
The soft-start feature minimizes the inrush current and decreases the stress of the power
components during the power-up phase. The L6984 implements the soft-start clamping the
device current limitation in four different steps.
During normal operation a new soft-start cycle takes place in case of:
Thermal shutdown event
UVLO event
EN pin rising
Figure 7 shows the soft-start feature. The green trace represents the inductor current which
shows different current protection thresholds.
Figure 7. Soft-start feature
3.4 Light load operation
The LNM pinstrapping during the power-up phase determines the light load operation.
3.4.1 Low noise mode (LNM)
Low noise mode implements a forced PWM operation over the different loading conditions.
The LNM features a constant switching frequency to minimize the noise in the final
application and a constant voltage ripple at fixed VIN. The regulator in steady loading
condition never skips pulses and it operates in continuous conduction mode (CCM) over the
different loading conditions.
DocID025378 Rev 3 17/34
L6984 Device description
34
Figure 8. Low noise mode operation
Typical applications for the LNM operation are car audio, sensors.
3.4.2 Low consumption mode (LCM)
The low consumption mode maximizes the efficiency at the light load. As soon as the output
voltage drops, the regulator generates a pulse to have the FB back in regulation. In order to
minimize the current consumption in the LCM part of the internal circuitry is disabled in the
time between bursts.
Figure 9. LCM operation at zero load
Device description L6984
18/34 DocID025378 Rev 3
Figure 10. LCM operation over loading condition (1)
Given the energy stored in the inductor during a burst, the voltage ripple depends on the
capacitor value:
Equation 10
Figure 11. LCM operation over loading condition (2)
When the load current is higher, the IRIPPLE/2 the regulator works in CCM.
VOUT RIPPLE
QIL
COUT
--------------
iLt dt
0
TBURST
COUT
--------------------------------------------==
DocID025378 Rev 3 19/34
L6984 Device description
34
Figure 12. The regulator works in CCM
3.5 Switchover feature
The switch over maximizes the efficiency at the light load that is crucial for LCM
applications.
The main switching controller is supplied by the VCC pin regulator
An integrated LDO regulates VCC = 3.3 V if VBIAS voltage is < 2.4 V.
VCC is connected to VBIAS through a MOSFET switch if VBIAS > 3.2 V and the embedded
LDO is disabled to increase the light load efficiency.
3.5.1 LCM
The LCM operation satisfies the requirements of battery powered applications where it is
crucial to increase the efficiency at the light load.
In order to minimize the regulator quiescent current request from the input voltage, the
VBIAS pin can be connected to an external voltage source in the range 3 V < VBIAS < 5.5 V.
In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current
drawn from the input voltage can be calculated as:
Equation 11
where IQ OP VIN, IQ OP VBIAS are defined in Table 5: Electrical characteristics on page 7 and
L6984 is the efficiency of the conversion in the working point.
IQ VIN IQ OP VIN
1
L6984
---------------- VBIAS
VIN
-------------- IQ OP VBIAS
+=
Device description L6984
20/34 DocID025378 Rev 3
3.5.2 LNM
Equation 11 is also valid when the device works in LNM and it can boost the efficiency at the
medium load since the regulator always operates in continuous conduction mode.
3.6 Overcurrent protection
The current protection circuitry features a constant current protection, so the device limits
the maximum current (see Table 5: Electrical characteristics on page 7) in overcurrent
condition.
The low-side switch pulse-by-pulse current sensing, called “valley”, implements the constant
current protection. In overcurrent condition the internal logic keeps the low-side switch
conducting as long as the switch current is higher than the valley current threshold.
As a consequence the maximum DC output current is:
Equation 12
Figure 13. Constant current operation in dynamic short-circuit
IMAX IVALLEY_TH
IRIPPLE
2
--------------------+ IVALLEY_TH
VIN VOUT
–
L
------------------------------TON
+==
DocID025378 Rev 3 21/34
L6984 Device description
34
Figure 14. Valley current sense implements constant current protection
3.7 PGOOD
The internal circuitry monitors the regulated output voltage and keeps the PGOOD open
collector output in low impedance as long as the feedback voltage is below the VPGD L
threshold (see Table 5).
Figure 15. PGOOD behavior during soft-start time
The PGOOD is driven low impedance if VFB = VCC (internal voltage divider, see Section 3.1
on page 12) and VBIAS > VPGD H threshold (see Table 5 on page 7).
The VPGD H threshold has no effect on PGOOD behavior in case the external voltage divider
is being used.
Device description L6984
22/34 DocID025378 Rev 3
3.8 Overvoltage protection
The overvoltage protection monitors the FB pin and enables the low-side MOSFET to
discharge the output capacitor if the output voltage is 20% over the nominal value. A new
soft-start takes place after the OVP event ends.
Figure 16. Overvoltage operation
The OVP feature is a second level protection and should never be triggered in normal
operating conditions if the system is properly dimensioned. In other words, the selection of
the external power components and the dynamic performance should guarantee an output
voltage regulation within the overvoltage threshold even during the worst case scenario in
term of load transitions.
The protection is reliable and also able to operate even during normal load transitions for
a system whose dynamic performance is not in line with the load dynamic request. As
a consequence the output voltage regulation would be affected.
In Figure 16 the PGOOD output is driven in low impedance (refer to Section 3.7) as long as
the OVP event is present (VFB = VCC, that is an internal resistor divider for VOUT = 3.3 V).
3.9 Thermal shutdown
The shutdown block disables the switching activity if the junction temperature is higher than
a fixed internal threshold (150 °C typical). The thermal sensing element is close to the
power elements, ensuring fast and accurate temperature detection. A hysteresis of
approximately 20 °C prevents the device from turning ON and OFF continuously. When the
thermal protection runs away a new soft-start cycle will take place.
DocID025378 Rev 3 23/34
L6984 Design of the power components
34
4 Design of the power components
4.1 Input capacitor selection
The input capacitor voltage rating must be higher than the maximum input operating voltage
of the application. During the switching activity a pulsed current flows into the input capacitor
and so its RMS current capability must be selected accordingly with the application
conditions. Internal losses of the input filter depend on the ESR value, so usually low ESR
capacitors (like multilayer ceramic capacitors) have a higher RMS current capability. On the
other hand, given the RMS current value, lower ESR input filter has lower losses and so
contributes to higher conversion efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 13
Where IO is the maximum DC output current, D is the duty cycles,
is the efficiency. This
function has a maximum at D = 0.5 and, considering = 1, it is equal to IO/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 14
and
Equation 15
Where
VHIGH_SIDE and
VLOW_SIDE are the voltage drops across the embedded switches.
The peak-to-peak voltage across the input filter can be calculated as:
Equation 16
In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target
VPP can be written as follows:
Equation 17
IRMS IOD2D
2
---------------– D2
2
-------+=
DMAX
VOUT VLOW_SIDE
+
VINMIN VLOW_SIDE VHIGH_SIDE
–+
--------------------------------------------------------------------------------------------------=
DMIN
VOUT VLOW_SIDE
+
VINMAX VLOW_SIDE VHIGH_SIDE
–+
----------------------------------------------------------------------------------------------------=
VPP
IO
CIN fSW
----------------------- 1D
----–
DD
----1D–+ESR IO
+=
CIN
IO
VPP fSW
-------------------------1D
----–
DD
----1D–+=
Design of the power components L6984
24/34 DocID025378 Rev 3
Considering this function has its maximum in D = 0.5:
Equation 18
Typically CIN is dimensioned to keep the maximum peak-to-peak voltage across the input
filter in the order of 5% VIN_MAX.
4.2 Inductor selection
The inductor current ripple flowing into the output capacitor determines the output voltage
ripple (please refer to Section 4.3: Output capacitor selection). Usually the inductor value is
selected in order to keep the current ripple lower than 20% - 40% of the output current over
the input voltage range. The inductance value can be calculated by the following equation:
Equation 19
Where TON and TOFF are the on and off time of the internal power switch. The maximum
current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle
(see Section 4.1 to calculate minimum duty). So fixing IL = 20 % to 40 % of the maximum
output current, the minimum inductance value can be calculated:
Equation 20
where FSW is the switching frequency 1/(TON + TOFF).
For example for VOUT = 3.3 V, VIN = 12 V, IO = 0.4 A and FSW = 600 kHz the minimum
inductance value to have IL = 30 % of IO is about 33 µH.
The peak current through the inductor is given by:
Equation 21
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
Table 6. Input capacitors
Manufacture Series Size Cap value (F) Rated voltage (V)
TDK
C3225X7S1H106M 1210
10 50C3216X5R1H106M 1206
Taiyo Yuden UMK325BJ106MM-T 1210
CIN_MIN
IO
2VPP_MAX fSW
----------------------------------------------=
IL
VIN VOUT
–
L
------------------------------TON
VOUT
L
-------------- TOFF
==
LMIN
VOUT
IMAX
---------------- 1D
MIN
–
FSW
-----------------------=
ILPKIO
IL
2
--------+=
DocID025378 Rev 3 25/34
L6984 Design of the power components
34
In the table below some inductor part numbers are listed.
4.3 Output capacitor selection
4.3.1 Output voltage ripple
The triangular shape current ripple (with zero average value) flowing into the output
capacitor gives the output voltage ripple, that depends on the capacitor value and the
equivalent resistive component (ESR). As a consequence the output capacitor has to be
selected in order to have a voltage ripple compliant with the application requirements.
The voltage ripple equation can be calculated as:
Equation 22
Usually the resistive component of the ripple can be neglected if the selected output
capacitor is a multilayer ceramic capacitor (MLCC).
For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.12 A, fSW = 600 kHz (resulting by the
inductor value) and COUT = 4.7 F MLCC:
Equation 23
The output capacitor value has a key role to sustain the output voltage during a steep load
transient. When the load transient slew rate exceeds the system bandwidth, the output
capacitor provides the current to the load. In case the final application specifies a high slew
rate load transient, the system bandwidth must be maximized and the output capacitor has
to sustain the output voltage for time response shorter than the loop response time.
Table 7. Inductors
Manufacturer Series Inductor value (H) Saturation current (A)
Coilcraft
LPS6225 47 to 150 0.98 to 0.39
LPS5030 10 to 47 1.4 to 0.5
VOUT ESR IMAX
IMAX
8C
OUT fSW
-------------------------------------+=
VOUT
VOUT
------------------ 1
VOUT
-------------- IMAX
8C
OUT fSW
------------------------------------- 1
3.3
--------0.12
84.7F600kHz
-------------------------------------------------
5mV
3.3
-------------= 0.15%==
Design of the power components L6984
26/34 DocID025378 Rev 3
In the table below some capacitor series are listed.
4.3.2 COUT specification and loop stability
Output capacitor value
A minimum output capacitor value is required for the COT loop stability:
Equation 24
Equivalent series resistor (ESR)
The maximum ESR of the output capacitor is:
Equation 25
Table 8. Output capacitors
Manufacturer Series Cap value (F) Rated voltage (V) ESR (m)
MURATA
GRM32 22 to 100 6.3 to 25 < 5
GRM31 10 to 47 6.3 to 25 < 5
PANASONIC
ECJ 10 to 22 6.3 < 5
EEFCD 10 to 68 6.3 15 to 55
SANYO TPA/B/C 100 to 470 4 to 16 40 to 80
TDK C3225 22 to 100 6.3 < 5
COUT
35
VOUT fSW
-----------------------------
ESRMAX 2.8 10 3–VOUT
DocID025378 Rev 3 27/34
L6984 Application board
34
5 Application board
The reference evaluation board schematic is shown in Figure 17.
Figure 17. Evaluation board schematic
Table 9. Bill of material
--
5 105 10
--
5 105 10
& 10& 10
& X)& X)
--
73
(1
73
(1
& Q) 9& Q) 9
73
*1'
73
*1'
&
Q)
&
Q)
73 9287
73 9287
5
N
5
N / X+/ X+
5
5
&
10
&
10
& X) 9& X) 9
5 05 0
5
10
5
10
--
8 /
8 /
3*22'
(1
9,1
9&&
)%
*1'
/;
721
9%,$6
/10
(3
73 9%,$6
73 9%,$6
73 3*22'
73 3*22'
73
9,1
73
9,1
5 0HJ5 0HJ
5
10
5
10
& 10& 10
$0
Reference Part number Description Manufacturer
C1 C3216X5R1H106M 10 F - 50 V - 1206 TDK
C2 100 nF - 50 V - 0805
C4 470 nF - 10 V - 0603
C6 C3216X5R1E226M 22 F - 25 V - 1206 TDK
L1 LPS6225-683MLC 68 H Coilcraft
R1 1 M - 1% - 0603
R4 1 M - 5% - 0603
R6 100 k - 5% - 0603 V
R8 0 - 0603
U1 L6984 STM
J1 JUMPER - CLOSED
J2 JUMPER - CLOSED
J3 JUMPER - OPEN
J4 JUMPER - OPEN
R2, R3, C3, R5, C5, R7, C7 NOT MOUNTED
TP1, TP2, TP3, TP4, TP5,
TP6, TP7
VBIAS, PGOOD, VIN, VOUT, EN, GND,
GND
Application board L6984
28/34 DocID025378 Rev 3
Figure 18. Top layer 3 x 3 DFN demonstration board
Figure 19. Bottom layer 3 x 3 DFN demonstration board
DocID025378 Rev 3 29/34
L6984 Application board
34
Figure 20. Top layer 4 x 4 DFN demonstration board
Figure 21. Bottom layer 4 x 4 DFN demonstration board
Package information L6984
30/34 DocID025378 Rev 3
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
DocID025378 Rev 3 31/34
L6984 Package information
34
Figure 22. VFDFPN10 4 x 4 x 1.0 mm package outline
Table 10. VFDFPN10 4 x 4 x 1.0 mm package mechanical data
Symbol
Dimensions (mm)
Min. Typ. Max.
A 0.80 0.85 0.90
A1 0.02
A2 0.65
A3 0.20
b 0.20 0.25 0.30
D 3.90 4.00 4.10
E 3.90 4.00 4.10
E2 2.15 2.25 2.35
e 0.45 0.50 0.55
H 0.46
L 0.30 0.40 0.50
L1 0.35 0.45 0.55
9)4)31[[
Package information L6984
32/34 DocID025378 Rev 3
Figure 23. VDFPN10 3 x 3 x 1.0 mm package outline
1. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other
feature of package body. Exact shape and size of this feature is optional.
Table 11. VDFPN10 3 x 3 x 1.0 mm mechanical data
Symbol
Dimensions (mm)
Note
Min. Typ. Max.
A 0.80 0.90 1.00
(1)
1. VFDFPN stands for “Thermally Enhanced Very thin Fine pitch Dual Flat Packages No lead”.
Very thin: 0.80 mm < A . 1.00 mm / fine pitch: e < 1.00 mm.
A1 0.02 0.05
A2 0.55 0.65 0.80
A3 0.20
b 0.18 0.25 0.30
D 2.85 3.00 3.15
D2 2.20 2.70
E 2.85 3.00 3.15
E2 1.40 1.75
e 0.50
L 0.30 0.40 0.50
ddd 0.08
9)')31[[
DocID025378 Rev 3 33/34
L6984 Order codes
34
7 Order codes
8 Revision history
Table 12. Order codes
Part number Package Packaging
L6984 VFDFPN10 4 x 4 Tube
L6984TR VFDFPN10 4 x 4 Tape and reel
L6984A VDFPN10 3 x 3 Tube
L6984ATR VDFPN10 3 x 3 Tape and reel
Table 13. Document revision history
Date Revision Changes
11-Oct-2013 1 Initial release.
30-May-2014 2
Updated main title: 36 V 400 mA synchronous step-down switching regulator on
page 1 (replaced “350 mA” by “400 mA”).
Updated Section : Features on page 1 (replaced “350 mA” by “400 mA ”in “DC output
current”).
Updated Section : Description on page 1 (replaced “350 mA” by “400 mA” in “DC”).
Updated Figure 1: Application schematic on page 1 (replaced by new figure, moved
from page 2 to page 1).
Added Contents on page 2.
Updated Table 1.: Pin description on page 4 (minor modifications throughout table).
Updated Section 1.3: Maximum ratings on page 5 (added text above Table 2, added
IHS and ILS max. values in Table 2).
Updated Table 3.: Thermal data on page 5 (added value for “Rth JA” symbol).
Updated Table 5.: Electrical characteristics on page 7 (updated notes 1. to 3., minor
modifications throughout table).
Added Section 3: Device description on page 10, Section 4: Design of the power
components on page 23 and Section 5: Application board on page 27.
Added and updated cross-references throughout document.
Minor modifications throughout document.
04-Jul-2014 3 Updated Table 1.: Pin description on page 4 (updated Description of VCC pin).
Updated Section 3.5: Switchover feature on page 19 (added text).
L6984
34/34 DocID025378 Rev 3
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