a
ADG725/ADG731
16-/32-Channel, Serially Controlled 4
1.8 V to 5.5 V, 2.5 V, Analog Multiplexers
FEATURES
3-Wire SPI Compatible Serial Interface
1.8 V to 5.5 V Single Supply
2.5 V Dual-Supply Operation
4 On Resistance
0.5 On Resistance Flatness
7 mm x 7 mm 48-Lead Chip Scale Package (LFCSP)
or 48-Lead TQFP Package
Rail-to-Rail Operation
Power-On Reset
42 ns Switching Times
Single 32-to-1 Channel Multiplexer
Dual/Differential 16-to-1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent Devices with Parallel
Interface, See ADG726/ADG732
APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems
Medical Instrumentation
Automatic Test Equipment
FUNCTIONAL BLOCK DIAGRAM
S1
S32
D
ADG731
INPUT SHIFT
REGISTER
S1A
DA
S16A
S1B
S16B
DB
ADG725
INPUT SHIFT
REGISTER
SCLK DIN SYNC
SCLK DIN SYNC
GENERAL DESCRIPTION
The ADG731/ADG725 are monolithic, CMOS, 32-channel/
dual 16-channel analog multiplexers with a serially controlled
3-wire interface. The ADG731 switches one of 32 inputs
(S1–S32) to a common output, D. The ADG725 can be config-
ured as a dual mux switching one of 16 inputs to one output, or a
differential mux switching one of 16 inputs to a differential output.
These mulitplexers utilize a 3-wire serial interface that is com-
patible with SPI
®
, QSPI
™
, MICROWIRE
™
, and some DSP
interface standards. On power-up, the Internal Shift Register
contains all zeros and all switches are in the OFF state.
These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high switch-
ing speed with very low on resistance and leakage currents.
They operate from a single supply of 1.8 V to 5.5 V or a
±2.5 V dual supply, making them ideally suited to a variety of
applications. On resistance is in the region of a few ohms, is
closely matched between switches, and is very flat over the full
signal range.
These parts can operate equally well as either multiplexers or
demultiplexers and have an input signal range that extends to the
supplies. In the OFF condition, signal levels up to the supplies
are blocked. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
The ADG731 and ADG725 are serially controlled 32-channel,
and dual/differential 16-channel multiplexers, respectively. They
are available in either a 48-lead LFCSP or TQFP package.
PRODUCT HIGHLIGHTS
1. 3-Wire Serial Interface.
2. 1.8 V to 5.5 V Single-Supply or ±2.5 V Dual-Supply
Operation. These parts are specified and guaranteed
with 5 V ±10%, 3 V ±10% single-supply,
and ±2.5 V ±10% dual-supply rails.
3. On Resistance of 4 W.
4. Guaranteed Break-Before-Make Switching Action.
5. 7 mm ¥ 7 mm 48-Lead Chip Scale Package (LFCSP) or
48-Lead TQFP Package.
Rev. B Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
–2–
ADG725/ADG731–SPECIFICATIONS
1
(VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
B Version
Parameter +25⬚C –40⬚C to +85⬚C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to V
DD
V
On Resistance (R
ON
)4 Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA;
5.56 Ω max Test Circuit 1
On Resistance Match between 0.3Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA
Channels (ΔR
ON
)0.8Ω max
On Resistance Flatness (R
FLAT(ON)
)0.5Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA
1Ω max
LEAKAGE CURRENTS V
DD
= 5.5 V
Source OFF Leakage I
S
(OFF) ±0.01 nA typ V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V;
±0.25 ±1 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.05 nA typ V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V;
ADG725 ±0.5±2.5 nA max Test Circuit 3
ADG731 ±1±5 nA max
Channel ON Leakage I
D
, I
S
(ON) ±0.05 nA typ V
D
= V
S
= 1 V or 4.5 V;
ADG725 ±0.5±2.5 nA max Test Circuit 4
ADG731 ±1±5 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.4V min
Input Low Voltage, V
INL
0.8 V max
Input Current
I
INL
or I
INH
0.005 μA typ V
IN
= V
INL
or V
INH
±0.5μA max
C
IN
, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
42 ns typ R
L
= 300 Ω, C
L
= 35 pF; Test Circuit 5
53 62 ns max V
S1
= 3 V/0 V, V
S32
= 0 V/3 V
Break-Before-Make Time Delay, t
D
30 ns typ R
L
= 300 Ω, C
L
= 35 pF
1 ns minV
S
= 3 V; Test Circuit 6
Charge Injection 5 pC typ V
S
= 2.5 V, R
S
= 0 Ω, C
L
= 1 nF;
Test Circuit 7
Off Isolation –72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk –72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 9
–3 dB Bandwidth
ADG725 34 MHz typ R
L
= 50 Ω, C
L
= 5 pF; Test Circuit 10
ADG731 18 MHz typ
C
S
(OFF) 15 pF typ f = 1 MHz
C
D
(OFF)
ADG725 170 pF typ f = 1 MHz
ADG731 340 pF typ f = 1 MHz
C
D
, C
S
(ON)
ADG725 175 pF typ f = 1 MHz
ADG731 350 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
= 5.5 V
I
DD
10 μA typ Digital Inputs = 0 V or 5.5 V
20 μA max
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. B
ADG725/ADG731
–3–
SPECIFICATIONS
1
(VDD = 3 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
B Version
Parameter +25⬚C –40⬚C to +85⬚C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to V
DD
V
On Resistance (R
ON
)7 Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA;
11 12 Ω max Test Circuit 1
On Resistance Match between 0.35 Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA
Channels (ΔR
ON
)1Ω max
On Resistance Flatness (R
FLAT(ON)
)3Ω max V
S
= 0 V to V
DD
, I
DS
= 10 mA
LEAKAGE CURRENTS V
DD
= 3.3 V
Source OFF Leakage I
S
(OFF) ±0.01 nA typ V
S
= 3 V/1 V, V
D
= 1 V/3 V;
±0.25 ±1 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.05 nA typ V
S
= 1 V/3 V, V
D
= 3 V/1 V;
ADG725 ±0.5±2.5 nA max Test Circuit 3
ADG731 ±1±5 nA max
Channel ON Leakage I
D
, I
S
(ON) ±0.05 nA typ V
S
= V
D
= 1 V or 3 V;
ADG725 ±0.5±2.5 nA max Test Circuit 4
ADG731 ±1±5 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.0V min
Input Low Voltage, V
INL
0.7 V max
Input Current
I
INL
or I
INH
0.005 μA typ V
IN
= V
INL
or V
INH
±0.5μA max
C
IN
, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
60 ns typ R
L
= 300 Ω, C
L
= 35 pF; Test Circuit 5
80 90 ns max V
S1
= 2 V/0 V, V
S32
= 0 V/2 V
Break-Before-Make Time Delay, t
D
30 ns typ R
L
= 300 Ω, C
L
= 35 pF
1 ns minV
S
= 2 V; Test Circuit 6
Charge Injection 1 pC typ V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF;
Test Circuit 7
Off Isolation –72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk –72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 9
–3 dB Bandwidth
ADG725 34 MHz typ R
L
= 50 Ω, C
L
= 5 pF; Test Circuit 10
ADG731 18 MHz typ
C
S
(OFF) 15 pF typ f = 1 MHz
C
D
(OFF)
ADG725 170 pF typ f = 1 MHz
ADG731 340 pF typ f = 1 MHz
C
D
, C
S
(ON)
ADG725 175 pF typ f = 1 MHz
ADG731 350 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
= 3.3 V
I
DD
5μA typ Digital Inputs = 0 V or 3.3 V
10 μA max
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. B
–4–
ADG725/ADG731
DUAL-SUPPLY SPECIFICATIONS1(VDD = +2.5 V 10%, VSS = –2.5 V 10%, GND = 0 V,
unless otherwise noted.)
B Version
Parameter +25⬚C –40⬚C to +85⬚C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
SS
to V
DD
V
On Resistance (R
ON
)4 Ω typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA;
5.56 Ω max Test Circuit 1
On Resistance Match Between 0.3Ω typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA
Channels (ΔR
ON
)0.8Ω max
On Resistance Flatness (R
FLAT(ON)
)0.5Ω typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA
1Ω max
LEAKAGE CURRENTS V
DD
= +2.75 V, V
SS
= –2.75 V
Source OFF Leakage I
S
(OFF) ±0.01 nA typ
V
S
= +2.25 V/–1.25 V, V
D
= –1.25 V/+2.25 V;
±0.25 ±0.5 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.05 nA typ
V
S
= +2.25 V/–1.25 V, V
D
= –1.25 V/+2.25 V;
ADG725 ±0.5±2.5 nA max Test Circuit 3
ADG731 ±1±5 nA max
Channel ON Leakage I
D
, I
S
(ON) ±0.01 nA typ
V
S
= V
D
= +2.25 V/–1.25 V; Test Circuit 4
ADG725 ±0.5±2.5 nA max
ADG731 ±1±5 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
1.7V min
Input Low Voltage, V
INL
0.7 V max
Input Current
I
INL
or I
INH
0.005 μA typ V
IN
= V
INL
or V
INH
±0.5μA max
C
IN
, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
55 ns typ R
L
= 300 Ω, C
L
= 35 pF; Test Circuit 5
75 84 ns max V
S1
= 1.5 V/0 V, V
S32
= 0 V/1.5 V
Break-Before-Make Time Delay, t
D
15 ns typ R
L
= 300 Ω, C
L
= 35 pF
1 ns minV
S
= 1.5 V; Test Circuit 6
Charge Injection 1 pC typ V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; Test Circuit 7
Off Isolation –72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk –72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 9
–3 dB Bandwidth
ADG725 34 MHz typ R
L
= 50 Ω, C
L
= 5 pF; Test Circuit 10
ADG731 18 MHz typ
C
S
(OFF) 13 pF typ
C
D
(OFF)
ADG725 130 pF typ f = 1 MHz
ADG731 260 pF typ f = 1 MHz
C
D
, C
S
(ON)
ADG725 150 pF typ f = 1 MHz
ADG731 300 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
= +2.75 V
I
DD
10 μA typ Digital Inputs = 0 V or 2.75 V
20 μA max
I
SS
10 μA typ V
SS
= –2.75 V
20 μA max Digital Inputs = 0 V or 2.75 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. B
ADG725/ADG731
–5–
TIMING CHARACTERISTICS
1, 2
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
f
SCLK
30 MHz max SCLK Cycle Frequency
t
1
33 ns min SCLK Cycle Time
t
2
13 ns min SCLK High Time
t
3
13 ns min SCLK Low Time
t
4
13 ns minSYNC to SCLK Falling Edge Setup Time
t
5
40 ns minMinimum SYNC Low Time
t
6
5 ns min Data Setup Time
t
7
4.5 ns min Data Hold Time
t
8
33 ns minMinimum SYNC High Time
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
SCLK
SYNC
DIN DB7 DB0
t8t4
t5
t6
t7
t2t3
t1
Figure 1. 3-Wire Serial Interface Timing Diagram
A3 A2 A1 A0
EN CSA X
DB0 (LSB)
DB7 (MSB)
DATA BITS
CSB
Figure 2. ADG725 Input Shift Register Contents
A3 A2 A1 A0
EN CS X
DB0 (LSB)
DB7 (MSB)
DATA BITS
A4
Figure 3. ADG731 Input Shift Register Contents
REV. B
–6–
ADG725/ADG731
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG725/ADG731 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V
Analog Inputs
2
. . . . . . . . . . . . . .V
SS
– 0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Digital Inputs
2
. . . . . . . . . . . . . . . . . .–0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .60 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . .30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
Thermal Impedance (4-Layer Board)
48-lead LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . .25°C/W
48-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .54.6°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . .300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . .235°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at SCLK, SYNC, DIN, S, or D will be clamped by internal diodes.
Current should be limited to the maximum ratings given.
REV. B
ADG725/ADG731
–7–
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTIONS
ADG725 ADG731 Mnemonic Function
1–12, 25–40, 1–12, 25–40, Sxx Source. May be an input or output.
45–48 45–48
13, 14 13, 14 V
DD
Power Supply Input. These parts can be operated from a single supply of 1.8 V to 5.5 V
and a dual supply of ±2.5 V.
17 17 SYNC Active Low Control Input. This is the frame synchronization signal for the input
data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input
Shift Register is enabled. An 8-bit counter is also enabled. Data is transferred on the
falling edges of the following clocks. After eight falling clock edges, switch conditions
are automatically updated. SYNC may be used to frame the signal or just pulled low
for a short period of time to enable the counter and input buffers.
18 18 DIN Serial Data Input. Data is clocked into the 8-bit Input Register MSB first on the falling
edge of the serial clock input.
19 19 SCLK Serial Clock Input. Data is clocked into the Input Shift Register on the falling edge of
the serial clock input. These devices can accommodate serial input rates of up to 30 MHz.
23 23 GND Ground Reference
24 24 V
SS
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications,
connect to GND.
41, 43 N/A DA, DB Drain. May be an input or output.
N/A 43 D
&1"%
Drain. May be an input or output.
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48-Lead LFCSP and TQFP
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
S28
S27
S26
S25
S24
S23
S22
S12
S11
S10
S9
S8
S7
S6
N,C = NO7,17(51$//< CONNECT
S5
S4
S3
S2
S21
S20
S19
S18
ADG731
S1 S17
S13
S14
S15
S16
N,C
D
N,C
N,C
S32
S31
S30
S29
V
DD
V
DD
N,C
N,C
SYNC
DIN
SCLK
N,C
N,C
N,C
GND
V
SS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
S12B
S11B
S10B
S9B
S8B
S7B
S6B
S12A
S11A
S10A
S9A
S8A
S7A
S6A
N,C = NO7 ,17(51$//<CONNECT('
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66
S5A
S4A
S3A
S2A
S5B
S4B
S3B
S2B
ADG725
S1A S1B
S13A
S14A
S15A
S16A
N,C
DA
N,C
DB
S16B
S15B
S14B
S13B
VDD
VDD
N,C
N,C
SYNC
DIN
SCLK
N,C
N,C
N,C
GND
VSS
REV. B
–8–
ADG725/ADG731
Table I. ADG725 Truth Table
A3 A2 A1 A0 EN CSA CSB Switch Condition
X X X X X 1 1 Retains Previous Switch Condition
X X X X 1 X X All Switches OFF
0 0 0 0 0 0 0 S1A – DA, S1B – DB
0 0 0 1 0 0 0 S2A – DA, S2B – DB
0 0 1 0 0 0 0 S3A – DA, S3B – DB
0 0 1 1 0 0 0 S4A – DA, S4B – DB
0 1 0 0 0 0 0 S5A – DA, S5B – DB
0 1 0 1 0 0 0 S6A – DA, S6B – DB
0 1 1 0 0 0 0 S7A – DA, S7B – DB
0 1 1 1 0 0 0 S8A – DA, S8B – DB
1 0 0 0 0 0 0 S9A – DA, S9B – DB
1 0 0 1 0 0 0 S10A – DA, S10B – DB
1 0 1 0 0 0 0 S11A – DA, S11B – DB
1 0 1 1 0 0 0 S12A – DA, S12B – DB
1 1 0 0 0 0 0 S13A – DA, S13B – DB
1 1 0 1 0 0 0 S14A – DA, S14B – DB
1 1 1 0 0 0 0 S15A – DA, S15B – DB
1 1 1 1 0 0 0 S16A – DA, S16B – DB
X = Don’t Care
Table II. ADG731 Truth Table
A4 A3 A2 A1 A0 EN CSA Switch Condition
X X X X X X 1 Retains Previous Switch Condition
X X X X X 1 X All Switches OFF
00000 0 0 1
00001 0 0 2
00010 0 0 3
00011 0 0 4
00100 0 0 5
00101 0 0 6
00110 0 0 7
00111 0 0 8
01000 0 0 9
01001 0 0 10
01010 0 0 11
01011 0 0 12
01100 0 0 13
01101 0 0 14
01110 0 0 15
01111 0 0 16
10000 0 0 17
10001 0 0 18
10010 0 0 19
10011 0 0 20
10100 0 0 21
10101 0 0 22
10110 0 0 23
10111 0 0 24
11000 0 0 25
11001 0 0 26
11010 0 0 27
11011 0 0 28
11100 0 0 29
11101 0 0 30
11110 0 0 31
11111 0 0 32
X = Don’t Care
REV. B
ADG725/ADG731
–9–
TERMINOLOGY
V
DD
Most Positive Power Supply Potential.
V
SS
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect to GND.
I
DD
Positive Supply Current.
I
SS
Negative Supply Current.
GND Ground (0 V) Reference.
S Source Terminal. May be an input or output.
DDrain Terminal. May be an input or output.
V
D
(V
S
) Analog Voltage on Terminals D, S.
R
ON
Ohmic Resistance between D and S.
⌬R
ON
On Resistance Match between any Two Channels.
R
FLAT(ON)
Flatness is defined as the difference between the maximum and minimum value of on resistance,
as measured over the specified analog signal range.
I
S
(OFF) Source Leakage Current with the Switch OFF.
I
D
(OFF) Drain Leakage Current with the Switch OFF.
I
D
, I
S
(ON) Channel Leakage Current with the Switch ON.
V
INL
Maximum Input Voltage for Logic 0.
V
INH
Minimum Input Voltage for Logic 1.
I
INL
(I
INH
) Input Current of the Digital Input.
C
S
(OFF) OFF Switch Source Capacitance. Measured with reference to ground.
C
D
(OFF) OFF Switch Drain Capacitance. Measured with reference to ground.
C
D
,
C
S
(ON) ON Switch Capacitance. Measured with reference to ground.
C
IN
Digital Input Capacitance.
t
TRANSITION
Delay time measured between the 50% points of the eighth clock falling edge and 90% points of the output
when switching from one address state to another.
t
D
OFF time measured between the 80% points of both switches when switching from one address state to another.
Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching.
OFF Isolation A measure of unwanted signal coupling through an OFF switch.
Crosstalk A measure of unwanted signal is coupled through from one channel to another as a result of parasitic capacitance.
On Response The Frequency Response of the ON Switch.
Insertion Loss The Loss Due to the On Resistance of the Switch.
REV. B
–10–
ADG725/ADG731–Typical Performance Characteristics
V
D
, V
S
– V
8
0.0 5.5
0
5.04.54.03.53.02.52.01.51.00.5
1
2
3
4
5
6
7
V
DD
= 2.7V
V
DD
= 3.0V
V
DD
= 4.5V
RESISTANCE –
V
DD
= 3.3V
V
DD
= 5V
V
DD
= 5.5V
T
A
= 25C
V
SS
= 0V
TPC 1. On Resistance vs.
V
D
(V
S
), Single Supply
V
D
, V
S
– V
8
0.0
0
1
2
3
4
5
6
7
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
+85C
–40C
RESISTANCE –
+25C
V
SS
= 0V
TPC 4. On Resistance vs. V
D
(V
S
),
Single Supply
VD, VS – V
QINJ – pC
25
–15–3 –2 5
–101234
20
5
0
–5
–10
15
10
TA = 25C
VDD = +2.5
VSS = –2.5
VDD = +3V
VSS = 0V
VDD = +5V
VSS = 0V
TPC 7. ADG731 Charge Injection
vs. Source Voltage
V
D
, V
S
– V
8
–2.75
0
1
2
3
4
5
6
7
–1.75 –0.75 0.25 1.25 2.25
V
DD
= +2.25V
V
SS
= –2.25V
T
A
= 25C
V
DD
= +2.5V
V
SS
= –2.5V
V
DD
= +2.75V
V
SS
= –2.75V
RESISTANCE –
TPC 2. On Resistance vs.
V
D
(V
S
), Dual Supply
V
D
, V
S
– V
8
–2.5
0
1
2
3
4
5
6
7
–2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5
+85C
–40C
+25C
RESISTANCE –
TPC 5. On Resistance vs.
V
D
(V
S
), Dual Supply
TEMPERATURE – C
–40 –20 80
0 204060
TIME – ns
80
70
0
30
20
10
60
40
50
V
SS
= 0V V
DD
= 3V
V
DD
= 5V
TPC 8. Switching Times vs.
Temperature
V
D
, V
S
– V
8
0.0
0
1
2
3
4
5
6
7
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
+85C
–40C
V
SS
= 0V
RESISTANCE –
+25C
TPC 3. On Resistance vs. V
D
(V
S
)
for Different Temperatures,
Single Supply
TEMPERATURE – C
0.5
5
–0.5 15 8525 35 45 55 65 75
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
V
DD
= 5V
V
SS
= 0V
CURRENT – nA
I
D
(OFF)
I
D
(ON) I
S
(OFF)
TPC 6. Leakage Currents vs.
Temperature
VDD – V
01 6
2345
LOGIC THRESHOLD VOLTAGE – V
1.8
1.6
0
0.8
0.6
0.4
0.2
1.4
1.0
1.2
TA = 25C
FALLING
RISING
TPC 9. Logic Threshold Voltage
vs. Supply Voltage
REV. B
ADG725/ADG731
–11–
FREQUENCY – MHz
0
–100
–70
–60
–50
–40
–30
–20
–10
0.03 0.1 1 10 100
–80
–90
V
DD
= 5V
T
A
= 25C
ATTENUATION – dB
TPC 10. OFF Isolation vs. Frequency
FREQUENCY – MHz
ATTENUATION – dB
0.003 0.1 100110
0
–10
–100
–20
–30
–40
–50
–60
–70
–80
–90
V
DD
= 3V, 5V
T
A
= 25C
TPC 11. Crosstalk vs. Frequency
FREQUENCY – MHz
0
–14
–12
–10
–8
–6
–4
–2
0.03 0.1 1 10 100
V
DD
= 5V
T
A
= 25C
ADG731
ADG725
ATTENUATION – dB
TPC 12. ON Response vs. Frequency
Test Circuits
R
ON
= V
1
/I
DS
V
S
V1
I
DS
D
S
Test Circuit 1. On Resistance
S1
D
V
S
GND
A
V
S
S2
S32
EN LOGIC 1
V
DD
V
SS
V
DD
V
SS
I
S
(OFF)
V
D
Test Circuit 2. I
S
(OFF)
V
D
S1
S2
S32
V
S
D
GND
V
DD
V
DD
A
V
SS
V
SS
A
EN LOGIC 1
I
D
(OFF)
Test Circuit 3. I
D
(OFF)
I
D
(ON)
V
D
S1
S32
V
S
DA
GND
V
DD
V
DD
V
SS
V
SS
A
Test Circuit 4. I
D
(ON)
REV. B
–12–
ADG725/ADG731
50%
V
OUT
tTRANSITION
90%
90%
tTRANSITION
SCLK 50%
V
OUT
D
VS1
*SIMILAR CONNECTION FOR ADG725
GND
ADG731*
S1
S32
S2 TO S31
VS32
R
L
300
C
L
35pF
V
DD
V
DD
V
SS
V
SS
VS1
VS32
8TH FALLING EDGE 8TH FALLING EDGE
Test Circuit 5. Switching Time of Multiplexer, t
TRANSITION
VDD
VDD
VOUT
D
VS
ADG731*
S1
S32
RL
30 0
CL
35pF
tOPE N
80% 80%
0V
VS
SCLK
*SIMILAR CONNECTION FOR ADG725
VSS
V
SS
GND VOUT
S2 THRU S31
8TH FALLING EDGE
Test Circuit 6. Break-Before-Make Delay, t
OPEN
VOUT
V
OUT
SCLK
QINJ = CL

V OUT
VOUT
D
ADG731*
CL
1nF
S
RS
VS
VDD
VDD
*SIMILAR CONNECTION FOR ADG725
GND
VSS
VSS
8th FALLING EDGE
Test Circuit 7. Charge Injection
TEST CIRCUITS (continued)
REV. B
ADG725/ADG731
–13–
ADG731*
*SIMILAR CONNECTION FOR ADG725
VS
V
OUT
NETWORK
ANALYZER
RL
GND
S
D
50
OFF ISOLATION = 20 LOG
VOUT
VS
VDD
0.1F
VDD
VSS
0.1F
VSS
50
50
Test Circuit 8. OFF Isolation
V
DD
D
S2
S32 VS
V
OUT
NETWORK
ANALYZER
RL
S1
ADG731*
VDD
V
SS
V
SS
GND
*SIMILAR CONNECTION FOR ADG725
CHANNEL-TO-CHANNEL CROSSTALK
50
50
50
=
20
LOG
VOUT
VS
Test Circuit 9. Channel-to-Channel Crosstalk
ADG731
*
*SIMILAR CONNECTION FOR ADG725
VS
VOUT
NETWORK
ANALYZER
RL
GND
S
D
VDD
0.1F
VDD
VSS
0.1F
VSS
INSERTION LOSS = 20 LOG
50
50
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Test Circuit 10. Bandwidth
POWER-ON RESET
On power-up of the device, all switches will be in the OFF
condition. The Internal Shift Register is filled with zeros and
will remain so until a valid write takes place.
SERIAL INTERFACE
The ADG725 and ADG731 have a 3-wire serial interface
(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI,
and MICROWIRE interface standards and most DSPs.
Figure 1 shows the timing diagram of a typical write sequence.
Data is written to the 8-bit Shift Register via DIN under the
control of the SYNC and SCLK signals.
When SYNC goes low, the Input Shift Register is enabled. An
8-bit counter is also enabled. Data from DIN is clocked into the
Shift Register on the falling edge of SCLK. Figures 2 and 3
show the contents of the Input Shift Registers for these devices.
When the part has received eight clock cycles after SYNC has
been pulled low, the switches are automatically updated with
the new configuration and the Input Shift Register is disabled.
The ADG725 CSA and CSB data bits allow the user the flex-
ibility to change the configuration of either or both banks of the
multiplexer.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the ADG725/ADG731 is via a serial
bus that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
interface consisting of a clock signal, a data signal, and a
synchronization signal. The ADG725/ADG731 requires an
8-bit data-word with data valid on the falling edge of SCLK.
Figures 4–7 illustrate simple 3-wire interfaces with popular
microcontrollers and DSPs.
ADSP-21xx to ADG725/ADG731 Interface
The ADSP-21xx family of DSPs are easily interfaced to the
ADG725/ADG731 without the need for extra logic. Figure 4
shows an example of an SPI interface between the ADG725/
ADG731 and the ADSP-2191M. SCK of the ADSP-2191M
drives the SCLK of the mux, while the MOSI output drives the
serial data line, DIN. SYNC is driven from one of the port lines,
in this case SPIxSEL.
ADSP-2191M
*
MOSI
SPIxSEL
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
ADG725/ADG731
SYNC
SCLK
DIN
Figure 4. ADSP-2191M to ADG725/ADG731 Interface
REV. B
–14–
ADG725/ADG731
A serial interface between the ADG725/ADG731 and the ADSP-
2191M SPORT is shown in Figure 5. In this interface example,
SPORT0 is used to transfer data to the switch. Transmission is
initiated by writing a word to the Tx Register after the SPORT
has been enabled. In a write sequence, data is clocked out on
each rising edge of the DSP’s serial clock and clocked into the
ADG725/ADG731 on the falling edge of its SCLK. The update
of each switch condition takes place automatically after the eighth
SCLK falling edge, regardless of the frame sync condition.
Communication between two devices at a given clock speed is
possible when the following specs are compatible: frame sync
delay and frame sync setup and hold, data delay and data setup
and hold, and SCLK width. The ADG725/ADG31 expects a
t
4
(SYNC falling edge to SCLK falling edge set-up time) of 13 ns
minimum. Consult the ADSP-21xx User Manual for information
on clock and frame sync frequencies for the SPORT Register.
The SPORT Control Register should be set up as follows:
TFSW = 1, Alternate Framing
INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
ITFS = 1, Internal Framing Signal
SLEN = 0111, 8-Bit Data-Word
ADSP-2191M
*
DT
TFS
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
ADG725/ADG731
SYNC
SCLK
DIN
Figure 5. ADSP-2191M to ADG725/ADG731 Interface
8051 to ADG725/ADG731 Interface
A serial interface between the ADG725/ADG731 and the 8051
is shown in Figure 6. TXD of the 8051 drives SCLK of the
ADG725/ADG731, while RXD drives the serial data line, DIN.
P3.3 is a bit-programmable pin on the serial port and is used to
drive SYNC.
The 8051 provides the LSB of its SBUF Register as the first bit
in the data stream. The user will have to ensure that the data in
the SBUF Register is arranged correctly as the switch expects
MSB first.
When data is to be transmitted to the switch, P3.3 is taken low.
Data on RXD is clocked out of the microcontroller on the rising
edge of TXD and is valid on the falling edge. As a result, no
glue
logic is required between the ADG725/ADG731 and
microcontroller interface.
80C51/80L51
*
RXD
P3.3
TXD
*ADDITIONAL PINS OMITTED FOR CLARITY
ADG725/ADG731
SYNC
SCLK
DIN
Figure 6. 8051 to ADG725/ADG731 Interface
MC68HC11 Interface to ADG725/ADG731
Figure 7 shows an example of a serial interface between the
ADG725/ADG731 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the mux, while the MOSI
output drives the serial data line, DIN. SYNC is driven from
one of the port lines, in this case PC7. The 68HC11 is config-
ured for Master Mode: MSTR = 1, CPOL = 0, and CPHA = 1.
When data is transferred to the part, PC7 is taken low, and data
is transmitted MSB first. Data appearing on the MOSI output is
valid on the falling edge of SCK.
MC68HC11
*
MOSI
PC7
SYNC
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
ADG725/ADG731
SCLK
DIN
Figure 7. MC68HC11 Interface to ADG725/ADG731
APPLICATION CIRCUITS
ADG725/ADG731 in an Optical Network Control Loop
The ADG725/ADG731 can be used in optical network applica-
tions that have higher port counts and greater multiplexing
requirements. The ADG725/ADG731 are well suited to these
applications because they allow a single control circuit to con-
nect a higher number of channels without increasing board size
and design complexity.
In the circuit shown in Figure 8, the 0 V to 5 V outputs of the
AD5532HS are amplified to a range of 0 V to 180 V and then
used to control actuators that determine the position of MEMS
mirrors in an optical switch. The exact position of each mirror is
measured using sensors. The sensor readings are muxed using
the ADG731, a 32-channel switch, and fed back to a single-
channel 14-bit ADC (AD7894).
The control loop is driven by an ADSP-2191L, a 32-bit DSP
with an SPI compatible SPORT interface. It writes data to the
DAC, controls the multiplexer, and reads data from the ADC
via a 3-wire serial interface.
.........
1
32
AD7894
ADSP-2191M
.........
1
32
ADG731
AD5532HS MEMS
MIRROR
ARRAY
SENSORS
Figure 8. Optical Network Control Loop
Expand the Number of Selectable Serial Devices Using the
ADG725/ADG731
The SYNC pin of the ADG725/ADG731 can be used to select
one of a number of multiplexers. All devices receive the same
serial clock and serial data, but only one device will receive the
REV. B
ADG725/ADG731
–15–
SYNC signal at any one time. The mux addressed will be deter-
mined by the decoder. There will be some digital feedthrough
from the digital input lines. Using a burst clock will minimize the
effects of digital feedthrough on the analog signal channels.
Figure 9 shows a typical circuit.
ENABLE
DIN
SCLK
DGND
CODED
ADDRESS
DECODER
VDD
EN
DIN
SCLK
DIN
SCLK
DIN
SCLK
ADG725/
ADG731
SYNC
DIN
SCLK
SYNC
SYNC
SYNC
D
D
D
D
OTHER SPI
DEVICE
ADG725/
ADG731
OTHER SPI
DEVICE
Figure 9. Addressing Multiple ADG725/ADG731s
Using a Decoder
REV. B
ADG725/ADG731
Rev. B | Page 16
OUTLINE DIMENSIONS
Figure 10. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
Figure 11. 48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG725BCPZ –40°C to +85°C 48-Lead Frame Chip Scale Package [LFCSP] CP-48-4
ADG725BSUZ –40°C to +85°C 48-Lead Thin Plastic Quad Flat Package [TQFP] SU-48
ADG731BCPZ –40°C to +85°C 48-Lead Frame Chip Scale Package [LFCSP] CP-48-4
ADG731BCPZ-REEL –40°C to +85°C 48-Lead Frame Chip Scale Package [LFCSP] CP-48-4
ADG731BCPZ-REEL7 –40°C to +85°C 48-Lead Frame Chip Scale Package [LFCSP] CP-48-4
ADG731BSUZ –40°C to +85°C 48-Lead Thin Plastic Quad Flat Package [TQFP] SU-48
1 Z = RoHS Compliant Part.
112408-B
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURA TION AND
FUNCTION DES CRIPTIONS
SECTION OF T HIS DATA SHEET.
COM P LIA NT T O JEDEC ST AN DARDS MO -220-WKKD.
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
7.00
BSC SQ
48
13
24
25
36
37
12
EXPOSED
PAD
PIN 1
INDICATOR
5.20
5.10 S Q
5.00
0.45
0.40
0.35
S
EATING
PLANE
0.80
0.75
0.70 0. 05 M A X
0.02 NO M
0.25 M IN
0.20 RE F
COPLANARITY
0.08
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MS-026ABC
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
9.00
BSC SQ
7.00
BSC SQ
1.20
MAX
TOP VIEW
(PINS DOWN)
1
12 13 25
24
36
37
48
0.75
0.60
0.45
PIN 1
VIEW A
1.05
1.00
0.95
0.20
0.09
0.08 MAX
COPLANARITY
SEATING
PLANE
0° MIN
7°
3.5°
0°
0.15
0.05
VIEW A
ROTATED 90° CCW
ADG725/ADG731
Rev. B | Page 17
REVISION HISTORY
9/15—Rev. A to Rev. B
Changed NC Pin to NIC Pin ........................................ Throughout
Added Exposed Pad Notation, ADG725 Pin Configuration ...... 7
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
6/03—Rev. 0 to Rev. A
Edits to Ordering Guide .................................................................. 6
Edits to Pin Configurations ............................................................. 7
Edits to Pin Function Descriptions ................................................ 7
Changes to Test Circuit 3 ............................................................... 11
Updated Outline Dimensions ....................................................... 16
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02766-0-9/15(B)