DALLAS SEMICONDUCTOR DS1990A Serial Number iButton DS1990A SPECIAL FEATURES Upgrade of DS1990 allows multiple Serial Number iButtons to reside on a common bus Unique 48-bit serial number Low-cost electronic key for access control 8-bit CRC for checking data integrity Can be read in less than 5 ms Operating temperature range of -40C to +85C COMMON iButton FEATURES Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48- bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike Multidrop controller for MicroLAN Digital identification by momentary contact Chip-based data carrier compactly stores information Data can be accessed while affixed to an object Economically communicates to bus master with a single digital signal at 16.3k bits per second Standard 16 mm diameter and 1-Wire protocol ensure compatibility with iButton family Button shape is self-aligning with cup- shaped probes Durable stainless steel case engraved with registration number withstands harsh environments Easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim Presence detector acknowledges when reader first applies voltage Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for use in Class 1, Division 1, Group A, B, C and D locations 1 of 10 F3 MICROCAN DALLAS YYWW REGISTERED RR 66 01 OQO000OFBC52B GROUND F5 MICROCAN 0.3 YYWW REGISTERED RR 1 E6 OQOOO0OOFBD8B3 GROUND All dimensions shown in millimeters ORDERING INFORMATION DS1990A-F3 F3 MicroCan DS1990A-F5 F5 MicroCan EXAMPLES OF ACCESSORIES DS9096P Self-Stick Adhesive Pad DS9101 Multi-Purpose Clip DS9093RA Mounting Lock Ring DS9093F Snap-In Fob DS9092 iButton Probe 081999DS1990A iButton DESCRIPTION The DS1990A Serial Number iButton is a rugged data carrier that acts as an electronic registration number for automatic identification. The DS1990A consists of a factory-lasered, 64-bit ROM that includes an unique 48-bit serial number, an 8-bit CRC and an 8-bit Family Code (01h). Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return. The DS1990A is fully compatible with the DS1990 Serial Number iButton but provides the additional 1-Wire protocol capability that allows the Search ROM command to be interpreted by the DS1990A and therefore allows multiple DS1990A devices to reside on a single data line. The durable MicroCan package is highly resistant to environmental hazards such as dirt, moisture and shock. Its compact coin-shaped profile is self-aligning with mating receptacles, allowing the DS1990A to be used easily by human operators. Accessories permit the DS1990A to be mounted on plastic key tabs, photo ID badges, printed circuit boards or any smooth surface of an object. Applications include access control, work-in-progress tracking, tool management and inventory control. OPERATION The DS1990As internal ROM is accessed via a single data line. The 48-bit serial number, 8-bit family code and 8-bit CRC are retrieved using the Dallas 1-Wire protocol. This protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. All data is read and written least significant bit first. 1-WIRE BUS SYSTEM The 1-Wire bus is a system which has a single bus master system and one or more slaves. In all instances, the DS1990A is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal type and timing). For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards. Hardware Configuration The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an open drain connection or 3-state outputs. The DS1990A is an open drain part with an internal circuit equivalent to that shown in Figure 2. The bus master can be the same equivalent circuit. If a bidirectional pin is not available, separate output and input pins can be tied together. The bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figure 3. The value of the pullup resistor should be approximately 5 kQ for short line lengths. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second. The idle state for the 1-Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120 Us, one or more of the devices on the bus may be reset. 2 of 10DS1990A DS1990A MEMORY MAP Figure 1 8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (01h) MSB LSB MSB LSB MSB LSB DS1990A EQUIVALENT CIRCUIT Figure 2 R x Data(inner surface) + Tp Tx Typ. 100Q MOSFET \/V_ Ground (outer rim) BUS MASTER CIRCUIT Figure 3 A) Open Drain Vpp | BUS MASTER DS5000 OR 8051 EQUIVALENT Vpp en Drain 5 kQ ort Pin i To data connection of DS1990A r B) Standard TTL v Vpp | BUS MASTER 5 kQ TTL-Equivatent Port Pins o<h| To data connection -{>0 of DS1990A 5kQ v 3 of 10DS1990A TRANSACTION SEQUENCE The sequence for accessing the DS1990A via the 1-Wire port is as follows: Initialization ROM Function Command Read Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1990A is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the four ROM function commands. All ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in Figure 4): Read ROM [33h] or [OFh] This command allows the bus master to read the DS1990As 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS1990A on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The DS1990A Read ROM function will occur with a command byte of either 33h or OFh in order to ensure compatibility with the DS1990, which will only respond to a OFh command word with its 64-bit ROM data. Match ROM [55h] / Skip ROM [CCh] The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Match ROM and a Skip ROM command. (See the Book of DS19xx iButton Standards.) Since the DS1990A contains only the 64- bit ROM with no additional data fields, the Match ROM and Skip ROM are not applicable and will cause no further activity on the 1-Wire bus if executed. The DS1990A does not interfere with other 1-Wire parts on a multidrop bus that do respond to a Match ROM or Skip ROM (example DS1990A and DS1994 on the same bus). Search ROM [FOh] When a system is initially brought up, the bus master might not know the number of devices on the 1- Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual example. 4 of 1033h or OFh READ ROM COMMAND ROM FUNCTIONS FLOW CHART Figure 4 MASTER Tx < RESET PULSE y DS1990A Tx PRESENCE PULSE ! FUNCTION COMMAND MASTER Ty ROM DS1990A Tx FAMILY CODE 1 BYTE DS1990A Tx SERIAL NUMBER 6 BYTES DS1990A Ty CRC BYTE FOh SEARCH ROM COMMAND DS1990A Tx BIT 0 DS1990A Ty BIT 0 MASTER Tx BIT 0 z BIT O MATCH? DS1990A Ty BIT 1 DS1990A Tx BIT 1 MASTER Tx BIT 1 Y vy DS1990A Ty BIT 63 DS1990A Tx BIT 63 MASTER Ty BIT 63 BIT 63 MATCH? 5 of 10DS1990A 1-WIRE SIGNALING The DS1990A requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset sequence with Reset Pulse and Presence Pulse, write 0, write 1 and read data. All these signals except presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS1990A is shown in Figure 5. A Reset Pulse followed by a Presence Pulse indicates the DS1990A is ready to send or receive data given the correct ROM command. The bus master transmits (Tx ) a reset pulse ( a low signal for a minimum of 480 us). The bus master then releases the line and goes into receive mode (Rx ). The 1-Wire bus is pulled to a high state via the 5 kQ pullup resistor. After detecting the rising edge on the data contact, the DS1990A waits (tppy , 15-60 us) and then transmits the presence pulse (tpp_, 60-240 us). READ/WRITE TIME SLOTS The definitions of write and read time slots are illustrated in Figure 6. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS1990A to the master by triggering a delay circuit in the DS1990A. During write time slots, the delay circuit determines when the DS1990A will sample the data line. For a read data time slot, if a O is to be transmitted, the delay circuit determines how long the DS1990A will hold the data line low overriding the 1 generated by the master. If the data bit is a 1, the iButton will leave the read data time slot unchanged. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSES Figure 5 |_ MASTER Ty RESET PULSE |__ MASTER Rx PRESENCE PULSE" | [ a | t tRSTH VPuLLUP VPULLUP MIN IH MIN ViL MAX OV tr tppH RESISTOR 480 Ls S trstL< c * 480 Us < trstu< co (includes recovery time) MASTER 15 Ls < tppy < 60 Us EaiaeE DS1990A 60 Us < tppL< 240 Ls * Tn order not to mask interrupt signaling by other devices on the 1-Wire bus, tas7+ ta should always be less than 960 us. 6 of 10DS1990A READ/WRITE TIMING DIAGRAM Figure 6 Write-One Time Slot tsLorT VeULLUP VPULLUP MIN Vint MIN DS1990A ViL MAX SAMPLING WINDOW ov 60 ps 60 lis S$ tstor < 120 Ls 1 Ls < trowi< 15 Ls 1 Ls < trac <0 Write-Zero Time Slot tREC VeULLUP VPULLUP MIN 14 MIN DS1990A VIL MAX OV 60 ps tLowo 60 Lis S$ tlowo< tstor< 120 Ls 1 Ls < trrc< 0 Read-Data Time Slot VeuLLuP VPULLUP MIN Vin MIN MASTER SAMPLING Vik MAX WINDOW ov tRELEASE | RESISTOR 60 Us $ tstor< 120 Us 1 Us S trowr< 15 Us MASTER O < trrieasn < 45 Us amon DS1990A 1 Us S trpc< trpv = 15 Us tsu = 1 us 7 of 10DS1990A CRC ASSEMBLY LANGUAGE PROCEDURE Table 1 DO_CRC: PUSH ACC ; save the accumulator PUSH B ; save the B register PUSH ACC ; save bits to be shifted MOV B,#8 set shift=8bits CRC_LOOP: XRL A,CRC ; calculate CRC RRC A ; move it to the carry MOV A,CRC ; get the last CRC value JNC ZERO ; skip if data=0 XRL A,#18H ; update the CRC value ZERO: RRC A ; position the new CRC MOV CRCVA ; store the new CRC POP ACC ; get the remaining bits RR A ; position the next bit PUSH ACC ; save the remaining bits DJINZ B,CRC_LOOP ; repeat for eight bits POP ACC ; clean up the stack POP B ; restore the B register POP ACC ; restore the accumulator RET CRC GENERATION To validate the data transmitted from the DS1990A, the bus master may generate a CRC value from the data as it is received. This generated value is compared to the value stored in the last eight bits of the DS1990A. The bus master computes the CRC over the 8-bit family code and all 48 ID number data bits, but not over the stored CRC value itself. If the two CRC values match, the transmission is error-free. An example of how to generate the CRC using assembly language software is shown in Table 1. This assembly language code is written for the DS5000 Soft microcontroller which is compatible with the 8031/51 Microcontroller family. The procedure DO_CRC calculates the cumulative CRC of all the bytes passed to it in the accumulator. It should be noted that the variable CRC needs to be initialized to 0 before the procedure is executed. Each byte of the data is then placed in the accumulator and DO-CRC is called to update the CRC variable. After all the data has been passed to DO_CRC, the variable CRC will contain the result. The equivalent polynomial function of this software routine is: For more details, see the Book of DS19xx iButton Standards. CRC = x84 x4-x741 8 of 10DS1990A ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground -0.5V to +7.0V Operating Temperature -40C to +85C Storage Temperature -55C to +125C * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (Vpup=2.8V to 6.0V; -40C to +85 C) PARAMETER SYMBOL | MIN TYP MAX UNITS NOTES Logic 1 Vin 2.2 Vcc +0.3 Vv 1,6 Logic 0 VoL -0.3 +0.8 Vv 1 Output Logic Low @ 4 mA VoL 0.4 Vv 1 Output Logic High Vou Veup 6.0 V 1,2 Input Load Current I, 5 uA 3 Operating Charge Qop 30 nC 7,8 CAPACITANCE (TA = 25) PARAMETER SYMBOL | MIN TYP MAX UNITS NOTES lO (1-Wire) Cour 100 800 pF 9 AC ELECTRICAL CHARACTERISTICS (Vpup=2.8V to 6.0V; -40C to +85 C) PARAMETER SYMBOL | MIN TYP MAX UNITS NOTES Time Slot tsLoT 60 120 Us Write 1 Low Time tlow1 1 15 us Write 0 Low Time tLowo 60 120 Ls Read Data Valid trpv exactly 15 Ls Release Time tRELEASE 0 15 45 Us Read Data Setup tsu 1 us 5 Recovery Time trac 1 Ls Reset Time High trsTH 480 Ls 4 Reset Time Low test. 480 us 10 Presence Detect High tppr 15 60 us Presence Detect Low tppL 60 240 us 9 of 10DS1990A NOTES: 1. 2. 3. 4. 10. All voltages are referenced to ground. Vpup= external pullup voltage. Input load is to ground. An additional reset or communication sequence cannot begin until the reset high time has expired. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 us of this falling edge and will remain valid for 14 Us minimum. (15 us total from falling edge on 1-Wire bus.) Vin is a function of the external pullup resistor and the Voc supply. 30 nanocoulombs per 72 time slots @ 5.0V. At Vec=5.0V with a 5 k pullup to V ccand a maximum time slot of 120 Us. Capacitance on the I/O pin could be 800 pF when power is first applied. If a 5 kQ resistor is used to pull up the I/O line to Vcc, 5 Us after power has been applied the parasite capacitance will not affect normal communications. The reset low time (tgs) should be restricted to a maximum of 960 us, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses if this device is used in parallel with a DS1994. 10 of 10