Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 fido1100(R) Data Sheet 32-Bit Real-Time Communications Controller IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 1 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Copyright 2017 by Innovasic, Inc. Published by Innovasic, Inc. 5635 Jefferson St. NE, Suite A, Albuquerque, New Mexico 87109 USA fido(R), fido1100(R), and SPIDER are trademarks of Innovasic, Inc. I2CTM Bus is a trademark of Philips Electronics N.V. Motorola is a registered trademark of Motorola, Inc. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 2 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 TABLE OF CONTENTS List of Figures ..................................................................................................................................5 List of Tables ...................................................................................................................................6 1. Overview.................................................................................................................................7 2. Features ...................................................................................................................................9 2.1 Core CPU ....................................................................................................................10 2.2 JTAG ...........................................................................................................................10 2.3 Internal Memory and Memory Management ..............................................................11 2.4 External Bus Interface .................................................................................................12 2.5 PMU/UIC/CPU DMA .................................................................................................12 2.6 Internal Peripherals .....................................................................................................13 2.6.1 Timer Counter Units (TCU) ...........................................................................13 2.6.2 Analog-to-Digital Converter (ADC)...............................................................14 2.6.3 Timers .............................................................................................................14 2.7 Power Control .............................................................................................................14 3. Libraries and Support Tools .................................................................................................15 4. Packaging, Pin Descriptions, and Physical Dimensions .......................................................16 4.1 PQFP Package .............................................................................................................17 4.1.1 PQFP Pinout ...................................................................................................17 4.1.2 PQFP Physical Dimensions ............................................................................24 4.2 BGA 15- by 15-mm Package ......................................................................................25 4.2.1 BGA 15- by 15-mm Pinout.............................................................................25 4.2.2 BGA 15- by 15-mm Physical Package Dimensions .......................................33 4.2.3 BGA 15- by 15-mm Signal Routing ...............................................................34 4.3 Power and Ground Signals ..........................................................................................36 5. Electrical Characteristics ......................................................................................................38 6. Thermal Characteristics ........................................................................................................41 7. Reset .....................................................................................................................................42 7.1 Overview .....................................................................................................................42 7.2 Signal Considerations and Reset Timing ....................................................................42 7.3 Clock Signals...............................................................................................................44 7.4 Typical Clock Source Implementations ......................................................................44 7.4.1 Normal or Driven Clock Source .....................................................................44 7.4.2 Using an External Crystal ...............................................................................44 7.5 Off-Chip Component Value ........................................................................................46 8. Signals...................................................................................................................................47 8.1 External Bus Operation ...............................................................................................47 8.1.1 Overview.........................................................................................................47 IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 3 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 9. 10. 11. 12. 13. 14. Data Sheet September 10, 2014 8.2 General Setup and Hold Timing..................................................................................47 8.3 External Bus Timing ...................................................................................................48 Setup and Hold Timing .........................................................................................................49 9.1.1 External Bus Timing for a 32-Bit Transfer (without RDY_N) ......................51 9.1.2 External Bus Timing for a 32-Bit Transfer (with RDY_N) ...........................52 9.1.3 External Bus Timing for 8-Bit/16-Bit Transfer (without RDY_N) ................54 9.1.4 External Bus Timing for 8-Bit/16-Bit Transfer (with RDY_N) .....................55 9.2 SDRAM Timing ..........................................................................................................56 9.2.1 SDRAM CAS Timing.....................................................................................56 9.2.2 SDRAM Row Activation Timing ...................................................................57 9.2.3 SDRAM Read Operation Timing ...................................................................59 9.2.4 SDRAM Read Burst Timing ..........................................................................59 9.2.5 SDRAM Write Operation, Write Burst, Write-to-Write, and Write-toPrecharge Timing............................................................................................60 JTAG.....................................................................................................................................64 10.1 JTAG Scan Chain Debug Functionality ......................................................................65 Ordering Information ............................................................................................................67 Errata.....................................................................................................................................68 12.1 Summary .....................................................................................................................68 12.2 Detail ...........................................................................................................................68 Revision History ...................................................................................................................72 For Additional Information...................................................................................................74 IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 4 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 LIST OF FIGURES Figure 1. Block Diagram for the fido1100......................................................................................8 Figure 2. PQFP Package Diagram ................................................................................................17 Figure 3. PQFP Physical Package Dimensions.............................................................................24 Figure 4. BGA 15- by 15-mm Package Diagram .........................................................................26 Figure 5. BGA 15- by 15-mm Physical Package Dimensions ......................................................33 Figure 6. BGA 15- by 15-mm Signal Routing..............................................................................35 Figure 7. Reset Timing .................................................................................................................43 Figure 8. Extended Reset Timing .................................................................................................43 Figure 9. Driven Clock Source .....................................................................................................45 Figure 10. Crystal Oscillator Third Overtone Off-Chip Components .........................................45 Figure 11. Crystal Oscillator Fundamental Overtone Off-Chip Components ..............................45 Figure 12. Propagation Delay .......................................................................................................49 Figure 13. Setup Time...................................................................................................................49 Figure 14. Hold Time ....................................................................................................................50 Figure 15. Recovery Time ............................................................................................................50 Figure 16. Removal Time .............................................................................................................50 Figure 17. Minimum Pulse Width ................................................................................................51 Figure 18. External Bus Timing for a Single, 32-Bit Cycle (without RDY_N) ...........................52 Figure 19. External Bus Timing for a 32-Bit Transfer (with RDY_N) ........................................53 Figure 20. External Bus Timing for 8-Bit/16-Bit Transfer (without RDY_N).............................54 Figure 21. External Bus Timing for 8-Bit/16-Bit Transfer (with RDY_N) ..................................55 Figure 22. SDRAM CAS Timing .................................................................................................57 Figure 23. Specific Row Activation Timing .................................................................................58 Figure 24. Meeting tRCD (min) When 2 < tRCD (min)/tCK 3 ................................................58 Figure 25. SDRAM Read Operation Timing ................................................................................59 Figure 26. SDRAM Read Burst Timing .......................................................................................60 Figure 27. SDRAM Write Operation Timing ...............................................................................61 Figure 28. SDRAM Write Burst Timing ......................................................................................62 Figure 29. SDRAM Write-to-Write Timing .................................................................................62 Figure 30. SDRAM Write-to-Precharge Timing ..........................................................................63 Figure 31. JTAG State Machine ...................................................................................................64 Figure 32. JTAG Port Register Interface ......................................................................................65 Figure 33. Timing of JTAG Signals .............................................................................................65 IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 5 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 LIST OF TABLES Table 1. Key Features .....................................................................................................................7 Table 2. Test Pin Descriptions ......................................................................................................11 Table 3. PQFP Pin Listing ............................................................................................................18 Table 4. BGA 15- by 15-mm Package Pin Listing .......................................................................27 Table 5. Analog Power and Ground Signals .................................................................................36 Table 6. Crystal Oscillator Power and Ground Signals ................................................................36 Table 7. 2.5 VDC Digital Core Power Signals .............................................................................36 Table 8. 3.3 VDC Digital IO Power Signals .................................................................................37 Table 9. Digital Ground Signals ...................................................................................................37 Table 10. Absolute Maximum Ratings .........................................................................................38 Table 11. ESD and Latch-Up Characteristics ...............................................................................38 Table 12. Recommended Operating Conditions ...........................................................................38 Table 13. DC Characteristics ........................................................................................................39 Table 14. Input Impedance ............................................................................................................39 Table 15. AC Characteristics of Crystal Oscillator .......................................................................39 Table 16. Analog-to-Digital Converter Characteristics ................................................................40 Table 17. Power Consumption ......................................................................................................40 Table 18. Thermal Resistance Characteristics ..............................................................................41 Table 19. Hardware Signals Involved When Asserting Reset ......................................................42 Table 20. Suggested Off-Chip Component Values .......................................................................46 Table 21. Debug Scan Chain Commands Supported by the JTAG TAP......................................66 Table 22. Part Numbers by Package Types ..................................................................................67 Table 23. Summary of Errata ........................................................................................................68 Table 24. Revision History ...........................................................................................................72 IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 6 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 1. Data Sheet September 10, 2014 Overview Innovasic Semiconductor's fido1100 is the first product in the fido family of real-time communication controllers. The fido communication controller architecture is uniquely optimized for solving memory bottlenecks, and is designed from the ground up for deterministic processing. Critical timing parameters, such as context switching and interrupt latency, are precisely predictable for real-time tasks. The fido1100 also incorporates the Universal I/O Controller (UIC) that is configurable to support various communication protocols across multiple platforms. This flexibility relieves the designer of the task of searching product matrices to find the set of peripherals that most closely match the system interface needs. The Software Profiling and Integrated Debug EnviRonment (SPIDER) has extensive real-time code debug capabilities without the burden of code instrumentation (see Table 1). Figure 1 illustrates the top-level blocks of the fido1100 architecture. Table 1. Key Features Features * Programmable UIC * * * Five Hardware Contexts Low-Jitter Execution * * * SPIDER Long-Life-Cycle Support * * * Benefits Provides the ability to customize peripherals to match user application. Single chip can solve multiple end-product demands. Reduces costs through optimized inventory management. Runs tight-control loops in separate contexts while RTOS manages high level tasks in another context. Provides context isolation with robust time-and-space partitioning. Performs tasks at much lower clock rates (66MHz versus >200MHz), reducing power budget and simplifying board design. Reduces system integration and debug time through in-system, "what-if" testing without code changes. Reduces firmware development time thus cutting costs. Up to 1Mbyte of trace buffer. Fulfills Innovasic's corporate policy of supporting products for the customer's entire life-cycle, eliminating product obsolescence concerns. IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 7 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet April 10, 2013 T0IN RREM and MPU T1IN T0IC[3:0] T1IC[3:0] Timer Counter Unit T0OC[3:0] DMA[1:0]_ACK INT[7:0] DMA[1:0]_REQ T1OC[3:0] SPIDERTM Debug A[30:0] D[15:0] CS[7:0]_N RW_N RDY_N HLDREQ_N HLDGNT_N BE[1:0]_N OE_N CPU DMA External Bus Interface Context Manager Priority Control Core CPU SRAM Timers Execution Unit JTAG Debug TDI TDO TCK TMS MEMCLK BA[1:0] CAS_N RAS_N SDRAM Controller Peripheral Management Unit and Frame Buffers CKE 10-Bit 8-Channel ADC UIC_0 UIC_1 UIC_2 UIC_3 UIC0[17:0] UIC1[17:0] UIC2[17:0] UIC3[17:0] AN[7:0] VRH VRL Figure 1. Block Diagram for the fido1100 IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 8 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 2. Data Sheet April 10, 2013 Features The fido1100 communication controller's features include: * 32-bit Core CPU * CISC architecture optimized for real time * CPU32+ (Motorola(R) 68000) instruction-set compatible * Five hardware contexts, each with its own register set and interrupt vector table * An 8- or 16-bit external bus interface with programmable chip selects * 24 Kbytes of high-speed internal user SRAM * 32 Kbytes of high-speed internal user-mappable Relocatable Rapid Execution Memory (RREM) * A Memory Protection Unit (MPU) * An SDRAM controller * Flat, contiguous memory space * Non-aligned memory access support * Dedicated Peripheral Management Unit (PMU) * Four Universal I/O Controllers (UICs) capable of supporting the following protocols: - GPIO - 10/100 Ethernet with flexible MAC Address Filtering schemes - EIA-232 - CAN - SPI - I2C Bus - SMBus - HDLC * Two channels of full-featured direct memory access (DMA) with deterministic arbitration * Two Timer/Counter Units (TCU) * A Watchdog timer, system timer, and context timers IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 9 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet April 10, 2013 * JTAG emulation and debug interface * Available in 208-pin PQFP and BGA 15- by 15-mm packages * 3.3V operation with 5V-tolerant I/O * Industrial temperature grade * Software development supported by libraries and tools including UIC firmware for various interface protocols and formats, as well as a customized GNU tool set. 2.1 Core CPU The fido1100 core is based on the CPU32 architecture, and is compatible with the CPU32 instruction set. The fido1100 incorporates five independent hardware contexts. While all contexts share the same Execution Unit, each of the five hardware contexts in the fido1100 has its own register set, execution priority and exception vector table. From an application's view, this unique feature of the fido1100 allows it to operate as five independent machines in one: 2.2 * 32-bit address and data paths on-chip * 66-MHz operation * Instruction execution from external memory or fast internal memory. * Each hardware context has its own copy of: - Eight 32-bit User Data Registers (D0-D7) - Seven 32-bit Address Registers (A0-A6) - Two 32-bit Stack Pointers (A7 and A7') - One 32-bit Program Counter - One 16-bit Status Register (SR) - One 32-bit Vector Base Register (VBR) JTAG The fido1100 is fully compliant with the IEEE 1149.1 Test Access Port and Boundary-Scan architecture (see Table 2). The fido1100 architecture is equipped with the TAP (Test Access Port) interface, TAP controller, instruction register, instruction decoder, boundary-scan register, and by-pass register. IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 10 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet April 10, 2013 Table 2. Test Pin Descriptions Pin TDO Direction In TDI TMS In In TCK In Description Test Data Output--The tri-state test data output changing on the falling edge of the TCK input. This is actively driven only in the shift-DR and shift-IR controller states. Test Data Input--The test data input sampled on the rising edge of the TCK input. Test Mode Select Input--The test mode select input used to sequence the TAP controller state machine. If TMS is a 1 for 5 clock cycles, it sends the TAP controller into reset. If TMS is 0, the TAP controller goes to IDLE. Test Clock Input--All JTAG commands and serial data are synchronized by this signal. The JTAG Interface is used for controlling the SPIDER Debug Features of the fido1100. * Breakpoints--Eight hardware context-aware breakpoints that can be chained to set up if/then triggering conditions. - Hardware breakpoints are enabled in software or over JTAG * Watchpoints--Eight hardware watchpoints. * Trace--Follow program execution with trace buffers. - Single address, single buffer, and circular buffer trace modes - Trace buffer can be written anywhere in the address space or to a peripheral * Debug Control--Hardware single-step and context status control. - Access to all memory and registers that are accessible to software - Byte, word, and long-word access in full-address mode or offset mode - Invalid address access (keystroke errors) over JTAG will not kill the session - Direct programming of FLASH on the evaluation board without target software support - Built-in hardware support to halt contexts and execute single instructions without software - JTAG access to registers, stack space, etc., even if the processor is halted * Statistical Profiling--SPIDER provides statistical software profiling to identify critical pieces of code. 2.3 Internal Memory and Memory Management * User SRAM--Internal 24-Kbyte memory that can be used by applications for general purpose data needs or as trace buffers. * Relocatable Rapid Execution Memory (RREM)--Internal 32-Kbyte memory that can be used as an instruction source for code that requires maximum execution speed. IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 11 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller * 2.4 Data Sheet April 10, 2013 Memory Protection Unit (MPU)--Access-control method for 16 user-configurable blocks of internal or external memory on a context basis. A block of memory may be inaccessible, read only or read/write accessible to a selectable set of contexts. The MPU provides the space partitioning needed in deterministic, real-time systems. External Bus Interface The interface to all external memory. It handles memory interface timing and arbitration of external bus requests. The external bus interfaces provide all address, data, and control line to implement either an 8- or 16-bit microcontroller system bus. * Address/data bus - 31-bit address bus to access up to 2 Gbytes of memory space - 8- or 16-bit data bus - Zero-overhead Endian conversion * Chip Selects--Eight programmable chip selects with programmable size, data width, and timing. * SDRAM Controller--Supports 8- or 16-bit data interfaces to SDRAM and provides the necessary control signals to interface to external SDRAM. The interface to the external SDRAM uses the 16-bit-wide data bus and 13 bits of the address bus of the External Bus Interface. The dedicated clock signal for this interface (MEMCLK) operates at the same frequency as the internal master clock. - Operates at a maximum clock rate of 66 MHz - Executes read, write, pre-charge, auto refresh, power down, and initialize SDRAM modes - Fixed, 4-word bursts to/from SDRAM interface - Periodically issues auto refresh command to prevent SDRAM data loss * External Bus Arbitration--The fido1100 provides signals to allow it to operate in a multibus master environment. 2.5 PMU/UIC/CPU DMA The PMU, UIC, and CPU DMA work together as a fast data transport scheme that requires minimal Core CPU overhead or intervention. * Peripheral Management Unit (PMU)--A set of user-configurable buffers for data transmission and reception via the UICs. * Universal Input/Output Controller (UIC)--Programmable protocol engine. IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 12 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet April 10, 2013 The UIC is a very flexible hardware solution designed to support numerous interface requirements. When working in concert with the on-board Peripheral Management Unit (PMU) and on-board data buffers, the operation of the interfaces requires little core processor intervention. This allows the processor to use its bus bandwidth for more important functions than managing data traffic. The UIC design can support complex protocols such as Ethernet or GPIO functions. * Four software-configurable UICs * Each supports 10/100 Ethernet, CAN, UART, SPI, I2C, HDLC, or GPIO functionality * Software libraries are provided for various interface protocols and formats * User-programmable integrated 256-location MAC address filter * Dedicated PMU offloads main CPU bus traffic * Large 1K x 32 transmit buffer and 2K x 32 receive buffers * At a minimum, each UIC can support 1 Ethernet port (MII), 2 UARTs, or 18 GPIO * CPU DMA--Two independent channels of DMA for data transfer 2.6 Internal Peripherals The fido1100 incorporates the following set of internal peripherals: 2.6.1 * Timer Counter Units (TCU) Two Timer Counter Units (TCU)--The fido1100 is equipped with two Timer Counter Units. - Four channels per timer; any channel can be either input capture or output compare. - Input captures can be either rising or falling edge. - External signal clocking can be rising edge, falling edge, or both edges of input signal. - Output compare can be assert high, assert low, or toggle mode. - Underflow, overflow, input-capture, or output-compare conditions can trigger an interrupt. - Timers can be programmed for auto-stop or auto-reload. - Timer can generate an internal interrupt to wake up the processor from sleep mode. - Timer periods in excess of 50 seconds are achievable. IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 13 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 2.6.2 Analog-to-Digital Converter (ADC) - - - - - - - 2.6.3 2.7 Data Sheet April 10, 2013 8-channel, 10-bit ADC Maximum throughput rate of 200 Kbps High- and low-reference voltage pins ensure accuracy and temperature compensation Very low 5-mW power consumption and includes a built-in power-down mode Single- or multiple-channel conversion scan modes Interrupt generated at the end of conversion is assigned a priority and a context Interrupts from the analog-to-digital converter can be disabled Timers * System Timer. - Provides five periodic System Timer interrupts. o 16-bit counter with 16-bit prescale allows a range of System Timer interrupts from 80 nS to 50 seconds with a 66-MHz system clock. o These interrupts can be assigned to the fast-context switching hardware providing a zero overhead system executive or the System Timer interrupts can simply produce a traditional vectored interrupt request to provide a system with basic timing needs. * Watchdog Timer - 16-bit counter with an 11-bit prescaler * Context Timers - Each hardware context has a set of timing registers that can track, specify, and limit execution time. Power Control All internal peripherals can be put into a low-power consumption mode. IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 14 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 3. Data Sheet April 10, 2013 Libraries and Support Tools * Full library support * UIC libraries * Embedded communication stacks * TCP/IP * GPIO sample programs * Customized GNU tool set * Eclipse IDE * Sourcery G++ from Code Sourcery IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 15 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 4. Data Sheet April 10, 2013 Packaging, Pin Descriptions, and Physical Dimensions Information on the packages and pin descriptions for the fido1100 communication controller PQFP and BGA 15- by 15-mm package is provided individually. Refer to sections, figures, and tables for information on the device of interest. IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 16 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 4.1 PQFP Package 4.1.1 PQFP Pinout Data Sheet April 10, 2013 RESET_N RESET_OUT_N The pinout for the fido1100 communication controller PQFP package is as shown in Figure 2. The corresponding pinout is provided in Table 3. Figure 2. PQFP Package Diagram IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 17 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet April 10, 2013 Table 3. PQFP Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0 VRL VRH VDDA GNDA INT0 INT1 INT2 VDDC INT3 INT4_DMA0_ ACK INT5_DMA1_ ACK INT6_DMA0_ REQ INT7_DMA1_ REQ VDDIO D0 D1 D2 D3 D4 D5 D6 D7 GND D8 D9 D10 D11 Type Input Input Input Input Input Input Input Input Input Input Power Ground Input Input Input Power Input Bidirectional Description Analog-to-digital converter input channel 7 Analog-to-digital converter input channel 6 Analog-to-digital converter input channel 5 Analog-to-digital converter input channel 4 Analog-to-digital converter input channel 3 Analog-to-digital converter input channel 2 Analog-to-digital converter input channel 1 Analog-to-digital converter input channel 0 Analog-to-digital converter low-input reference Analog-to-digital converter high-input reference Analog supply voltage (+3.3VDC) Analog ground Interrupt_0 Interrupt_1 Interrupt_2 Digital core supply voltage (+2.5VDC) Interrupt_3 Muxed pin, Interrupt_4 or DMA channel 0 acknowledge Bidirectional Muxed pin, Interrupt_5 or DMA channel 1 acknowledge Input Muxed pin, Interrupt_6 or DMA channel 0 request Input Muxed pin, Interrupt_7 or DMA channel 1 request Power Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Digital I/O supply voltage (+3.3VDC) External Bus Interface data Bit [0] External Bus Interface data Bit [1] External Bus Interface data Bit [2] External Bus Interface data Bit [3] External Bus Interface data Bit [4] External Bus Interface data Bit [5] External Bus Interface data Bit [6] External Bus Interface data Bit [7] Digital ground External Bus Interface data Bit [8] External Bus Interface data Bit [9] External Bus Interface data Bit [10] External Bus Interface data Bit [11] IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 18 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet April 10, 2013 Table 3. PQFP Pin Listing (Continued) Pin 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Signal Name D12 VDDIO D13 D14 D15 RDY_N GND MEMCLK GND BE0_N BE1_N OE_N VDDC RW_N BA_0 BA_1 CAS_N GND RAS_N CKE HOLDREQ_N HOLDGNT_N RESET_N RESET_OUT_N GND A0 A1 A2 A3 VDDIO A4 A5 A6 A7 GND A8 A9 A10 A11 Type Bidirectional Power Bidirectional Bidirectional Bidirectional Input Ground Output Ground Output Output Output Power Output Output Output Output Ground Output Output Input Output Input Output Ground Output Output Output Output Power Output Output Output Output Ground Output Output Output Output Description External Bus Interface data Bit [12] Digital I/O supply voltage (+3.3VDC) External Bus Interface data Bit [13] External Bus Interface data Bit [14] External Bus Interface data Bit [15] External Bus Interface External Ready Indication Digital ground Memory clock used by external memory Digital ground Byte enable 0, active low Byte enable 1, active low Output enable, active low Digital core supply voltage (+2.5VDC) Read or write control (active low write) Bank Enable 0 Bank Enable 1 Column activate signal, active low Digital Ground Row activate signal, active low Clock enable to be used in conjunction with MEMCLK External Bus hold request, active low External Bus grant request, active low Reset input Reset output Digital ground External Bus Interface address Bit [0] External Bus Interface address Bit [1] External Bus Interface address Bit [2] External Bus Interface address Bit [3] Digital I/O supply voltage (+3.3VDC) External Bus Interface address Bit [4] External Bus Interface address Bit [5] External Bus Interface address Bit [6] External Bus Interface address Bit [7] Digital ground External Bus Interface address Bit [8] External Bus Interface address Bit [9] External Bus Interface address Bit [10] External Bus Interface address Bit [11] IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 19 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet April 10, 2013 Table 3. PQFP Pin Listing (Continued) Pin 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Signal Name VDDC A12 A13 A14 A15 VDDC A16 A17 A18 A19 VDDIO A20 A21 A22 A23 GND A24 A25_RESET_ DELAY A26_SIZE 94 A27_CS7_N 95 A28_CS6_N 96 A29_CS5_N 97 A30_CS4_N 98 99 100 101 102 103 104 105 106 107 108 CS0_N CS1_N CS2_N CS3_N TDI TDO TCK TMS VDDC UIC0_0 UIC0_1 Type Power Output Output Output Output Power Output Output Output Output Power Output Output Output Output Ground Output Internal Pull-up Internal Pull-up Output Description Digital core supply voltage (+2.5VDC) External Bus Interface address Bit [12] External Bus Interface address Bit [13] External Bus Interface address Bit [14] External Bus Interface address Bit [15] Digital core supply voltage (+2.5VDC) External Bus Interface address Bit [16] External Bus Interface address Bit [17] External Bus Interface address Bit [18] External Bus Interface address Bit [19] Digital I/O supply voltage (+3.3VDC) External Bus Interface address Bit [20] External Bus Interface address Bit [21] External Bus Interface address Bit [22] External Bus Interface address Bit [23] Digital ground External Bus Interface address Bit [24] Muxed pin, External Bus Interface address Bit [25] or POR counter bypass Muxed pin, External Bus Interface address Bit [26] or data bus size select (0 = 8-Bit, 1= 16=Bit) Muxed pin, External Bus Interface address Bit [27] or Chip select 7 (chip select active low) Output Muxed pin, External Bus Interface address Bit [28] or Chip select 6 (chip select active low) Output Muxed pin, External Bus Interface address Bit [29] or Chip select 5 (chip select active low) Output Muxed pin, External Bus Interface address Bit [30] or Chip select 4 (chip select active low) Output Chip select 0 (chip select active low) Output Chip select 1 (chip select active low) Output Chip select 2 (chip select active low) Output Chip select 3 (chip select active low) Input JTAG data input Output JTAG data output Input JTAG clock input Input JTAG control signal Power Digital core supply voltage (+2.5VDC) Bidirectional Universal I/O Controller 0, pin 0 Bidirectional Universal I/O Controller 0, pin 1 IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 20 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet April 10, 2013 Table 3. PQFP Pin Listing (Continued) Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 Signal Name UIC0_2 UIC0_3 GND UIC0_4 UIC0_5 UIC0_6 UIC0_7 UIC0_8 VDDCLK XTAL0 XTAL1 GNDCLK UIC0_9 UIC0_10 UIC0_11 UIC0_12 UIC0_13 UIC0_14 UIC0_15 UIC0_16 UIC0_17 GND UIC1_0 UIC1_1 UIC1_2 UIC1_3 VDDIO UIC1_4 UIC1_5 UIC1_6 UIC1_7 UIC1_8 UIC1_9 VDDC UIC1_10 UIC1_11 UIC1_12 UIC1_13 UIC1_14 Type Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Power supply Clock Clock Ground Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Description Universal I/O Controller 0, pin 2 Universal I/O Controller 0, pin 3 Digital ground Universal I/O Controller 0, pin 4 Universal I/O Controller 0, pin 5 Universal I/O Controller 0, pin 6 Universal I/O Controller 0, pin 7 Universal I/O Controller 0, pin 8 Power Supply for the Crystal Oscillator (+2.5VDC) Crystal input pin 0 (Osc. In) Crystal input/output pin 1 (Osc. Out) Digital ground Universal I/O Controller 0, pin 9 Universal I/O Controller 0, pin 10 Universal I/O Controller 0, pin 11 Universal I/O Controller 0, pin 12 Universal I/O Controller 0, pin 13 Universal I/O Controller 0, pin 14 Universal I/O Controller 0, pin 15 Universal I/O Controller 0, pin 16 Universal I/O Controller 0, pin 17 Digital ground Universal I/O Controller 1, pin 0 Universal I/O Controller 1, pin 1 Universal I/O Controller 1, pin 2 Universal I/O Controller 1, pin 3 Digital I/O supply voltage (+3.3VDC) Universal I/O Controller 1, pin 4 Universal I/O Controller 1, pin 5 Universal I/O Controller 1, pin 6 Universal I/O Controller 1, pin 7 Universal I/O Controller 1, pin 8 Universal I/O Controller 1, pin 9 Digital core supply voltage (+2.5VDC) Universal I/O Controller 1, pin 10 Universal I/O Controller 1, pin 11 Universal I/O Controller 1, pin 12 Universal I/O Controller 1, pin 13 Universal I/O Controller 1, pin 14 IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 21 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet April 10, 2013 Table 3. PQFP Pin Listing (Continued) Pin 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 Signal Name GND UIC1_15 UIC1_16 UIC1_17 VDDIO UIC2_0 UIC2_1 UIC2_2 UIC2_3 VDDC UIC2_4 UIC2_5 UIC2_6 UIC2_7 GND UIC2_8 UIC2_9 UIC2_10 UIC2_11 VDDIO UIC2_12 UIC2_13 UIC2_14 UIC2_15 GND UIC2_16 UIC2_17 UIC3_0 UIC3_1 VDDC UIC3_2 UIC3_3 UIC3_4 UIC3_5 GND UIC3_6 UIC3_7 UIC3_8 UIC3_9 Type Ground Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Description Digital ground Universal I/O Controller 1, pin 15 Universal I/O Controller 1, pin 16 Universal I/O Controller 1, pin 17 Digital I/O supply voltage (+3.3VDC) Universal I/O Controller 2, pin 0 Universal I/O Controller 2, pin 1 Universal I/O Controller 2, pin 2 Universal I/O Controller 2, pin 3 Digital core supply voltage (+2.5VDC) Universal I/O Controller 2, pin 4 Universal I/O Controller 2, pin 5 Universal I/O Controller 2, pin 6 Universal I/O Controller 2, pin 7 Digital ground Universal I/O Controller 2, pin 8 Universal I/O Controller 2, pin 9 Universal I/O Controller 2, pin 10 Universal I/O Controller 2, pin 11 Digital I/O supply voltage (+3.3VDC) Universal I/O Controller 2, pin 12 Universal I/O Controller 2, pin 13 Universal I/O Controller 2, pin 14 Universal I/O Controller 2, pin 15 Digital ground Universal I/O Controller 2, pin 16 Universal I/O Controller 2, pin 17 Universal I/O Controller 3 pin 0 Universal I/O Controller 3 pin 1 Digital core supply voltage (+2.5VDC) Universal I/O Controller 3 pin 2 Universal I/O Controller 3 pin 3 Universal I/O Controller 3 pin 4 Universal I/O Controller 3 pin 5 Digital ground Universal I/O Controller 3 pin 6 Universal I/O Controller 3 pin 7 Universal I/O Controller 3 pin 8 Universal I/O Controller 3 pin 9 IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 22 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet April 10, 2013 Table 3. PQFP Pin Listing (Continued) Pin 187 188 189 190 191 192 193 194 195 196 197 Signal Name VDDIO UIC3_10 UIC3_11 UIC3_12 UIC3_13 GND UIC3_14 UIC3_15 UIC3_16 UIC3_17 T0IC0_T0OC0 Type Power Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 198 T0IC1_T0OC1 Bidirectional 199 T0IC2_T0OC2 Bidirectional 200 T0IC3_T0OC3 Bidirectional 201 202 GND T1IC0_T1OC0 Ground Bidirectional 203 T1IC1_T1OC1 Bidirectional 204 T1IC2_T1OC2 Bidirectional 205 T1IC3_T1OC3 Bidirectional 206 207 208 VDDC T0IN T1IN Power Input Input Description Digital I/O supply voltage (+3.3VDC) Universal I/O Controller 3 pin 10 Universal I/O Controller 3 pin 11 Universal I/O Controller 3 pin 12 Universal I/O Controller 3 pin 13 Digital Ground Universal I/O Controller 3 pin 14 Universal I/O Controller 3 pin 15 Universal I/O Controller 3 pin 16 Universal I/O Controller 3 pin 17 Muxed pin, Timer Counter Unit 0 input capture 0 or output compare 0 Muxed pin, Timer Counter Unit 0 input capture 1 or output compare 1 Muxed pin, Timer Counter Unit 0 input capture 2 or output compare 2 Muxed pin, Timer Counter Unit 0 input capture 3 or output compare 3 Digital ground Muxed pin, Timer Counter Unit 1 input capture 0 or output compare 0 Muxed pin, Timer Counter Unit 1 input capture 1 or output compare 1 Muxed pin, Timer Counter Unit 1 input capture 2 or output compare 2 Muxed pin, Timer Counter Unit 1 input capture 3 or output compare 3 Digital core supply voltage (+2.5VDC) Timer Counter Unit 0 external clock source Timer Counter Unit 1 external clock source IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 23 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 4.1.2 Data Sheet April 10, 2013 PQFP Physical Dimensions The physical dimensions for the 208-pin PQFP package are as shown in Figure 3. Legend: Symbol A A1 A2 b c D E e HD HE L L1 y Dimension in mm Min Nom Max - - 4.07 0.25 - - 3.15 3.23 3.30 0.18 - 0.28 0.13 - 0.23 27.90 28.00 28.10 27.90 28.00 28.10 0.50 BSC 30.35 30.60 30.85 30.35 30.60 30.85 0.35 0.50 0.65 1.30 REF - - 0.19 0 - 7 Dimension in Inches Min Nom Max - - 0.160 0.010 - - 0.124 0.127 0.130 0.007 - 0.011 0.005 - 0.009 1.098 1.102 1.106 1.098 1.102 1.106 0.020 BSC 1.195 1.205 1.215 1.195 1.205 1.215 0.014 0.020 0.026 0.051 REF - - 0.004 0 - 7 Notes: 1. Dimension D & E do not include interlead flash. 2. Dimension B does not include damper protrusion/intrusion. 3. Controlling dimension: mm 4. General appearance spec. should be based on visual inspection spec. Figure 3. PQFP Physical Package Dimensions IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 24 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 4.2 BGA 15- by 15-mm Package 4.2.1 BGA 15- by 15-mm Pinout Data Sheet April 10, 2013 The pinout for the fido1100 communication controller BGA 15- by 15-mm package is as shown in Figure 4. The corresponding pinout is provided in Table 4. IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 25 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 1 T1IC1_ A T1OC1 2 T0IC2_ T0OC2 T1IC2_ T1OC2 3 4 T0IC0_ UIC3_15 T0OC0 T1IC0_ T0IC1_ T1OC0 T0OC1 T1IC3_ T0IN T1OC3 5 UIC3_13 6 7 12 13 14 UIC3_7 UIC3_4 UIC3_1 UIC3_0 UIC2_15 UIC2_13 UIC2_10 UIC2_7 UIC2_6 UIC1_17 UIC3_11 UIC3_8 UIC3_5 UIC3_2 UIC2_17 UIC2_14 UIC2_11 UIC2_8 UIC2_5 UIC2_0 UIC1_14 B UIC3_17 UIC3_14 UIC3_10 UIC3_6 UIC3_3 UIC2_16 UIC2_12 UIC2_9 UIC2_4 UIC2_1 UIC1_16 UIC1_12 C VDDIO GND GND UIC2_2 UIC1_13 UIC1_9 D UIC3_12 UIC3_9 9 10 11 15 16 17 A AN_2 C AN_0 AN_5 D VDDA AN_1 AN_6 GND E GNDA VRH AN_3 GND GND UIC1_15 UIC1_10 UIC1_6 E F INT2 INT0 VRL AN_7 UIC2_3 UIC1_11 UIC1_8 UIC1_5 F INT3 INT1 AN_4 VDDIO UIC1_7 UIC1_4 UIC1_2 G INT5_ DMA1_ VDDC ACK VDDIO UIC1_3 UIC1_1 UIC1_0 H INT6_ DMA0_ REQ T0IC3_ T0OC3 GND GND 8 B INT4_ G DMA0_ ACK INT7_ H DMA1_ REQ UIC3_16 Data Sheet April 10, 2013 T1IN VDDC VDDC VDDC VDDIO VDDIO J D0 D1 D2 VDDIO VDDIO UIC0_17 UIC0_16 UIC0_15 J K D3 D4 D6 VDDIO VDDC UIC0_14 UIC0_13 UIC0_12 K L D5 D7 D11 OE_N VDDC UIC0_10 UIC0_9 UIC0_11 L M D8 D10 D15 CAS_N GNDCLK VDDCLK UIC0_8 XTAL1 M N D9 D13 BE1_N GND GND UIC0_5 UIC0_7 XTAL0 N P D12 RDY_N BA_1 GND GND UIC0_0 UIC0_4 UIC0_6 P R D14 BE0_N BA_0 RAS_N HOLDGNT_N A3 A6 A10 A15 A18 A22 T GND RW_N CKE RESET_ OUT_N A2 A5 A8 A11 A14 A17 A20 A24 A0 A1 A4 A7 A9 A12 A13 A16 A19 A23 3 4 5 6 7 8 9 10 11 12 U MEMCLK HOLDREQ_N 1 2 GND GND RESET_N VDDIO VDDC VDDC A21 A26_SIZE GND A27_CS7_N A29_CS5_N A28_CS6_N CS3_N CS2_N CS0_N CS1_N TCK TDI TDO TMS 15 16 17 A25_RESET_ A30_CS4_N DELAY 13 14 UIC0_2 UIC0_3 R UIC0_1 T U = Signals. = Indicates power. = Indicates ground. Figure 4. BGA 15- by 15-mm Package Diagram IA211080807-10 UNCONTROLLED WHEN PRINTED OR COPIED Page 26 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Table 4. BGA 15- by 15-mm Package Pin Listing Pin F4 D3 C2 G4 E3 B1 D2 C1 F3 E2 D1 E1 F2 G3 F1 D7 G2 G1 H3 H2 H1 D10 J1 J2 J3 K1 K2 L1 K3 L2 D4 M1 N1 M2 L3 Signal Name AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 AN_0 VRL VRH VDDA GNDA INT0 INT1 INT2 VDDC INT3 INT4_DMA0_ ACK INT5_DMA1_ ACK INT6_DMA0_ REQ INT7_DMA1_ REQ VDDIO D0 D1 D2 D3 D4 D5 D6 D7 GND D8 D9 D10 D11 Type Input Input Input Input Input Input Input Input Input Input Power Ground Input Input Input Power Input Bidirectional Description Analog-to-digital converter input channel 7 Analog-to-digital converter input channel 6 Analog-to-digital converter input channel 5 Analog-to-digital converter input channel 4 Analog-to-digital converter input channel 3 Analog-to-digital converter input channel 2 Analog-to-digital converter input channel 1 Analog-to-digital converter input channel 0 Analog-to-digital converter low-input reference Analog-to-digital converter high-input reference Analog supply voltage (+3.3VDC) Analog ground Interrupt_0 Interrupt_1 Interrupt_2 Digital core supply voltage (+2.5VDC) Interrupt_3 Muxed pin, Interrupt_4 or DMA channel 0 acknowledge Bidirectional Muxed pin, Interrupt_5 or DMA channel 1 acknowledge Input Muxed pin, Interrupt_6 or DMA channel 0 request Input Muxed pin, Interrupt_7 or DMA channel 1 request Power Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Digital I/O supply voltage (+3.3VDC) External Bus Interface data Bit [0] External Bus Interface data Bit [1] External Bus Interface data Bit [2] External Bus Interface data Bit [3] External Bus Interface data Bit [4] External Bus Interface data Bit [5] External Bus Interface data Bit [6] External Bus Interface data Bit [7] Digital ground External Bus Interface data Bit [8] External Bus Interface data Bit [9] External Bus Interface data Bit [10] External Bus Interface data Bit [11] IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 27 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Table 4. BGA 15- by 15-mm Package Pin Listing (Continued) Pin P1 D11 N2 R1 M3 P2 T1 U1 D5 R2 N3 L4 D8 T2 R3 P3 M4 P6 R4 T3 U2 R5 P7 T4 D13 U3 U4 T5 R6 D12 U5 T6 R7 U6 D14 T7 U7 R8 Signal Name D12 VDDIO D13 D14 D15 RDY_N GND MEMCLK GND BE0_N BE1_N OE_N VDDC RW_N BA_0 BA_1 CAS_N GND RAS_N CKE HOLDREQ_N HOLDGNT_N RESET_N RESET_OUT_N GND A0 A1 A2 A3 VDDIO A4 A5 A6 A7 GND A8 A9 A10 Type Bidirectional Power Bidirectional Bidirectional Bidirectional Input Ground Output Ground Output Output Output Power Output Output Output Output Ground Output Output Input Output Input Output Ground Output Output Output Output Power Output Output Output Output Ground Output Output Output Description External Bus Interface data Bit [12] Digital I/O supply voltage (+3.3VDC) External Bus Interface data Bit [13] External Bus Interface data Bit [14] External Bus Interface data Bit [15] External Bus Interface External Ready Indication Digital ground Memory clock used by external memory Digital ground Byte enable 0, active low Byte enable 1, active low Output enable, active low Digital core supply voltage (+2.5VDC) Read or write control (active low write) Bank Enable 0 Bank Enable 1 Column activate signal, active low Digital Ground Row activate signal, active low Clock enable to be used in conjunction with MEMCLK External Bus hold request, active low External Bus grant request, active low Reset input Reset output Digital ground External Bus Interface address Bit [0] External Bus Interface address Bit [1] External Bus Interface address Bit [2] External Bus Interface address Bit [3] Digital I/O supply voltage (+3.3VDC) External Bus Interface address Bit [4] External Bus Interface address Bit [5] External Bus Interface address Bit [6] External Bus Interface address Bit [7] Digital ground External Bus Interface address Bit [8] External Bus Interface address Bit [9] External Bus Interface address Bit [10] IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 28 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Table 4. BGA 15- by 15-mm Package Pin Listing (Continued) Pin T8 D9 U8 U9 T9 R9 H4 U10 T10 R10 U11 G14 T11 P11 R11 U12 E4 T12 U13 P12 Signal Name A11 VDDC A12 A13 A14 A15 VDDC A16 A17 A18 A19 VDDIO A20 A21 A22 A23 GND A24 A_25_RESET_ DELAY A_26_SIZE R12 A27_CS7_N Type Output Power Output Output Output Output Power Output Output Output Output Power Output Output Output Output Ground Output Internal Pull-up Internal Pull-up Output T13 A28_CS6_N Output R13 A29_CS5_N Output U14 A30_CS4_N Output T14 T15 R15 R14 U15 U16 T16 U17 K14 CS0_N CS1_N CS2_N CS3_N TDI TDO TCK TMS VDDC Output Output Output Output Input Output Input Input Power Description External Bus Interface address Bit [11] Digital core supply voltage (+2.5VDC) External Bus Interface address Bit [12] External Bus Interface address Bit [13] External Bus Interface address Bit [14] External Bus Interface address Bit [15] Digital core supply voltage (+2.5VDC) External Bus Interface address Bit [16] External Bus Interface address Bit [17] External Bus Interface address Bit [18] External Bus Interface address Bit [19] Digital I/O supply voltage (+3.3VDC) External Bus Interface address Bit [20] External Bus Interface address Bit [21] External Bus Interface address Bit [22] External Bus Interface address Bit [23] Digital ground External Bus Interface address Bit [24] Muxed pin, External Bus Interface address Bit [25] or POR counter bypass Muxed pin, External Bus Interface address Bit [26] or data bus size select (0 = 8-Bit, 1= 16=Bit) Muxed pin, External Bus Interface address Bit [27] or Chip select 7 (chip select active low) Muxed pin, External Bus Interface address Bit [28] or Chip select 6 (chip select active low) Muxed pin, External Bus Interface address Bit [29] or Chip select 5 (chip select active low) Muxed pin, External Bus Interface address Bit [30] or Chip select 4 (chip select active low) Chip select 0 (chip select active low) Chip select 1 (chip select active low) Chip select 2 (chip select active low) Chip select 3 (chip select active low) JTAG data input JTAG data output JTAG clock input JTAG control signal Digital core supply voltage (+2.5VDC) IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 29 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Table 4. BGA 15- by 15-mm Package Pin Listing (Continued) Pin P15 T17 R16 R17 E14 P16 N15 P17 N16 M16 M15 N17 M17 M14 L16 L15 L17 K17 K16 K15 J17 J16 J15 N4 H17 H16 G17 H15 J4 G16 F17 E17 G15 F16 D17 L14 E16 F15 Signal Name UIC0_0 UIC0_1 UIC0_2 UIC0_3 GND UIC0_4 UIC0_5 UIC0_6 UIC0_7 UIC0_8 VDDCLK XTAL0 XTAL1 GNDCLK UIC0_9 UIC0_10 UIC0_11 UIC0_12 UIC0_13 UIC0_14 UIC0_15 UIC0_16 UIC0_17 GND UIC1_0 UIC1_1 UIC1_2 UIC1_3 VDDIO UIC1_4 UIC1_5 UIC1_6 UIC1_7 UIC1_8 UIC1_9 VDDC UIC1_10 UIC1_11 Type Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Power supply Clock Clock Ground Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Description Universal I/O Controller 0, pin 0 Universal I/O Controller 0, pin 1 Universal I/O Controller 0, pin 2 Universal I/O Controller 0, pin 3 Digital ground Universal I/O Controller 0, pin 4 Universal I/O Controller 0, pin 5 Universal I/O Controller 0, pin 6 Universal I/O Controller 0, pin 7 Universal I/O Controller 0, pin 8 Power Supply for the Crystal Oscillator (+2.5VDC) Crystal input pin 0 (Osc. In) Crystal input/output pin 1 (Osc. Out) Digital ground Universal I/O Controller 0, pin 9 Universal I/O Controller 0, pin 10 Universal I/O Controller 0, pin 11 Universal I/O Controller 0, pin 12 Universal I/O Controller 0, pin 13 Universal I/O Controller 0, pin 14 Universal I/O Controller 0, pin 15 Universal I/O Controller 0, pin 16 Universal I/O Controller 0, pin 17 Digital ground Universal I/O Controller 1, pin 0 Universal I/O Controller 1, pin 1 Universal I/O Controller 1, pin 2 Universal I/O Controller 1, pin 3 Digital I/O supply voltage (+3.3VDC) Universal I/O Controller 1, pin 4 Universal I/O Controller 1, pin 5 Universal I/O Controller 1, pin 6 Universal I/O Controller 1, pin 7 Universal I/O Controller 1, pin 8 Universal I/O Controller 1, pin 9 Digital core supply voltage (+2.5VDC) Universal I/O Controller 1, pin 10 Universal I/O Controller 1, pin 11 IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 30 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Table 4. BGA 15- by 15-mm Package Pin Listing (Continued) Pin C17 D16 B17 N14 E15 C16 A17 J14 B16 C15 D15 F14 P9 C14 B15 A16 A15 P4 B14 C13 A14 B13 K4 C12 A13 B12 A12 P5 C11 B11 A11 A10 P10 B10 C10 A9 B9 Signal Name UIC1_12 UIC1_13 UIC1_14 GND UIC1_15 UIC1_16 UIC1_17 VDDIO UIC2_0 UIC2_1 UIC2_2 UIC2_3 VDDC UIC2_4 UIC2_5 UIC2_6 UIC2_7 GND UIC2_8 UIC2_9 UIC2_10 UIC2_11 VDDIO UIC2_12 UIC2_13 UIC2_14 UIC2_15 GND UIC2_16 UIC2_17 UIC3_0 UIC3_1 VDDC UIC3_2 UIC3_3 UIC3_4 UIC3_5 Type Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Description Universal I/O Controller 1, pin 12 Universal I/O Controller 1, pin 13 Universal I/O Controller 1, pin 14 Digital ground Universal I/O Controller 1, pin 15 Universal I/O Controller 1, pin 16 Universal I/O Controller 1, pin 17 Digital I/O supply voltage (+3.3VDC) Universal I/O Controller 2, pin 0 Universal I/O Controller 2, pin 1 Universal I/O Controller 2, pin 2 Universal I/O Controller 2, pin 3 Digital core supply voltage (+2.5VDC) Universal I/O Controller 2, pin 4 Universal I/O Controller 2, pin 5 Universal I/O Controller 2, pin 6 Universal I/O Controller 2, pin 7 Digital ground Universal I/O Controller 2, pin 8 Universal I/O Controller 2, pin 9 Universal I/O Controller 2, pin 10 Universal I/O Controller 2, pin 11 Digital I/O supply voltage (+3.3VDC) Universal I/O Controller 2, pin 12 Universal I/O Controller 2, pin 13 Universal I/O Controller 2, pin 14 Universal I/O Controller 2, pin 15 Digital ground Universal I/O Controller 2, pin 16 Universal I/O Controller 2, pin 17 Universal I/O Controller 3 pin 0 Universal I/O Controller 3 pin 1 Digital core supply voltage (+2.5VDC) Universal I/O Controller 3 pin 2 Universal I/O Controller 3 pin 3 Universal I/O Controller 3 pin 4 Universal I/O Controller 3 pin 5 IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 31 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Table 4. BGA 15- by 15-mm Package Pin Listing (Continued) Pin C9 A8 B8 A7 P8 C8 B7 A6 A5 B6 C7 A4 B5 C6 A3 Signal Name UIC3_6 UIC3_7 UIC3_8 UIC3_9 VDDIO UIC3_10 UIC3_11 UIC3_12 UIC3_13 GND UIC3_14 UIC3_15 UIC3_16 UIC3_17 T0IC0_T0OC0 Type Bidirectional Bidirectional Bidirectional Bidirectional Power Bidirectional Bidirectional Bidirectional Bidirectional Ground Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional B4 T0IC1_T0OC1 Bidirectional A2 T0IC2_T0OC2 Bidirectional C5 T0IC3_T0OC3 Bidirectional P13 B3 GND T1IC0_T1OC0 Ground Bidirectional A1 T1IC1_T1OC1 Bidirectional B2 T1IC2_T1OC2 Bidirectional C4 T1IC3_T1OC3 Bidirectional C3 D6 P14 H14 T0IN T1IN GND VDDIO Input Input Ground Power Description Universal I/O Controller 3 pin 6 Universal I/O Controller 3 pin 7 Universal I/O Controller 3 pin 8 Universal I/O Controller 3 pin 9 Digital I/O supply voltage (+3.3VDC) Universal I/O Controller 3 pin 10 Universal I/O Controller 3 pin 11 Universal I/O Controller 3 pin 12 Universal I/O Controller 3 pin 13 Digital Ground Universal I/O Controller 3 pin 14 Universal I/O Controller 3 pin 15 Universal I/O Controller 3 pin 16 Universal I/O Controller 3 pin 17 Muxed pin, Timer Counter Unit 0 input capture 0 or output compare 0 Muxed pin, Timer Counter Unit 0 input capture 1 or output compare 1 Muxed pin, Timer Counter Unit 0 input capture 2 or output compare 2 Muxed pin, Timer Counter Unit 0 input capture 3 or output compare 3 Digital ground Muxed pin, Timer Counter Unit 1 input capture 0 or output compare 0 Muxed pin, Timer Counter Unit 1 input capture 1 or output compare 1 Muxed pin, Timer Counter Unit 1 input capture 2 or output compare 2 Muxed pin, Timer Counter Unit 1 input capture 3 or output compare 3 Timer Counter Unit 0 external clock source Timer Counter Unit 1 external clock source Digital Ground Digital I/O supply voltage (+3.3VDC) IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 32 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 4.2.2 Data Sheet September 10, 2014 BGA 15- by 15-mm Physical Package Dimensions The physical dimensions for the BGA 15- by 15-mm package are as shown in Figure 5. Notes: 1. Controlling dimension: Millimeter. 2. Primary datum C and seating plane are defined by the spherical crowns of the solder balls. 3. Dimension b is measured at the maximum solder-ball diameter, parallel to primary datum C. 4. There will be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge. 5. Special Characteristics C Class: bbb ddd. 6. The pattern of Pin 1 fiducial is for reference only. Legend: Dimension in mm Symbol A A1 A2 c D E D1 E1 e b aaa bbb ddd eee fff MD/ME MIN - 0.16 0.84 0.32 14.90 14.90 - - - 0.25 NOM - 0.21 0.89 0.36 15.00 15.00 12.80 12.80 0.80 0.30 0.10 0.10 0.12 0.15 0.08 17/17 MAX 1.20 0.26 0.94 0.40 15.10 15.10 - - - 0.35 Dimension in Inches MIN - 0.006 0.033 0.013 0.587 0.587 - - - 0.010 NOM - 0.008 0.035 0.014 0.591 0.591 0.504 0.504 0.031 0.012 0.004 0.004 0.005 0.006 0.003 17/17 MAX 0.047 0.010 0.037 0.016 0.594 0.594 - - - 0.014 Figure 5. BGA 15- by 15-mm Physical Package Dimensions IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 33 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 4.2.3 Data Sheet September 10, 2014 BGA 15- by 15-mm Signal Routing The 15- by15-mm BGA can be easily routed using economical and readily available PCB fabrication design rules. In order to route all signals from the fido1100 BGA, 2 layers in addition to power and ground are required, using 0.1mm trace/space technology. Since 0.1mm = 3.937mil, most PCB fabricators will consider this 4mil trace/space. The PCB land pattern for the BGA should use 0.3mm round pads. Since the BGA pitch is 0.8mm, this leaves 0.5mm of space between pads. Using 0.1mm trace/space, 2 signals may be routed between each pair of pads (2 traces + 3spaces = 0.5mm). Figure 8 shows how this is accomplished. Referring to Figure 6, signal layer 1 is shown in black, signal layer 2 is shown in red, and the vias are shown in blue. Signal layer 1 is the top side with the BGA pads, while signal layer 2 may be any other layer, but is typically the bottom side. All vias with no trace routed out from the BGA are power or ground. Note that the innermost row of pads is all power and ground, except for 9 pads which are signals. Three of these signals are easily routed on signal layer 1, but 6 of them require the use of vias and signal layer 2. If all of the signals are not required for a given design, it may be possible to route all of the used signals on signal layer 1. It may be beneficial to place more vias and to route more signals on layers other than signal layer 1. This could produce a better PCB layout, but care should be exercised to not include an excessive number of vias. The use of too many vias can lead to inadequate copper on the power/ground plane layers surrounding the center area of the BGA, resulting in relative isolation of the BGA power/ground via connections. Note the open space between pads M17 and N17 (A1 is upper left corner). These signals are XTAL1 and XTAL0. It is best not to route other signals between these pads, especially if a crystal is used for the clock source. The power connections to the inner ring of pads have 4 vias for +3.3V and 4 vias for +2.5V. The use of a single bypass capacitor for each via, and alternating 0.1uF and 0.01uF values on each supply, provide reasonable bypass capacitance for the fido1100. Using 8 capacitors in this manner allows the use of capacitors in the 0603 package for economical PCB assembly. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 34 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Figure 6. BGA 15- by 15-mm Signal Routing IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 35 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 4.3 Data Sheet September 10, 2014 Power and Ground Signals Tables 5 - 9 provide analog power and ground signals, crystal oscillator power and ground signals, 2.5 VDC digital core power signals, 3.3 VDC digital IO power signals, and digital ground signals, respectively. The recommended bypass capacitors for the fido1100 are: * Use a mix of 0.1 f and 0.01 f capacitors. * Bypass capacitors should be located as close as possible to power pins they are connected to. Table 5. Analog Power and Ground Signals BGA PQFP 15 x 15 11 D1 12 E1 Signal Name VDDA GNDA Type Power Ground Description Analog supply voltage (+3.3VDC) Analog ground Table 6. Crystal Oscillator Power and Ground Signals BGA PQFP 15 x 15 117 M15 120 M14 Signal Name VDDCLK GNDCLK Type Description Power supply Power Supply for the Crystal Oscillator (+2.5VDC) Ground Digital ground Table 7. 2.5 VDC Digital Core Power Signals BGA PQFP 15 x 15 Signal Name 16 D7 VDDC 48 D8 VDDC 75 D9 VDDC 80 H4 VDDC 106 K14 VDDC 142 L14 VDDC 157 P9 VDDC 177 P10 VDDC 206 - VDDC - - VDDC Type Power Power Power Power Power Power Power Power Power Power Description Digital core supply voltage (+2.5VDC) Digital core supply voltage (+2.5VDC) Digital core supply voltage (+2.5VDC) Digital core supply voltage (+2.5VDC) Digital core supply voltage (+2.5VDC) Digital core supply voltage (+2.5VDC) Digital core supply voltage (+2.5VDC) Digital core supply voltage (+2.5VDC) Digital core supply voltage (+2.5VDC) Digital core supply voltage (+2.5VDC) IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 36 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Table 8. 3.3 VDC Digital IO Power Signals BGA PQFP 15 x 15 Signal Name 22 D10 VDDIO 37 D11 VDDIO 65 D12 VDDIO 85 G14 VDDIO 135 J4 VDDIO 152 J14 VDDIO 167 K4 VDDIO 187 P8 VDDIO - H14 VDDIO Type Power Power Power Power Power Power Power Power Power Description Digital I/O supply voltage (+3.3VDC) Digital I/O supply voltage (+3.3VDC) Digital I/O supply voltage (+3.3VDC) Digital I/O supply voltage (+3.3VDC) Digital I/O supply voltage (+3.3VDC) Digital I/O supply voltage (+3.3VDC) Digital I/O supply voltage (+3.3VDC) Digital I/O supply voltage (+3.3VDC) Digital I/O supply voltage (+3.3VDC) Table 9. Digital Ground Signals BGA PQFP 15 x 15 Signal Name 31 D4 GND 42 T1 GND 44 D5 GND 53 P6 GND 60 D13 GND 70 D14 GND 90 E4 GND 111 E14 GND 130 N4 GND 148 N14 GND 162 P4 GND 172 P5 GND 182 B6 GND 192 P13 GND 201 P14 GND - - GND Type Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Description Digital ground Digital ground Digital ground Digital Ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital Ground Digital ground Digital Ground IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 37 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 5. Data Sheet September 10, 2014 Electrical Characteristics Tables 10 - 14 show the absolute maximum ratings, ESD and latch-up characteristics, recommended operating conditions, DC characteristics, and input impedance, respectively. Table 10. Absolute Maximum Ratings Symbol VDDC VDDIO VAIN TA TS TJ Parameter Name Digital core supply voltage Digital I/O supply voltage Analog input voltage with respect to ground Ambient temperature Storage temperature Junction Temperature Conditions - - - - - - Min -0.3 -0.3 -0.3 -40 -55 -40 Typ - - - - - - Max 3.05 5.5 3.9 +85 +150 +125 Units V V V o C o C o C Note: Operation of the fido1100 outside of maximum operating ratings may result in failure of the device. Table 11. ESD and Latch-Up Characteristics Symbol VHBM VMM ILATP ILATN Parameter Name Human body model Machine model Positive latch-up current Negative latch-up current Conditions - - - - Min 2000 200 - - Typ - - - - Max - - 50 -50 Units V V A A Table 12. Recommended Operating Conditions Symbol VDDC VDDIO fXTAL TA VDDA VRH VRL CL Parameter Name Digital core supply voltage Digital I/O supply voltage Crystal frequency Ambient temperature Analog supply voltage ADC reference voltage--high ADC reference voltage--low Digital output load capacitance Conditions - - - - - - - See note Min 2.25 3.0 - -40 3.0 - - - Typ 2.5 3.3 - - 3.3 3.0 0 3.1 Max 2.75 3.6 66 +85 3.6 - - - Units V V MHz o C V V V pF Note: This parameter is guaranteed by design and not tested in production. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 38 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Table 13. DC Characteristics o o TA = -40 C and +85 C; VDDC = 2.5V 10%; VDDIO = 3.3V 10%; Symbol Parameter Name Conditions Min Typ VIH Input high voltage - 2.0 - VIL Input low voltage - - - ILKG Input leakage current - -10 1 CIN Input capacitance - - 3.6 VOH Output high voltage |IOH| = 8 mA 2.4 - VOL Output low voltage |IOL| = 8 mA - - IOZ Tri-state leakage - -10 1 COUT Package output capacitance - - 3.6 FCLK = 66MHz Max Units - V 0.8 V 10 A - pF - V 0.4 V 10 A - pF Table 14. Input Impedance Input leakage current: Tristate leakage current: Pin capacitance (input or output): 10 A with no pull-up/pull-down 10 A ~3.5 pF not including package contribution Table 15. AC Characteristics of Crystal Oscillator Symbol fOSC tST Parameter Crystal oscillator range Startup time Conditions TA = 25C TA = 25C Typ - 20 Max 66 - Units MHz ms IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 39 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Table 16. Analog-to-Digital Converter Characteristics Symbol VINA CINA Res INL DNL SINAD FSMPL PD SMP Parameter Name Conditions Min Input voltage range - 0.1VDDA Input capacitance - - Resolution - - Integral non-linearity - - Differential non-linearity guaranteed no missing codes - Signal to noise plus distortion Fin = 10 KHz - Sample clock frequency - 0.5 Power dissipation TA = 25C - Sample rate - - Typ 20 10 2 1 54 - 5 - Max 0.9VDDA - - - - - 2.6 - 200 Units V pF Bits Lsb Lsb dB MHz mW Ksps Notes: 1. The ADC in the fido1100 uses its own VDD (VDDA) and GND (GNDA) connections along with VREF High (VRH) and VREF Low (VRL) signals. 2. VRH must be less than or equal to VDDA. 3. VRL must be greater than or equal to GNDA. 4. To ensure maximum conversion accuracy, VDDA, GNDA, VRH, and VRL should be as clean and free of noise as possible. Table 17. Power Consumption Conditions Core Voltage 2.5 VDC Current Power I/O Voltage 3.3 VDC Current Power Total Power Halted after a Reset 109.240 mA 273.100 mW 2.500 mA 8.25 mW 281.35 mW Light Processing Load 214.000 mA 535.000 mW 7.700 mA 25.41 mW 560.41 mW Heavy Processing Load 227.000 mA 567.500 mW 17.000 mA 56.1 mW 623.60 mW Sleep Mode 320.90 mW Stop Mode 302.91 mW Low Power Stop Mode (LPSTOP) 8.68 mW IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 40 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 6. Data Sheet September 10, 2014 Thermal Characteristics The thermal resistance characteristics for the 28 x 28 mm PQFP and the 15 x 15 mm BGA packages are provided in Table 18. All data is simulated based on the 2S2P board type. The board type is defined by JEDEC standard JESD51-7 for the PQFP package and by JESD51-9 for the BGA package. Table 18. Thermal Resistance Characteristics Name Description Airflow (m/S) 15 x 15 mm BGA 28 x 28 mm PQFP JC (C/W) Junction to Case 0 7.2 16.3 JA (C/W) Junction to Ambient 0 56.8 35.1 JA (C/W) Junction to Ambient 1 51.1 30.9 JA (C/W) Junction to Ambient 2 48.8 28.7 JA (C/W) Junction to Ambient 3 47.2 27.5 IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 41 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 7. Reset 7.1 Overview Data Sheet September 10, 2014 This section describes the reset signal considerations and the reset timing. The Power On Reset Register has a control bit to determine whether Major Reset or Minor Reset processing is performed after reset is asserted. The section below presents the hardware signal characteristics. See The fido1100 User Guide for more details on the Power On Reset Control Register. 7.2 Signal Considerations and Reset Timing The fido1100 requires the RESET_N signal to be asserted LOW for a minimum of 100 S after VDDIO and VDDC are at their nominal values and stable. The RESET_N signal must have a rise time of less than 100 nS. Table 19 presents the hardware signals involved or affected and should be considered when asserting reset. Table 19. Hardware Signals Involved When Asserting Reset Signal Name RESET_N RESET_OUT_N A_25_RESET_DELAY A27_CS7_N Type Input Output Muxed, Internal Pull-up Muxed, Internal Pull-up Muxed A28_CS6_N Muxed A29_CS5_N Muxed A30_CS4_N Muxed CS0_N Output A_26_SIZE Description Reset input Reset output Muxed pin, External Bus Interface address Bit [25] or POR counter bypass Muxed pin, External Bus Interface address Bit [26] or data bus size select (0 = 8-bit, 1 = 16-bit) Muxed pin, External Bus Interface address Bit [27] or Chip select 7 (chip select active low) Muxed pin, External Bus Interface address Bit [28] or Chip select 6 (chip select active low) Muxed pin, External Bus Interface address Bit [29] or Chip select 5 (chip select active low) Muxed pin, External Bus Interface address Bit [30] or Chip select 4 (chip select active low) Chip select 0 (chip select active low) When RESET_N is asserted, the following sequence occurs: * The A25_Reset_Delay signal is sampled to determine the length of the reset clock delay - Low--reset clock delay 100 secs - High--reset clock delay 20 msecs Note: After this delay, the part performs major or minor reset processing and is released to run. * The A_26_SIZE pin is sampled for the external bus interface size - Low--8-bit width - High--16-bit width IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 42 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 * The RESET_OUT_N signal is driven low for the determined clock delay Figures 7 and 8 present the reset timing and extended reset timing diagrams, respectively. The A_26_SIZE signal is not shown, but it is sampled. CLK CLK Clock Running | <--- Clock Stable RESET_N RESET RESET_OUT RESET_OUT_N RESET_DELAY RESET_DELAY ADDR 24:0 24:0 (ADDR 25) 0x000000 0x000000 15:0 DATA 15:0 CS0 100uS Power On Reset 100uS Hardware Reset TimeGen Figure 7. Reset Timing CLK CLK Clock Running | <--- Clock Stable RESET_N RESET RESET_OUT RESET_OUT_N RESET_DELAY RESET_DELAY ADDR ADDR 24:0 24:0 (ADDR 25) 0x000000 0x000000 15:0 DATA 15:0 CS0 CS0 20mS Hardware Reset 20mS Power On Reset TimeGen Figure 8. Extended Reset Timing Note: If A25_RESET_DELAY is high at the rising edge of RESET_N, internal reset and RESET_OUT_N are extended from 100 s to 20 mS. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 43 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 The following multiplexed signals are tri-stated during reset and should be pulled high if being used as chip selects or pulled low if being used as address lines (the fido1100 boots at address 0x00000000). If not being used, they can be pulled either high or low. * * * * A27_CS7_N A28_CS6_N A29_CS5_N A30_CS4_N At Reset, the CS0_N signal defaults to low for external memory access, supporting the boot sequence from address 0x00000000. 7.3 Clock Signals 7.4 Typical Clock Source Implementations The fido1100 can operate in one of two modes: (1) Normal or driven clock source input or (2) using an external crystal to set the operating frequency of the internal oscillator. Note: VDDCLK and GNDCLK must be connected even when not using an external crystal. 7.4.1 Normal or Driven Clock Source System configuration--Drive external clock source into XTAL0 (see Figure 9). XTAL1 is left unconnected. XTAL0 is effectively a Schmitt trigger input. Target frequency should have a duty cycle of approximately 40% to 60%. 7.4.2 Using an External Crystal * System Configuration (third overtone)--Crystal across XTAL0/XTAL1 (see Figure 10), 36 pF load caps to ground, 0.1-F cap, and 0.33-H inductor in series from XTAL1 to ground. * System Configuration (fundamental tone)--Crystal across XTAL0/XTAL1 (see Figure 11) and 20-pF load caps to ground. Note: Load capacitor and inductor values may be different based on crystal used. Please consult with your crystal supplier for more information. Third overtone configuration is recommended for 24- to 66-MHz operation and fundamental tone configuration is recommended for 1- to 24-MHz operation. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 44 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 GNDCLK XTAL1 GNDCLK VDDCLK L1 C2 Not Connected XTAL1 fido1100 XTAL0 C3 fido1100 Crystal C1 External Clock Source XTAL0 2.5V VDDCLK Figure 9. Driven Clock Source CLKVCC 2.5V Figure 10. Crystal Oscillator Third Overtone Off-Chip Components GNDCLK C2 XTAL1 fido1100 Crystal C1 XTAL0 VDDCLK 2.5V Figure 11. Crystal Oscillator Fundamental Overtone Off-Chip Components IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 45 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 7.5 Data Sheet September 10, 2014 Off-Chip Component Value Table 20 shows the suggested off-chip component values: Table 20. Suggested Off-Chip Component Values Operating frequency C1 C2 C3 L1 66MHz 36pF 36pF 0.1F 330nH 20 MHZ 20pF 20pF NA NA Notes: 1. Different C1, C2 values lead to different oscillation characteristics and should be selected based on system (board) level considerations. 2. Using C1 = C2 is recommended. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 46 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 8. Signals 8.1 External Bus Operation 8.1.1 Overview Data Sheet September 10, 2014 The fido1100 interfaces to external memory and peripherals through a set of programmable chipselect and bus-timing registers. It also has a built-in SDRAM controller to interface to SDRAM. This chapter provides timing diagrams for hardware considerations. For definitions of registers that control external bus timing and the SDRAM timing, please see The fido1100 User Guide. The external address bus of the fido1100 is 31-bit, and the external data bus is configurable to support either an 8- or 16-bit bus. In this section, timing diagrams are provided for the following: 8.2 * General Setup and Hold Timing * External Bus Timing - 32-bit transfer without external ready (RDY_N) - 32-bit transfer with external ready (RDY_N) - 8-bit/16-bit single cycle without external ready (RDY_N) - 8-bit/16-bit cycle with external ready (RDY_N) * SDRAM Timing - SDRAM CAS Timing - SDRAM Row Activation Timing - SDRAM Read Operation Timing - SDRAM Read Burst Timing - SDRAM Write Operation, Write Burst, Write-to-Write Operation, and Write-toPrecharge Timing General Setup and Hold Timing All timing delays are characterized at the 50% to 50% point. This includes propagation delay times through combinatorial functions as well as setup, hold time, and release-time definitions for sequential elements (see Chapter 9, Setup and Hold Timing, for diagrams). IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 47 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 8.3 Data Sheet September 10, 2014 External Bus Timing Signals listed on the External Bus Timing diagrams are described below. * TwWAIT - If RDY_ENABLE=0, specifies the width of the chip select active period for the nonburst-mode write cycle. The allowed range is 0-31, resulting in a wait time of 1-32 clocks. - If RDY_ENABLE=1, specifies the wait time before the RDY_N line is first sampled for the write cycle. This provides a max wait time of 484 nS at 66 MHz. Anything greater than this will require the external RDY_N line and external logic. * TrWAIT - If RDY_ENABLE=0, specifies the width of the chip select active period for the nonburst-mode read cycle. The allowed range is 0-31, resulting in a wait time of 1-32 clocks. - If RDY_ENABLE=1, specifies the wait time before the RDY_N line is first sampled for the read cycle. This provides a max wait time of 484 nS at 66 MHz. Anything greater than this will require the external RDY_N line and external logic. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 48 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 9. Data Sheet September 10, 2014 Setup and Hold Timing All timing delays are characterized at the 50% to 50% point. This includes propagation delay times through combinatorial functions as well as setup, hold-time, and release-time definitions for sequential elements. * Propagation Delay--Time between an input signal transition and the resultant output signal transition (see Figure 12). Tplh = 14ns. Tphl = 14ns. Figure 12. Propagation Delay * Setup Time--The minimum time that input data must remain unchanged prior to an active clock transition (see Figure 13). Setup = 2ns. Figure 13. Setup Time IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 49 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller * Data Sheet September 10, 2014 Hold Time--The minimum time that input data must remain unchanged subsequent to an active clock transition (see Figure 14). Hold = 2ns. Figure 14. Hold Time * Recovery Time--The minimum time that the Set or Reset input must remain unactivated prior to an active clock transition (see Figure 15). Recovery = 3ns. Figure 15. Recovery Time * Removal Time--The minimum time that the Set or Reset input must remain activated subsequent to an active clock transition (see Figure 16). Removal = 3ns. Figure 16. Removal Time IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 50 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller * Data Sheet September 10, 2014 Minimum Pulse Width--The minimum length of time between the leading and trailing edges of a pulse (see Figure 17). Timings are based on a 66-MHz clock yielding 15-ns cycles. MPW_H = 7ns. MPW_L = 7ns. Figure 17. Minimum Pulse Width * THLD--Specifies the time between when the CSn_N and BEn_N signals go inactive (hi) and the address is removed, 0-7 clocks. * TCS--Specifies the time between when the address bus is driven and the CSn_N and BEn_N signals go active (low), 0-3 clocks. * TOE--Specifies the time between when the CSn_N and BEn_N signals go active (low) and the OE signal goes active (low), 0-3 clocks. * TWEF--Specifies the time between when the CSn_N and BEn_N signals go active (low) and the WE_N signal goes active (low), 0-3 clocks. * TWER--Specifies the time between when the WE_N signal goes inactive (hi) and the CSn_N and BEn_N signals go inactive (hi), 0-3 clocks. 9.1.1 External Bus Timing for a 32-Bit Transfer (without RDY_N) This timing is programmable via the External Bus Chip Select Timing Register (see Figure 18). * All timing is relative to the rising edge of the clock. * The chip-select and byte-enable signals (CSn_N and BEn_N) go active (low) 0-3 clocks (TCS) after the address bus is driven. * The chip-select, output-enable, and byte-enable signals (CSn_N, BEn_N, and OE_N) go inactive (hi) 0-7 clocks (THLD) before the address is removed (on the last cycle). IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 51 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Figure 18. External Bus Timing for a Single, 32-Bit Cycle (without RDY_N) * The write-cycle timing is controlled by TwWAIT setting (shown as TxWAIT in the diagram), 2-33 clocks.The read-cycle timing is controlled by TrWAIT setting (shown as TxWAIT in the diagram), 2-33 clocks. * The output-enable signal (OE_N) goes active (low) 0-3 clocks (TOE) after the chip select. * The output-enable signal (OE_N) goes inactive (hi) coincident with the chip select. * The write-enable signal (WE_N) goes active (low) 0-3 clocks (TWEF) after the chip select (first cycle only). For subsequent cycles, the WE_N line will go active (low) 0-3 clocks (TWEF) after the address bus changes. * The write-enable signal (WE_N) goes inactive (hi) 0-3 clocks (TWER) before the end of the wait time and hence before the address bus changes (subsequent cycles). This is when the data is considered "written." 9.1.2 External Bus Timing for a 32-Bit Transfer (with RDY_N) This timing is programmable via the External Bus Chip Select Timing Register (see Figure 19). IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 52 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Figure 19. External Bus Timing for a 32-Bit Transfer (with RDY_N) * The TxWAIT setting determines when first to start sampling the low active RDY_N line (labeled with an arrow marked "1" in the diagram). * In the case of a write transfer after the low active RDY_N line is first sampled low (labeled with an arrow marked "2" in the diagram), the write cycle will complete on the next rising edge of the clock as shown (labeled with an arrow marked "3" in the diagram). * In the case of a read transfer once the low active RDY_N line is first sampled low (labeled with an arrow marked "2" in the diagram), the read data will be sampled on the second rising edge of the clock. * The write-cycle timing is controlled by TwWAIT setting (shown as TxWAIT in the diagram), 2-33 clocks. * The read-cycle timing is controlled by TrWAIT setting (shown as TxWAIT in the diagram), 2-33 clocks. * If the RDY_N line never goes low, the cycle will end (as a bus error) after a timeout of TxWAIT + 256 clocks. * If the RDY_N line is unused (tied low via an internal pull down) or goes low immediately, the cycle will be controlled by TxWAIT as described above. * In the case of a write transfer, the write-enable signal (WE_N) goes active (low) 0-3 clocks after the CS_N goes low. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 53 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller * 9.1.3 Data Sheet September 10, 2014 The write-enable signal (WE_N) goes inactive (hi) 0-3 clocks (TWER) before the end of the chip-select time. External Bus Timing for 8-Bit/16-Bit Transfer (without RDY_N) This timing is programmable via the External Bus Chip Select Control Register (see Figure 20). Figure 20. External Bus Timing for 8-Bit/16-Bit Transfer (without RDY_N) * All timing is relative to the rising edge of the clock. * The chip-select and byte-enable signals (CSn_N and BEn_N) go active (low) 0-3 clocks (TCS) after the address bus is driven. * The chip-select and byte-enable signals (CSn_N and BEn_N) go inactive (hi) 0-7 clocks (THLD) before the address is changed. * The write-cycle timing is controlled by TwWAIT setting (shown as TxWAIT in the diagram), 2-33 clocks. * The read-cycle timing is controlled by TrWAIT setting (shown as TxWAIT in the diagram), 2-33 clocks. * The output-enable signal (OE_N) goes active (low) 0-3 clocks (TOE) after the chip select. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 54 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 * The output-enable signal (OE_N) goes inactive (hi) coincident with the chip select. This is also when the read data is sampled. * The write-enable signal (WE_N) goes active (low) 0-3 clocks (TWEF) after the chip select. * The write-enable signal (WE_N) goes inactive (hi) 0-3 clocks (TWER) before the end of the cycle (CSn_N is removed). 9.1.4 External Bus Timing for 8-Bit/16-Bit Transfer (with RDY_N) This timing is programmable via the External Bus Chip Select Control Register (see Figure 21). Figure 21. External Bus Timing for 8-Bit/16-Bit Transfer (with RDY_N) * The write-cycle timing is controlled by TwWAIT setting (shown as TxWAIT in the diagram), 2-33 clocks. * The read-cycle timing is controlled by TrWAIT setting (shown as TxWAIT in the diagram), 2-33 clocks. * The TxWAIT setting determines when first to start sampling the low active RDY_N line (labeled with an arrow marked "1" in the diagram). * In the case of a write transfer, once the low active RDY_N line is first sampled low (labeled with an arrow marked "2" in the diagram), the write cycle will complete on the IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 55 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 next rising edge of the clock as shown (labeled with an arrow marked "3" in the diagram). * In the case of a read transfer, once the low active RDY_N line is first sampled low (labeled with an arrow marked "2" in the diagram), the read data will be sampled on the second rising edge of the clock. * If the RDY_N line never goes low, the cycle will end (as a bus error) after a timeout of TxWAIT + 256 clocks. * If the RDY_N line is unused (tied low via an internal pull down) or goes low immediately, the cycle will be controlled by TxWAIT as shown above. * In the case of a write transfer, the write enable signal (WE_N) goes active (low) 0-3 clocks after the CS_N goes low. * The write enable signal (WE_N) goes inactive (hi) 0-3 clocks (TWER) before the end of the chip-select time. Note: This timing picture also reflects the default bus timing for all memory addresses not decoded by the internal chip-select unit. In this case, the timing is controlled by the External Bus Default Timing Register. 9.2 SDRAM Timing 9.2.1 SDRAM CAS Timing The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving because of the clock edge one cycle earlier (n + m - 1) and, provided the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 22. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 56 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Figure 22. SDRAM CAS Timing 9.2.2 SDRAM Row Activation Timing Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 23). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. The tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125-MHz clock (8-ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 24, which covers any case where 2 < tRCD (MIN)/tCK 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 57 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Figure 23. Specific Row Activation Timing Figure 24. Meeting tRCD (min) When 2 < tRCD (min)/tCK 3 IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 58 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 9.2.3 Data Sheet September 10, 2014 SDRAM Read Operation Timing READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled (see Figure 25). Figure 25. SDRAM Read Operation Timing During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go high, and full-page burst will continue until terminated. (At end of the page, it will wrap to column 0 and continue.) 9.2.4 SDRAM Read Burst Timing Data from any READ burst may be truncated with subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 59 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one (see Figure 26). For CAS latencies of two and three, data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 64 Mbyte SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 16 or each subsequent READ may be performed to a different bank. Figure 26. SDRAM Read Burst Timing 9.2.5 SDRAM Write Operation, Write Burst, Write-to-Write, and Write-to-Precharge Timing WRITE bursts are initiated with a WRITE command. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 60 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z, and any additional input data will be ignored. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command (see Figures 27 - 30). Figure 27. SDRAM Write Operation Timing IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 61 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Figure 28. SDRAM Write Burst Timing Figure 29. SDRAM Write-to-Write Timing IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 62 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Figure 30. SDRAM Write-to-Precharge Timing IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 63 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 10. Data Sheet September 10, 2014 JTAG The TAP controller is a synchronous Finite State Machine and responds to changes in the TMS and TCK signals. States transition occurs on the rising edge of TCK. Values shown to the side of each state represent the state of TMS at the time of the rising edge of TCK (see Figure 31). There are two paths through the state machine. The instruction path captures and loads the JTAG instructions into the instruction register. The data path captures and loads data into the other three registers. The TAP controller executes the last instruction decode until a new instruction is entered at the Update-IR state or until a reset is sent to the controller. 1 Test-Logic-Reset 1 0 1 Run-Test/Idle 1 Select-DR-Scan 0 Select-IR-Scan 0 0 Capture-IR Capture-DR 0 Shift-DR 0 0 1 1 Shift-IR Exit1-IR Exit1-DR 0 0 0 1 1 1 0 1 Exit2-IR Exit2-DR 1 1 Update-IR Update-DR 1 0 Pause-IR Pause-DR 0 0 1 1 0 1 0 Figure 31. JTAG State Machine The JTAG port has four Read/Write registers. An ID register, By-Pass Register, Boundary Scan, and Instruction Register (see Figure 32). The TDO pin remains in the high impedance state except during a shift-DR or shift-IR controller state. In the shift-DR and shift-IR controller states, TDO is updated on the falling edge of TCK. TMS and TDI are sampled on the rising edge of TCK. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 64 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Input Mux Output Mux ID Register By-Pass Register TDI Boundary Scan Instruction Register Instruction Decode TMS TCK Tap Controller TDO Figure 32. JTAG Port Register Interface The timing of the JTAG signals is shown in Figure 33. The TDO pin remains in the high impedance state except during a shift-DR or shift-IR controller state. In the shift-DR and shift-IR controller states, TDO is updated on the falling edge of TCK. TMS and TDI are sampled on the rising edge of TCK. Figure 33. Timing of JTAG Signals 10.1 JTAG Scan Chain Debug Functionality The JTAG port contains an 8-bit-wide instruction register. Instructions are transferred to this register during the shift-IR state of the TAP state machine and are decoded by entering the Update-IR state of the TAP. The JTAG controller executes the last decoded instruction until another new one is entered and decoded. The instructions and data are entered serially through the TDI pin, LSB first. The JTAG Test Access Port (TAP) instruction shift register will support the debug scan chain commands shown in Table 21. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 65 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 Table 21. Debug Scan Chain Commands Supported by the JTAG TAP JTAG Instruction 00010000 00010001 00010010 00010011 00010100 11111110 11111000 11111010 11111111 00000111 00001111 Scan Chain Function READWRITEADDRCMD (Read/Write Memory/Registers Address and Command) READDATA (Read Memory/Registers Data) WRITEDATA (Write Memory/Registers Data) READPC_ANDCONTEXT (Read Program Counter and Active context) READWRITEDRBUGREG (Read/Write Debug Control Register) IDCODE (Read Device ID Register) EXTEST (IO Boundary Scan) SAMPLE/PRELOAD (Sample Boundary Scan chain on "Capture-DR" state, Load Boundary Scan chain on `Update-DR' state) BYPASS (Use TDI/TDO Bypass Register) RUNBIST (Run Built in Self-Test) ENABLEATPG (Enable ATPG Mode for Manufacturing Test) Scan Chain Length 37 bits Scan Chain Reference Number 1 Public or Private Private 32 bits 32 bits 37 bits 2 7 4 Private Private Private 15 bits 5 Private 32 bits n bits (I/O Pins) N bits (I/O Pins) 3 6 Public Public 6 Public 1 bit 16 bits N/A 9 8 N/A Public Public Private Notes: 1. The boundary-scan scan chain is selected via the EXETEST, SAMPLE, and PRELOAD instructions. 2. The SAMPLE and PRELOAD instructions have the SAME binary code. (They are identified as separate instructions in the JTAG Spec, but are allowed to have the same binary code for backwards compatibility with previous version of spec.) 3. Any undefined bit pattern that is shifted into the Instruction Register will perform the same function as the BYPASS instruction. 4. On Power-on Reset, or when the JTAG state machine enters the "Test Logic Reset" the instruction register will reset its value to operate as the IDCODE Instruction (per JTAG Spec). IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 66 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 11. Data Sheet September 10, 2014 Ordering Information The fido1100 parts currently available are listed in Table 22. Table 22. Part Numbers by Package Types Innovasic Part Number Package Type fido1100PQF208IR1 208-Lead QFP Lead-free (RoHS-compliant) 28- by 28-mm Package fido1100BGB208IR1 208-Ball BGA, .8mm pitch Lead-free (RoHS-compliant) 15- by 15-mm Package Temperature Grade Industrial Industrial IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 67 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 12. Data Sheet September 10, 2014 Errata This chapter addresses issues discovered by our internal testing organization that may affect the implementation of the fido1100. This information should be used in conjunction with The fido1100 User Guide and The fido1100 Instruction Set Reference Guide to circumvent problems during the design process and is not intended as a standalone design guide. Although fido1100-specific terms are clearly described, in the interest of conciseness, many terms already familiar to designers and developers are left undefined. 12.1 Summary Table 23 presents a summary of errata. Table 23. Summary of Errata Errata No. Problem Ver. 1 1 ADC Start Register Bit 0 (START) does not self-clear when non-scanning mode conversion for single channel or multi-channel is selected. Exists 2 Fatal fault recovery sequence can be disturbed by interrupts. Exists 3 The vectors are reversed when a trapx instruction is executed coincident with an interrupt to a higher priority context. Exists 4 When using the RDY_N signal to insert wait states (chip select timing register RDY_ENABLE bit = 1), the Address bus timing is incorrect. Exists 5 When using a JMP or JSR instruction in PC indirect with base displacement addressing mode in assembly code projects, the CPU does not execute the instruction correctly. Exists 12.2 Detail Errata No. 1 Problem: ADC Start Register Bit 0 (START) does not self-clear when non-scanning mode conversion for single channel or multi-channel is selected. Description: * Scanning mode is controlled by ADC Control Register Bit 6 (SCAN). IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 68 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 * ADC Control Register Bit 4 (CD-Conversion Done) will correctly indicate that conversion(s) are done. * An ADC interrupt will be issued if ADC interrupts are enabled. ADC interrupts are enabled by setting ADC Control Register Bit 3 (IRQ_En) to 1. * ADC Data Available Register will correctly indicate which channels have updated results in their Data Registers. Workaround: When using non-scanning mode conversions, enable the ADC between each commanded conversion (single channel or multi-channel): * Clear ADC Control Register Bit 7 (EN) to 0. * Set ADC Control Register Bit 7 (EN) to 1. * Set ADC Start Register Bit 0 (START) to 1 to start the conversion process. * ADC Conversion complete will be indicated by: - An ADC interrupt, if ADC Control Register Bit 3 (IRQ_En) is set to 1. - ADC Control Register Bit 4 (CD-Conversion Done) will set to indicate that conversion(s) are done. Errata No. 2 Problem: Fatal fault recovery sequence can be disturbed by interrupts. Description: Context Fatal Faults can occur if a context's stack pointer becomes corrupted. It is a feature of the hardware to detect this "Fatal Fault" and allow a graceful recovery by directing an exception to the Master Context. This operation can be disturbed if, by chance, an interrupt is triggered during a bus cycle leading to a Fatal Fault. This problem occurs no matter which context the interrupt is directed to. It need not be the faulting context. Furthermore, since neither interrupt timing nor fatal faults are predictable, there is no way to guarantee this cannot happen. The effect of this error depends on the interrupt mode of the context to which the interrupt is directed. If the interrupted context is running in Fast Single Threaded mode, when an interrupt targeted to it occurs during a faulting bus cycle (caused by another context) the CPU will lock up after the faulting bus cycle completes. If the interrupted context is in Standard or Fast Vectored mode the CPU will not lock up but the normal fault handling process will be disrupted. The effect is: * * Both the interrupted and the faulting context will be set to Halted. The fatal fault exception will be directed to the interrupted context rather than the Master. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 69 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller * * * Data Sheet September 10, 2014 The expected interrupt will be directed (queued behind the fatal fault exception) to the interrupted context. The Master context will be moved to the ready state, with no modification of its program counter, thus it will start running from where it left off previously. All other contexts are unaffected. Errata No. 3 Problem: The vectors are reversed when a trapx instruction is executed coincident with an interrupt to a higher priority context. Description: Given a low priority context currently executing and the master context and a higher priority context sleeping, if an interrupt comes in for the higher priority context simultaneously with the execution of a trapx instruction in the low priority context, it can happen that the interrupt handler is executed by the master context (even though intended for the higher priority context), while the trapx handler is executed by the higher priority context. Workaround: The workaround involves several issues: 1. Any interrupt handlers intended for other than the lowest priority context should be executable by the master context. 2. The master context must have a valid vector to the appropriate interrupt handlers. Either the master context and the other contexts share a vector table or the vectors are duplicated on the master context's table. If the master context is executed in a different mode than the other contexts (e.g. master in standard mode, other context in fast-vectored mode), then a second interrupt handler must be coded that is compatible with the master context's operating mode. 3. Trapx handlers should verify that they are being executed in the master context. This assumes that they are performing some action that can only be executed in the master context, and if so, then they should execute and set a flag to alert the caller that they executed. If not, then they should return without setting the flag. Also, trapx handlers must be present (in the appropriate execution mode) on all vector tables. 4. The routine executing a trapx instruction should check the handshake flag from the trapx handler after execution of the instruction. If it is not set appropriately, the trapx should be executed again. The approach given in 3 and 4 above, while more complex than simply having the trapx handler issue a trapx instruction if not executed in the master context, avoids the issue of IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 70 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Data Sheet September 10, 2014 trapx handlers that rely on the Faulted Context register to determine what specific action to take. Errata No. 4 Problem: When using the RDY_N signal to insert wait states (chip select timing register RDY_ENABLE bit = 1), the Address bus timing is incorrect. Description: When used in this way, the Address bus will change states coincident with, or in some cases, before the end of the bus cycle. This can cause data corruption in memory. Workaround: There is no work around for this problem. It is recommended to avoid use of the RDY_N signal and the RDY_ENABLE bit of the chip select timing registers. Errata No. 5 Problem: When using a JMP or JSR instruction in PC indirect with base displacement addressing mode in assembly code projects, the CPU does not execute the instruction correctly. Description: Instead of jumping indirectly to the location pointed to by the effective address, execution jumps to the effective address directly. Workaround: There is no workaround for this problem. For assembly code projects, avoiding use of the PC indirect addressing with base displacement mode is recommended. IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 71 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 13. Data Sheet September 10, 2014 Revision History Table 24 presents the sequence of revisions to document IA211080807. Table 24. Revision History Date Revision Description Page(s) August 8, 2007 00 First edition released. NA September 11, 2008 01 Reformatted to meet publication standards. Technical data updated. Errata added. NA Changed "RESET" to "RESET_N" and "RESET_OUT" to "RESET_OUT_N" in text, figures, and tables. 17, 19, 26, 28, 35, 37, 50, 51 October 9, 2008 02 In Table 5, changed pin numbers in data row 14 from "F3" to "G3"and in data row 19 from "G3" to "H3." In Table 5, changed pin numbers in data row 11 from "M14" to "M15" and in data row 14 from "M15" to "M14." Deleted last row of Table 5 (duplicate). In Table 7, changed numbers in data row 1 from "M14" to "M15" and in data row 2 from "M15" to "M14." In Table 10, changed numbers in data rows 13, 14, 15, and 16 to "B6," "P13," "P14," and "-," from "P5," "B6," "P13," and "P14," respectively, for column labeled "BGA 15 x 15." Added 2 new sentences at beginning of Section 7.2, "Signal Considerations and Reset Timing." Changed "CLKVDD" to "VDDCLK" and "CLKGND" to "GNDCLK" in note and Figures 11, 12, and 13. Updated errata chapter to reflect errata for Version 01. To conform to publication standards, removed illustration from cover. Changed Table 24, "Part Numbers by Package Types," to reflect Version 01 part numbers. Revised ordering information - package information; Added Errata 2. Revised description of when bus cycle terminates in a Read cycle; Added two errata. 36 39 40 43 44 50 52, 53 76 through 87 October 10, 2008 03 March 12, 2009 04 July 28, 2009 05 November 20, 2009 06 Updated LPSTOP power consumption. 49 April 15, 2010 07 Added BGA signal routing guidance. 43, 44 April 25, 2012 08 Added Errata 5 81 IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 72 of 74 1, 75 75 - 78 61, 64, 76, 78, 79 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller Date Revision Data Sheet September 10, 2014 Description Page(s) December 11, 2012 09 Removed references to 10x10 BGA package; Added thermal characteristics data. 10, 41 April 10, 2013 10 Corrected oscillator startup time (tST) 39 September 10, 2014 11 Modified timing information for TwWait and TrWait. 61-66 IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 73 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184 Flexible Input Deterministic Output (fido(R)) 32-Bit Real-Time Communications Controller 14. Data Sheet September 10, 2014 For Additional Information Innovasic's fido1100 is the first product in the fido family of real-time communication controllers. The fido communication controller architecture is uniquely optimized for solving memory bottlenecks, and is designed from the ground up for deterministic processing. Critical timing parameters, such as context switching and interrupt latency, are precisely predictable for real-time tasks. The fido1100 also incorporates the Universal I/O Controller (UIC) that is configurable to support various communication protocols across multiple platforms. This flexibility relieves the designer of the task of searching product matrices to find the set of peripherals that most closely match the system interface needs. The Software Profiling and Integrated Debug EnviRonment (SPIDER) has extensive real-time code debug capabilities without the burden of code instrumentation. The fido1100 User Guide and The fido1100 Instruction Set Reference Guide as well as other helpful tools and files are available. For example, the GDB debugger supports both profiling and tracing of executing code. The Innovasic Support Team is continually planning and creating tools for your use. Visit http://www.innovasic.com for up-to-date documentation and software. Our goal is to provide timely, complete, accurate, useful, and easy-to-understand information. Please feel free to contact our experts at Innovasic at any time with suggestions, comments, or questions. Innovasic Support Team 5635 Jefferson St. NE, Suite A Albuquerque, NM 87109 USA (505) 883-5263 Fax: (505) 883-5477 Toll Free: (888) 824-4184 E-mail: support@innovasic.com Website: http://www.Innovasic.com IA211080807-11 UNCONTROLLED WHEN PRINTED OR COPIED Page 74 of 74 http://www.innovasic.com Customer Support: 1-888-824-4184