MC13111AFB
MC13111AFTA
MC13111BFB
MC13111BFTA
MC13110A/B
MC13111A/B
UNIVERSAL
NARROWBAND FM RECEIVER
INTEGRATED CIRCUIT
FB SUFFIX
PLASTIC PACKAGE
CASE 848B
(QFP–52)
52
Order this document by MC13110A/D
1
Device Tested Operating
Temperature Range Package
ORDERING INFORMATION
MC13110AFB
TA = – 40° to +85°C
QFP–52
FTA SUFFIX
PLASTIC PACKAGE
CASE 932
(LQFP–48)
48 1
MC13110AFTA LQFP–48
MC13110BFB QFP–52
MC13110BFTA LQFP–48
QFP–52
LQFP–48
QFP–52
LQFP–48
1
MOTOROLA RF/IF DEVICE DATA
Advance Information
Universal Cordless Telephone
Subsystem IC
The MC13110A/B and MC13111A/B integrates several of the functions
required for a cordless telephone into a single integrated circuit. This
significantly reduces component count, board space requirements, external
adjustments, and lowers overall costs. It is designed for use in both the
handset and the base.
•MC13110A and MC13111A: Fully Programmable in all Power Modes
•MC13110B and MC13111B: MPU Clk Out and Second Local Oscillator
are “Always On”. There is No Inactive Mode
•Dual Conversion FM Receiver
– Complete Dual Conversion Receiver – Antenna Input to Audio Out
80 MHz Maximum Carrier Frequency
– RSSI Output
– Carrier Detect Output with Programmable Threshold
– Comparator for Data Recovery
– Operates with Either a Quad Coil or Ceramic Discriminator
•Compander
– Expander Includes Mute, Digital Volume Control, Speaker Driver,
Programmable Low Pass Filter, and Gain Block
– Compressor Includes Mute, Programmable Low Pass Filter, Limiter,
and Gain Block
•MC13110A/B only: Frequency Inversion Scrambler
– Function Controlled via MPU Interface
– Programmable Carrier Modulation Frequency
•Dual Universal Programmable PLL
– Supports New 25 Channel U.S. Standard with No External Switches
– Universal Design for Domestic and Foreign Cordless Telephone
Standards
– Digitally Controlled Via a Serial Interface Port
– Receive Side Includes 1st LO VCO, Phase Detector, and 14–Bit
Programmable Counter and 2nd LO with 12–Bit Counter
– Transmit Section Contains Phase Detector and 14–Bit Counter
– MPU Clock Outputs Eliminates Need for MPU Crystal
•Low Battery Detect
– Provides Two Levels of Monitoring with Separate Outputs
– Separate, Adjustable Trip Points
•2.7 to 5.5 V Operation (15 µA Current Consumption in Inactive Mode)
•AN1575: Refer to this Application Note for a List of the “Worldwide
Cordless Telephone Frequencies
Rx Phase
Detector
Tx Phase
Detector
Low Battery
Detect
Simplified Block Diagram
This device contains 8262 active transistors.
Expander
1st
Mixer
Data Out
Rx In 2nd
Mixer
Tx PD Out
Tx Out
Limiting IF
Amplifier Detector
Rx Out
Tx In
Low Battery
Indicator
Rx PD In
Rx PD Out
1st LO 2nd LO Carrier Detect Out
SPI
RSSI
RSSI
µP Serial
Interface
Compressor
Scrambler
Scrambler
= MC13110A/B Only
NOTE:
MPU Clock Out
2nd LO
This document contains information on a new product. Specifications and information herein
are subject to change without notice. Motorola, Inc. 1998 Rev 1
MC13110A/B MC13111A/B
2MOTOROLA RF/IF DEVICE DATA
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
13
12
11
10
9
8
7
6
5
4
3
2
1
27
28
29
30
31
32
33
34
35
36
37
38
39
BD1 Out
DA Out
BD2 Out
T
C Cap
C In
Amp Out
T
DA In
V
R
Det Out
RSSI
xOut
xIn
CCAudio
xAudio In
LO
LO
V
Gnd Audio
SA Out
SA In
E Out
E
E In
Scr Out
Ref
Ref
VB
1
2
cap
capCtrl
1Out
1In
Q Coil
Lim Out
V
Lim C2
Lim C1
Lim In
SGnd RF
Mix
Gnd RF
CCRF
2In
Mix2Out
Mix1Out
Mix1In
Mix1In1
2
Out
Vag
PD
ref
Gnd PLL
T
Data
EN
Clk
Clk Out
CD Out
xPD
TxVCO
PLL V
Rx
LO2
InLO2
1st Mix 2nd Mix
2nd LO
1st LO
1st LO
VCO
IF Amp/
Limiter Detector
RSSI
LPF AALPF
÷2
2nd LO SC Filter
Clock Mic Amp
Tx Gain
Adjust
LPF
ALC
C Cap
Compressor
Limiter
Tx
Mute
Ref2
Ref1Low Battery
Detect Data
Amp
Carrier
Detect
Rx Gain
Adjust
Rx
Mute
Speaker
Amp
Speaker
Mute
Expander
Vol
Control
1st LO VB
÷25
÷4
÷1
12 b Prog
Ref Ctr
2nd LO
14 b Prog
Rx Ctr Vref Reg 2.5 V
14 b Prog
Tx Ctr µP Serial
Interface
Prog
Clk Ctr
Tx Phase
Detect
Rx Phase
Detect
2nd LO
10.240
PIN CONNECTIONS
QFP–52
12
11
10
9
8
7
6
5
4
3
2
1
Vag
PD
ref
Gnd PLL
T
Data
EN
Clk
Clk Out
xPD
TxVCO
PLL V
Rx
OutLO2
13
14
15
16
17
18
19
20
21
22
23
24
DA Out
BD Out
T
C Cap
C In
Amp Out
T
DA In
V
R
Det Out
Q Coil
xOut
xIn
CCAudio
xAudio In
25
26
27
28
29
30
31
32
33
34
35
36
Lim Out
V
Lim C2
Lim C1
Lim In
RSSI
Mix
Gnd RF
CCRF
2In
Mix2Out
Mix1Out
Mix1In
Mix1In1
2
48
47
46
45
44
43
42
41
40
39
38
37
LO
LO
V
Gnd Audio
SA Out
SA In
E Out
E
E In
Scr Out
LO2
VB
cap
capCtrl
1Out
1In 1st Mix 2nd Mix
2nd LO
LPF AALPF
Carrier
Detect
Data
Amp
VCC Audio
µP Serial
Interface
Prog
Clk Ctr
Tx Phase
Detect
Rx Phase
Detect
Reg 2.5 V
14 b Prog
Tx Ctr
Mic Amp
Speaker
Amp
Speaker
Mute Expander
Vol
Control
÷25
÷4
÷1
12 b Prog
Ref Ctr
VB
1st LO
Programmable
Low Battery
Detect
In
CD Out
LQFP–48
6 b Prog
SC Clk Ctr
1st LO
Detector
RSSI
IF Amp/
Limiter
2nd LO
1st LO
VCO
14 b Prog
Rx Ctr Vref
2nd LO
10.240
LPF
LPF
4.129 kHz
Bypass
Bypass
4.129 kHz
÷40 Scrambler
Modulating Clock
= MC13110A/B Only
Scrambler
NOTE:
Rx Gain
Adjust
Rx
Mute
÷2SC Filter
Clock
Tx Gain
Adjust
LPF
ALC
C Cap
Compressor
Limiter
Tx
Mute
6 b Prog
SC Clk Ctr
LPF
LPF
4.129 kHz
Bypass
Bypass
4.129 kHz
÷40 Scrambler
Modulating Clock
Scrambler
2nd LO
MC13110A/B MC13111A/B
3
MOTOROLA RF/IF DEVICE DATA
MAXIMUM RATINGS
Characteristic Symbol Value Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Supply Voltage
ÁÁÁÁ
ÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
–0.5 to +6.0
ÁÁÁ
ÁÁÁ
Vdc
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Junction Temperature
ÁÁÁÁ
ÁÁÁÁ
TJ
ÁÁÁÁÁ
ÁÁÁÁÁ
–65 to +150
ÁÁÁ
ÁÁÁ
°C
Maximum Power Dissipation, TA = 25°C PD70 mW
NOTES: 1.Devices should not be operated at these limits. The “Recommended Operating Conditions”
provide for actual device operation.
2.ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Min Typ Max Unit
Supply Voltage VCC 2.7 3.6 5.5 Vdc
Operating Ambient Temperature TA–40 – 85 °C
Input Voltage Low (Data, Clk, EN) VIL – – 0.3 V
Input Voltage High (Data, Clk, EN) VIH PLL Vref –
0.3 – – V
Bandgap Reference Voltage VB– 1.5 – V
NOTE: 3.All limits are not necessarily functional concurrently.
DC ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, TA = 25°C, unless otherwise specified, IP3 = 0;
Test Circuit Figure 1.)
Characteristic Symbol Figure Min Typ Max Unit
Static Current 1
Active Mode ACT ICC 5.5 8.5 10.5 mA
Receive Mode Rx ICC 3.1 4.1 5.3 mA
Standby Mode STD ICC –465 560 µA
Inactive Mode [Note 4] INACT ICC –15 30 µA
Current Increase When IP3 = 1
(Active and Receive Modes) IIP3 1 – 1.4 1.8 mA
NOTE: 4.MC13110B/MC1311 1B versions have no inactive mode.
MC13110A/B MC13111A/B
4MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic Figure Input
Pin Measure
Pin Symbol Min Typ Max Unit
FM RECEIVER (fRF = 46.77 MHz [USA Ch 21], fdev = ±3.0 kHz, fmod = 1.0 kHz, Vcap ctrl = 1.2 V)
Input Sensitivity (for 12 dB SINAD at Det Out
Using C–Message Weighting Filter)
50 Ω Termination, Generator Referred
68, 69 Mix1
In1/In2Det Out VSIN –
–2.2
–100 –
–
µVrms
dBm
Single–Ended, Matched Input, Generator
Referred –
–0.4
–115 –
–
Differential, Matched Input, Generator Referred –
–0.4
–115 –
–
First and Second Mixer Voltage Gain Total
(Vin = 1.0 mVrms, with CF1 and CF2 Load) 1 Mix1
In1 or In2Mix2 Out MXgainT 24 29 – dB
Isolation of First Mixer Output and Second Mixer
Input (Vin = 1.0 mVrms, with CFI Removed) – Mix1
In1 or In2Mix2 In Mix–Iso – 60 – dB
Total Harmonic Distortion (Vin = 3.16 mVrms) 1 Mix1
In1 or In2Det Out THD – 1.4 2.0 %
Recovered Audio (Vin = 3.16 mVrms) 1 Mix1
In1 or In2Det Out AFO 80 112 150 mVrms
AM Rejection Ratio (Vin = 3.16 mVrms, 30% AM,
@ 1.0 kHz) 1 Mix1
In1 or In2Det Out AMR 30 48 – dB
Signal to Noise Ratio (Vin = 3.16 mVrms,
No Modulation) – Mix1
In1 or In2Det Out SNR – 48 – dB
FIRST MIXER (No Modulation, fin = USA Ch21, 46.77 MHz, 50 Ω Termination at Inputs)
Input Impedance
Single–Ended 16 –Mix1
In1 or In2RPS1
CPS1 –
–1.6
3.7 –
–
kΩ
pF
Differential 16 Mix1
In1/In2RPD1
CPD1 –
–1.6
1.8 –
–
Output Impedance 14 – Mix1 Out RP1 Out
CP1 Out –
–300
3.7 –
–Ω
pF
Voltage Conversion Gain
(Vin = 1.0 mVrms, with CF1 Filter as Load) 17, 18 Mix1
In1 or In2Mix1 Out MXgain1 –12 – dB
1.0 dB Voltage Compression Level (Input Referred)
IP3 Bit Set to 0 19, 21 Mix1
In1 or In2Mix1 Out VO Mix1
1 dB –
–20
–21 –
–
mVrms
dBm
IP3 Bit Set to 1 20, 21 –
–56
–12 –
–
Third Order Intercept (Input Referred) [Note 5]
IP3 Bit Set to 0 19, 21 Mix1
In1 or In2Mix1 Out TOImix1 –
–64
–11 –
–
mVrms
dBm
IP3 Bit Set to 1 20, 21 –
–178
–2.0 –
–
–3.0 dB IF Bandwidth 22 Mix1 In1
or In2Mix1 Out Mix1 BW – 13 – MHz
NOTE: 5.Third order intercept calculated for input levels 10 dB below 1.0 dB compression point.
MC13110A/B MC13111A/B
5
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic UnitMaxTypMinSymbol
Measure
Pin
Input
Pin
Figure
SECOND MIXER (No Modulation, fin = 10.7 MHz, 50 Ω Termination at Inputs)
Input Impedance 24 Mix2 In Mix2 In RP2 In
CP2 In –
–2.8
3.6 –
–kΩ
pF
Output Impedance 24 – Mix2 Out RP2 Out
CP2 Out –
–1.5
6.1 –
–kΩ
pF
Voltage Conversion Gain
(Vin = 1.0 mVrms, with CF2 Filter as Load) 26, 27 Mix2 In Mix2 Out MXgain2 –20 – dB
1.0 dB Voltage Compression Level (Input Referred)
IP3 Bit Set 0 28, 30 Mix2 In Mix2 Out VO
Mix2
1 dB –
–32
–17 –
–
mVrms
dBm
IP3 Bit Set 1 29, 30 –
–45
–14 –
–
Third Order Intercept (Input Referred) [Note 6]
IP3 Bit Set 0 28, 30 Mix2 In Mix2 Out TOImix2 –
–136
–4.3 –
–
mVrms
dBm
IP3 Bit Set 1 29, 30 –
–158
–3.0 –
–
–3.0 dB IF Bandwidth 31 Mix2 In Mix2 Out Mix2 BW – 2.5 – MHz
LIMITER/DEMODULATOR (fin = 455 kHz, fdev = ±3.0 kHz, fmod = 1.0 kHz)
Input Impedance 49 Lim In Lim In RPLim
CPLim –
–1.5
16 –
–kΩ
pF
Detector Output Impedance – – Det Out RO– 1.1 – kΩ
IF –3.0 dB Limiting Sensitivity 1 Lim In Det Out IF Sens – 71 100 µVrms
Demodulator Bandwidth – Lim In Det Out BW – 20 – kHz
RSSI/CARRIER DETECT (No Modulation)
RSSI Output Dynamic Range 56 Mix1 In RSSI RSSI – 80 – dB
DC Voltage Range 56 Mix1 In RSSI DC RSSI – 0.2 to
1.5 – Vdc
Carrier Detect Threshold
CD Threshold Adjust = (10100)
(Threshold Relative to Mix1 In Level)
57 Mix1 In CD Out VT– 15 – µVrms
Hysteresis, CD = (10100)
(Threshold Relative to Mix1 In Level) 57 Mix1 In CD Out Hys – 2.0 – dB
Output High Voltage
CD = (00000), RSSI = 0.2 V 1 RSSI CD Out VOH VCC –
0.1 3.6 – V
Output Low Voltage
CD = (11111), RSSI = 0.9 V 1 RSSI CD Out VOL –0.02 0.4 V
Carrier Detect Threshold Adjustment Range
(Programmable through MPU Interface) 126 – – VT
Range ––20 to
11 –dB
Carrier Detect Threshold – Number of
Programmable Levels 126 – – VTn –32 – –
NOTE: 6.Third order intercept calculated for input levels 10 dB below 1.0 dB compression point.
MC13110A/B MC13111A/B
6MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic UnitMaxTypMinSymbol
Measure
Pin
Input
Pin
Figure
Rx AUDIO PATH (fin = 1.0 kHz, Active Mode, scrambler bypassed)
Absolute Gain (Vin = –20 dBV) 1, 72 Rx Audio In SA Out G –4.0 0 4.0 dB
Gain T racking
(Referenced to E Out for Vin = –20 dBV) 1, 76 E In E Out GtdB
Vin = –30 dBV –21 –20 –19
Vin = –40 dBV –42 –40 –38
Total Harmonic Distortion (Vin = –20 dBV) 1, 76 Rx Audio In SA Out THD – 0.7 1.0 %
Maximum Input Voltage (VCC = 2.7 V) 76 R x Audio In – – – –11.5 – dBV
Maximum Output Voltage (Increase input voltage
until output voltage THD = 5.0%, then measure
output voltage)
1E In E Out VOmax –2.0 0 – dBV
Input Impedance – Rx Audio In – Zin –600 – kΩ
E In – 7.5 –
Attack T ime
Ecap = 0.5 µF, Rfilt = 40 k (See Appendix B) – E In E Out ta– 3.0 – ms
Release T ime
Ecap = 0.5 µF, Rfilt = 40 k (See Appendix B) – E In E Out tr– 13.5 – ms
Compressor to Expander Crosstalk
Vin = –10 dBV, V(E In) = AC Gnd 1C In E Out CT– –90 –70 dB
Rx Muting (∆ Gain)
Vin = –20 dBV, Rx Gain Adj = (01111) 1 Rx Audio In E Out Me– –84 –60 dB
Rx High Frequency Corner
Rx Path, V Rx Audio In = –20 dBV 1 Rx Audio In Scr Out Rx fch 3.779 3.879 3.979 kHz
Low Pass Filter Passband Ripple (Vin = –20 dBV) 1, 73 Rx Audio In Scr Out Ripple – 0.4 0.6 dB
Rx Gain Adjust Range (Programmable through
MPU Interface) 125 Rx Audio In Scr Out Rx
Range ––9.0 to
10 – dB
Rx Gain Adjust Steps – Number of
Programmable Levels 125 Rx Audio In Scr Out Rx n – 20 – dB
Audio Path Noise, C–Message Weighting
(Input AC–Grounded) 70 Rx Audio In Scr Out
E Out
SA Out
EN –
––85
<–95
<–95
–
–dBV
Volume Control Adjust Range 123 E In E Out Vcn
Range ––14 to
16 – dB
Volume Control – Number of Programmable
Levels 123 E In E Out Vcn –16 – –
SPEAKER AMP/SP MUTE (Active Mode)
Maximum Output Swing
RL = No Load, Vin = 3.4 Vpp
RL = 130 Ω, Vin = 2.8 Vpp
RL = 620 Ω, Vin = 4.0 Vpp
1, 79 SA In SA Out VOmax 2.8
2.0
–
3.2
2.6
3.4
–
–
–
Vpp
Speaker Amp Muting
Vin = –20 dBV, RL = 130 Ω1SA In SA Out Msp ––92 –60 dB
MC13110A/B MC13111A/B
7
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic UnitMaxTypMinSymbol
Measure
Pin
Input
Pin
Figure
DATA AMP COMPARATOR
Hysteresis 1 DA In DA Out Hys 30 42 50 mV
Threshold Voltage – DA In DA Out VT– VCC –
0.7 – V
Input Impedance 1 – DA In ZI200 250 280 kΩ
Output Impedance – – DA Out ZO– 100 – kΩ
Output High Voltage
Vin = VCC – 1.0 V, IOH = 0 mA 1DA In DA Out VOH VCC –
0.1 3.6 – V
Output Low Voltage
Vin = VCC – 0.4 V, IOL = 0 mA 1DA In DA Out VOL –0.1 0.4 V
Maximum Frequency – DA In DA Out Fmax –10 – kHz
MIC AMP (fin = 1.0 kHz, External resistors set to gain of 1, Active Mode)
Open Loop Gain – Tx In Amp Out AVOL – 100,000 – V/V
Gain Bandwidth – Tx In Amp Out GBW – 100 – kHz
Maximum Output Swing (RL = 10 kΩ) – Tx In Amp Out VOmax –3.2 – Vpp
Tx AUDIO PATH (fin = 1.0 kHz, Tx Gain Adj = (01111); ALC, Limiter, and Mutes Disabled; Active Mode, scrambler bypassed)
Absolute Gain (Vin = –10 dBV) 1, 83 Tx In Tx Out G –4.0 0 4.0 dB
Gain T racking
(Referenced to Tx Out for Vin = –10 dBV)
Vin = –30 dBV
Vin = –40 dBV
1, 87 Tx In Tx Out Gt
–11
–17 –10
–15 –9.0
–13
dB
Total Harmonic Distortion (Vin = –10 dBV) 1, 87 Tx In Tx Out THD – 0.8 1.8 %
Maximum Output Voltage (Increase input voltage
until output voltage THD = 5.0%, then measure
output voltage. Tx Gain Adjust = 8 dB)
1 Tx In Tx Out VOmax –2.0 0 – dBV
Input Impedance – – C In Zin –10 – kΩ
Attack T ime (Ccap = 0.5 µF, Rfilt = 40 k (See
Appendix B)) –C In Tx Out ta–3.0 – ms
Release T ime (Ccap = 0.5 µF, Rfilt = 40 k (See
Appendix B)) –C In Tx Out tr–13.5 – ms
Expander to Compressor Crosstalk (Vin = –20 dBV,
Speaker Amp No Load, V(C In) = AC Gnd) 1E In Tx Out CT––60 –40 dB
Tx Muting (Vin – 10 dBV) 1 Tx In Tx Out Mc––88 –60 dB
ALC Output Level (ALC enabled)
Vin = –10 dBV
Vin = –2.5 dBV
1, 87,
90 Tx In Tx Out ALCout –15
–13 –13
–11 –8.0
–6.0
dBV
ALC Slope (ALC enabled) 1 Tx In Tx Out Slope 0.1 0.25 0.4 dB/dB
Vin = –10 dBv
Vin = –2.5 dBv
ALC Input Dynamic Range – C In Tx Out DR – –16 to
–2.5 – dBV
Limiter Output Level (Vin = –2.5 dBV,
Limiter enabled) 1 Tx In Tx Out Vlim –10 –8.0 – dBV
Tx High Frequency Corner [Note 7]
(VTx In = –10 dBV, Mic Amp = Unity Gain) 1 Tx In Tx Out Tx fc3.6 3.7 3.8 kHz
NOTE: 7.The filter specification is based on a 10.24 MHz 2nd LO, and a switched–capacitor (SC) filter counter divider ratio of 31. If other 2nd LO frequencies
and/or SC filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting SC filter clock frequency.
MC13110A/B MC13111A/B
8MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic UnitMaxTypMinSymbol
Measure
Pin
Input
Pin
Figure
Tx AUDIO PATH (fin = 1.0 kHz, Tx Gain Adj = (01111); ALC, Limiter, and Mutes Disabled; Active Mode, scrambler bypassed)
Low Pass Filter Passband Ripple (Vin = –10 dBV) 1, 84 Tx In Tx Out Ripple – 0.7 1.2 dB
Maximum Compressor Gain (Vin = –70 dBV) – C In Tx Out AVmax –23 – dB
Tx Gain Adjust Range (Programmable through
MPU Interface) 125 C In Tx Out Tx Range – –9.0 to
10 – dB
Tx Gain Adjust Steps – Number of Programmable
Levels 125 C In Tx Out Tx n – 20 – –
Rx AND Tx SCRAMBLER (2nd LO = 10.24 MHz, Tx Gain Adj = (01111), Rx Gain Adj = (01111), Volume Control = (0 dB Default Levels),
SCF Clock Divider = 31. Total is divide by 62 for SCF clock frequency of 165.16 kHz)
Rx High Frequency Corner (Note 8)
Rx Path, f = 479 Hz, V Rx Audio In = –20 dBV – Rx Audio In Scr Out Rx fch 3.55 3.65 3.75 kHz
Tx High Frequency Corner (Note 8)
Tx Path, f = 300 Hz, V Tx In = –10 dBV,
Mic Amp = Unity Gain
– Tx In Tx Out Tx fch 3.829 3.879 3.929 kHz
Absolute Gain
Rx: Vin = –20 dBV
Tx: Vin = –10 dBV, Limiter disabled –
–Rx Audio In
Tx In E Out
Tx Out
AV –4.0
–4.0 0.4
–1.0 4.0
4.0
dB
Pass Band Ripple
Rx + Tx Path – 1.0 µF from Tx Out to
Rx Audio In, fin = low corner frequency to
high corner frequency
–C In E Out Ripple – 1.9 2.5 dB
Scrambler Modulation Frequency
Rx: 100 mV (–20 dBV)
Tx: 316 mV (–10 dBV) –
–Rx Audio In
C In E Out
Tx Out
fmod 4.119 4.129 4.139 kHz
Group Delay
Rx + Tx Path – 1.0 µF from Tx Out to
Rx Audio In, fin = 1.0 kHz –C In E Out GD – 1.0 – ms
xin
fin = low corner frequency to high corner
frequency –C In E Out GD – 4.0 –
Carrier Breakthrough
Rx + Tx Path – 1.0 µF from Tx Out to
Rx Audio In
–C In E Out CBT – –60 – dB
Baseband Breakthrough
Rx + Tx Path – 1.0 µF from Tx Out to
Rx Audio In,
fin = 1.0 kHz, fmeas = 3.192 kHz
– C In E Out BBT – –50 – dB
LOW BATTERY DETECT
Average Threshold
Voltage Before Electronic Adjustment
(Vref_Adj = (0111))
1, 131 Ref1
Ref2BD1 Out
BD2 Out VTi1.38 1.48 1.58 V
Average Threshold
Voltage After Electronic Adjustment
(Vref_Adj = (adjusted value))
1 Ref1
Ref2BD1 Out
BD2 Out VTf1.475 1.5 1.525 V
Hysteresis – Ref1
Ref2BD1 Out
BD2 Out Hys – 4.0 – mV
Input Current (Vin = 1.0 and 2.0 V) 1 – Ref1
Ref2Iin –50 – 50 nA
Output High Voltage (Vin = 2.0 V) 1 Ref1
Ref2BD1 Out
BD2 Out VOH VCC –
0.1 3.6 – V
NOTE: 8.The filter specification is based on a 10.24 MHz 2nd LO, and a switch–capacitor (SC) filter counter divider ratio of 31. If other 2nd LO frequencies
and/or SC filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting SC filter clock frequency.
MC13110A/B MC13111A/B
9
MOTOROLA RF/IF DEVICE DATA
ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.6 V, VB = 1.5 V, TA = 25°C, Active or Rx Mode, unless otherwise specified;
Test Circuit Figure 1.)
Characteristic UnitMaxTypMinSymbol
Measure
Pin
Input
Pin
Figure
LOW BATTERY DETECT
Output Low Voltage (Vin = 1.0 V) 1 Ref1
Ref2BD1 Out
BD2 Out VOL –0.2 0.4 V
BATTERY DETECT INTERNAL THRESHOLD
After Electronic Adjustment of VB Voltage 1, 128 VCC Audio BD2 Out V
BD Select = (111) IBS73.381 3.455 3.529
BD Select = (110) IBS63.298 3.370 3.442
BD Select = (101) IBS53.217 3.287 3.357
BD Select = (100) IBS43.134 3.202 3.270
BD Select = (011) IBS32.970 3.034 3.098
BD Select = (010) IBS22.886 2.948 3.010
BD Select = (001) IBS12.802 2.862 2.922
PLL PHASE DETECTOR
Output Source Current
(VPD = Gnd + 0.5 V to PLL V ref – 0.5 V) – – Rx PD
Tx PD IOH –1.0 – mA
Output Sink Current
(VPD = Gnd + 0.5 V to PLL V ref – 0.5 V) – – Rx PD
Tx PD IOL –1.0 – mA
PLL LOOP CHARACTERISTICS
Maximum 2nd LO Frequency
(No Crystal) – LO2 In – f2ext –12 – MHz
Maximum 2nd LO Frequency
(With Crystal) – – LO2 In
LO2 Out f2ext –12 – MHz
Maximum Tx VCO (Input Frequency),
Vin = 200 mVpp – – Tx VCO ftxmax –80 – MHz
PLL VOLTAGE REGULATOR
Regulated Output Level (IL = 0 mA, after Vref
Adjustment) 1 – PLL V ref VO2.4 2.5 2.6 V
Line Regulation (IL = 0 mA, VCC = 3.0 to 5.5 V) 1 VCC Audio PLL Vref VReg Line – 11.8 40 mV
Load Regulation (IL = 1.0 mA) 1 VCC Audio PLL V ref VReg
Load –20 –1.4 – mV
MICROPROCESSOR SERIAL INTERFACE
Input Current Low (Vin = 0.3 V, Standby Mode) 1 – Data,
Clk, EN IIL –5.0 0.4 – µA
Input Current High (Vin = 3.3 V, Standby Mode) 1 – Data,
Clk, EN IIH –1.6 5.0 µA
Hysteresis Voltage – – Data,
Clk, EN Vhys –1.0 – V
Maximum Clock Frequency – Data,
EN, Clk – – – 2.0 – MHz
Input Capacitance – Data,
Clk, EN – Cin –8.0 – pF
EN to Clk Setup T ime 106 – EN, Clk tsuEC –200 – ns
Data to Clk Setup T ime 105 – Data, Clk tsuDC –100 – ns
Hold T ime 105 – Data, Clk th– 90 – ns
Recovery Time 106 – EN, Clk trec –90 – ns
Input Pulse Width – – EN, Clk tw– 100 – ns
MPU Interface Power–Up Delay (90% of PLL V ref
to Data,Clk, EN) 108 – – tpuMPU –100 – µs
MC13110A/B MC13111A/B
10 MOTOROLA RF/IF DEVICE DATA
Figure 1. Production Test Circuit (52 Pin QFP)
4700 32.4 k
0.1 3.01 k
0.047
1.5 k22.1 k 10.240 MHz
5.0 – 50 8.2 0.1
1.0 Fµ
0.1
10 Fµ0.1
TxVCO
52
51
50
49
48
47
46
45
44
43
42
41
40
14
15
16
17
18
19
20
21
22
23
24
25
26
27282930313233343536373839
13121110987543216
V
CCA
0.1
0.1
7.5 k
49.9 k
33
RF In 0.01
49.9 0.01
CF1
10.7 MHz CF2
455 kHz
332
VCC
0.1
0.1 0.1
10 L2
22.1 k
MPU Clock Output
0.01
RxLoop Filter
10 Fµ
0.1
0.1
L3
1.0 k
1.0 k
Vref2
Vref1
110
10 Fµ
1.0 Fµ
49.9 k
NOTE: This schematic is only a partial representation of the actual production test circuit.
100 k
100 k VCC
TxOut
Data Out
BD1Out
BD2Out
VCC
Carrier
Detect Out
VCCA
DA In
0.1
0.1
49.9 k
0.1
10 Fµ0.1
VCCAudio
0.01 1000
0.1
49.9 k
15 k
100 k
0.1
7.5 k
1.0µF
To VCC
R
Mix
Det Out
TxIn
Scr Out
E In
E Out
SA In
SA Out
RSSI
Det Out
R
V
DA In
T
Amp Out
C In
C Cap
T
BD
DA Out
BD
LO
LO
V Cap Ctrl
Gnd Audio
SA Out
SA In
E Out
E Cap
E In
Scr Out
Ref
Ref
V
1
In
1Out
2
1
B
xAudio In
CC Audio
xIn
xOut
2Out
1Out
T
SGnd RF
Lim In
Lim Out
LO
LO
V
T
Gnd PLL
Data
EN
Clk
Clk Out
CD
2In
2Out
Gnd RF
Q
ag
Out
PLL V
Mix
Mix
Mix
Mix
Lim C
Coil
xPD
ref
xPD
xVCO
1
1In2
1Out
2Out
2In
Lim C
V
1
2
CCRF
In1
RxAudio In
Mic Amp Out
Legend:
If 1, then capacitor value = pF
If <1, then capacitor value = F
µ
≥
MC13111A/B
IC
0.1 C In
MC13110A/B
MC13110A/B MC13111A/B
11
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Pin
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
LQFP–48
ÁÁÁÁ
ÁÁÁÁ
QFP–52
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
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48
1
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1
2
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LO2 In
LO2 Out
LO2
Out
2
LO2
In
1
PLL
Vref
PLL
Vref
100
100
PLL
Vref
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ÁÁÁÁÁÁÁÁÁÁÁ
Á
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These pins form the PLL reference oscillator when
connected to an external parallel–resonant crystal
(10.24 MHz typical). The reference oscillator is
also the second Local Oscillator (LO2) for the RF
receiver. “LO2 In” may also serve as an input for
an externally generated reference signal which is
typically ac–coupled.
When the IC is set to the inactive mode, LO2 In is
internally pulled low to disable the oscillator. The
input capacitance to ground at each pin (LO2 In/
LO2 Out) is 3.0 pF.
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2
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3
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Vag
Vag
3
PLL
Vref
VCC
Audio
30 k
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Vag is the internal reference voltage for the
switched capacitor filter section. This pin must be
decoupled with a 0.1 µF capacitor.
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3
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4
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Rx PD
(Output)
46
PLL
Vref
PLL
Vref
15
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Á
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Á
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This pin is a tri–state voltage output of the Rx and
Tx Phase Detector. It is either “high”, “low”, or “high
impedance,” depending on the phase difference of
the phase detector input signals. During lock, very
narrow pulses with a fre
q
uenc
y
e
q
ual to the
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5
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6
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Tx PD
(Output) Rx PD,
Tx PD
4
,
6
15
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Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
narrow
ulses
with
a
frequency
equal
to
the
reference frequency are present. This pin drives
the external Rx and Tx PLL loop filters. Rx and Tx
PD outputs can sink or source 1.0 mA.
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4
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5
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PLL V ref
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PLL V ref
5
132 k
VCC
Audio
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PLL Vref is a PLL voltage regulator output pin. An
internal voltage regulator provides a stable power
supply voltage for the Rx and Tx PLL’s and can
also be used as a regulated supply voltage for
other IC’s. It can source up to 1.0 mA externally.
Proper supply filtering is a must on this pin. PLL
Vref is pulled up to VCC audio for the standby and
inactive modes (Note 1).
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6
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7
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ÁÁÁÁÁ
Gnd PLL
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground pin for digital PLL section of IC.
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7
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8
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Tx VCO
(Input)
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Á
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TX VCO
8
PLL
Vref
1.0 k
PLL
Vref
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Tx VCO is the transmit divide counter input which
is driven by an ac–coupled external transmit loop
VCO. The minimum signal level is 200 mVpp @
60.0 MHz. This pin also functions as the test mode
input for the counter tests.
MC13110A/B MC13111A/B
12 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Pin
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁ
ÁÁÁÁ
QFP–52
ÁÁÁÁ
ÁÁÁÁ
LQFP–48
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8
9
10
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9
10
11
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Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Data
EN
Clk
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Data, EN, Clk
9, 10, 11
VCC
Audio
240
PLL
Vref
1.0 µA
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Microprocessor serial interface input pins are for
programming various counters and control
functions. The switching thresholds are referenced
to PLL V ref and Gnd PLL. The inputs operate up to
VCC. These pins have 1.0 µA internal pull–down
currents.
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ÁÁ
Á
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ÁÁ
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Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
11
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
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ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
12
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Clk Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Clk Out
12
VCC
Audio
VCC
Audio
1.0 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
The microprocessor clock output is derived from
the 2nd LO crystal oscillator and a programmable
divider with divide ratios of 2 to 312.5. It can be
used to drive a microprocessor and thereby
reduce the number of crystals required in the
system design. The driver has an internal resistor
in series with the output which can be combined
with an external capacitor to form a low pass filter
to reduce radiated noise on the PCB. This output
also functions as the output for the counter test
modes.
1) For the MC13110A/B and MC13111A/B the Clk
Out can be disabled via the MPU interface.
2) For the MC13110B and MC13111B this output is
always active (on) (Note 2).
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
12
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
13
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD Out
(I/O)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
CD
Comparator
CD Out
13
VCC
Audio
240
PLL
Vref
Hardware
Interrupt
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Dual function pin;
1) Carrier detect output (open collector with
external 100 kΩ pull–up resistor.
2) Hardware interrupt input which can be used to
“wake–up” from the Inactive Mode.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
–
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
14
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BD1 Out
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
14 16
VCC
Audio
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Low battery detect output #1 is an open collector
with external pull–up resistor.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
14
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
16
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
BD2 Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
BD1 Out
BD2 Out
14
,
16
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Low battery detect output #2 is an open collector
with external pull–up resistor.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
13
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
15
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
DA Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
DA Out
15
VCC
Audio
VCC
Audio
100 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Data amplifier output (open collector with internal
100 kΩ pull–up resistor).
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
15
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
17
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Tx Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Tx Out
17
VCC
Audio
VB
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx Out is the Tx path audio output. Internally this
pin has a low–pass filter circuitry with –3 dB
bandwidth of 4.0 kHz. Tx gain and mute are
programmable through the MPU interface. This pin
is sensitive to load capacitance.
MC13110A/B MC13111A/B
13
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Pin
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁ
ÁÁÁÁ
QFP–52
ÁÁÁÁ
ÁÁÁÁ
LQFP–48
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
16
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
18
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
C Cap
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
C Cap
18
VCC
Audio VCC
Audio
40 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
C Cap is the compressor rectifier filter capacitor
pin. It is recommended that an external filter
capacitor to VCC audio be used. A practical
capacitor range is 0.1 to 1.0 µF. 0.47 µF is the
recommended value.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
17
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
19
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
C In
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
C In
19
VCC
Audio
12.5 k
VB
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
C In is the compressor input. This pin is internally
biased and has an input impedance of 12.5 k. C In
must be ac–coupled.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
18
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
20
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Amp Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
VCC
Audio
21
VCC
Audio
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Microphone amplifier output. The gain is set with
external resistors. The feedback resistor should be
less than 200 kΩ.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
19
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
21
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Tx In
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Amp Out
20
VB
Tx In
21
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx In is the Tx path input to the microphone
amplifier (Mic Amp). An external resistor is
connected to this pin to set the Mic Amp gain and
input impedance. Tx In must be ac–coupled, too.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
20
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
22
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
DA In
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
DA In
22
VCC
Audio
250 k 250 k
VCC
Audio
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
The data amplifier input (DA In) resistance is
250 kΩ and must be ac–coupled. Hysteresis is
internally provided.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
21
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
23
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
VCC Audio
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
VCC audio is the supply for the audio section. It is
necessary to adequately filter this pin.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
22
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
24
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Rx Audio In
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Rx Audio In
24
VCC
Audio
600 k
VB
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
The Rx audio input resistance is 600 kΩ and must
be ac–coupled.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
23
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
25
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Det Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Det Out
25
VCC
Audio
VCC
RF
240
30 µA
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Det Out is the audio output from the FM detector.
This pin is dc–coupled from the FM detector and
has an output impedance of 1100 Ω.
MC13110A/B MC13111A/B
14 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Pin
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁ
ÁÁÁÁ
QFP–52
ÁÁÁÁ
ÁÁÁÁ
LQFP–48
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
30
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
26
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
RSSI
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
VCC
Audio
186 k
26
VCC
RF
VCC
RF
RSSI
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
RSSI is the receive signal strength indicator. This
pin must be filtered through a capacitor to ground.
The capacitance value range should be 0.01 to
0.1 µF. This is also the input to the Carrier Detect
comparator. An external R to ground shifts the
RSSI voltage.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
24
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
27
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Q Coil
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Q Coil
27
VCC
RF VCC
RF
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
A quad coil or ceramic discriminator connects this
pin as part of the FM demodulator circuit.
DC–couple this pin to VCC RF through the quad
coil or the external resistor.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
26
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
29
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
VCC RF
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
VCC supply for RF receiver section (1st LO, mixer,
limiter, demodulator). Proper supply filtering is
needed on this pin too.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
25
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
28
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Lim Out
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Lim C
1
31
VCC
RF
28
VCC
RF
VCC
RF VCC
RF
53.5 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
A quad coil or ceramic discriminator are connected
to these pins as part of the FM demodulator circuit.
A coupling capacitor connects this pin to the quad
coil or ceramic discriminator as part of the FM
demodulator circuit. This pin can drive coupling
capacitors up to 47 pF with no deterioration in
performance.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
27
28
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
30
31
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Lim C2
Lim C1
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
i1
Lim Out
Lim In
32
L
i
m C
2
30
52
k
1.5 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
IF amplifier/limiter capacitor pins. These
decoupling capacitors should be 0.1 µF. They
determine the IF limiter gain and low frequency
bandwidth.
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
29
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
32
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Lim In
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
L
i
m C
252
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Signal input for IF amplifier/limiter. Signals should
be ac–coupled to this pin. The input impedance is
1.5 kΩ at 455 kHz.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
–
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
33
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SGnd RF
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
This pin is not connected internally but should be
grounded to reduce potential coupling between
pins.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
31
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
34
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Mix2 In
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Mix2 In
34
VCC
RF
VCC
RF
3.0 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mix2 In is the second mixer input. Signals are to be
ac–coupled to this pin, which is biased internally to
VCC RF. The input impedance is
2.8 kΩ at 455 kHz. The input impedance can be
reduced by connecting an external resistor to
VCC RF.
MC13110A/B MC13111A/B
15
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Pin
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁ
ÁÁÁÁ
QFP–52
ÁÁÁÁ
ÁÁÁÁ
LQFP–48
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
32
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
35
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Mix2 Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Mix2 Out
35
VCC
RF
VCC
RF
1.2 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Mix2 Out is the second mixer output. The second
mixer has a 3 dB bandwidth of 2.5 MHz and an
output impedance of 1.5 kΩ. The output current
drive is 50 µA.
ÁÁÁÁ
ÁÁÁÁ
33
ÁÁÁÁ
ÁÁÁÁ
36
ÁÁÁÁÁ
ÁÁÁÁÁ
Gnd RF
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground pin for RF section of the IC.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
34
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
37
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Mix1 Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Mix1 Out
37
VCC
RF
VCC
RF
200
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
The first mixer has a 3 dB IF bandwidth of 13 MHz
and an output impedance of 300 Ω. The output
current drive is 300 µA and can be programmed
for 1.0 mA.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
35
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
38
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Mix1 In2
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
VCC
RF VCC
RF
950 950
Vref
20 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Signals should be ac–coupled to this pin, which is
biased internally to VCC – 1.6 V. The single–ended
and differential input impedance are about 1.6 and
1.8 kΩ at 46 MHz, respectively.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
36
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
39
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Mix1 In1
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Mix1 In2,
Mix1 In1
38, 39
95 95
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
37
38
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
40
41
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
LO1 In
LO1 Out
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
LO1
Out
41
LO1
In
40
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tank Elements, an internal varactor and capacitor
matrix for 1st LO multivibrator oscillator are
connected to these pins. The oscillator is useable
up to 80 MHz.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
39
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
42
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Vcap Ctrl
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Vcap
Ctrl
42
VCC
RF
55 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Vcap Ctrl is the 1st LO varactor control pin. The
voltage at this pin is referenced to Gnd Audio and
varies the capacitance between LO1 In and
LO2 Out. An increase in voltage will decrease
capacitance.
ÁÁÁÁ
ÁÁÁÁ
40
ÁÁÁÁ
ÁÁÁÁ
43
ÁÁÁÁÁ
ÁÁÁÁÁ
Gnd Audio
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ground for audio section of the IC.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
41
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
44
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SA Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
44
VCC
Audio
SA n
45
VCC
Audio
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
The speaker amplifier gain is set with an external
feedback resistor. It should be less than 200 kΩ.
The speaker amplifier can be muted through the
MPU interface.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
42
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
45
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SA In
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
SA Out
44
VB
SA
I
n
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
An external resistor is connected to the speaker
amplifier input (SA In). This will set the gain and
input impedance and must be ac–coupled.
MC13110A/B MC13111A/B
16 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Pin
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Equivalent Internal Circuit (52 Pin QFP)
ÁÁÁÁÁ
ÁÁÁÁÁ
Symbol/
Type
ÁÁÁÁ
ÁÁÁÁ
QFP–52
ÁÁÁÁ
ÁÁÁÁ
LQFP–48
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
43
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
46
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
E Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
E Out
46
VCC
Audio
VB
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
The output level of the expander output is
determined by the volume control. Volume control
is programmable through the MPU interface.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
44
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
47
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
E Cap
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
E Cap
47
VCC
Audio
VCC
Audio
40 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
E Cap is the expander rectifier filter capacitor pin.
Connect an external filter capacitor between VCC
audio and E Cap. The recommended capacitance
range is 0.1 to 1.0 µF. 0.47 µF is the suggested
value.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
45
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
48
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
E In
(Input)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
E In
48
VCC
Audio
VB
30 k
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
The expander input pin is internally biased and has
input impedance of 30 kΩ.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
46
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
49
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Scr Out
(Output)
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Scr Out
49
VCC
Audio
VB
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Scr Out is the Rx audio output. An internal low
pass filter has a –3 dB bandwidth of 4.0 kHz.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
–
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
50
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Ref2
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
50, 51
V
CC
Audio
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reference voltage input for Low Battery Detect #2.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
–
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
51
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Ref1
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Ref2, Ref1
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Reference voltage input for Low Battery Detect #1.
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
47
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
52
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
VB
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
VB
52
VCC
Audio
VCC
Audio
240
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
VB is the internal half supply analog ground
reference. This pin must be filtered with a
capacitor to ground. A typical capacitor range of
0.5 to 10 µF is desired to reduce crosstalk and
noise. It is important to keep this capacitor value
equal to the PLL V ref capacitor due to logic timing
(Note 9).
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTE: 9.A capacitor range of 0.5 to 10 µF is recommended. The capacitor value should be the same used on the VB pin (Pin 52). An additional high
quality parallel capacitor of 0.01 µF is essential to filter out spikes originating from the PLL logic circuitry.
MC13110A/B MC13111A/B
17
MOTOROLA RF/IF DEVICE DATA
DEVICE DESCRIPTION AND APPLICATION INFORMATION
The following text, graphics, tables and schematics are
provided to the user as a source of valuable technical
information about the Universal Cordless Telephone IC. This
information originates from thorough evaluation of the device
performance for the US and French applications. This data
was obtained by using units from typical wafer lots. It is
important to note that the forgoing data and information was
from a limited number of units. By no means is the user to
assume that the data following is a guaranteed parametric.
Only the minimum and maximum limits identified in the
electrical characteristics tables found earlier in this spec are
guaranteed.
General Circuit Description
The MC13110A/B and MC13111A/B are a low power dual
conversion narrowband FM receiver designed for
applications up to 80 MHz carrier frequency. This device is
primarily designated to be used for the 49 MHz cordless
phone (CT–0), but has other applications such as low data
rate narrowband data links and as a backend device for 900
MHz systems where baseband analog processing is
required. This device contains a first and second mixer,
limiter, demodulator, extended range receive signal strength
(RSSI), receive and transmit baseband processing, dual
programmable PLL, low battery detect, and serial interface
for microprocessor control. The FM receiver can also be
used with either a quadrature coil or ceramic resonator.
Refer to the Pin Function Description table for the simplified
internal circuit schematic and description of this device.
DC Current and Battery Detect
Figures 3 through 6 are the current consumption for
Inactive, Standby, Receive, and Active modes versus supply
voltages. Figures 7 and 8 show the typical behavior of current
consumption in relation to temperature. The relationship of
additional current draw due to IP3 bit set to <1> and supply
voltage are shown in Figures 9 and 10.
For the Low Battery Detect, the user has the option to
operate the IC in the programmable or non–programmable
modes. Note that the 48 pin package can only be used in the
programmable mode. Figure 128 describes this operation
(refer to the Serial Interface section under Clock Divider
Register).
In the programmable mode several different internal
threshold levels are available (Figure 2). The bits are set
through the SCF Clock Divider Register as shown in Figures
108 and 126. The reference for the internal divider network is
VCC Audio. The voltages on the internal divider network are
compared to the Internal Reference Voltage, VB, generated
by an internal source. Since the internal comparator used is
non–inverting, a high at VCC Audio will yield a high at the
battery detect output, and vice versa for VCC Audio set to a
low level. For the 52 pin package option, the Ref 1 and Ref 2
pins need to be tied to VCC when used in the programmable
mode. It is essential to keep the external reference pins
above Gnd to prevent any possible power–on reset to be
activated.
When considering the non–programmable mode (bits set
to <000>) for the 52 pin package, the Ref 1 and Ref 2 pins
become the comparators reference. An internal switch is
activated when the non–programmable mode is chosen
connecting Ref 1 and Ref 2. Here, two external precision
resistor dividers are used to set independent thresholds for
two battery detect hysteresis comparators. The voltages on
Ref 1 and Ref 2 are again compared to the internally
generated 1.5 V reference voltage (VB).
The Low Battery Detect threshold tolerance can be
improved by adjusting a trim–pot in the external resistor
divider (user designed). The initial tolerance of the internal
reference voltage (VB) is ±6.0%. Alternately, the tolerance of
the internal reference voltage can be improved to ±1.5%
through MPU serial interface programming (refer to the Serial
Interface section, Figure 131). The internal reference can be
measured directly at the “VB” pin. During final test of the
telephone, the VB internal reference voltage is measured.
Then, the internal reference voltage value is adjusted
electronically through the MPU serial interface to achieve the
desired accuracy level. The voltage reference register value
should be stored in ROM during final test so that it can be
reloaded each time the combo IC is powered up. The Low
Battery Detect outputs are open collector. The battery detect
levels will depend on the accuracy of the VB voltage. Figure
12 indicates that the VB voltage is fairly flat over temperature.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 2. Internal Low Battery Detect Levels
(with VB = 1.5 V)
Battery
Detect
Select
Ramping
Up
(V)
Ramping
Down
(V)
Average
(V) Hysteresis
(mV)
0 – – – –
1 2.867 2.861 2.864 4.0
2 2.953 2.947 2.950 6.0
3 3.039 3.031 3.035 8.0
4 3.207 3.199 3.204 8.0
5 3.291 3.285 3.288 6.0
6 3.375 3.367 3.371 8.0
7 3.461 3.453 3.457 8.0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTE: 10. Battery Detect Select 0 is the non–programmable operating
mode.
MC13110A/B MC13111A/B
18 MOTOROLA RF/IF DEVICE DATA
Figure 3. Current versus Supply
Voltage Inactive Mode
0
5.0
10
15
20
25
30
35
40
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC, SUPPLY VOLTAGE (V)
Figure 4. Current versus Supply
Voltage Standby Mode, MCU
Clock Output – On at 2.048 MHz
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
MCU Clock Out Off
MCU Clock Out On
IINACT IC, SUPPLY CURRENT ( µA)
STD ICC, SUPPLY CURRENT (mA)
0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VCC, SUPPLY VOLT AGE (V)
DC CURRENT
Figure 5. Current versus Supply
Voltage Receive Mode
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
MCU Clock Out Off
MCU Clock Out On
VCC, SUPPLY VOLT AGE (V)
R
CC,
SU
PPLY C
URRENT
(m
A
)
xI
7.7
Figure 6. Current versus Supply Voltage
Active Mode
7.0
7.1
7.2
7.3
7.4
7.5
7.6
7.8
7.9
8.0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
MCU Clock Out Off
MCU Clock Out On
ACT I , SUPPLY CURRENT (mA)
CC
VCC, SUPPLY VOLT AGE (V)
Figure 7. Current versus
Temperature Normalized to 25°C
–10
–5.0
0
5.0
10
15
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
T
A
, TEMPERATURE (°C)
Inactive
Standby
DELT A CURRENT DRAIN (% FROM 25 C)
°
–12
–10
–8.0
–6.0
–4.0
–2.0
0
2.0
4.0
6.0
0
Figure 8. Current versus
Temperature Normalized to 25°C
–40 –30 –20 –10 10 20 30 40 50 60 70 80 90
T
A
, TEMPERATURE (°C)
Active
Receive
DELT A CURRENT DRAIN (% FROM 25 C)
°
MC13110A/B MC13111A/B
19
MOTOROLA RF/IF DEVICE DATA
DC CURRENT
1.40
1.42
1.50
1.30
1.32
1.34
1.36
1.38
1.44
1.46
1.48
Figure 9. Additional Supply Current Consumption
versus Supply Voltage, IP3 = <1>
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VCC, SUPPLY VOLTAGES (V)
DELT A CURRENT DRAIN (mA)
Figure 10. Additional IP3
Supply Current Consumption versus
Temperature Normalized to 25°C
–20
–15
–10
–5
0
5
10
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
TA, TEMPERATURE (°C)
DELT A CURRENT DRAIN (% FROM 25 C)
°
ÁÁÁÁÁ
ÁÁÁÁÁ
Receive/Active
ÁÁÁÁ
ÁÁÁÁ
Receive/Active
650
500
Figure 11. Current Standby
Mode versus MCU Clock Output
300
350
400
450
550
600
700
750
800
1.0 10 100 1000
MCU CLK OUT DIVIDE VALUE
No load
MCU clock off
10 pF load
STD
I ,
SU
PPLY C
URRENT
(m
A
)
CC
Figure 12. VB Voltage versus Temperature
Normalized to 1.5 V at 25°C
1.4925
1.4950
1.4975
1.5000
1.5025
1.5050
1.5075
–20–100 102030405060708090
T
A
, TEMPERATURE (°C)
V , NORMALIZED VB VOLTAGE (V)
s
MC13110A/B MC13111A/B
20 MOTOROLA RF/IF DEVICE DATA
FIRST AND SECOND MIXER
Mixer Description
The 1st and 2nd mixers are similar in design. Both are
double balanced to suppress the LO and the input
frequencies to give only the sum and difference frequencies
at the mixer output. Typically the LO is suppressed better
than –50 dB for the first mixer and better than –40 dB for the
second mixer . The gain of the 1st mixer has a –3.0 dB corner
at approximately 13 MHz and is used at a 10.7 MHz IF. It has
an output impedance of 300 Ω and matches to a typical
10.7 MHz ceramic filter with a source and load impedance of
330 Ω. A series resistor may be used to raise the impedance
for use with crystal filters. They typically have an input
impedance much greater than 330 Ω.
First Mixer
Figures 17 through 20 show the first mixer transfer curves
for the voltage conversion gain, output level, and
intermodulation. Notice that there is approximately 10 dB
linearity improvement when the “IP3 Increase” bit is set to
<1>. The “IP3 Increase” bit is a programmable bit as shown in
the Serial Programmable Interface section under the Rx
Counter Latch Register. The IP3 = <1> option will increase
the supply current demand by 1.3 mA.
Figure 13. First Mixer Input and Output Impedance
Schematic
1st Mixer
Mix1 In Mix1 Out
RPI CPI RPO
CPO
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 14. First Mixer Output Impedance
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Unit
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Output Impedance
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
B IP3 = <0> (Set Low)
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
304 Ω // 3.7 pF
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
B IP3 = <1> (Set High)
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
300 Ω // 4.0 pF
Figures 13, 14, and 16 represent the input and output
impedance for the first mixer. Notice that the input
single–ended and differential impedances are basically the
same. The output impedance as described in Figure 14 will
be used to match to a ceramic or crystal filter’s input
impedance. A typical ceramic filter input impedance is 330 Ω
while crystal filter input impedance is usually 1500 Ω. Exact
impedance matching to ceramic filters are not critical,
however, more attention needs to be given to the filter
characteristics of a crystal filter. Crystal filters are much
narrower . It is important to accurately match to these filters to
guaranty a reasonable response.
To find the IF bandwidth response of the first mixer refer to
Figure 22. The –3.0 dB bandwidth point is approximately 13
MHz. Figure 15 is a summary of the first mixer feedthrough
parameters.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 15. First Mixer Feedthrough Parameters
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Parameter
ÁÁÁÁÁ
ÁÁÁÁÁ
(dBm)
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
1st LO Feedthrough @ Mix1 In1
ÁÁÁÁÁ
ÁÁÁÁÁ
–70.0
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
1st LO Feedthrough @ Mix1 Out
ÁÁÁÁÁ
ÁÁÁÁÁ
–55.5
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
RF Feedthrough @ Mix1 Out with –30 dBm
ÁÁÁÁÁ
ÁÁÁÁÁ
–61.0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 16. First Mixer Input Impedance over Input Frequency
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
US Center Channels
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
France Center Channels
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Unit
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
49 MHz
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
46 MHz
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
41 MHz
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
26 MHz
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Single–Ended
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
1550 Ω // 3.7 pF
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1560 Ω // 3.7 pF
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
1570 Ω // 3.8 pF
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
1650 Ω // 3.7 pF
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Differential
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
1600 Ω // 1.8 pF
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1610 Ω // 1.8 pF
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
1670 Ω // 1.8 pF
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
1710 Ω // 1.8 pF
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Note: 11. Single–Ended data is from measured results. Differential data is from simulated results.
MC13110A/B MC13111A/B
21
MOTOROLA RF/IF DEVICE DATA
Mix1Out, MIXER OUTPUT (dBm)
1.0
15
–40
0
–40
14
2.7
–10
–40
0
–40
14
f, IF FREQUENCY (MHz)
Mix1 In, MIXER INPUT LEVEL (dBm)
Mix1 In, MIXER INPUT LEVEL (dBm)
VO1.0 dB Mix
VCC Audio, AUDIO SUPPLY VOLTAGE (V)
Mix1Out, MIXER OUTPUT (dBm)
Mix1 In, MIXER INPUT LEVEL (dBm)
MXgain1, VOLTAGE
Figure 17. First Mixer Voltage Conversion
Gain, IP3_bit = 0
Mix1 In, MIXER INPUT LEVEL (dBm)
Figure 18. First Mixer Voltage Conversion
Gain, IP3_bit = 1
Figure 19. First Mixer Output Level and
Intermodulation, IP3_bit = 0 Figure 20. First Mixer Output Level and
Intermodulation, IP3_bit = 1
Figure 21. First Mixer Compression versus
Supply Voltage Figure 22. First IF Bandwidth
Fundamental Level
3rd Order
Intermodulation
Fundamental Level
3rd Order
Intermodulation
CONVERSION GAIN (dB)
12
–20
10
–20
12
–40
8.0
–40
10
–60–60
8.0
4.0
–80–80
2.0
–100–100
10
–12
5.0
–14
0
–16
–5.0
–18
–10
–20
–15–22
–35–35 –30–30 –25–25 –20–20 –15–15 –10–10
10
–35
3.3
–35 –30–30 –25–25 –20
4.2
–20 –15
4.8
–15 –10
5.4
–10
1003.6 3.9 4.53.0 5.1
IP3_bit = 1
1, 1.0 dB
VOLT AGE COMPRESSION (dBm)
6.0
6.0
IP3_bit = 0
MXgain1, VOLTAGE
CONVERSION GAIN (dB)
MXgain1, VOLT AGE
CONVERSION GAIN (dB)
VCC = 3.6 V
IF = 10.695 MHz, 330 ΩVCC = 3.6 V
IF = 10.695 MHz, 330 Ω
VCC = 3.6 V
IF = 10.695 MHz, 330 ΩVCC = 3.6 V
IF = 10.695 MHz, 330 Ω
FIRST MIXER
IF = 10.695 MHz, 330 Ω
VCC = 3.6 V
RL = 330 Ω
LO = 36.075 MHz
MC13110A/B MC13111A/B
22 MOTOROLA RF/IF DEVICE DATA
Second Mixer
Figures 26 through 29 represents the second mixer
transfer characteristics for the voltage conversion gain,
output level, and intermodulation. There is a slight
improvement in gain when the “IP3 bit” is set to <1> for the
second mixer. (Note: This is the same programmable bit
discussed earlier in the section.)
Figure 23. Second Mixer Input and Output
Impedance Schematic
2nd Mixer
Mix2 In Mix2 Out
RPI CPI RPO
CPO
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 24. Second Mixer Input and Output
Impedances
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Unit
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Input Impedance
RPI // CPI
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Output
Impedance
RPO // CPO
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
IP3 = <0> (Set Low)
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
2817 Ω // 3.6 pF
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1493 Ω // 6.1 pF
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
IP3 = <1> (Set High)
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
2817 Ω // 3.6 pF
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1435 Ω // 6.2 pF
The 2nd mixer input impedance is typically 2.8 kΩ. It
requires an external 360 Ω parallel resistor for use with a
standard 330 Ω, 10.7 MHz ceramic filter. The second mixer
output impedance is 1.5 kΩ making it suitable to match
standard 455 kHz ceramic filters.
The IF bandwidth response of the second mixer is shown
in Figure 31. The –3.0 dB corner is 2.5 MHz. The feedthrough
parameters are summarized in Figure 25.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 25. Second Mixer Feedthrough Parameters
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Parameter
ÁÁÁÁÁ
ÁÁÁÁÁ
(dBm)
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
2nd LO Feedthrough @ Mix2 Out
ÁÁÁÁÁ
ÁÁÁÁÁ
–42.9
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
IF Feedthrough @ Mix2 Out with –30 dBm
ÁÁÁÁÁ
ÁÁÁÁÁ
–61.7
MC13110A/B MC13111A/B
23
MOTOROLA RF/IF DEVICE DATA
0.12.7
Mix2Out, MIXER OUTPUT (dBm)VO1.0 dB Mix2, 1.0 dB MXgain2, VOL TAGE
CONVERSION GAIN (dB)
25
10
–10
–40
10
22
f, IF FREQUENCY (MHz)
Mix2 In, MIXER INPUT LEVEL (dBm)
Mix2 In, MIXER INPUT LEVEL (dBm)
VCC Audio, AUDIO SUPPLY VOLTAGE (V)
Mix2 In, MIXER INPUT LEVEL (dBm)
Figure 26. Second Mixer Conversion Gain,
IP3_bit = 0
Mix2 In, MIXER INPUT LEVEL (dBm)
Figure 27. Second Mixer Conversion Gain,
IP3_bit = 1
Figure 28. Second Mixer Output Level and
Intermodulation, IP3_bit = 0 Figure 29. Second Mixer Output Level and
Intermodulation, IP3_bit = 1
Figure 30. Second Mixer Compression
versus Supply Voltage Figure 31. Second IF Bandwidth
Mix2Out, MIXER OUTPUT (dBm)
VOLT AGE COMPRESSION (dBm)
Fundamental Level
3rd Order
Intermodulation
IP3_bit = 1
IP3_bit = 0
Fundamental Level
3rd Order
Intermodulation
–10
20
–30
18
–50
16
–70
–90
–12
–14
–16
–18
–20
–22
12
14
22
20
–10
18
–30
16
–50
14
–70
–90
20
15
10
5.0
0
–40
–40–40 –35–35 –30–30 –25–25 –20–20 –15–15 –10–10
1.0
–35
3.3
–35 –30–30 –25–25 –20
4.2
–20 –15
4.8
–15 –10
5.4
–10
103.6 3.9 4.53.0 5.1
MXgain2, VOL TAGE
CONVERSION GAIN (dB)
MXgain2, VOL TAGE
CONVERSION GAIN (dB)
VCC = 3.6 V
IF = 455 kHz
RL = 1500 Ω
SECOND MIXER
VCC = 3.6 V
IF = 455 kHz
RL = 1500 Ω
VCC = 3.6 V
IF = 455 kHz
RL = 1500 Ω
VCC = 3.6 V
IF = 455 kHz
RL = 1500 Ω
IF = 455 kHz
RL = 1500 ΩVCC = 3.6 V
RL = 1500 Ω
MC13110A/B MC13111A/B
24 MOTOROLA RF/IF DEVICE DATA
First Local Oscillator
The 1st LO is a multi–vibrator oscillator. The tank circuit is
composed of a parallel external capacitance and inductance,
internal programmable capacitor matrix, and internal
varactor. The local oscillator requires a voltage controlled
input to the internal varactor and an external loop filter driven
by on–board phase–lock control loop (PLL). The 1st LO
internal component values have a tolerance of ±15%. A
typical dc bias level on the LO Input and LO Output is 0.45
Vdc. The temperature coefficient of the varactor is
+0.08%/°C. The curve in Figure 33 is the varactor control
voltage range as it relates to varactor capacitance. It
represents the expected internal capacitance for a given
control voltage (VcapCtrl) of the MC13110A/B and
MC131 11A/B. Figure 32 shows a representative schematic of
the first LO function.
LO1 In
LO1 Out
Vcap Ctrl
Programmable
Internal
Capacitor
1st LO
Varactor
Varactor Cext Lext
Figure 32. First Local Oscillator Schematic
To select the proper Lext and Cext we can do the following
analysis. From Figure 34 it is observed that an inductor will
have a significant affect on first LO performance, especially
over frequency. The overall minimum Q required for first LO
to function as it relates to the LO frequency is also given in
Figure 34.
Choose an inductor value, say 470 nH. From Figure 34,
the minimum operating Q is approximately 25. From the
following equation:
Q Coil = Rp/X Coil
where: Rp = parallel equivalent impedance (Figure 35).
Cext can be determined as follows:
fLO
+
1
2
p
LextCext
Ǹ
where: Lext = external inductance, Cext = external
capacitance.
Figure 34 clearly indicates that for lower coil values, higher
quality factors (Q) are required for the first LO to function
properly. Also, lower LO frequencies need higher Q’s. In
Figure 35 the internal programmable capacitor selection
relative to the first LO frequency and the parallel impedance
is shown. This information will help the user to decide what
inductor (Lext) to choose for best performance in terms of Q.
Refer to the Auxiliary Register in the Serial Interface
Section for further discussion on LO programmability.
MC13110A/B MC13111A/B
25
MOTOROLA RF/IF DEVICE DATA
100
120
0
100
OVERALL MINIMUM Q VALUE
LO INDUCTOR VALUE (nH)
R
P,
RE
P
RESENTAT
I
VE
P
ARA
LL
E
L
Ω
C1–C15, CAPACITANCE SELECT
Figure 33. First LO Varicap Capacitance
versus Control Voltage Figure 34. First LO Minimum Required Overall
Q Value versus Inductor Value
Figure 35. Representative Parallel Impedance
versus Capacitor Select Figure 36. Varicap Value at VCV = 1.0 V
Over Temperature
Figure 37. Control Voltage versus
Channel Number, U.S. Handset Application Figure 38. Control Voltage versus
Channel Number, U.S. Baseset Application
30 MHz
40 MHz
50 MHz
30 MHz
40 MHz
50 MHz
IMPEDANCE (k )
100
80
60
40
20
0
10
1000
1 6 4 3 8 9 10 11 12 13 14 15257
FIRST LOCAL OSCILLATOR
0
15
, C
A
P
A
CI
TAN
C
E
(
p
F)
VcapCtrl, CONTROL VOLTAGE (V)
14
12
13
11
10
9.0
8.0
7.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
cap
10.2
Vcap, CAPACIT ANCE (pF)
TA, AMBIENT TEMPERATURE (°C)
9.8
9.4
9.8 –20 0 25 70 8555
10.6
11
1
1.7
CH1–CH25, U.S. HANDSET CHANNEL APPLICATION
Cap 11
Cap 10
Cap 9
Cap 6
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9 3 5 7 9 11 13 15 17 19 21 23 25
1.8
Ctrl, CONTROL VOLT AGE (V)
1.7
CH1–CH25, U.S. BASESET CHANNEL APPLICATION
Cap 8 Cap 3
Cap 4
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.81 3 5 7 9 11 13 15 17 19 21 23 25
Vcap
1.8
C
trl
, CO
NTR
OL
V
OL
TA
G
E
(
V
)
V
cap
MC13110A/B MC13111A/B
26 MOTOROLA RF/IF DEVICE DATA
Second Local Oscillator
The 2nd LO is a CMOS oscillator. It is used as the PLL
reference oscillator and local oscillator for the second
frequency conversion in the RF receiver. It is designed to
utilize an external parallel resonant crystal. See schematic in
Figure 39.
Figure 39. Second Local Oscillator Schematic
2nd LO
RPI CPI RPO
CPO
Gm
LO2 In LO2 Out
Xtal
C2
C1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 40. Second Local Oscillator
Input and Output Impedance
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Input Impedance (RPI // CPI)
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
11.6 kΩ // 2.9 pF
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Output Impedance (RPO // CPO)
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
9.6 kΩ // 2.7 pF
Figure 41 shows a typical gain/phase response of the
second local oscillator. Load capacitance (CL), equivalent
series resistance (ESR), and even supply voltage will have
and affect on the 2nd LO response as shown in Figures 45
and 46. Except for the standby mode open loop gain is fairly
constant as supply voltage increases from 2.5 V. This is due
to the regulated voltage of 2.5 V on PLL Vref. From the graphs
it can seen that optimum performance is achieved when C1
equals C2 (C1/C2 = 1).
Figure 46 represents the ESR versus crystal load
capacitance for the 2nd LO. This relationship was defined by
using a 6.0 dB minimum loop gain margin at 3.6 V. This is
considered the minimum gain margin to guarantee oscillator
start–up.
Oscillator start–up is also significantly affected by the
crystal load capacitance selection. In Figures 42 and 43 the
relationship between crystal load capacitance, supply
voltage, and external load capacitance ratio (C2/C1), can be
seen. The lower the load capacitance the better the
performance.
Given the desired crystal load capacitance, C1 and C2
can be determined from Figure 47. It is also interesting to
point out that current consumption increases when C1 ≠ C2,
as shown in Figure 44.
Be careful not to overdrive the crystal. This could cause a
noise problem. An external series resistor on the crystal
output can be added to reduce the drive level, if necessary.
Vgain2, LO VOLTAGE GAIN (dB)
0
6.0
10.235
15
START–UP TIME (ms)
CAPACITOR RATIO (C2:C1)
Figure 41. Second LO Gain/Phase @ –10 dBm
f, FREQUENCY (MHz)
Figure 42. Start–Up Time versus Capacitor
Ratio, Inactive to Rx Mode
Gain
10.24 MHz Crystal
CL = 10 pF
RS = 20 Ω
VCC = 5.0 V
VCC = 3.6 V
VCC = 2.3 V
VCC = 2.7 V
10
5.0
0
–5.0
–10
–15
–20
–25
5.0
4.0
3.0
2.0
1.0
0
10.24 10.245
Phase
90
67.5
45
22.5
0
–22.5
–45
–67.5
–90 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
10.24 MHz Crystal
CL = 10 pF
RS = 20 Ω
C1 = C2 = 15 pF
SECOND LOCAL OSCILLATOR
MC13110A/B MC13111A/B
27
MOTOROLA RF/IF DEVICE DATA
0
30
0
800
0
20
CAPACITOR RATIO (C2:C1)
ISTD, STANDBY CURRENT ( A)µ
CAPACITOR RATIO (C2:C1)
CAPACITOR RATIO (C2:C1)
AVOL, OPEN LOOP GAIN (dB)
VCC = 2.3 V
VCC = 2.7, 3.6, 5.0 V
10.24 MHz Crystal
CL = 10 pF
RS = 20 Ω
Rx Mode
10.24 MHz Crystal
CL = 10 pF
RS = 20 Ω
10.24 MHz Crystal
CL = 24 pF
RS = 16 ΩStandby Current with Clk_Out
Running at 2.048 MHz
Standby Current
with Clk_Out Off
Oscillator Level
VCC = 5.0 V
VCC = 3.6 V
VCC = 2.7 V
VCC = 2.3 V
LO2, SECOND OSCILLAT OR LEVEL (dBm)
START–UP TIME (ms)
16
12
8.0
4.0
0
25
20
15
10
5.0
0
700
600
500
400
300
200
100
0
0.5 0.5
0.5
1.0 1.0
1.0
1.5 1.5
1.5
2.0 2.0
2.0
2.5 2.5
2.5
3.0 3.0
3.0
3.5 3.5
3.5
4.0 4.0
4.0
13
12
11
10
9.0
SECOND LOCAL OSCILLATOR
Figure 43. Start–Up Time versus Capacitor
Ratio, Inactive to Rx Mode Figure 44. Second LO Current Consumption
versus Capacitor Ratio
Figure 45. Maximum Open Loop Gain
versus Capacitor Ratio
10
1000
ΩESR, EQUIVALENT RESISTANCE ( )
CRYSTAL LOAD CAPACITANCE (pF)
Figure 46. Maximum Allowable
Equivalent Series Resistance (ESR)
versus Crystal Load Capacitance
10
100
12 14 16 18 20 22 24 26 28 30 32
Curve Valid for fosc in the Range of 10 MHz to 12 MHz
0
70
OPTIMUM C1 AND C2 VALUE (pF)
REQUIRED PARALLEL CRYSTAL LOAD CAPACITANCE (pF)
Figure 47. Optimum Value for C1 and C2
versus Equivalent Required Parallel
Capacitance of the Crystal
50
60
40
30
20
10
05.0 10 15 20 30 3525
C1 = C2
MC13110A/B MC13111A/B
28 MOTOROLA RF/IF DEVICE DATA
IF Limiter and Demodulator
The limiting IF amplifier typically has about 110 dB of gain;
the frequency response starts rolling off at 1.0 MHz.
Decoupling capacitors should be placed close to Pins 31 and
32 to ensure low noise and stable operation. The IF input
impedance is 1.5 kΩ. This is a suitable match to 455 kHz
ceramic filters.
Figure 48. IF Limiter Schematic
Lim OutLim In
Limiter Stage
RPI CPI
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 49. Limiter Input Impedance
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Unit
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Input Impedance
(RPI)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Input Impedance
(CPI)
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Lim In
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1538 Ω
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
15.7 pF
Figure 50. Quadrature Detector
Demodulator Schematic
Q CoilLim Out1
C28
10 p
Rext
22.1 k Toko Q Coil
7MCS–8128Z
The quadrature detector is coupled to the IF with an
external capacitor between Pins 27 and 28. Thus, the
recovered signal level output is increased for a given
bandwidth by increasing the capacitor. The external
quadrature component may be either a LCR resonant circuit,
which may be adjustable, or a ceramic resonator which is
usually fixed tuned. (More on ceramic resonators later.)
The bandwidth performance of the detector is controlled
by the loaded Q of the LC tank circuit (Figure 50). The
following equation defines the components which set the
detector circuit’s bandwidth:
(1) RT = Q XL,
where RT is the equivalent shunt resistance across the LC
tank. XL is the reactance of the quadrature inductor at the IF
frequency (XL= 2π f L).
The 455 kHz IF center frequency is calculated by:
(2) fc = [2π (L Cp)1/2] – 1
where L is the parallel tank inductor. Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a detector at 455
kHz and a specific loaded Q:
The loaded Q of the quadrature detector is chosen
somewhat less than the Q of the IF bandpass for margin. For
an IF frequency of 455 kHz and an IF bandpass of 20 kHz,
the IF bandpass Q is approximately 23; the loaded Q of the
quadrature tank is chosen slightly lower at 15.
Example:
Let the total external C = 180 pF. (Note: the capacitance is
the typical capacitance for the quad coil.) Since the external
capacitance is much greater than the internal device and
PCB parasitic capacitance, the parasitic capacitance may be
neglected.
Rewrite equation (2) and solve for L:
L = (0.159)2/(C fc2 )
L = 678 µH ; Thus, a standard value is chosen:
L = 680 µH (surface mount inductor)
The value of the total damping resistor to obtain the
required loaded Q of 15 can be calculated from equation (1):
RT = Q(2π f L)
RT = 15(2π)(0.455)(680) = 29.5 kΩ
The internal resistance, Rint at the quadrature tank Pin 27
is approximately 100 kΩ and is considered in determining the
external resistance, Rext which is calculated from:
Rext = ((RT)(Rint))/(Rint – RT)
Rext = 41.8 kΩ;Thus, choose a standard value:
Rext = 39 kΩ
In Figure 50, the Rext is chosen to be 22.1 kΩ. An
adjustable quadrature coil is selected. This tank circuit
represents one popular network used to match to the
455 kHz carrier frequency. The output of the detector is
represented as a “S–curve” as shown in Figure 52. The goal
is to tune the inductor in the area that is most linear on the
“S–curve” (minimum distortion) to optimize the performance
in terms of dc output level. The slope of the curve can also be
adjusted by choosing higher or lower values of Rext . This will
have an affect on the audio output level and bandwidth. As
Rext is increased the detector output slope will decrease.
The maximum audio output swing and distortion will be
reduced and the bandwidth increased. Of course, just the
opposite is true for smaller Rext.
A ceramic discriminator is recommended for the
quadrature circuit in applications where fixed tuning is
desired. The ceramic discriminator and a 5.6 kΩ resistor are
placed from Pin 27 to VCC . A 22 pF capacitor is placed from
Pin 28 to 27 to properly drive the discriminator. MuRata Erie
has designed a resonator for this part (CDBM455C48 for
USA & A/P regions and CDBM450C48 for Europe). This
resonator has been designed specifically for the
MC13110/111 family. Figure 51 shows the schematic used to
generate the “S–curve” and waveform shown in Figure 54
and 55.
MC13110A/B MC13111A/B
29
MOTOROLA RF/IF DEVICE DATA
Figure 51. Ceramic Resonator Demodulator
Schematic with Murata CDBM450C48
C28
390 p
Rext
2.7 k Ceramic Resonator
Murata
CDBM450C34
Lim Out1Q Coil
(CDBM455C48 US; CDBM450C48 France)
The “S–curve” for the ceramic discriminator shown in
Figure 54 is centered around 450 kHz. It is for the French
application. The same resonator is also used for the US
application and is centered around 455 kHz. Clearly, the
“S–curves” for the resonator and quad coil have very similar
limiter outputs. As discussed previously, the slope of the
“S–curve” centered around the center frequency can be
controlled by the parallel resistor , Rext. Distortion, bandwidth,
and audio output level will be affected.
Figure 52. S–Curve of Limiter
Discriminator with Quadrature Coil
0.2
0.6
1.0
1.4
2.2
425 435 445 485
Lim In, INPUT FREQUENCY (kHz)
1.8
455 465 475
Det Out, DC VOLTAGE (V)
Toko 7MCS–8128Z
Figure 53. Typical Limiter Output
Waveform with Quadrature Coil
IF LIMITER AND DEMODULATION
Figure 54. S–Curve of Limiter
Discriminator with Ceramic Resonator
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.7
440 442 444 446 448 460
Lim In, INPUT FREQUENCY (kHz)
1.4
1.5
450 452 454 456 458
Det Out, DC VOLTAGE (V)
Murata CDBM450C48
1.6
Figure 55. Typical Limiter Output
Waveform with Ceramic Resonator
AC VOLTAGE LEVEL (V)
f = 455 kHz
Vpptyp = 344 mV
0
1.0
t, TIME (ms)
600
400
200
800
AC VOLTAGE LEVEL (V)
f = 450 kHz
Vpptyp = 370 mV
0
1.0
t, TIME (ms)
600
400
200
800
MC13110A/B MC13111A/B
30 MOTOROLA RF/IF DEVICE DATA
RSSI and Carrier Detect
The Received Signal Strength Indicator (RSSI) indicates
the strength of the IF level. The output is proportional to the
logarithm of the IF input signal magnitude. RSSI dynamic
range is typically 80 dB. A 187 kΩ resistor to ground is
provided internally to the IC. This internal resistor converts
the RSSI current to a voltage level at the “RSSI” pin. To
improve the RSSI accuracy over temperature an internal
compensated reference is used. Figure 56 shows the RSSI
versus RF input. The slope of the curve is 16.5 mV/dB.
The Carrier Detect Output (CD Out) is an open–collector
transistor output. An external pull–up resistor of 100 kΩ will
be required to bias this device. To form a carrier detect filter a
capacitor needs to be connected from the RSSI pin to
ground. The carrier detect threshold is programmable
through the MPU interface (see “Carrier Detect Threshold
Programming” in the serial interface section). The range can
be scaled by connecting additional external resistance from
the RSSI pin to ground in parallel with the capacitor. From
Figure 57, the affect of an external resistor at RSSI on the
carrier detect level can be noticed. Since there is hysteresis
in the carrier detect comparator, one trip level can be found
when the input signal is increased while the another one can
be found when the signal is decreased.
Figure 58 represents the RSSI ripple in relation to the RF
input for different filtering capacitors at RSSI. Clearly, the
higher the capacitor, the less the ripple. However, at low
carrier detect thresholds, the ripple might supersede the
hysteresis of the carrier detect. The carrier detect output may
appear to be unstable. Using a large capacitor will help to
stabilize the RSSI level, but RSSI charge time will be
affected. Figure 59 shows this relationship.
The user must decide on a compromise between the RSSI
ripple and RSSI start–up time. Choose a 0.01 µf capacitor as
a starting point. For low carrier detect threshold settings, a
0.047 µf capacitor is recommended.
–60
RSSI AND CARRIER DETECT
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
–120 –100 –80 –60 –40 –20 0
Mix1 In, RF INPUT (dBm)
Figure 56. Typical RSSI Voltage
Level versus RF Input
RSS
I O
UT
P
UT
(
Vdc
)
–90
–80
–70
–50
–40
–30
–20
0
100 1000
RRSSI, LOAD RESISTANCE (kΩ)
Figure 57. Carrier Detect Threshold versus
External RSSI Resistor
–10
Decreasing Signal
Limiter Input
Mixer 1
Input
Increasing Signal
Decreasing Signal
Increasing Signal
MIX
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
11
–120 –110 –100 –90 –80 –70 –60
Mix
1
In, RF INPUT (dBm)
Figure 58. RSSI Ripple versus RF Input Level for
Different RSSI Capacitors
0
5.0
10
15
20
25
35
0.01 0.10
C
RSS
I, LOAD CAPACIT ANCE (µF)
Figure 59. RSSI Charge Time
versus Capacitor Value
30
RSSI CHARGE TIME (ms)
8.0
9.0
10 10 nF
22 nF
33 nF
47 nF
100 nF
0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
RSS
I
R
IPPL
E
(m
Vr
ms)
1IN, RF INPUT (dBm)
MC13110A/B MC13111A/B
31
MOTOROLA RF/IF DEVICE DATA
RF System Performance
The sensitivity of the IC is typically 0.4 µVrms matched
(single ended or differential) with no preamp. To achieve
suitable system performance, a preamp and passive
duplexer may be used. In production final test, each section
of the IC is separately tested to guarantee its system
performance in the specific application. The preamp and
duplexer (differential, matched input) yields typically
–115 dBm @ 12 dB SINAD sensitivity performance under full
duplex operation. See Figure 45 and 48.
The duplexer is important to achieve full duplex operation
without significant “de–sensing” of the receiver by the
transmitter. The combination of the duplexer and preamp
circuit should attenuate the transmitter power to the receiver
by over 60 dB. This will improve the receiver system noise
figure without giving up too much IMD performance.
The duplexer may be a two piece unit offered by Shimida,
Sansui, or Toko products (designed for 25 channel CT–0
cordless phone). The duplexer frequency response at the
receiver port has a notch at the transmitter frequency band of
about 35 to 40 dB with a 2.0 to 3.0 dB insertion loss at the
receiver frequency band.
The preamp circuit utilizes a tuned transformer at the
output side of the amplifier. This transformer is designed to
bandpass filter at the receiver input frequency while rejecting
the transmitter frequency. The tuned preamp also improves
the noise performance by reducing the bandwidth of the pass
band and by reducing the second stage contribution of the
1st mixer. The preamp is biased such that it yields suitable
noise figure and gain.
The following matching networks have been used to
obtain 12 dB SINAD sensitivity numbers:
1:5 15
1:5 15
Figure 60. Matching Input Networks
Differential Match
Single–ended Match
Single–ended 50 Ω
Mix1 In1
Mix1 In2
Mix1 In1
Mix1 In2
Mix1 In1
Mix1 In2
RF In1
RF In1
RF In1
360
680
39
39
49.9 Ω
0.01
0.01
The exact impedance looking into the RF In1 pin is
displayed in the following table along with the sensitivity
levels.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 61. 12 dB SINAD Sensitivity Levels, US
Handset Application Channel 21
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Sensitivity
(dBm)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Input
Impedance
(dBm)
Differential matched –1 15.3 50.2 ± 0.1j
Single–ended match –114.8 50.2 ± 0.1j
Single–ended 50 Ω–100.1 50.2 ± 0.1j
The graphs in Figures 64 to 69 are performance results
based on Evaluation Board Schematic (Figure 138). This
evaluation board did not use a duplexer or preamp stage.
Figure 62 is a summary of the RF performance and Figure 63
contains the French RF Performance Summary.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 62. RF Performance Summary
for US Applications
MC13110A/MC13111A (fdev = 3.0 kHz, fmod = 1.0 kHz, 50 Ω)
Parameter Handset Baseset Unit
Sensitivity at
12 dB SINAD –100.1 –100.1 dBm
Recovered Audio 132 132 mV rms
SINAD @ –30 dBm 41.8 41.4 dB
THD @ –30 dBm 0.8 0.8 %
S/N @ –30 dBm 78.2 78.5 dB
AMRR @ –30 dBm 73.4 72.2 dB
RSSI range >80 >80 dB
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 63. RF Performance Summary
for US French Applications
MC13110A/MC13111A (fdev = 1.5 kHz, fmod = 1.0 kHz, 50 Ω)
Parameter Handset Baseset Unit
Sensitivity at
12 dB SINAD –91 –90.8 dBm
Recovered Audio 89.8 90 mV rms
SINAD @ –30 dBm 42.1 44.3 dB
THD @ –30 dBm 0.8 0.8 %
S/N @ –30 dBm 75.7 75.1 dB
AMRR @ –30 dBm 56 84.7 dB
RSSI range >80 >80 dB
MC13110A/B MC13111A/B
32 MOTOROLA RF/IF DEVICE DATA
–110
–90
–70
–50
–30
–10
–120 –100 –80 –60 –40 –20 0
S+N+D
N+D
AMR
N
SA Out, SPEAKER AMPLIFIER OUTPUT (dBV)
Mix1 In1, FIRST MIXER INPUT (dBm)
–102
–101
–100
–99
–98
–97
–96
15913172125
12 dB SINAD (dBm)
US CHANNEL NUMBERS
0
10
20
30
40
50
60
70
80
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
–120 –100 –80 –60 –40 –20 0
SINAD
S/N
RSSI
Mix1 In, RF INPUT (dBm)
Figure 64. Typical Receiver Performance
Parameters U.S. Handset Application Channel 21
RSSI OUTPUT (V)
SINAD, S/N (dB)
35
40
45
50
55
60
65
70
85
128
129
130
131
132
133
134
135
138
1357911 25
SINAD
S/N
AMRR
U.S. HANDSET CHANNEL NUMBER
Figure 65. Typical Performance Parameters
Over U.S. Handset Channel Frequencies
SA Out, SPEAKER AMPLIFIER OUTPUT (mV rms)
SINAD, S/N, AMRR (dB)
80
75
13 15 17 19 21 23
136
137
SA Out Level
35
40
45
50
55
60
65
70
85
128
129
130
131
132
133
134
135
138
1357911 25
SINAD
S/N
AMRR
U.S. BASESET CHANNEL NUMBER
Figure 66. Typical Performance Parameters
Over U.S. Baseset Channel Frequencies
SA Out, SPEAKER AMPLIFIER OUTPUT (mV rms)
SINAD, S/N, AMRR (dB)
80
75
13 15 17 19 21 23
136
137
SA Out Level
RF SYSTEM PERFORMANCE
Figure 67. Typical Receiver Performance for
US Handset Application Channel 21
Figure 68. 12 dB SINAD Sensitivity Over
US Handset Application Channels Figure 69. 12 dB SINAD Sensitivity Over
US Baseset Application Channels
–102
–101
–100
–99
–98
–97
–96
1 5 9 13172125
12 dB SINAD (dBm)
US CHANNEL NUMBERS
MC13110A/B MC13111A/B
33
MOTOROLA RF/IF DEVICE DATA
Receive Audio Path
The Rx Audio signal path begins at “Rx Audio In” and goes
through the IC to “E Out”. The “Rx Audio In”, “Scr Out”, and
“E In” pins are all ac–coupled. This signal path consists of
filters; programmable Rx gain adjust, Rx mute, and volume
control, and finally the expander. The typical maximum
output voltage at “E Out” should be approximately 0 dBV @
THD = 5.0% .
Figures 71 to 73 represent the receive audio path filter
response. The filter response attenuation is very sharp above
3900 Hz, which is the cutoff frequency. Inband (audio),
out–of–band, and ripple characteristics are also shown in
these graphs.
The group delay (Figure 75) has a peak around 6.5 kHz.
This spike is formed by rapid change in the phase at the
frequency. In practice this does not cause a problem since
the signal is attenuated by at least 50 dB.
The output capability at “Scr Out” and “E Out” are shown in
Figures 76, 77, and 78. The results were obtained by
increasing the input level for 2.0% distortion at the outputs.
In Figure 70, noise data for the Rx audio path is shown.
At Scr Out, the noise level clearly rises when the scrambler is
enabled. However, assuming a nominal output level of –20
dBV (100 mVrms) at the 0 dB gain setting, the noise floor is
more than 56 dB below the audio signal. However, the noise
data at E Out and SA Out is much more improved.
Speaker Amp
The Speaker Amp is an inverting rail–to–rail operational
amplifier. The noninverting input is connected to the internal
VB reference. External resistors and capacitors are used to
set the gain and frequency response. The “SA In” input pin
must be ac–coupled. The typical output voltage at “SA Out” is
2.6 Vpp with a 130 Ω load. The speaker amp response is
shown in Figures 79 and 80.
Data Amp Comparator
The data amp comparator is an inverting hysteresis
comparator. Its open collector output has an internal 100 kΩ
pull–up resistor. A band pass filter is connected between the
“Det Out” pin and the “DA In” pin with component values as
shown in the Application Circuit schematic. The “DA In” input
signal needs to be ac–coupled, too.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 70. Rx Path Noise Data
Receive
Scrambler Receive Gain
(dB) Volume
(dB) SCR_Out
(dBV) E_Out
(dBV) SA_Out
(dBV)
off/on muted muted < –95 < –95 < –95
off –9.0 –14 –92 < –95 < –95
off 0 0 –85 < –95 < –95
off 1.0 16 –76 < –95 < –95
on (MC13110A/B) –9.0 –14 –85 < –95 < –95
on (MC13110A/B) 0 0 –77 < –95 < –95
on (MC13110A/B) 10 16 –66 < –95 < –95
MC13110A/B MC13111A/B
34 MOTOROLA RF/IF DEVICE DATA
Eout, OUTPUT VOLTAGE LEVEL (dBV) °PHASE ( )
–40
5.0
100
180
100
5.0
100
10
100
0.5
100
10
E
in
, INPUT VOLTAGE LEVEL (dBV)
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
V
OL
TA
G
E
G
A
I
N
(
d
B)
Figure 71. Rx Audio Wideband Frequency Response
f, FREQUENCY (Hz)
Figure 72. Rx Audio Inband Frequency Response
Figure 73. Rx Audio Ripple Response Figure 74. Rx Audio Inband Phase Response
Figure 75. Rx Audio Inband Group Delay Figure 76. Rx Audio Expander Response
135
–5.0
90
–15
0.3
45
0
–25
0.1
–45
–90
–0.1
–0.3 –135
–180
–55
–0.5
–110
–5.0
1.0 –15
–25
–45
0.1
–55
–650
10001000 10000 100000 100001000000
–20
10001000
1000
10000
10000
10000
0
G
R
O
U
P
DE
L
A
Y (ms)
–35
Expander Transfer
Distortion
–10
–30
–50
–90
–70
–45
f, FREQUENCY (Hz)
–35
–35 –30 –25 –15 –10 –5.0
D
I
ST
O
RT
IO
N
(%)
28
24
20
16
8.0
4.0
0
12
Rx Audio In
to Scr Out
Vin = –20 dBV
Rx Audio In
to Scr Out
Vin = –20 dBV
Rx Audio In
to Scr Out
Vin = –20 dBV
Rx Audio In
to Scr Out
Vin = –20 dBV
V
,
gain
VOLT AGE GAIN (dB)
V ,
gain
Rx Audio In
to Scr Out
Vin = –20 dBV
V
OL
TA
G
E
G
A
I
N
(
d
B)
V
,
gain
Rx AUDIO
MC13110A/B MC13111A/B
35
MOTOROLA RF/IF DEVICE DATA
Scr Out, OUTPUT VOLTAGE LEVEL (dBV)
–9.0 Rx PROGRAMMABLE VOLUME LEVEL SETTINGRx PROGRAMMABLE GAIN CONTROL SETTING
Figure 77. Rx Audio Maximum Output Voltage
versus Gain Control Setting Figure 78. Rx Audio Maximum Output Voltage
versus Volume Setting
–4.0
–8.0
–10
–12
–16
–20 –7.0 –5.0 –3.0 –1.0 1.0 3.0 5.0 7.0 9.0
1.4
1.2
1.0
0.8
0.6
0.4
0
–14 –10 –6.0 –2.0 2.0 6.0 10 14
VCC = 3.6 V
THD = 2%
Eout, OUTPUT VOLTAGE LEVEL (dBV)
–6.0
–14
–18 0.2
VCC = 3.6 V
THD = 2%
SA Out, OUTPUT VOLTAGE LEVEL(dBV)
SA Out, OUTPUT VOLTAGE LEVEL (dBV)
1.8
SA In, INPUT VOLTAGE LEVEL (dBV)
Figure 79. Rx Audio Speaker Amplifier Drive
SA In, INPUT VOLTAGE LEVEL (dBV)
Figure 80. Rx Audio Speaker Amplifier Distortion
No Load
130 Ω
1.4
0
25
15
5.0
000 0.80.8 1.6 2.4 2.81.6 2.4 3.23.2
620 Ω
No Load
620 Ω
1.6
1.2
1.0
0.8
0.6
0.4
0.2
20
10
0.4 1.2 2.0 2.8 0.4 1.2 2.0
130 Ω
Rx AUDIO
MC13110A/B MC13111A/B
36 MOTOROLA RF/IF DEVICE DATA
Transmit Audio Path
This portion of the audio path goes from “C In” to “Tx Out”.
The “C In” pin will be ac–coupled. The audio transmit signal
path includes automatic level control (ALC) (also referred to
as the Compressor), Tx mute, limiter, filters, and Tx gain
adjust. The ALC provides “soft” limiting to the output signal
swing as the input voltage slowly increases. With this
technique the gain is slightly lowered to help reduce distortion
of the audio signal. The limiter section provides hard limiting
due to rapidly changing signal levels, or transients. This is
accomplished by clipping the signal peaks. The ALC, Tx
mute, and limiter functions can be enabled or disabled via the
MPU serial interface. The Tx gain adjust can also be remotely
controlled to set different desired signal levels. The typical
maximum output voltage at “Tx Out” should be approximately
0 dBV @ THD = 5.0%.
Figures 82 to 86 represent the transmit audio path filter
response. The filter response attenuation, again, is very
definite above 3800 Hz. This is the filter cutoff frequency.
Inband (audio), wideband, and ripple characteristics are also
shown in these graphs.
The compressor transfer characteristics, shown in
Figure 87, has three different slopes. A typical compressor
slope can be found between –55 and –15 dBV. Here the
slope is 2.0. At an input level above –15 dBV the automatic
level control (ALC) function is activated and prevents hard
clipping of the output. The slope below –55 dBV input level is
one. This is where the compressor curve ends. Above 5.0
dBV the output actually begins to decrease and distort. This
is due to supply voltage limitations.
In Figure 88 the ALC function is off. Here the compressor
curve continues to increase above –15 dBV up to –4.0 dBV.
The limiter begins to clip the output signal at this level and
distortion is rapidly rising. Similarly, Figure 68 (ALC and
Limiter Off) shows to compressor transfer curve extending all
the way up to the maximum output. Finally , Figure 90 through
93 show the Tx Out signal versus several combinations of
ALC and Limiter selected.
Figure 81 is the noise data measured for the
MC131 10A/1311 1A. This data is for 0 dB gain setting and –20
dBV (100 mVrms) audio levels.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 81. Tx Path Noise Data
Transmit
Scrambler Transmit
Gain
(dB)
Amp_Out
(dBV) Tx_Out
(dBV)
off/on muted muted < –95
off –9.0 < –95 –83
off 0 < –95 –74
off 10 < –95 –64
on (MC13110A) –9.0 < –95 –82
on (MC13110A) 0 < –95 –73
on (MC13110A) 10 –< –95 –63
Mic Amp
Like the Speaker Amp the Mic Amp is also an inverting
rail–to–rail operational amplifier. The noninverting input
terminal is connected to the internal VB reference. External
resistors and capacitors are used to set the gain and
frequency response. The “Tx In” input is ac–coupled.
MC13110A/B MC13111A/B
37
MOTOROLA RF/IF DEVICE DATA
100100
180
5.0
0.3
100
10
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 82. Tx Audio Wideband Frequency Response Figure 83. Tx Audio Inband Frequency Response
Figure 84. Tx Audio Ripple Response Figure 85. Tx Audio Inband Phase Response
–10
–30
–50
–70
–100
0.1
–0.1
–0.3
–0.6
–0.7
–5.0
–15
–25
–35
–55
135
45
–45
–135
–180
100
1000
1000 10000 1000
1000
100000 10000
10000
1000000
10000
C In to Tx Out
Vin = –10 dBV C In to Tx Out
Vin = –10 dBV
C In to Tx Out
Vin = –10 dBV
–90 –45
0.2
0
–0.2
–0.4
–0.5 C In to Tx Out
Vin = –10 dBV
°PHASE ( )
90
0
–90
V
OL
TA
G
E
G
A
I
N
(
d
B)
V
,
gain
VOLT AGE GAIN (dB)
V ,
gain
V
OL
TA
G
E
G
A
I
N
(
d
B)
V
,
gain
0
–20
–40
–60
–80
Tx AUDIO
Out, OUTPUT VOLTAGE LEVEL (dBV)
–60
0
100
10
C In, INPUT VOLTAGE LEVEL (dBV)
GROUP DELAY (ms)
Figure 86. Tx Audio Inband Group Delay
f, FREQUENCY (Hz)
Figure 87. Tx Audio Compressor Response
Compressor
–10
1.0
–20
0
–25
–35
–40 101000 10000
C In to Tx Out
Vin = –10 dBV
Tx
0.1 Distortion
ALC On,
Limiter On or Off
–5.0
–15
–30
–50 –40 –30 –20 –10 0
D
I
ST
O
RT
IO
N
(%)
4.0
2.0
0
3.0
1.0
MC13110A/B MC13111A/B
38 MOTOROLA RF/IF DEVICE DATA
–9.0
OUTPUT LEVEL (mV)
t, TIME (µs)
t, TIME (µs)
t, TIME (µs)
Tx PROGRAMMABLE GAIN CONTROL SETTING
A
–4.0
–12
–16
–20
Out, OUTPUT VOLTAGE LEVEL (dBV)Tx
B
C
–8.0
–7.0 –5.0 –3.0 –1.0 1.0 3.0 5.0 7.0 9.0
A: ALC Off, Limiter Off
B: ALC Off, Limiter On
C: ALC On, Limiter On or Off
VCC = 3.6 V
OUTPUT LEVEL (mV)
OUTPUT LEVEL (mV)
Limiter and ALC Off
Limiter On and ALC Off Limiter On and ALC On
0
200 mV/Div
500 µs/Div
200 mV/Div
500 µs/Div
200 mV/Div
500 µs/Div
Out, OUTPUT VOLTAGE LEVEL (dBV)Tx
Out, OUTPUT VOLTAGE LEVEL (dBV)TxDISTORTION (%)
4.0
2.0
0
3.0
1.0
DISTOR TION (%)
4.0
2.0
0
3.0
1.0
0
–60
0
C In, INPUT VOLTAGE LEVEL (dBV)C In, INPUT VOLTAGE LEVEL (dBV)
–5.0
–40
–10
–15
–20
–30
–40 –50–50 –40 –30 –20 –10 0 10 –40 –30 –10 0–20
ALC Off,
Limiter On
Distortion
ALC Off,
Limiter Off
10–60
–25
–35
–5.0
–10
–15
–20
–25
–30
–35
Compressor Transfer
Compressor Transfer
Distortion
Figure 88. Tx Audio Compressor Response Figure 89. Tx Audio Compressor Response
Figure 90. Tx Audio Maximum Output Voltage
versus Gain Control Setting Figure 91. Tx Output Audio Response
Figure 92. Tx Output Audio Response Figure 93. Tx Audio Output Response
Tx AUDIO
MC13110A/B MC13111A/B
39
MOTOROLA RF/IF DEVICE DATA
PLL SYNTHESIZER SECTION
PLL Frequency Synthesizer General Description
Figure 95 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL)
designed into the MC13110A/B and MC13111A/B IC. This
dual PLL is fully programmable through the MCU serial
interface and supports most country channel frequencies
including USA (25 ch), Spain, Australia, Korea, New Zealand,
U.K., Netherlands, France, and China (see channel frequency
tables in AN1575, “Worldwide Cordless Telephone
Frequencies”).
The 2nd local oscillator and reference divider provide the
reference frequency signal for the Rx and Tx PLL loops. The
programmed divider value for the reference divider is
selected based on the crystal frequency and the desired Rx
and Tx reference frequency values. For the U.K., additional
divide by 25 and divide by 4 blocks are provided to allow for
generation of the 1.0 kHz and 6.2 kHz reference frequencies.
The 14–bit Rx counter is programmed for the desired first
local oscillator frequency. The 14–bit Tx counter is
programmed for the desired transmit channel frequency. All
counters power–up to a set default state for USA channel #21
using a 10.24 MHz reference frequency crystal (see power–up
default latch register state in the Serial Programmable
Interface section).
To extend the sensitivity of the 1st LO for U.S. 25 channel
operation, internal fixed capacitors can be connected to the
tank circuit through microprocessor programmable control.
When designing the external PLL loop filters, it is
recommended that the Tx and Rx phase detectors be
considered as current drive type outputs. The loop filter
control voltage must be 0.5 V away from either the positive or
negative supply rail.
PLL I/O Pin Configurations
The 2nd LO, Rx and T x PLL ’s, and MPU serial interface are
powered by the internal voltage regulator at the “PLL V ref” pin.
The “PLL Vref” pin is the output of a voltage regulator which is
powered from the “VCC Audio” power supply pin. It is regulated
by an internal bandgap voltage reference. Therefore, the
maximum input and output levels for most of the PLL I/O pins
(LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the regulated
voltage at the “PLL Vref” pin. The ESD protection diodes on
these pins are also connected to “PLL V ref”.
Internal level shift buffers are provided for the pins (Data,
Clk, EN, Clk Out) which connect directly to the
microprocessor. The maximum input and output levels for
these pins is VCC. Figure 94 shows a simplified schematic of
the I/O pins.
Figure 94. PLL I/O Pin Simplified Schematics
PLL Vref
(2.5 V)
InI/O
VCC Audio
(2.7 to 5.5 V) PLL Vref
(2.5 V) VCC Audio
(2.7 to 5.5 V)
Clk Out PinData, Clk and EN PinsLO2 In, LO2 Out,
Rx PD, Tx PD and
T
x
VCO Pins
Out
2.0 µA
PLL Loop Control Voltage Range
The control voltage for the Tx and Rx loop filters is set by
the phase detector outputs which drive the external loop
filters. The phase detectors are best considered to have a
current mode type output. The output can have three states;
ground, high impedance, and positive supply, which in this
case is the voltage at “PLL Vref”. When the loop is locked the
phase detector outputs are at high impedance. An exception
of this state is for narrow current pulses, referenced to either
the positive or negative supply rails. If the loop voltages get
within 0.5 V of either rail the linear current output starts to
degrade. The phase detector current source was not
designed to operate at the supply rails. VCO tuning range will
also be limited by this voltage range
The maximum loop control voltage is the “PLL Vref” voltage
which is 2.5 V. If a higher loop control voltage range is
desired, the “PLL Vref” pin can be pulled to a higher voltage.
It can be tied directly to the VCC voltage (with suitable filter
capacitors connected close to each pin). When this is done,
the internal voltage regulator is automatically disabled. This
is commonly used in the telephone base set where an
external 5.0 V regulated voltage is available. It is important to
remember, that if “PLL Vref” is tied to VCC and VCC is not a
regulated voltage, the PLL loop parameters and lock–up time
will vary with supply voltage variation. The phase detector
gain constant, Kpd, will not be affected if the “PLL V ref” is tied
to VCC.
Figure 95. Dual PLL Simplified Block Diagram
14–b Programmable
Rx Counter
14–b Programmable
Tx Counter
12–b
Programmable
Reference
Counter
÷25
÷1
÷4
LO2 In
LO2 Out
1
2
Tx PD
8
6
Tx VCO
Rx PD
4
LO1 In
40
LO1 Out
41
Tx Phase
Detector
(Current
Output)
Rx Phase
Detector
(Current
Output)
LP Loop Filter
Tx Ref
Rx Ref
U.K. Base
U.K. Handset
U.K. Handset
U.K. Base
Vcap Ctrl
42
1st LO
LP Loop Filter
Tx
VCO
Programmable
Internal Capacitor
MC13110A/B MC13111A/B
40 MOTOROLA RF/IF DEVICE DATA
Loop Filter Characteristics
Lets consider the following discussion on loop filters. The
fundamental loop characteristics, such as capture range,
loop bandwidth, lock–up time, and transient response are
controlled externally by loop filtering.
Figure 96 is the general model for a Phase Lock Loop
(PLL).
Phase
Detector (Kpd)Filter
(Kf)VCO
(Ko)fo
Divider
(Kn)
fi
Figure 96. PLL Model
Where: Kpd = Phase Detector Gain Constant
Kf = Loop Filter Transfer Function
Ko = VCO Gain Constant
Kn = Divide Ratio (1/N)
fi = Input frequency
fo = Output frequency
fo/N = Feedback frequency divided by N
From control theory the loop transfer function can be
represented as follows:
A = Kpd Kf Ko Kn Open loop gain
Kpd can be either expressed as being 2.5 V/4.0 π or
1.0 mA/2.0 π for the CT–0 circuits. More details about
performance of different type PLL loops, refer to Motorola
application note AN535.
The loop filter can take the form of a simple low pass filter.
A current output, type 2 filter will be used in this discussion
since it has the advantage of improved step response,
velocity, and acceleration.
The type 2 low pass filter discussed here is represented as
follows:
From
Phase
Detector To VCO
R2
C2C1
Figure 97. Loop Filter
with Additional Integrating Element
From Figure 97, capacitor C1 forms an additional
integrator, providing the type 2 response, and filters the
discrete current steps from the phase detector output. The
function of the additional components R2 and C2 is to create
a pole and a zero (together with C1) around the 0 dB point of
the open loop gain. This will create sufficient phase margin
for stable loop operation.
In Figure 98, the open loop gain and the phase is
displayed in the form of a Bode plot. Since there are two
integrating functions in the loop, originating from the loopfilter
and the VCO gain, the open loop gain response follows a
second order slope (–40 dB/dec) creating a phase of –180
degrees at the lower and higher frequencies. The filter
characteristic needs to be determined such that it is adding a
pole and a zero around the 0 dB point to guarantee sufficient
phase margin in this design (Qp in Figure 98).
Phase
Figure 98. Bode Plot of Gain and
Phase in Open Loop Condition
A
, O
p
e
n
L
oop
Ga
in
w
p
Open Loop Gain
Qp
–180
–90
0
0
The open loop gain including the filter response can be
expressed as:
Aopenloop
+
KpdKo(1
)
jw(R2C2))
jwKn
ǒ
jw
ǒ
1
)
jw
ǒ
R2C1C2
C1
)
C2
ǓǓǓ
(1)
The two time constants creating the pole and the zero in
the Bode plot can now be defined as:
T1
+
R2C1C2
C1
)
C2 T2
+
R2C2 (2)
By substituting equation (2) into (1), it follows:
Aopenloop
+ǒ
KpdKoT1
w2C1KnT2
Ǔǒ
1
)
jwT2
1
)
jwT1
Ǔ
(3)
The phase margin (phase + 180) is thus determined by:
Qp
+
arctan(wT2)–arctan(wT1)(4)
At w=wp, the derivative of the phase margin may be set to
zero in order to assure maximum phase margin occurs at wp
(see also Figure 98). This provides an expression for wp:
dQp
dw
+
0
+
T2
1
)
(wT2)2–T1
1
)
(wT1)2(5)
w
+
wp
+
1
T2T1
Ǹ
(6)
Or rewritten:
T1
+
1
wp2T2 (7)
MC13110A/B MC13111A/B
41
MOTOROLA RF/IF DEVICE DATA
By substituting into equation (4), solve for T2:
T2
+
tan
ǒ
Qp
2
)
p
4
Ǔ
wp(8)
By choosing a value for wp and Qp, T1 and T2 can be
calculated. The choice of Qp determines the stability of the
loop. In general, choosing a phase margin of 45 degrees is a
good choice to start calculations. Choosing lower phase
margins will provide somewhat faster lock–times, but also
generate higher overshoots on the control line to the VCO.
This will present a less stable system. Larger values of phase
margin provide a more stable system, but also increase
lock–times. The practical range for phase margin is 30
degrees up to 70 degrees.
The selection of wp is strongly related to the desired
lock–time. Since it is quite complicated to accurately
calculate lock time, a good first order approach is:
T_lock
[
3
wp(9)
Equation (9) only provides an order of magnitude for lock
time. It does not clearly define what the exact frequency
difference is from the desired frequency and it does not show
the effect of phase margin. It assumes, however, that the
phase detector steps up to the desired control voltage
without hesitation. In practice, such step response approach
is not really valid. The two input frequencies are not locked.
Their phase maybe momentarily zero and force the phase
detector into a high impedance mode. Hence, the lock times
may be found to be somewhat higher.
In general, wp should be chosen far below the reference
frequency in order for the filter to provide sufficient
attenuation at that frequency. In some applications, the
reference frequency might represent the spacing between
channels. Any feedthrough to the VCO that shows up as a
spur might affect adjacent channel rejection. In theory, with
the loop in lock, there is no signal coming from the phase
detector. But in practice leakage currents will be supplied to
both the VCO and the phase detector. The external
capacitors may show some leakage, too. Hence, the lower
wp, the better the reference frequency is filtered, but the
longer it takes for the loop to lock.
As shown in Figure 98, the open loop gain at wp is 1 (or
0 dB), and thus the absolute value of the complex open loop
gain as shown in equation (3) solves C1:
C1
+ǒ
KpdKoT1
w2KnT2
Ǔǒ
1
)
wpT2
Ǔ
2
ǒ
1
)
wpT1
Ǔ
2
Ǹ
(10)
With C1 known, and equation (2) solve C2 and R2:
C2
+
C1
ǒ
T2
T1
*
1
Ǔ
(11)
R2
+
T2
C2 (12)
The VCO gain is dependent on the selection of the
external inductor and the frequency required. The free
running frequency of the VCO is determined by:
f
+
1
2
p
LCT
Ǹ
(13)
In which L represents the external inductor value and CT
represents the total capacitance (including internal
capacitance) in parallel with the inductor. The VCO gain can
be easily calculated via the internal varicap transfer curve
shown below.
Figure 99. Varicap Capacitance
versus Control Voltage
0
15
, CAPACIT ANCE (pF)
14
12
13
11
10
9.0
8.0
7.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vcap
As can be derived from Figure 99, the varicap capacitance
changes 1.3 pF over the voltage range from 1.0 V to 2.0 V:
D
Cvar
+
1.3 pF
V(14)
Combining (13) with (14) the VCO gain can be determined
by:
Ko
+
1
jw
ȧ
ȧ
ȥ
ȡ
Ȣ
1
2
p
L
ǒ
CT
)
D
Cvar
2
Ǔ
Ǹ*
1
2
p
L
ǒ
CT
)
D
Cvar
2
Ǔ
Ǹȧ
ȧ
Ȧ
ȣ
Ȥ
(15)
Although the basic loopfilter previously described provides
adequate performance for most applications, an extra pole
may be added for additional reference frequency filtering.
Given that the channel spacing in a CT–0 telephone set is
based on the reference frequency, and any feedthrough to
MC13110A/B MC13111A/B
42 MOTOROLA RF/IF DEVICE DATA
the first LO may effect parameters like adjacent channel
rejection and intermodulation. Figure 100 shows a loopfilter
architecture incorporating an additional pole.
From
Phase
Detector To VCO
R2
C2C1
Figure 100. Loop Filter
with Additional Integrating Element
C3
R3
For the additional pole formed by R3 and C3 to be efficient,
the cut–off frequency must be much lower than the reference
frequency. However, it must also be higher than wp in order
not to compromise phase margin too much. The following
equations were derived in a similar manner as for the basic
filter previously described.
Similarly, it can be shown:
Aopenloop
+
–KpdKo
Knw2
ǒ
(C1
)
C2
)
C3)–w
2
C1C2C3R2R3
Ǔ)
1
)
jwT2
1
)
jwT1 (16)
In which:
T1
+
(C1
)
C2)T2
)
(C1C2)T3
C1
)
C2
)
C3
*
w2C1T2T3 (17)
T2
+
R2C2 T3
+
R3C3 (19)(18)
From T1 it can be derived that:
C2
+
(T1
)
T2)C3
*
C1
ǒ
T2
)
T3
*
T1
)
w2T1T2T3
Ǔ
T3
*
T1 (20)
In analogy with (10), by forcing the loopgain to 1 (0 dB) at
wp, we obtain:
C1(T1
)
T2)
)
C2T3
)
C3T2
+ǒ
KpdKo
Knwp2
Ǔ
1
)ǒ
wpT2
Ǔ
2
1
)ǒ
wpT1
Ǔ
2
Ǹ
(21)
Solving for C1:
C1
+
(T2
*
T1)T3C3
*
(T3
*
T1)T2C3
)
(T3
*
T1)
ǒ
KpdKoT1
wp2Kn
Ǔ
1
)ǒ
wpT2
Ǔ
2
1
)ǒ
wpT1
Ǔ
2
Ǹ
(T3
*
T1)T2
)
(T3
*
T1)T3
*ǒ
T2
)
T3
*
T1
)
wp2T1T2T3
Ǔ
T3 (22)
By selecting wp via (9), the additional time constant
expressed as T3, can be set to:
T3
+
1
Kwp(23)
MC13110A/B MC13111A/B
43
MOTOROLA RF/IF DEVICE DATA
The K–factor shown determines how far the additional
pole frequency will be separated from wp. Selecting too small
of a K–factor, the equations may provide negative
capacitance or resistor values. Too large of a K–factor may
not provide the maximum attenuation.
By selecting R3 to be 100 kΩ, C3 becomes known and C1
and C2 can be solved from the equations. By using equations
(8) and (7), time constants T2 and T1 can be derived by
selecting a phase margin. Finally , R2 follows from T2 and C2.
The following pages, the loopfilter components are
determined for both handset and baseset the US application
based on the equations described. Choose K to be
approximately five times wp (5.0wp).
In an application, wp is chosen to be 20 times less than the
reference frequency of 5.0 kHz and the phase margin has
been set to 45 degrees. This provides a lock time according
to (9) of about 2.0 ms (order of magnitude). With the adjacent
channels spaced at least 15 kHz away, reference
feedthrough at wp will not be directly disastrous but still, the
additional pole may be added in the loopfilter design for
added safety.
In an application, wp is chosen to be 20 times less than the
reference frequency of 5.0 kHz and the phase margin has
been set to 45 degrees. This provides a lock time according
to (9) of about 2.0 ms (order of magnitude). With the adjacent
channels spaced at least 15 kHz away, reference
feedthrough at wp will not be directly disastrous but still, the
additional pole may be added in the loopfilter design for
added safety.
Open Loop Gain (dB)
Figure 101. Open Loop Response Handset US
with Selected Values
f, FREQUENCY (Hz)
Phase
Margin
100 1000 10000 100000 1000000
–80
–40
0
40
80
0
20
40
60
80
Phase Margin (degrees)
Loop
Gain
From
Phase
Detector To VCO
22 k
.0686800 1000
100 k
Figure 102. Open Loop Response Baseset US
with Selected Values
From
Phase
Detector To VCO
18 k
.0828200 1000
100 k
Open Loop Gain (dB)
f, FREQUENCY (Hz)
Phase
Margin
100 1000 10000 100000 1000000
–80
–40
0
40
80
0
20
40
60
80
Phase Margin (degrees)
Loop
Gain
Figure 103. Handset US
Conditions
L = 470 uH Fref = 5.0 kHz
RF = 46.77 MHz Qp = 45 degrees
VCO center = 36.075 MHz wp = wref / 20 radians
Results Equations Select
Kpd = 159.2 uA/rad
KVCO = 3.56 Mrad/V (14), (15)
T2 = 1540 µs (8)
T1 = 264 µs (7)
T3 = 91 µs with K = 7
C1 = 7.6 nF (21) C1 = 6.8 nF
C2 = 70.9 nF (20) C2 = 68 nF
R2 = 21.7 kΩ(18) R2 = 22 kΩ
R3 = 100 kΩchoose: R3 = 100 kΩ
C3 = 909.5 pF (19) C3 = 1 nf
Figure 104. Baseset US
Conditions
L = 470 uH Fref = 5.0 kHz
RF = 49.83 MHz Qp = 45 degrees
VCO center = 39.135 MHz wp = wref / 20 radians
Results Equations Select
Kpd = 159.2 uA/rad
KVCO = 4.54 Mrad/V (14), (15)
T2 = 1540 µs (8)
T1 = 264 µs (7)
T3 = 91 µs with K = 7
C1 = 9.1 nF (21) C1 = 8.2 nF
C2 = 83.5 nF (20) C2 = 82 nF
R2 = 18.4 kΩ(18) R2 = 18 kΩ
R3 = 100 kΩchoose: R3 = 100 kΩ
C3 = 909.5 pF (19) C3 = 1 nf
MC13110A/B MC13111A/B
44 MOTOROLA RF/IF DEVICE DATA
SERIAL PROGRAMMABLE INTERFACE
Microprocessor Serial Interface
The Data, Clock, and Enable (“Data”, “Clk”, and “EN”
respectively) pins provide a MPU serial interface for
programming the reference counters, the transmit and
receive channel divide counters, the switched capacitor filter
clock counter , and various other control functions. The “Data”
and “Clk” pins are used to load data into the MC13111A/B
shift register (Figure 109). Figure 105 shows the timing
required on the “Data” and “Clk” pins. Data is clocked into the
shift register on positive clock transitions.
Figure 105. Data and Clock Timing Requirement
Data,
Clk, EN
Data
Clk
tsuDC
trtf
50%
50%
th
10%
90%
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the “EN” pin.
This is done in two steps. First, an 8–bit address is loaded
into the shift register and latched into the 8–bit address latch
register. Then, up to 16–bits of data is loaded into the shift
register and latched into the data latch register. It is specified
by the address that was previously loaded. Figure 106 shows
the timing required on the EN pin. Latching occurs on the
negative EN transition.
Figure 106. Enable Timing Requirement
Clk
EN
tsuEC
50%
50% 50%
trec
Previous Data Latched
Last
Clock First
Clock
50%
The state of the “EN” pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 107 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when “EN” is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the “EN” high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first. A minimum of four “Clk” rising edge
transition must occur before a negative “EN” transition will
latch data or an address into a register.
Figure 107. Microprocessor Interface
Programming Mode Diagrams
Data
Latch
8–Bit Address
EN
Data
EN
Address Register Programming Mode
16–Bit Data
Data Register Programming Mode
Latch
Latch
MSB
MSB LSB
LSB
The MPU serial interface is fully operational within 100 µs
after the power supply has reached its minimum level during
power–up (see Figure 108). The MPU Interface shift
registers and data latches are operational in all four power
saving modes; Inactive, Standby, Rx, and Active Modes.
Data can be loaded into the shift registers and latched into
the latch registers in any of the operating modes.
Figure 108. Microprocessor Serial
Interface Power–Up Delay
VCC tpuMPU
2.7 V
Data,
Clk, EN
MC13110A/B MC13111A/B
45
MOTOROLA RF/IF DEVICE DATA
Data Registers
Figure 109 shows the data latch registers and addresses
which are used to select each of each registers. Latch bits to
the left (MSB) are loaded into the shift register first. The LSB
bit must always be the last bit loaded into the shift register.
Bits proceeding the register must be “0’s” as shown.
Power–Up Defaults for Data Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The device is initially placed in the
Rx mode with all mutes active. The referenc e counter is set to
generate a 5.0 kHz reference frequency from a 10.24 MHz
crystal. The switched capacitor filter clock counter is set
properly for operation with a 10.24 MHz crystal. The Tx a n d Rx
counter registers are set for USA handset channel frequency,
number 21 (Channel 6 for previous FCC 10 Channel Band).
Figure 110 shows the initial power–up states for all latch
registers.
6. (00000110)
SCF Clock Dividers Latch (MC13111A/B only)
06–b Switched
Capacitor Filter
Clock Counter Latch
4–b Voltage
Reference Adjust MSB LSBMSB LSB
3–b Low Battery
Detect Threshold Select 00
Figure 109. Microprocessor Interface Data Latch Registers
14–b Tx CounterMSB LSB 1. (00000001)
2. (00000010)
3. (00000011)
4. (00000100)
5. (00000101)
6. (00000110)
Latch Address
Tx Counter Latch
Rx Counter Latch
Reference Counter Latch
Mode Control Latch
Gain Control Latch
SCF Clock Dividers Latch (MC13110A/B only)
12–b Reference CounterMSB LSB
U.K.
BS
Select
Stdby
Mode
4–b V ol Control Rx
Mode Tx
Mute Rx
Mute SP
Mute
5–b Tx Gain Control 5–b Rx Gain Control 5–b CD Threshold Control
U.K.
HS
Select
0ALC
Disable MPU
Clk 2 Limiter
Disable Clk
Disable
0
0
0
0
06–b Switched
Capacitor Filter
Clock Counter Latch
4–b Voltage
Reference Adjust MSB LSBMSB LSB
MSB LSB MSB LSB MSB LSB
MSB LSB
0
MPU
Clk 1 MPU
Clk 0
3–b Low Battery
Detect Threshold Select
14–b Rx CounterMSB LSB0 IP3
Increase
Tx Sbl
Bypass
7. (00000111)
Auxillary Latch
0 0 0 0 0 0 0 0 0 3–b Test Mode 4–b 1st LO Capacitor Selection
Rx Sbl
Bypass
MC13110A/B MC13111A/B
46 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 110. Latch Register Power–Up Defaults
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MSB
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
LSB
ÁÁÁÁÁ
ÁÁÁÁÁ
Register
ÁÁÁÁ
ÁÁÁÁ
Count
ÁÁ
ÁÁ
15
ÁÁÁ
ÁÁÁ
14
ÁÁÁ
ÁÁÁ
13
ÁÁ
ÁÁ
12
ÁÁÁ
ÁÁÁ
11
ÁÁ
ÁÁ
10
ÁÁÁ
ÁÁÁ
9
ÁÁÁ
ÁÁÁ
8
ÁÁ
ÁÁ
7
ÁÁÁ
ÁÁÁ
6
ÁÁ
ÁÁ
5
ÁÁÁ
ÁÁÁ
4
ÁÁÁ
ÁÁÁ
3
ÁÁ
ÁÁ
2
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
Tx
ÁÁÁÁ
ÁÁÁÁ
9966
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
Rx
ÁÁÁÁ
ÁÁÁÁ
7215
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
Ref
ÁÁÁÁ
ÁÁÁÁ
2048
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
Mode
ÁÁÁÁ
ÁÁÁÁ
N/A
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
Gain
ÁÁÁÁ
ÁÁÁÁ
N/A
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
SCF
(MC13110A/B)
ÁÁÁÁ
ÁÁÁÁ
31
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁ
ÁÁ
1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCF
(MC13111A/B)
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
31
ÁÁ
ÁÁ
ÁÁ
–
ÁÁÁ
Á
Á
Á
ÁÁÁ
0
ÁÁÁ
Á
Á
Á
ÁÁÁ
0
ÁÁ
ÁÁ
ÁÁ
0
ÁÁÁ
Á
Á
Á
ÁÁÁ
0
ÁÁ
ÁÁ
ÁÁ
1
ÁÁÁ
Á
Á
Á
ÁÁÁ
1
ÁÁÁ
Á
Á
Á
ÁÁÁ
1
ÁÁ
ÁÁ
ÁÁ
–
ÁÁÁ
Á
Á
Á
ÁÁÁ
–
ÁÁ
ÁÁ
ÁÁ
0
ÁÁÁ
Á
Á
Á
ÁÁÁ
1
ÁÁÁ
Á
Á
Á
ÁÁÁ
1
ÁÁ
ÁÁ
ÁÁ
1
ÁÁÁ
Á
Á
Á
ÁÁÁ
1
ÁÁ
ÁÁ
ÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
Aux
ÁÁÁÁ
ÁÁÁÁ
N/A
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁÁ
ÁÁÁ
–
ÁÁ
ÁÁ
–
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁ
ÁÁ
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTE: 12. Bits 6 and 7 in the SCF latch register are ”Don’t Cares” for the MC1311 1A/B since this part does not have a scrambler.
Tx and Rx Counter Registers
The 14 bit Tx and Rx counter registers are used to select
the transmit and receive channel frequencies. In the Rx
counter there is an “IP3 Increase” bit that allows the ability to
trade off increased receiver mixer performance versus
reduced power consumption. With “IP3 increase” = <1>,
there is about a 10 dB improvement in 1 dB compression and
3rd order intercept for both the 1st and 2nd mixers. However ,
there is also an increase in power supply current of 1.3 mA.
The power–up default for the MC13111A/B is “IP3 Increase”
= <0>. The register bits are shown in Figure 111.
Reference Counter Register
Reference Counter
Figure 113 shows how the reference frequencies for the
Rx and Tx loops are generated. All countries except the U.K.
require that the Tx and Rx reference frequencies be identical.
In this case, set “U.K. Base Select” and “U.K. Handset
Select” bits to “0”. Then the fixed divider is set to “1” and the
Tx and Rx reference frequencies will be equal to the crystal
oscillator frequency divided by the programmable reference
counter value.
The U.K. is a special case which requires a different
reference frequency value for Tx and Rx. For U.K. base
operation, set “U.K. Base Select” to “1”. For U.K. handset
operation, set “U.K. Handset Select” to “1”. The Netherlands
is also a special case. A 2.5 kHz reference frequency is used
for both the Tx and Rx reference and the total divider value
required is 4096. This is larger than the maximum divide
value available from the 12–bit reference divider (4095). In
this case, set “U.K. Base Select” to “1” and set “U.K. Handset
Select” to “1”. This will give a fixed divide by 4 for both the Tx
and Rx reference. Then set the reference divider to 1024 to
get a total divider of 4096.
Figure 111. Rx and Tx Counter Register Latch Bits
14–b Tx CounterMSB LSB
14–b Rx CounterMSB LSB
Tx Counter Latch
0
0
IP3
Increase
0
Rx Counter Latch
Figure 112. Reference Counter Register
12–b Ref CounterMSB LSB
U.K.
Handset
Select
U.K.
Base
Select
00
MC13110A/B MC13111A/B
47
MOTOROLA RF/IF DEVICE DATA
Figure 113. Reference Counter Register Programming Mode
0
0
1
1
0
1
0
1
1
25
4
4
1
4
25
4
LO2 Out
Tx Reference Frequency
12–b
Programmable
Reference
Counter
÷25
÷1.0
÷4.0
LO2 In
Rx Reference Frequency
U.K. Base
U.K. Handset
U.K. Handset
U.K. Base
U.K. Handset
Select U.K. Base
Select
LO2
Tx Divider
Value Rx Divider
Value Application
All but U.K. and Netherlands
U.K. Base Set
U.K. Hand Set
Netherlands Base and Hand Set
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 114. Reference Frequency and Divider Values
MC13110A/B
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MC13111A/B
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Reference
ÁÁÁÁÁ
ÁÁÁÁÁ
U.K. Base/
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
SC Filter
ÁÁÁÁÁ
ÁÁÁÁÁ
SC Filter
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Scrambler
ÁÁÁÁÁ
ÁÁÁÁÁ
Scrambler
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Crystal
ÁÁÁÁÁ
ÁÁÁÁÁ
Divider
ÁÁÁÁÁ
ÁÁÁÁÁ
Handset
ÁÁÁÁÁ
ÁÁÁÁÁ
Reference
ÁÁÁÁÁ
ÁÁÁÁÁ
Clock
ÁÁÁÁÁ
ÁÁÁÁÁ
Clock
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Modulation
ÁÁÁÁÁ
ÁÁÁÁÁ
Modulation
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Frequency
ÁÁÁÁÁ
ÁÁÁÁÁ
Value
ÁÁÁÁÁ
ÁÁÁÁÁ
Divider
ÁÁÁÁÁ
ÁÁÁÁÁ
Frequency
ÁÁÁÁÁ
ÁÁÁÁÁ
Divider
ÁÁÁÁÁ
ÁÁÁÁÁ
Frequency
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Divider
ÁÁÁÁÁ
ÁÁÁÁÁ
Frequency
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10.24 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
2048
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
5.0 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
31
ÁÁÁÁÁ
ÁÁÁÁÁ
165.16 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
40
ÁÁÁÁÁ
ÁÁÁÁÁ
4.129 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10.24 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
1024
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁÁ
ÁÁÁÁÁ
5.0 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
31
ÁÁÁÁÁ
ÁÁÁÁÁ
165.16 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
40
ÁÁÁÁÁ
ÁÁÁÁÁ
4.129 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
11.15 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
2230
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
5.0 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
34
ÁÁÁÁÁ
ÁÁÁÁÁ
163.97 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
40
ÁÁÁÁÁ
ÁÁÁÁÁ
4.099 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
12.00 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
2400
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
5.0 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
36
ÁÁÁÁÁ
ÁÁÁÁÁ
166.67 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
40
ÁÁÁÁÁ
ÁÁÁÁÁ
4.167 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
11.15 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
1784
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
6.25 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
34
ÁÁÁÁÁ
ÁÁÁÁÁ
163.97 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
40
ÁÁÁÁÁ
ÁÁÁÁÁ
4.099 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
11.15 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
446
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁÁ
ÁÁÁÁÁ
6.25 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
34
ÁÁÁÁÁ
ÁÁÁÁÁ
163.97 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
40
ÁÁÁÁÁ
ÁÁÁÁÁ
4.099 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
11.15 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
446
ÁÁÁÁÁ
ÁÁÁÁÁ
25
ÁÁÁÁÁ
ÁÁÁÁÁ
1.0 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
34
ÁÁÁÁÁ
ÁÁÁÁÁ
163.97 kHz
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
40
ÁÁÁÁÁ
ÁÁÁÁÁ
4.099 kHz
Figure 115. Mode Control Register
Stdby
Mode
4–b Volume
Control Rx
Mode Tx
Mute Rx
Mute SP
Mute
ALC
Disable Limiter
Disable Clk
Disable
0MPU
Clk 1 MPU
Clk 0
MPU
Clk 2
Reference Frequency Selection
The “LO2 In” and “LO2 Out” pins form a reference oscillator
when connected to an external parallel–resonant crystal. The
reference oscillator is also the second local oscillator for the
RF Receiver. Figure 114 shows the relationship between
different crystal frequencies and reference frequencies for
cordless phone applications in various countries. “LO2 In”
may also serve as an input for an externally generated
reference signal which is ac–coupled. The switched
capacitor filter 6–bit programmable counter must be
programmed for the crystal frequency that is selected since
this clock is derived from the crystal frequency and must be
held constant regardless of the crystal that is selected. The
actual switched capacitor clock divider ratio is twice the
programmed divider ratio due to the a fixed divide by 2.0 after
the programmable counter. The scrambler mixer modulation
frequency is the switched capacitor clock divided by 40 for
the MC13110A/B.
Mode Control Register
The power saving modes; mutes, disables, volume
control, and microprocessor clock output frequency are all
set by the Mode Control Register. Operation of the Control
Register is explained in Figures 115 through 119.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 116. Mute and Disable Control Bit Descriptions
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ALC Disable
ÁÁ
ÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Automatic Level Control Disabled
Normal Operation
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Tx Limiter Disable
ÁÁ
ÁÁ
ÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Tx Limiter Disabled
Normal Operation
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Clock Disable
(MC13110A/111A)
ÁÁ
ÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
MPU Clock Output Disabled
Normal Operation
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Clock Disable
(MC13110B/111B)
ÁÁ
ÁÁ
ÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Don’t Care
Normal Operation
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Tx Mute
ÁÁ
ÁÁ
ÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
T ransmit Channel Muted
Normal Operation
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Rx Mute
ÁÁ
ÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Receive Channel Muted
Normal Operation
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
SP Mute
ÁÁ
ÁÁ
ÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁ
Speaker Amp Muted
Normal Operation
MC13110A/B MC13111A/B
48 MOTOROLA RF/IF DEVICE DATA
Power Saving Operating Modes
When the MC13110A/B or MC13111A/B are used in a
handset, it is important to conserve power in order to prolong
battery life. There are five modes of operation for the
MC13110A/MC13111A; Active, Rx, Standby, Interrupt, and
Inactive. The MC13110B/MC13111B has three modes of
operation. They are Active, Rx, and Standby. In the Active
mode, all circuit blocks are powered. In the Rx mode, all
circuitry is powered down except for those circuit sections
needed to receive a transmission from the base. In the
Standby and Interrupt Modes, all circuitry is powered down
except for the circuitry needed to provide the clock output for
the microprocessor. In the Inactive Mode, all circuitry is
powered down except the MPU serial interface. Latch
memory is maintained in all modes. All mode functions are
the same for the MC13110B/MC13111B, except that there is
no Inactive mode. With the
B” version the MPU Clock is
always running so that there can never be a register reset if
the memory is disturbed. Figure 118 shows the control
register bit values for selection of each power saving mode
and Figure 1 18 shows the circuit blocks which are powered in
each of these operating modes.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 117. Power Saving Mode Selection
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Stdby Mode Bit
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Rx Mode Bit
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
“CD Out/
Hardware
Interrupt” Pin
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
Power
Saving
Mode
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MC13110A/MC13111A
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
Active
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
Rx
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
Standby
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
1 or High
Impedance
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
Inactive
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
Interrupt
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MC13110B/MC13111B [Note 14]
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
Active
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
Rx
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
X
ÁÁÁÁÁ
ÁÁÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
Standby
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
Interrupt
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTES: 13. “X” is a don’t care
14. MPU Clock Out is ”Always On”
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 118. Circuit Blocks Powered
During Power Saving Modes
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MC13110A/MC13111A
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MC13110B/MC13111B
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Circuit Blocks
ÁÁÁ
ÁÁÁ
Active
ÁÁÁ
ÁÁÁ
Rx
ÁÁÁÁ
ÁÁÁÁ
Standby
ÁÁÁ
ÁÁÁ
Inactive
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
“PLL V ref” Regulated
Voltage
ÁÁÁ
ÁÁÁ
X
ÁÁÁ
ÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X1
ÁÁÁ
ÁÁÁ
X1, 2
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MPU Serial Interface
ÁÁÁ
ÁÁÁ
X
ÁÁÁ
ÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁ
ÁÁÁ
X2
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
2nd LO Oscillator
ÁÁÁ
ÁÁÁ
X
ÁÁÁ
ÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MPU Clock Output
ÁÁÁ
ÁÁÁ
X
ÁÁÁ
ÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
X
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
RF Receiver and 1st LO
VCO
ÁÁÁ
ÁÁÁ
X
ÁÁÁ
ÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Rx PLL
ÁÁÁ
ÁÁÁ
X
ÁÁÁ
ÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Carrier Detect
ÁÁÁ
ÁÁÁ
X
ÁÁÁ
ÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Data Amp
ÁÁÁ
ÁÁÁ
X
ÁÁÁ
ÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Low Battery Detect
ÁÁÁ
ÁÁÁ
X
ÁÁÁ
ÁÁÁ
X
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Tx PLL
ÁÁÁ
ÁÁÁ
X
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁ
Rx and Tx Audio Paths
ÁÁÁ
X
ÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTES: 15. In Standby and Inactive Modes, “PLL Vref” remains powered
but is not regulated. It will fluctuate with VCC.
16. There is no Inactive mode for MC13110B/MC13111B.
Power Saving Application – Option 1 (MC13110B and
MC13111B Only)
When the handset is in standby, power can be reduced by
entering a “low power” mode and periodically switching to
“sniff” mode to check for incoming calls. Figure 119. shows
an application where the “Clk Out” pin provides the clock for
the MPU. In this application, the 2nd LO and MPU clock run
continuously . The MPU maintains control at all times and sets
the timing for transitions into the “sniff” mode. Power is saved
in the low power mode by putting the MC13110B/MC13111B
into its “Standby” mode. Only the 2nd LO and MPU clock
divider are active. By programming the MPU clock divider to
a large divide value of 20, 80, or 312.5 this will reduce the
MPU clock frequency and save power in the MPU.
MC13110A/B MC13111A/B
49
MOTOROLA RF/IF DEVICE DATA
Power Saving Application – Option 2 (MC13110A and
MC13111A Only)
In some handset applications it may be desirable to power
down all circuitry including the microprocessor (MPU). First
put the MC13110A/MC13111A into the Inactive mode. This
turns off the MPU Clock Output (see Figure 120) and
disables the microprocessor. Once a command is given to
switch the IC into an “Inactive” mode, the MPU Clock output
will remain active for a minimum of one reference counter
cycle (about 200 µs) and up to a maximum of two reference
counter cycles (about 400 µs). This is performed in order to
give the MPU adequate time to power down.
An external timing circuit should be used to initiate the
turn–on sequence. The “CD Out” pin has a dual function. In
the Active and Rx modes it performs the carrier detect
function. In the Standby and Inactive modes the carrier
detect circuit is disabled and the “CD Out” pin is in a “High”
state, because of an external pull–up resistor. In the Inactive
mode, the “CD Out” pin is the input for the hardware interrupt
function. When the “CD Out” pin is pulled “low”, by the
external timing circuit, the IC switches from the Inactive to the
Interrupt mode. Thereby turning on the MPU Clock Output.
The MPU can then resume control of the IC. The “CD Out”
pin must remain low until the MPU changes the operating
mode from Interrupt to Standby, Active, or Rx modes.
Figure 119. Power Saving Application – Option 1
Timer
MPU Clk
Divider
Clk In
SPI Port
Clk Out
SPI Port
LO2 Out
LO2 In
MC13110B
MC13111B Microprocessor
Mode
MPU Timer
MPU
Clock
Out
“Low Power” “Sniff”
Standby Mode Rx Mode
32.8, 128 or 512 kHz 4.0 MHz
MC13110A/B MC13111A/B
50 MOTOROLA RF/IF DEVICE DATA
Figure 120. Power Saving Application – Option 2 (MC13110A/MC13111A Only)
MPU Clk
Divider
Clk In
SPI Port
Clk Out
SPI Port
LO2 Out
LO2 In
MC13110A/
MC13111A Microprocessor
CD Out/
HW Interrupt
Interrupt
External Timer
VCC
Mode
EN
CD Out/Hardware Interrupt
MPU Clock Out
CD Out Low
Delay after MPU selects Inactive Mode to when CD turns off.
CD Turns Off
External Timer
Pulls Pin Low
MPU Initiates
Mode Change
Timer Output
Disabled
MPU Initiates
Inactive Mode
“MPU Clock Out” remains active for a minimum of one count of reference
counter after “CD Out/Hardware Interrupt” pin goes high
Active/RxInactive Interrupt Standby/Rx/Active
MPU “Clk Out” Divider Programming
The “Clk Out” signal is derived from the second local
oscillator . It can be used to drive a microprocessor (MPU) clock
input. This will eliminate the need for a separate crystal to drive
the MPU, thus reducing system cost. Figure 121 shows the
relationship between the second LO crystal frequency and the
clock output for each divide value. Figure 122 shows the “Clk
Out” register bit values. With a 10.24 MHz crystal, the divide by
312.5 gives the same clock frequency as a clock crystal and
allows the MPU to display the time on a LCD display without
additional external components.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 121. Clock Output Values
ÁÁÁÁÁ
ÁÁÁÁÁ
Crystal
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Clock Output Divider
ÁÁÁÁÁ
ÁÁÁÁÁ
Crystal
Frequency
ÁÁÁÁÁ
ÁÁÁÁÁ
2
ÁÁÁÁ
ÁÁÁÁ
2.5
ÁÁÁÁÁ
ÁÁÁÁÁ
3
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁ
ÁÁÁÁ
5
ÁÁÁÁÁ
ÁÁÁÁÁ
20
ÁÁÁÁ
ÁÁÁÁ
80
ÁÁÁÁÁ
ÁÁÁÁÁ
312.5
ÁÁÁÁÁ
ÁÁÁÁÁ
10.24 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
5.120 MHz
ÁÁÁÁ
ÁÁÁÁ
4.096 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
3.413 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
2.560 MHz
ÁÁÁÁ
ÁÁÁÁ
2.048 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
512 kHz
ÁÁÁÁ
ÁÁÁÁ
128 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
32.768 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
11.15 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
5.575 MHz
ÁÁÁÁ
ÁÁÁÁ
4.460 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
3.717 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
2.788 MHz
ÁÁÁÁ
ÁÁÁÁ
2.230 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
557 kHz
ÁÁÁÁ
ÁÁÁÁ
139 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
35.680 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
12.00 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
6.000 MHz
ÁÁÁÁ
ÁÁÁÁ
4.800 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
4.000 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
3.000 MHz
ÁÁÁÁ
ÁÁÁÁ
2.400 MHz
ÁÁÁÁÁ
ÁÁÁÁÁ
600 kHz
ÁÁÁÁ
ÁÁÁÁ
150 kHz
ÁÁÁÁÁ
ÁÁÁÁÁ
38.400 kHz
MC13110A/B MC13111A/B
51
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 122. Clock Output Divider
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
MPU Clk
Bit #2
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
MPU Clk
Bit #1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
MPU Clk
Bit #0
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Clk Out
Divider Value
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
2
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
3
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
5
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
2.5
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
20
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
80
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
312.5
MPU “Clk Out” Power–Up Default Divider Value
The power–up default divider value is “divide by 5”. This
provides a MPU clock of about 2.0 MHz after initial
power–up. The reason for choosing a relatively low clock
frequency at initial power–up is because some
microprocessors operate using a 3.0 V power supply and
have a maximum clock frequency of 2.0 MHz. After initial
power–up, the MPU can change the clock divider value and
set the clock to the desired operating frequency. Special care
was taken in the design of the clock divider to insure that the
transition between one clock divider value and another is
“smooth” (i.e. there will be no narrow clock pulses to disturb
the MPU).
MPU “Clk Out” Radiated Noise on Circuit Board
The clock line running between the MC13110A/B or
MC13111A/B and the microprocessor has the potential to
radiate noise. Problems in the system can occur , especially if
the clock is a square wave digital signal with large high
frequency harmonics. In order to minimize the radiated noise,
a 1000 Ω resistor is included on–chip in series with the “Clk
Out” output driver. A small capacitor or inductor with a
capacitor can be connected to the “Clk Out” line on the PCB
to form a one or two pole low pass filter. This filter should
significantly reduce noise radiated by attenuating the high
frequency harmonics on the signal line. The filter can also be
used to attenuate the signal level so that it is only as large as
required by the MPU clock input. To further reduce radiated
noise, the PCB signal trace length should be kept to a
minimum.
Volume Control Programming
The volume control adjustable gain block can be
programmed in 2 dB gain steps from –14 dB to +16 dB. The
power–up default value for the MC13110A/B and
MC13111A/B is 0 dB. (see Figure 123)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 123. Volume Control
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Volume Control
Bit #3
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Volume Control
Bit #2
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Volume Control
Bit #1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Volume Control
Bit #0
ÁÁÁÁ
ÁÁÁÁ
Volume
Control #
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Gain/Attenuation
Amount
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–14 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–12 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
2
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–10 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
3
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–8 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
4
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–6 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
5
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–4 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
6
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–2 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
7
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
8
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
2 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
9
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
4 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
10
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
6 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
11
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
8 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
12
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
10 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
13
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
12 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
14
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
14 dB
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
15
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
16 dB
MC13110A/B MC13111A/B
52 MOTOROLA RF/IF DEVICE DATA
Gain Control Register
The gain control register contains bits which control the Tx
V oltage Gain, Rx V oltage Gain, and Carrier Detect threshold.
Operation of these latch bits are explained in Figures 124,
125 and 126.
Tx and Rx Gain Programming
The Tx and Rx audio signal paths each have a
programmable gain block. If a Tx or Rx voltage gain, other
than the nominal power–up default, is desired, it can be
programmed through the MPU interface. Alternately, these
programmable gain blocks can be used during final test of the
telephone to electronically adjust for gain tolerances in the
telephone system (see Figure 125). In this case, the Tx and
Rx gain register values should be stored in ROM during final
test so that they can be reloaded each time the IC is powered
up.
Figure 124. Gain Control Latch Bits
5–b Tx Gain Control 5–b Rx Gain Control 5–b CD Threshold Control0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 125. Tx and Rx Gain Control
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Gain Control
Bit #4
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Gain Control
Bit #3
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Gain Control
Bit #2
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Gain Control
Bit #1
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Gain Control
Bit #0
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
Gain
Control #
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Gain/Attenuation
Amount
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
–
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
–
ÁÁÁÁÁ
ÁÁÁÁÁ
–
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
–
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
<6
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–9 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
6
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–9 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
7
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–8 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
8
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–7 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
9
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–6 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
10
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–5 dB
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
0
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
0
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
1
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
1
ÁÁÁÁ
Á
ÁÁ
Á
11
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
–4 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
12
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–3 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
13
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–2 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
14
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
–1 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
15
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
16
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
1 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
17
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
2 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
18
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
3 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
19
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
4 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
20
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
5 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
21
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
6 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
22
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
7 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
23
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
8 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
24
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
9 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
25
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
10 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
–
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
–
ÁÁÁÁÁ
ÁÁÁÁÁ
–
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
–
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
>25
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
10 dB
MC13110A/B MC13111A/B
53
MOTOROLA RF/IF DEVICE DATA
Carrier Detect Threshold Programming
The “CD Out” pin gives an indication to the microprocessor
if a carrier signal is present on the selected channel. The
nominal value and tolerance of the carrier detect threshold is
given in the carrier detect specification section of this
document. If a different carrier detect threshold value is
desired, it can be programmed through the MPU interface as
shown in Figure 126 below. Alternately, the carrier detect
threshold can be electronically adjusted during final test of
the telephone to reduce the tolerance of the carrier detect
threshold. This is done by measuring the threshold and then
by adjusting the threshold through the MPU interface. In this
case, it is necessary to store the carrier detect register value
in ROM so that the CD register can be reloaded each time the
combo IC is powered up. If a preamp is used before the first
mixer it may be desirable to scale the carrier detect range by
connecting an external resistor from the “RSSI” pin to
ground. The internal resistor is 187 kΩ.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 126. Carrier Detect Threshold Control
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
CD
Bit #4
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD
Bit #3
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD
Bit #2
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD
Bit #1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD
Bit #0
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
CD
Control #
ÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁ
Carrier Detect
Threshold
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–20 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–19 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
2
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–18 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
3
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–17 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–16 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
5
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–15 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
6
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–14 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
7
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–13 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
8
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–12 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
9
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–11 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
10
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–10 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
11
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–9 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
12
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–8 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
13
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–7 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
14
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–6 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
15
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–5 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
16
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–4 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
17
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–3 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
18
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–2 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
19
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
–1 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
20
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
0 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
21
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
1 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
22
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
2 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
23
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
3 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
24
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
4 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
25
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
5 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
26
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
6 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
27
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
7 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
28
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
8 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
29
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
9 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
30
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
10 dB
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
31
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
11 dB
MC13110A/B MC13111A/B
54 MOTOROLA RF/IF DEVICE DATA
Clock Divider/Voltage Adjust Register
This register controls the divider value for the
programmable switched capacitor filter clock divider, the low
battery detect threshold select, the voltage reference adjust,
and the scrambler bypass mode (MC13110A/B only).
Operation is explained in Figures 127 through 134. The Tx
and Rx Audio bits are don’t cares for either the MC13111A or
the MC13111B device. However, for the MC13110A/B, these
bits are defined. Figure 129 describes the operation. Note the
power–up default bit is set to <0>, which is the scrambler
bypass mode.
Low Battery Detect
The low battery detect circuit can be operated in
programmable and non–programmable threshold modes.
The non–programmable threshold mode is only available in
the 52 QFP package. In this mode, there are two low battery
detect comparators and the threshold values are set by
external resistor dividers which are connected to the REF1
and REF2 pins. In the programmable threshold mode,
several different threshold levels may be selected through
the “Low Battery Detect Threshold Register” as shown in Figure
128. The power–on default value for this register is <0,0,0> and
is the non–programmable mode. Figure 130 shows equivalent
schematics for the programmable and non–programmable
operating modes.
Figure 127. Clock Divider/Voltage Adjust Latch Bits
00 6–b Switched
Capacitor Filter Clock Counter Latch
4–b Voltage
Reference Adjust
3–b Low Battery
Detect Threshold Select
0 MSB MSBLSB LSB
(MC13111A/B)
Tx Sbl
Bypass Rx Sbl
Bypass 6–b Switched
Capacitor Filter Clock Counter Latch
4–b Voltage
Reference Adjust
3–b Low Battery
Detect Threshold Select
0 MSB MSBLSB LSB
(MC13110A/B)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 128. Low Battery Detect Threshold Selection
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Low Battery
Detect
Threshold
Select Bit #2
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Low Battery
Detect
Threshold
Select Bit #1
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Low Battery
Detect
Threshold
Select Bit #0
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Select #
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Operating Mode
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
Á
ÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁ
Nominal Low
Battery Detect
Threshold Value (V)
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Non–Programmable
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
N/A
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Programmable
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
2.850
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
2
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Programmable
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
2.938
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
3
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Programmable
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
3.025
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
4
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Programmable
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
3.200
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
5
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Programmable
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
3.288
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
6
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Programmable
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
3.375
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
7
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Programmable
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
3.463
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTE: 17. Nominal Threshold V alue is before electronic adjustment.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 129. MC13110A/B Bypass Mode Bit Description
(MC13110A/B Only)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Tx Scrambler
Bypass
ÁÁ
ÁÁ
ÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Tx Scrambler Post–Mixer LPF and Mixer Bypassed
Normal Operation with Tx Scrambler
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Rx Scrambler
Bypass
ÁÁ
ÁÁ
ÁÁ
ÁÁ
1
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Rx Scrambler Post–Mixer LPF and Mixer Bypassed
Normal Operation Rx Scrambler
MC13110A/B MC13111A/B
55
MOTOROLA RF/IF DEVICE DATA
Figure 130. Low Battery Detect Equivalent Schematics
Ref2
Ref 1
VB
50
51
52
BD2 Out
BD1 Out
16
14
Vref
Non–Programmable Threshold Mode: 52–QFP Package
VB
47
VCC Audio
BD Out
21
14
Vref
Programmable Threshold Mode: 48–LQFP Package
VB
52
VCC Audio
BD2 Out
23
16
Vref
Programmable Threshold Mode: 52–QFP Package
MC13110A/B MC13111A/B
56 MOTOROLA RF/IF DEVICE DATA
Voltage Reference Adjustment
An internal 1.5 V bandgap voltage reference provides the
voltage reference for the “BD1 Out” and “BD2 Out” low battery
detect circuits, the “PLL Vref” voltage regulator, the “VB”
reference, and all internal analog ground references. The
initial tolerance of the bandgap voltage reference is ±6%. The
tolerance of the internal reference voltage can be improved to
±1.5% through MPU serial interface programming. During
final test of the telephone, the battery detect threshold is
measured. Then, the internal reference voltage value is
adjusted electronically through the MPU serial interface to
achieve the desired accuracy level. The voltage reference
register value should be stored in ROM during final test so
that it can be reloaded each time the MC13110A/B or
MC13111A/B is powered up (see Figure 131).
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 131. Bandgap Voltage Reference Adjustment
ÁÁÁÁ
ÁÁÁÁ
Vref Adj.
Bit #3
ÁÁÁ
ÁÁÁ
Vref Adj.
Bit #2
ÁÁÁÁ
ÁÁÁÁ
Vref Adj.
Bit #1
ÁÁÁ
ÁÁÁ
Vref Adj.
Bit #0
ÁÁÁÁ
ÁÁÁÁ
Vref Adj.
#
ÁÁÁÁ
ÁÁÁÁ
Vref Adj.
Amount
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
–9.0%
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
–7.8%
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
2
ÁÁÁÁ
ÁÁÁÁ
–6.6%
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
3
ÁÁÁÁ
ÁÁÁÁ
–5.4%
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
4
ÁÁÁÁ
ÁÁÁÁ
–4.2%
ÁÁÁÁ
0
ÁÁÁ
1
ÁÁÁÁ
0
ÁÁÁ
1
ÁÁÁÁ
5
ÁÁÁÁ
–3.0%
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
6
ÁÁÁÁ
ÁÁÁÁ
–1.8%
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
7
ÁÁÁÁ
ÁÁÁÁ
–0.6%
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
8
ÁÁÁÁ
ÁÁÁÁ
+0.6 %
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
9
ÁÁÁÁ
ÁÁÁÁ
+1.8 %
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
10
ÁÁÁÁ
ÁÁÁÁ
+3.0 %
ÁÁÁÁ
1
ÁÁÁ
0
ÁÁÁÁ
1
ÁÁÁ
1
ÁÁÁÁ
11
ÁÁÁÁ
+4.2 %
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
12
ÁÁÁÁ
ÁÁÁÁ
+5.4 %
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
13
ÁÁÁÁ
ÁÁÁÁ
+6.6 %
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
14
ÁÁÁÁ
ÁÁÁÁ
+7.8 %
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
15
ÁÁÁÁ
ÁÁÁÁ
+9.0 %
Switched Capacitor Filter Clock Programming
A block diagram of the switched capacitor filter clock
divider is show in Figure 132. There is a fixed divide by 2 after
the programmable divider. The switched capacitor filter clock
value is given by the following equation;
(SCF Clock) = F(2nd LO) / (SCF Divider Value * 2).
The scrambler modulation clock frequency (SMCF) is
proportional to the SCF clock. The following equation defines
its value:
SMCF = (SCF Clock)/40
The SCF divider should be set to a value which brings the
SCF Clock as close to 165.16 kHz as possible. This is based
on the 2nd LO frequency which is chosen in Figure 114.
Figure 132. SCF Clock Divider Circuit
LO2 Out
6–b
Programmable
SCF Clock Counter
LO2 In
2nd LO
Crystal
SCF
Clock
Divide
By 2.0
Scrambler
Modulation
Clock
Divide
By 40
MC13110A/B
only
Corner Frequency Programming for MC13110A/B and
MC13111A/B
Four different corner frequencies may be selected by
programming the SCF Clock divider as shown in Figures 133
and 134. It is important to note, that all filter corner
frequencies will change proportionately with the SCF Clock
Frequency and Scrambler Modulation Frequency. The
power–up default SCF Clock divider value is 31.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 133. Corner Frequency Programming for 10.240 MHz 2nd LO
MC13110A/B
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MC13111A/B
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCF Clock
Divider
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
Total
Divide
Value
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
SCF Clock
Freq. (kHz)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Rx Upper
Corner
Frequency (kHz)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Tx Upper
Corner
Frequency (kHz)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Scrambler
Modulation
Frequency
(Clk/40) (kHz)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Scrambler
Lower Corner
Frequency (Hz)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Scrambler
Upper Corner
Frequency (kHz)
ÁÁÁÁÁ
ÁÁÁÁÁ
29
ÁÁÁÁ
ÁÁÁÁ
58
ÁÁÁÁ
ÁÁÁÁ
176.55
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
4.147
ÁÁÁÁÁ
ÁÁÁÁÁ
3.955
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
4.414
ÁÁÁÁÁ
ÁÁÁÁÁ
267.2
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3.902
ÁÁÁÁÁ
ÁÁÁÁÁ
29
30
ÁÁÁÁ
ÁÁÁÁ
58
60
ÁÁÁÁ
ÁÁÁÁ
176.55
170.67
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
4.147
4.008
ÁÁÁÁÁ
ÁÁÁÁÁ
3.955
3.823
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
4.414
4.267
ÁÁÁÁÁ
ÁÁÁÁÁ
267.2
258.3
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3.902
3.772
ÁÁÁÁÁ
31
ÁÁÁÁ
62
ÁÁÁÁ
165.16
ÁÁÁÁÁÁ
3.879
ÁÁÁÁÁ
3.700
ÁÁÁÁÁÁ
4.129
ÁÁÁÁÁ
250.0
ÁÁÁÁÁÁ
3.650
ÁÁÁÁÁ
ÁÁÁÁÁ
32
ÁÁÁÁ
ÁÁÁÁ
64
ÁÁÁÁ
ÁÁÁÁ
160.00
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3.758
ÁÁÁÁÁ
ÁÁÁÁÁ
3.584
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
4.000
ÁÁÁÁÁ
ÁÁÁÁÁ
242.2
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3.536
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTE: 18. All filter corner frequencies have a tolerance of ±3%.
19. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass
MC13110A/B MC13111A/B
57
MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 134. Corner Frequency Programming for 11.15 MHz 2nd LO
MC13110A/B
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MC13111A/B
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
SCF Clock
Divider
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
Total
Divide
Value
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
SCF Clock
Freq. (kHz)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Rx Upper
Corner
Frequency (kHz)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Tx Upper
Corner
Frequency (kHz)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Scrambler
Modulation
Frequency
(Clk/40) (kHz)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Scrambler
Lower Corner
Frequency (Hz)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Scrambler
Upper Corner
Frequency (kHz)
ÁÁÁÁÁ
ÁÁÁÁÁ
32
ÁÁÁÁ
ÁÁÁÁ
64
ÁÁÁÁ
ÁÁÁÁ
174.22
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
4.092
ÁÁÁÁÁ
ÁÁÁÁÁ
3.903
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
4.355
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
263.7
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3.850
ÁÁÁÁÁ
ÁÁÁÁÁ
32
33
ÁÁÁÁ
ÁÁÁÁ
64
66
ÁÁÁÁ
ÁÁÁÁ
174.22
168.94
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
4.092
3.968
ÁÁÁÁÁ
ÁÁÁÁÁ
3.903
3.785
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
4.355
4.223
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
263.7
255.7
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3.850
3.733
ÁÁÁÁÁ
ÁÁÁÁÁ
34
ÁÁÁÁ
ÁÁÁÁ
68
ÁÁÁÁ
ÁÁÁÁ
163.97
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3.851
ÁÁÁÁÁ
ÁÁÁÁÁ
3.673
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
4.099
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
248.2
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
3.624
ÁÁÁÁÁ
35
ÁÁÁÁ
70
ÁÁÁÁ
159.29
ÁÁÁÁÁÁ
3.741
ÁÁÁÁÁ
3.568
ÁÁÁÁÁÁ
3.982
ÁÁÁÁÁÁ
241.1
ÁÁÁÁÁÁ
3.520
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTES: 20. All filter corner frequencies have a tolerance of ±3%.
21. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass
Figure 135. Auxiliary Register Latch Bits
4–b 1st LO Capacitor
Selection
3–b Test ModeMSB LSB MSB LSB0000
00000
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 136. Digital Test Mode Description
ÁÁÁ
ÁÁÁ
TM #
ÁÁÁ
ÁÁÁ
TM 2
ÁÁÁ
ÁÁÁ
TM 1
ÁÁÁ
ÁÁÁ
TM 0
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Counter Under Test or
Test Mode Option
ÁÁÁÁÁ
ÁÁÁÁÁ
“Tx VCO”
Input Signal
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
“Clk Out” Output Expected
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Normal Operation
ÁÁÁÁÁ
ÁÁÁÁÁ
>200 mVpp
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
–
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Rx Counter
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.5 V
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Frequency/Rx Counter Value
ÁÁÁ
ÁÁÁ
2
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Tx Counter
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.5 V
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Frequency/Tx Counter Value
ÁÁÁ
ÁÁÁ
3
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Reference Counter + Divide by 4/25
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.5 V
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Frequency/Reference Counter Value * 100
ÁÁÁ
ÁÁÁ
4
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
SC Counter
ÁÁÁÁÁ
ÁÁÁÁÁ
0 to 2.5 V
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Frequency/SC Counter Value * 2
ÁÁÁ
ÁÁÁ
5
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ALC Gain = 10 Option
ÁÁÁÁÁ
ÁÁÁÁÁ
N/A
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
N/A
ÁÁÁ
ÁÁÁ
6
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ALC Gain = 25 Option
ÁÁÁÁÁ
ÁÁÁÁÁ
N/A
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
N/A
Auxiliary Register
The auxiliary register contains a 4–bit First LO Capacitor
Selection latch and a 3–bit Test Mode latch. Operation of
these latch bits are explained in Figures 135, 136 and 137.
Test Modes
Test modes are be selected through the 3–bit Test Mode
Register. In test mode, the “Tx VCO” input pin is multiplexed
to the input of the counter under test. The output of the
counter under test is multiplexed to the “Clk Out” output pin
so that each counter can be individually tested. Make sure
test mode bits are set to “0’s” for normal operation. Test
mode operation is described in Figure 136. During normal
operation, the “Tx VCO” input can be a minimum of 200 mVpp
at 80 MHz and should be AC coupled. Input signals should be
standard logic levels of 0 to 2.5 V and a maximum frequency of
16 MHz.
First Local Oscillator Programmable Capacitor Selection
There is a very large frequency difference between the
minimum and maximum channel frequencies in the 25
Channel U.S. standard. The internal varactor adjustment
range is not large enough to accommodate this large
frequency span. An internal capacitor with 15 programmable
capacitor values can be used to cover the 25 channel
frequency span without the need to add external capacitors
and switches. The programmable internal capacitor can also
be used to eliminate the need to use an external variable
capacitor to adjust the 1st LO center frequency during
telephone assembly. Figure 32 shows the schematic of the
1st LO tank circuit. Figure 137 shows the register control bit
values.
The internal programmable capacitor is composed of a
matrix bank of capacitors that are switched in as desired.
Programmable capacitor values between about 0 and 16 pF
can be selected in steps of approximately 1.1 pF. The internal
parallel resistance values in the table can be used to
calculate the quality factor (Q) of the oscillator if the Q of the
external inductor is known. The temperature coefficient of the
varactor is 0.08%/°C. The temperature coefficient of the
internal programmable capacitor is negligible. Tolerance on
the varactor and programmable capacitor values is ±15%.
MC13110A/B MC13111A/B
58 MOTOROLA RF/IF DEVICE DATA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 137. First Local Oscillator Internal Capacitor Selection
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
1st LO
Cap.
Bit 3
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
1st LO
Cap.
Bit 2
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
1st LO
Cap.
Bit 1
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
1st LO
Cap.
B it 0
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
1st LO
Cap.
Select
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Internal
Programmable
Capacitor
Value (pF)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Varactor
Value over
0. 3 to 2.5 V (pF)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Equivalent
Internal
Parallel
Resistance
at 40 MHz (kΩ)
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Equivalent
Internal
Parallel
Resistance
at 51 MHz (kΩ)
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁÁ
ÁÁÁÁÁ
0.0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
1200
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
736
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
2
ÁÁÁÁÁ
ÁÁÁÁÁ
0.6
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
79.3
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
48.8
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
1.7
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
131
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
80.8
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
5
ÁÁÁÁÁ
ÁÁÁÁÁ
2.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
31.4
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
19.3
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
6
ÁÁÁÁÁ
ÁÁÁÁÁ
3.9
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
33.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
20.8
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
7
ÁÁÁÁÁ
ÁÁÁÁÁ
4.9
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
66.6
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
41
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
4
ÁÁÁÁÁ
ÁÁÁÁÁ
6.0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
49.9
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
30.7
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
3
ÁÁÁÁÁ
ÁÁÁÁÁ
7.1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
40.7
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
25.1
ÁÁÁÁ
1
ÁÁÁÁ
0
ÁÁÁ
0
ÁÁÁÁ
0
ÁÁÁÁ
8
ÁÁÁÁÁ
8.2
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
27.1
ÁÁÁÁÁÁ
16.7
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
9
ÁÁÁÁÁ
ÁÁÁÁÁ
9.4
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
21.6
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
13.3
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
10
ÁÁÁÁÁ
ÁÁÁÁÁ
10.5
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
20.5
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
12.6
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
11
ÁÁÁÁÁ
ÁÁÁÁÁ
11.6
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
18.6
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
11.5
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
12
ÁÁÁÁÁ
ÁÁÁÁÁ
12.7
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
17.2
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
10.6
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
13
ÁÁÁÁÁ
ÁÁÁÁÁ
13.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
15.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
0
ÁÁÁÁ
ÁÁÁÁ
14
ÁÁÁÁÁ
ÁÁÁÁÁ
14.9
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
15.3
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.4
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁ
ÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁ
ÁÁÁÁ
15
ÁÁÁÁÁ
ÁÁÁÁÁ
16.0
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
9.7 to 5.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
14.2
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
8.7
MC13110A/B MC13111A/B
59
MOTOROLA RF/IF DEVICE DATA
OTHER APPLICATIONS INFORMATION
PCB Board Lay–Out Considerations
The ideal printed circuit board (PCB) lay out would be
double–sided with a full ground plane on one side. The
ground plane would be divided into separate sections to
prevent any audio signal from feeding into the first local
oscillator via the ground plane. Leaded components, can
likewise, be inserted on the ground plane side to improve
shielding and isolation from the circuit side of the PCB. The
opposite side of the PCB is typically the circuit side. It has the
interconnect traces and surface mount components. In cases
where cost allows, it may be beneficial to use multi–layer
boards to further improve isolation of components and
sensitive sections (i.e. RF and audio). For the CT–0 band, it
is also permissible to use single–sided PC layouts, but with
continuous full ground fill in and around the components.
The proper placement of certain components specified in
the application circuit may be very critical. In a lay–out
design, these components should be placed before the other
less critical components are inserted. It is also imperative
that all RF paths be kept as short as possible. Finally, the
MC13110A/B and MC13111A/B ground pins should be tied to
ground at the pins and VCC pins should have adequate
decoupling to ground as close to the IC as possible. In mixed
mode systems where digital and RF/Analog circuitry are
present, the VCC and VEE buses need to be ac–decoupled
and isolated from each other. The design must also take
great caution to avoid interference with low level analog
circuits. The receiver can be particularly susceptible to
interference as they respond to signals of only a few
microvolts. Again, be sure to keep the dc supply lines for the
digital and analog portions separate. Avoid ground paths
carrying common digital and analog currents, as well.
Component Selection
The evaluation circuit schematics specify particular
components that were used to achieve the results shown in
the typical curves and tables, but alternate components
should give similar results. The MC13110A/B and
MC131 1 1A /B IC are capable of matching the sensitivity, IMD,
adjacent channel rejection, and other performance criteria of
a multi–chip analog cordless telephone system. For the most
part, the same external components are used as in the
multi–chip solution.
VB and PLL Vref
VB is an internally generated bandgap voltage. It functions
as an ac reference point for the operational amplifiers in the
audio section as well as for the battery detect circuitry. This
pin needs to be sufficiently filtered to reduce noise and
prevent crosstalk between Rx audio to Tx audio signal paths.
A practical capacitor range to choose that will minimize
crosstalk and noise relative to start up time is 0.5 µf to 10 µf.
The start time for a 0.5 µf capacitor is approximately 5.0 ms,
while a 10µf capacitor is about 10 ms.
The “PLL V ref” pin is the internal supply voltage for the Rx
and Tx PLL’s. It is regulated to a nominal 2.5 V. The “VCC
Audio” pin is the supply voltage for the internal voltage
regulator . T wo capacitors with 10 µF and 0.01 µF values must
be connected to the “PLL Vref” pin to filter and stabilize this
regulated voltage. The “PLL Vref” pin may be used to power
other IC’s as long as the total external load current does not
exceed 1.0 mA. The tolerance of the regulated voltage is
initially ±8.0%, but is improved to ±4.0% after the internal
Bandgap voltage reference is adjusted electronically through
the MPU serial interface. The voltage regulator is turned off in
the Standby and Inactive modes to reduce current drain. In
these modes, the “PLL V ref” pin is internally connected to the
“VCC Audio” pin (i.e., the power supply voltage is maintained
but is now unregulated).
It is important to note that the momentary drop in voltage
below 2.5 V during this transition may affect initial PLL lock
times and also may trigger the reset. To prevent this, the PLL
Vref capacitor described above should be kept the same or
larger than the VB capacitor, say 10 µf as shown in the
evaluation and application diagrams.
DC Coupling
Choosing the right coupling capacitors for the compander
is also critical. The coupling capacitors will have an affect on
the audio distortion, especially at lower audio frequencies. A
useful capacitor range for the compander timing capacitors is
0.1 µf to 1.0 µf. It is advised to keep the compander
capacitors the same value in both the handset and baseset
applications.
All other dc coupling capacitors in the audio section will
form high pass filters. The designer should choose the
overall cut off frequency (–3.0 dB) to be around 200 Hz.
Designing for lower cut off frequencies may add unnecessary
cost and capacitor size to the design, while selecting too high
of a cut off frequency may affect audio quality. It is not
necessary or advised to design each audio coupling
capacitors for the same cut off frequency. Design for the
overall system cut off frequency. (Note: Do not expect the
application, evaluation, nor production test schematics to
necessarily be the correct capacitor selections.) The goals of
these boards may be different than the systems approach a
designer must consider.
For the supply pins (VCC Audio and VCC RF) choose a 10
µf in parallel with a high quality 0.01 µf capacitor. Separation
of the these two supply planes is essential, too. This is to
prevent interference between the RF and audio sections. It is
always a good design practice to add additional coupling on
each supply plane to ground as well.
The IF limiter capacitors are recommended to be 0.1 µf.
Smaller values lower the gain of the limiter stage. The
–3.0 dB limiting sensitivity and SINAD may be adversely
affected.
MC13110A/B MC13111A/B
60 MOTOROLA RF/IF DEVICE DATA
APPENDIX A
Figure 138.
12 Mix Out Lim In
2
BNC BNC
40
41
42
43
44
45
46
47
48
49
50
51
52
1 2 3 4 5 6 7 8 9 10 11 12 13
26
25
24
23
22
21
20
19
18
17
16
15
14
39 38 37 36 35 34 33 32 31 30 29 28 27
C38
0.01 C37
0.01 R34
txt C35
0.01
MC13111A
R37
txt C28
txt
F1
txt F2
txt
C31
0.1 C30
0.1 R28
txt L1
txt C53
1000 C54
0.01 C55
10 µ
R53 47 VCC
Gnd
RSSI
BNCDet Out
DA In
TxIn
Amp Out
TxOut
BD2Out
DA Out
BD1Out
RxPD PLL Vref TxPD TxVCO Clk Out CD Out
Connector
Controllor
RF In1
RF In2
LO2In
VcapCtrl
SA Out
E Out
Scr Out
BNC
BNC
BNC
C39 0.01
R39
49.9
R40
49.9 T2–L2
txt C40
txt
R44 150
C44
47µ
C45
220 p R45
47 k
R46
47 k C46 0.1
C47 0.47
C48 0.47
VCC
VCC VCC
R51a
82 k R50a
110 k
R51b
100 k R50b
100 k
C52
10 µ
R42a txt R4a txt
C42a
txt R42b
txt R4b
txt C1
txt C2
txt C3
0.1
XC
txt
C42b
txt C4
txt
C5a
0.01 R9
10 k R10
10 k R11
10 k R13
100 k
VCC
R14 100 k
R16 100 k
VCC
VCC
VCC
C18 0.47
C19
0.1
R20
47 k C20
220 p
R21 47 k C21 0.1
C23a 0.01
C24 0.01
C23b10 µ
C26 0.047
Mix1
In1Mix1
In2Mix1
Out Gnd
RF Mix2
Out Mix2
In SGnd
RF Lim
In Lim
C1 Lim
C2 VCC
RF Lim
Out Q
Coil
LO1In
LO1Out
VcapCtrl
Gnd Audio
SA Out
SA In
E Out
E Cap
E In
Scr Out
Ref2
Ref1
VB
RSSI
Det Out
RxAudio In
VCCAudio
DA In
TxIn
Amp Out
C In
C Cap
TxOut
BD2Out
DA Out
BD1
Out
LO2
In Vag PLL
VTx
PD Gnd
PLL Data EN Clk Clk
Out CD
Out
LO2
Out Rx
PD ref Tx
VCO
Mix Out Mix In
T1
txt
txt: see text
C5b
10 µ
Figure 138. Evaluation Board Schematic
MC13110A
MC13110A/B MC13111A/B
61
MOTOROLA RF/IF DEVICE DATA
APPENDIX A
Figure 139. Evaluation Board Bill of Materials for U.S. and French Application
USA Application Handset French Application Base
RF RF Crystal RF Ceramic
Comp. Number (50 Ω)RF Matched (50 Ω) (50 Ω)RF Matched
INPUT MATCHING
T1 n.m. Toko 1:5 n.m. n.m. Toko 1:5
292GNS–765A0 292GNS–765A0
C38 0.01 n.m. 0.01 0.01 n.m.
C39 0.01 n.m. 0.01 0.01 n.m.
10.7 MHz FILTER
F1 Ceramic Ceramic Crystal Ceramic Ceramic
R37 0 0 1.2 k 0 0
R34 360 360 3.01 k 360 360
450 kHz FILTER
F2 4 Element 4 Element 4 Element 4 Element 4 Element
Murata E Murata E Murata G Murata G Murata G
DEMODULATOR
L1 Q Coil Toko Q Coil Toko Ceramic Murata Ceramic Murata Ceramic Murata
7MCS–8128Z 7MCS–8128Z CDBM 450C34 CDBM 450C34 CDBM 450C34
R28 22.1 k 22.1 k 2.7 k 2.7 k 2.7 k
C28 10 p 10 p 390 p 390 p 390 p
OSCILLATOR
Xtal 10.24 10.24 11.15 11.15 11.15
C1 = 10 p C1 = 10 p C1 = 18 p C1 = 18 p C1 = 18 p
C2 18 p 18 p 33 p 33 p 33 p
C1 5–25 p 5–25 p 15 p + 5–25 p 15 p + 5–25 p 15 p + 5–25 p
FIRST LO
L2 0.47
Toko T1370 0.47
Toko T1370 0.22
Toko T1368 0.22
Toko T1368 0.22
Toko T1368
C40 HS/BS HS: 27 pF HS: 27 pF BS: 100 p BS: 100 p BS: 100 p
BS: 22 pF BS: 22 pF HS: 68 pF HS: 68 pF HS: 68 pF
LOOP FILTER HANDSET/BASESET
R4a HS: 0 HS: 0 HS: 0 HS: 0 HS: 0
BS: 0 BS: 0 BS: 0 BS: 0 BS: 0
R4b HS: 0 HS: 0 HS: 0 HS: 0 HS: 0
BS: 0 BS: 0 BS: 0 BS: 0 BS: 0
C4 HS: 6800 HS: 6800 HS: 8600 HS: 8600 HS: 8600
BS: 8200 BS: 8200 BS: 6800 BS: 6800 BS: 6800
R42a HS: 100 k HS: 100 k HS: 100 k HS: 100 k HS: 100 k
BS: 100 k BS: 100 k BS: 100 k BS: 100 k BS: 100 k
R42b HS: 22 k HS: 22 k HS: 18 k HS: 18 k HS: 18 k
BS: 18 k BS: 18 k BS: 22 k BS: 22 k BS: 22 k
C42a HS: 1000 HS: 1000 HS: 1000 HS: 1000 HS: 1000
BS: 1000 BS: 1000 BS: 1000 BS: 1000 BS: 1000
C42b HS: 0.068 HS: 0.068 HS: 0.082 HS: 0.082 HS: 0.082
BS: 0.082 BS: 0.082 BS: 0.068 BS: 0.068 BS: 0.068
MC13110A/B MC13111A/B
62 MOTOROLA RF/IF DEVICE DATA
APPENDIX B
APPLICATIONS CIRCUIT
RF Input
T RF–In
Gnd
Duplexer
12 3456
C2
0.1 R1
33 k R4
220 C4
0.01
Q1
MPSH10
Gnd
0.033
C3
Gnd
T1
R3
220
R2
100 k
8519N
P1 P2
P3
S1
S2
C6
47 µF
SP1
150–300Ω+
22 0.47µH
L3
R8
47 k R7 47 k
0.1
C10 C9
220
0.47
C12
VCC–A
0.47 C13
R10
110 k
R12
82 k
0.1
C16 0.1
C15 R13
100 k R11
100 k VB
10µF
C14
Gnd
C18
5.0–25 X1
10.24
C17
18
C19
0.1
100 k
1000
Gnd Gnd
C22
0.01 10µF
C23
C27
10
R16
30
3.3 µF
C24
22 µF
C25
R17
1.0 k
R18
680 R19
18 k T VT
4.7 µF
C26
Gnd
T VCO
R20
10 k
R21 10 k
R22 10 k
FL1
R36
330
FL2
23
123
1
C740.10
C73
0.10
C70
10
R34
22 k
Gnd
Gnd
VCC–RF P35
47
0.01
C72
C71
10 µF
T2
8128Z
RSSI
0.01
C86
C89
0.047 R32
8.2 k
R33
47 k
C87
1000
C88
0.15
0.01
C35
C34 33
0.1
C29
C28
0.47 VCC–A
T Audio
VCC–A
R25
100 k
R24
100 k
R23
100 k VCC Car–Detect
Batt Dead
R Data
Low Batt
Clk Out
Clk
EN
Data
C7
10
Gnd
Gnd
C33 3300
R28
27 k R30 680 k R29
27 k
0.047
C31
6800
C30
Gnd
Gnd
C84
0.01
R31
47
VCC–A VCC
3.9 k
1.0 k
10 µFC32 Gnd
Mic1 Mic
Electret
Figure 140. Basic Cordless Telephone Transceiver Application Circuit
12345678910111213
14
15
16
17
18
19
20
21
22
23
24
25
26
27282930313233343536373839
40
41
42
43
44
45
46
47
48
49
50
51
52 L
O
2
I
n
L
O
2
O
u
tV
a
g
R
x
P
D
L
L
V
r
e
f
P
T
x
P
D
n
d
P
L
L
GT
x
C
O
VD
a
t
aE
N
C
l
k
CD Out
u
t
O
C
l
k
VB
Ref1
Ref2
Scr Out
E In
Ecap
E Out
SA In
SA Out
Gnd Audio
Vcap Ctrl
LO1Out
LO1In
Mix1In1M
i
x
1
I
n
2
M
i
x
1
O
u
t
G
n
d
R
F
M
i
x
2
O
u
t
M
i
x
2
I
n
S
G
N
D
R
F
L
i
m
I
n
L
i
m
C
1
L
i
m
C
2
V
C
C
R
F
L
i
m
O
u
t
Q Coil
RSSI
Det Out
RxAudio In
VCC Audio
DA In
TxIn
Amp Out
C In
C Cap
TxOut
BD2Out
DA Out
BD1Out
IC1
R
xT
x
n
t
A
R26
R27
C5
n
d
Gn
d
G
n
d
GVCC–RF
x
x
x
x
x
MC13110A/B
Speaker
Figure 140.
++
++
+
+
1000
10
0.068
18 k 8200
µF
Legend:
If 1, then capacitor value = pF
If <1, then capacitor value = F
µ
≥
MC13111A/B
MC13110A/B MC13111A/B
63
MOTOROLA RF/IF DEVICE DATA
APPENDIX B
Batt1
V+
V– C54
10 FµC53
0.01
Gnd
VCC
VCC–RF
VCC–A
L6
56 Hµ
C55
0.22
Gnd
C58
10 Fµ
Gnd
Gnd
C56
0.1 C57
2.2 Fµ
TxAudio
R54
100 k
R53
68 k
R51
110 k R37
22 k
R39
110 k
TxData
R41
27 k R42
91 k
C40
10
C38
8.0
C37
6800
U5
C49
2.0
C48
120
L4
0.22 Hµ
C59
180 T VT
2109
VR2
1
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C46
36
C47
36 T VCO
R50
1.5 k
C45
10 Gnd
R49 100
C44
4700
13630
T3
Cx
7.5
P1
P2
P3
S1
S2 C41
51 T RF–In
51
L5
0.22 Hµ
C43
51
R47
75 k
R46
220 k
R45
110
R44
110
R43
110
0.022C50
0.022C51
0.022C52
C60
0.1 Fµ
x
VCC
VRx
x
x
IC2 MC2833D
Variable RF Osc
Decoupling RF Osc
Modulator RF
Mic Amp Tr 2
Mic Amp Tr 2
Gnd Tr 2
Tr 1 V
Tr 1 Tr 1
Reactance
Output
Input
Output
Input
Emitter
Base
Output
Base
Emitter
Collector
CC
Collector
+
+
+
Ω
Figure 140. Basic Cordless Telephone Transceiver Application Circuit (continued)
MC13110A/B MC13111A/B
64 MOTOROLA RF/IF DEVICE DATA
APPENDIX C – MEASUREMENT OF COMPANDER ATTACK/DECAY TIME
This measurement definition is based on EIA/CCITT
recommendations.
Compressor Attack Time
For a 12 dB step up at the input, attack time is defined as
the time for the output to settle to 1.5X of the final steady state
value.
Compressor Decay Time
For a 12 dB step down at the input, decay time is defined
as the time for the input to settle to 0.75X of the final steady
state value.
Decay Time
0.75X Final Value
1.5X Final Value
Attack Time
0 mV
0 mV
Input
Output
12 dB
Expander Attack
For a 6.0 dB step up at the input, attack time is defined as
the time for the output to settle to 0.57X of the final steady
state value.
Expander Decay
For a 6.0 dB step down at the input, decay time is defined
as the time for the output to settle to 1.5X of the final steady
state value.
Decay Time
1.5X Final Value
0.57X Final Value
Attack Time
0 mV
Input
Output
6.0 dB
0 mV
MC13110A/B MC13111A/B
65
MOTOROLA RF/IF DEVICE DATA
FB SUFFIX
PLASTIC PACKAGE
CASE 848B–04
(QFP–52)
ISSUE C
OUTLINE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION A T MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
DETAIL A
L
39
40 26
27
1
52 14
13
L
–A–
B
V
S
A–B
M
0.20 (0.008) D S
H
A–B0.05 (0.002)
S
A–B
M
0.20 (0.008) D S
C
–D–
B
V
–B–
S
A–B
M
0.20 (0.008) D S
H
A–B0.05 (0.002)
S
A–B
M
0.20 (0.008) D S
C
–H–
0.10 (0.004)
–C– SEATING
PLANE
DATUM
PLANE
M
G
H
E
CM
_
_
DETAIL C
U
_
Q
_
X
WK
T
R
DETAIL C
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.90 10.10 0.390 0.398
B9.90 10.10 0.390 0.398
C2.10 2.45 0.083 0.096
D0.22 0.38 0.009 0.015
E2.00 2.10 0.079 0.083
F0.22 0.33 0.009 0.013
G0.65 BSC 0.026 BSC
H––– 0.25 ––– 0.010
J0.13 0.23 0.005 0.009
K0.65 0.95 0.026 0.037
L7.80 REF 0.307 REF
M5 10 5 10
N0.13 0.17 0.005 0.007
Q0 7 0 7
R0.13 0.30 0.005 0.012
S12.95 13.45 0.510 0.530
T0.13 ––– 0.005 –––
U0 ––– 0 –––
V12.95 13.45 0.510 0.530
W0.35 0.45 0.014 0.018
X1.6 REF 0.063 REF
____
____
__
B
B
DETAIL A –A–, –B–, –D–
JN
D
F
BASE METAL
SECTION B–B
S
A–B
M
0.02 (0.008) D S
C
MC13110A/B MC13111A/B
66 MOTOROLA RF/IF DEVICE DATA
FTA SUFFIX
PLASTIC PACKAGE
CASE 932–02
(LQFP–48)
ISSUE D
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
A
A1
–T–
Z
0.200 (0.008) AB T–U
–U–
4X
Z0.200 (0.008) AC T–U
4X
B
B1
1
12
13 24
25
36
37
48
–Z–
S1
S
V
V1
P
AE AE
–T–, –U–, –Z–
DETAIL Y
DETAIL Y
BASE METAL
NJ
F
D
S
T–U
M
0.080 (0.003) Z S
AC
SECTION AE–AE
–AB–
–AC– AD
G0.080 (0.003) AC
M
_
TOP & BOTTOM
Q
_
W
K
X
E
C
H
0.250 (0.010)
GAUGE PLANE
R
9
DETAIL AD
DIM
AMIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
A1 3.500 BSC 0.138 BSC
B7.000 BSC 0.276 BSC
B1 3.500 BSC 0.138 BSC
C1.400 1.600 0.055 0.063
D0.170 0.270 0.007 0.011
E1.350 1.450 0.053 0.057
F0.170 0.230 0.007 0.009
G0.500 BASIC 0.020 BASIC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.500 0.700 0.020 0.028
M12 REF 12 REF
N0.090 0.160 0.004 0.006
P0.250 BASIC 0.010 BASIC
Q1 5 1 5
R0.150 0.250 0.006 0.010
S9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
V9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2 CONTROLLING DIMENSION: MILLIMETER.
3 DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4 DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5 DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6 DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7 DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014).
8 MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9 EXACT SHAPE OF EACH CORNER IS OPTIONAL.
__
____
OUTLINE DIMENSIONS
MC13110A/B MC13111A/B
67
MOTOROLA RF/IF DEVICE DATA
NOTES
MC13110A/B MC13111A/B
68 MOTOROLA RF/IF DEVICE DATA
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MC13110A/D
◊
