REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED 14-12-02 C. SAFFLE Make correction to the Output voltage differential test unit from "V" to "mV" as specified under Table I. - ro A REV SHEET REV A A SHEET 15 16 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil CHECKED BY RAJESH PITHADIA APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHARLES F. SAFFLE DRAWING APPROVAL DATE 14-10-28 REVISION LEVEL A MICROCIRCUIT, LINEAR, HIGH SPEED ECL CLOCK / DATA BUFFER, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 5962-13205 1 OF 16 5962-E082-15 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 R 13205 Federal stock class designator \ RHA designator (see 1.2.1) 01 V X A Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 Generic number ADCLK925 Circuit function High speed emitter coupled logic (ECL) clock / data buffer 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter X Descriptive designator Terminals CDFP4-F16 16 Package style Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 2 1.3 Absolute maximum ratings. 1/ Positive supply voltage (VCC) - negative supply voltage (VEE) ............................................... 6.0 V Input voltage and input current: Inputs D1, D1 ....................................................................................................................... VEE - 0.5 V to VCC + 0.5 V Inputs D1, D1 to center tap (VT) pin : (Current mode logic (CML) or positive emitter coupled logic (PECL) termination): ............40 mA Inputs D1 to D1 .................................................................................................................... 1.8 V Maximum voltage on output pins .............................................................................................. VCC + 0.5 V Maximum output current .......................................................................................................... 35 mA Input termination, VT to D1, D1 ............................................................................................... 2 V Voltage reference (VREF) ......................................................................................................... VCC - VEE Power dissipation (PD) ............................................................................................................. 380 mW Operating junction temperature (TJ) ......................................................................................... 150C Storage temperature range (TSTG) .......................................................................................... -65C to +150C Thermal resistance, junction to case (JC) ............................................................................... 125C/W 2/ Thermal resistance, junction to ambient (JA) .......................................................................... 132C/W 2/ 1.4 Recommended operating conditions. Positive supply voltage (VCC) - negative supply voltage (VEE) ............................................... 3.3 V Ambient operating temperature range (TA) .............................................................................. -55C to +125C 1.5 Operating performance characteristics. Unless otherwise specified, TA = +25C, VCC = VEE = 3.3 V, output terminated to 50 to (VCC - 2.0 V). Input capacitance (CIN) - pins D1, D1 .................................................................................... 1.0 pF Propagation delay temperature coefficient ............................................................................... 50 fs/C Propagation delay skew (output to output) ............................................................................... 10 ps maximum Random jitter ............................................................................................................................ 60 fs rms maximum 3/ Power supply rejection ............................................................................................................. 3 ps/V 4/ Output Swing supply rejection .................................................................................................. 26 dB 5/ Toggle rate VOD differential at 7.5 GHz ................................................................................... 0.45 VPP differential 6/ _______ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Measurement taken under absolute worst case conditions. Data taken with a thermal camera for highest power density location. See MIL-STD-1835 for average package JC thermal numbers. 3/ VID = 1600 mV, 8 V/ns, VICM = 1.85 V. 4/ Change in tPD per change in VCC, VCC - VEE = 3.0V = 20%. 5/ Change in output swing per change in VCC, VCC - VEE = 3.0V = 20%. 6/ VPP differential is VOD maximum - VOD minimum, which is VPP as measured by a differential probe. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 3 1.5 Operating performance characteristics - continued. Unless otherwise specified, TA = +25C, VCC = VEE = 3.3 V, output terminated to 50 to (VCC - 2.0 V). Additive phase noise: at 622.08 MHz, 10 Hz offset ................................................................................................... -138 dBc/Hz at 622.08 MHz, 100 Hz offset ................................................................................................. -144 dBc/Hz at 622.08 MHz, 1 kHz offset ................................................................................................... -152 dBc/Hz at 622.08 MHz, 10 kHz offset ................................................................................................. -159 dBc/Hz at 622.08 MHz, 100 kHz offset ............................................................................................... -161 dBc/Hz at 622.08 MHz, 1 MHz offset ................................................................................................ -161 dBc/Hz at 122.88 MHz, 10 Hz offset ................................................................................................... -135 dBc/Hz at 122.88 MHz, 100 Hz offset ................................................................................................. -145 dBc/Hz at 122.88 MHz, 1 kHz offset ................................................................................................... -153 dBc/Hz at 122.88 MHz, 10 kHz offset ................................................................................................. -160 dBc/Hz at 122.88 MHz, 100 kHz offset ............................................................................................... -161 dBc/Hz at 122.88 MHz, 1 MHz offset ................................................................................................ -161 dBc/Hz 1.6 Radiation features. Maximum total dose available (dose rate = 50 - 300 rads(Si)/s) .............................................. 100 krads(Si) 7/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. ______ 7/ These parts may be dose rate sensitive in a space environment and may demonstrate enhanced low dose rate effects. Radiation end point limits for the noted parameters are guaranteed only for the conditions specified in MIL-STD-883, method 1019, condition A. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 4 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 5 TABLE I. Electrical performance characteristics. Test Symbol Group A subgroups Conditions 1/ 2/ 3/ -55C TA +125C Device type VCC - VEE = 3.3 V, unless otherwise specified Limits Unit Min Max VEE + 1.6 VCC VEE + 1.6 VCC VEE VCC - 0.7 VEE VCC - 0.7 0.2 2.8 0.2 2.8 DC input characteristics section. Input voltage high level VIH 1,2,3 VID = VIH - VIL, 01 VIH, VIL applied during VOH, V VOL, VOD testing D,P,L,R Input voltage low level VIL 1 1,2,3 VID = VIH - VIL, 01 VIH, VIL applied during VOH, V VOL, VOD testing D,P,L,R Input differential range VID 1 1,2,3 VID = VIH - VIL, 01 VP-P VIH, VIL applied during VOH, VOL, VOD testing D,P,L,R Input current, D, D1 IIH, IIL 1 Open VT 1,2,3 D,P,L,R Input resistance, single ended mode 100 1 1,2,3 RIN D,P,L,R Input resistance, differential mode 01 100 01 45 58 45 58 100 110 100 110 VCC - 1.26 VCC - 0.76 3 VCC - 1.29 VCC - 0.76 1 VCC - 1.26 VCC - 0.76 1 1,2,3 RIND D,P,L,R A 01 1 DC output characteristics. Output voltage high level VOH 4/ 1,2 D,P,L,R 01 V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Group A subgroups Conditions 1/ 2/ 3/ -55C TA +125C Device type VCC - VEE = 3.3 V, unless otherwise specified Limits Unit Min Max VCC - 1.99 VCC - 1.54 VCC - 1.99 VCC - 1.54 610 1040 610 1040 2.14 2.29 2 2.05 2.35 3 2.10 2.40 1 2.14 2.29 1 1.90 2.05 2 1.80 2.10 3 1.85 2.15 1 1.90 2.05 170 280 170 280 290 DC output characteristics - continued. Output voltage low level VOL 4/ 1,2,3 D,P,L,R Output voltage differential VOD 1 4/ 1,2,3 D,P,L,R Reference voltage, VREF 1 IREF = 500 A D,P,L,R IREF = -500 A D,P,L,R RREF output resistance 01 1 output voltage Reference voltage, 01 1,2,3 RREF = VREF / IREF, 01 01 V mV V IREF = 500 A D,P,L,R 1 AC performance section. Propagation delay tPD VCC = 3.3 V 10%, 5/ 9,10,11 01 190 4,5,6 01 5 ps VICM = VREF, VID = 0.5 VP-P Toggle rate fmin 6/ 0.6 V differential output 5/ 5 5/ 7 GHz swing, VCC = 3.3 V 10% 0.5 V differential output swing, VCC = 3.3 V 10 % Rise / fall time t R / tF Measured 20% to 80% 5/ 9,10,11 01 30 85 ps See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 7 TABLE I. Electrical performance characteristics - continued. Test Symbol Group A subgroups Conditions 1/ 2/ 3/ -55C TA +125C Device type VCC - VEE = 3.3 V, unless otherwise specified Limits Min Unit Max Power supply section. Negative supply current IVEE 1,2,3 VCC - VEE = 3.3 V 10% D,P,L,R Positive supply current IVCC 01 1 1,2,3 VCC - VEE = 3.3 V 10% D,P,L,R -51 mA -51 01 1 97 mA 97 1/ Devices supplied to this drawing have been characterized through all levels P, L, R of irradiation and tested at the "P, L and R" levels. Pre and Post irradiation values are identical unless otherwise specified in Table I. When performing post irradiation electrical measurements for any RHA level, TA = +25C. 2/ These parts may be dose rate sensitive in a space environment and may demonstrate enhanced low dose rate effects. Radiation end point limits for the noted parameters are guaranteed only for the conditions specified in MIL-STD-883, method 1019, condition A. 3/ Unless otherwise specified, VCC - VEE = 3.3 V. Outputs terminated to 50 to (VCC - 2.0 V). 4/ This test is terminated to 50 to (VCC - 2.0 V). Tested at ( VCC, VIH,VIL ): (3.3, 3.3, 0.0); (3.3, 1.75, 1.55); (2.5, 2.5, 0.0); (2.5, 1.35, 1.15); (2.375, 2.375, 0.0), (2.375, 1.73,1.53), (3.63, 1.9, 1.7). 5/ Parameter is part of device initial characterization which is only repeated after design and process changes or with subsequent wafer lots. Parameter not tested post radiation. 6/ Functional automatic test equipment (ATE) production using nominal: VCC / VEE = 3.3 / 0.0 V, 50 to 1.3 V termination, VID = 800 mV differential input swing. Detection level for VOD 712 mV differential output swing (-5.0 dBm). STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 8 Device type 01 Case outline X Terminal number Terminal symbol 1 VREF 2 VT 3 D 4 D 5 NC/GND 6 NC/GND 7 NC/GND 8 NC/GND 9 VEE 10 VCC 11 Q2 12 Q2 13 Q1 14 Q1 15 VCC 16 VEE FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 9 Terminal symbol Description D Noninverting input. D Inverting input. NC/GND No internal circuitry connected to NC/GND pins so user may ground pin if desired. VEE Negative supply voltage. VCC Positive supply voltage. Q2 Inverting output 2. Q2 Noninverting output 2. Q1 Inverting output 1. Q1 Noninverting output 1. VREF VT Reference voltage. Reference voltage for biasing ac-coupled inputs. Center tap. Venter tap of 100 input resistor. FIGURE 1. Terminal connections - continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 10 FIGURE 2. Block diagram. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 11 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. 4.2.1 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections, and as specified herein. 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroups 7 and 8 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroups 4, 5, 6, 9, 10, and 11 are tested as part of device initial characterization and after design and process changes or with subsequent wafer lots as indicated in Table I. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 12 TABLE IIA. Electrical test requirements. Test requirements Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group A test requirements (see 4.4) Group C end-point electrical parameters (see 4.4) Group D end-point electrical parameters (see 4.4) Group E end-point electrical parameters (see 4.4) 1 Subgroups (in accordance with MIL-PRF-38535, table III) Device Device class Q class V 1 1,2,3, 1/ 4,5,6,9,10,11 1,2,3,4,5,6, 9,10,11 1,2,3,4,5,6, 9,10,11 1,2,3,4,5,6, 9,10,11 1,9 1,2,3, 1/ 2/ 3/ 4,5,6,9,10,11 1,2,3, 2/ 4,5,6,9,10,11 1,2,3, 2/ 3/ 4,5,6,9,10,11 1,2,3, 2/ 4,5,6,9,10,11 1,9 2/ 1/ PDA applies to subgroup 1. 2/ See table I for parameters tested or characterized for subgroups 4, 5, 6, 9, 10, and 11. 3/ Delta limits as specified in table IIB shall be required where specified, and the delta limits shall be computed with reference to the zero hour electrical parameters (see table I). TABLE IIB. Burn-in and operating life test delta parameters. TA = +25C. 1/ 2/ Parameters Symbol Delta limits Units Negative supply current IVEE 1 mA Positive supply current IVCC 1 mA Output voltage high level VOH 0.05 V Output voltage low level VOL 0.05 V Output voltage differential VOD 0.05 V RIN 2 RIND 2 Input resistance, single ended mode Input resistance, differential mode 1/ If device is tested at or below delta limit in table, no deltas are required. Deltas are performed at room temperature. 2/ Delta parameters are performed at VCC - VEE = 3.3 V. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 13 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C, after exposure, to the subgroups specified in table IIA herein. 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method 1019, condition A and as specified herein. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108. 6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0540. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-HDBK-103 and QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 14 6.7 Application notes. 6.7.1 Power / ground layout and bypassing. The subject device buffers are designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. A 1 F electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. In addition, multiple high quality 0.001 F bypass capacitors should be placed as close as possible to each of the VEE and VCC supply pins and should be connected to the GND plane with redundant vias. High frequency bypass capacitors should be carefully selected for minimum inductance and equivalent series resistance (ESR). Parasitic layout inductance should be strictly avoided to maximize the effectiveness of the bypass at high frequencies. 6.7.2 Output stages. The specified performance can be achieved only by using proper transmission line terminations. The outputs of the buffers are designed to directly drive 800 mV into 50 cable or microstrip / stripline transmission lines terminated with 50 referenced to VCC - 2 V. The output stage is shown in figure 3. The outputs are designed for best transmission line matching. If high speed signals must be routed more than a centimeter, either the microstrip or the stripline technique is required to ensure proper transition times and to prevent excessive output ringing and pulse width-dependent propagation delay dispersion. FIGURE 3. Simplified schematic diagram of the output stage. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 15 6.7.3 Optimizing high speed performance. As with any high speed circuit, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and cause oscillation. Discontinuities along input and output transmission lines can also severely limit the specified jitter performance by reducing the effective input slew rate. In a 50 environment, input and output matching have a significant impact on performance. The buffer provides internal 50 termination resistors for both D and D inputs. The return side should normally be connected to the reference pin provided. The termination potential should be carefully bypassed, using ceramic capacitors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. If the inputs are directly coupled to a source, care must be taken to ensure the pins are within the rated input differential and common-mode ranges. If the return is floated, the device exhibits 100 cross termination, but the source must then control the common-mode voltage and supply the input bias currents. There are electrostatic discharge (ESD)/clamp diodes between the input pins to prevent the application of excessive offsets to the input transistors. ESD diodes are not optimized for best ac performance. When a clamp is desired, it is recommended that appropriate external diodes be used. 6.7.4 Buffer random jitter. The device is specifically designed to minimize added random jitter over a wide input slew rate range. Provided sufficient voltage swing is present, random jitter is affected most by the slew rate of the input signal. Whenever possible, excessively large input signals should be clamped with fast Schottky diodes because attenuators reduce the slew rate. Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-13205 A REVISION LEVEL A SHEET 16 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 14-12-02 Approved sources of supply for SMD 5962-13205 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime -VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962R1320501VXA 24355 ADCLK925AF/QMLR 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 24355 Vendor name and address Analog Devices Route 1 Industrial Park P.O. Box 9106 Norwood, MA 02062 Point of contact: 7910 Triad Center Greensboro, NC 27409-9605 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.