167A690 182A934 32K x 8 Radiation Hardened Static RAM - 5 V Product Description Features Radiation * Fabricated with Bulk CMOS 0.8 m Process * Total Dose Hardness through 1x106 rad(Si) * Neutron Hardness through 1x1014 N/cm2 * Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s * Soft Error Rate of < 1x10-11 Upsets/Bit-Day * Dose Rate Survivability through 1x1012 rad(Si)/s * Latchup Free Other * Read/Write Cycle Times 30 ns (-55 C to 125C) * SMD Number 5962H92153 * Asynchronous Operation * CMOS or TTL Compatible I/O * Single 5 V 10% Power Supply * Low Operating Power * Packaging Options * 36-Lead Flat Pack (0.630" x 0.650") * 28-Lead DIP, MIL-STD-1835, CDIP2-T28 General Description The 32K x 8 radiation hardened static RAM is a high performance, low power device designed and fabricated in 0.8 m Radiation Hardened Complementary Metal Oxide Semiconductor (RHCMOS) technology. BAE SYSTEMS' device is designed for radiation environments using industry standard functionality. The memory can be personalized for either CMOS or Transistor Transistor Logic (TTL) input receivers. The SRAM operates over the full military temperature range and requires a single 5 V 10% power supply. Power consumption is typically less than 20 mW/MHz in operation, and less than 10 mW in the low power disabled mode. The SRAM read operation is fully asynchronous, with an associated typical access time of 20 nanoseconds. BAE SYSTEMS' bulk CMOS technology achieves radiation hardening via a combination of process technology enhancements and specific circuit improvements. BAE SYSTEMS * 9300 Wellington Road * Manassas, Virginia 20110-4122 A:11 Row Decoder ** * Functional Diagram 32,768 x 8 Memory Array E *** S Column Decoder Data Input/Output W G A:4 DQ:8 Signal Definitions A: 0-14 - Address input pins that select a particular eight-bit word within the memory array. DQ: 0-7 - Bi-directional data pins that serve as data outputs during a read operation and as data inputs during a write operation. S - Negative chip select, when at a low level, allows normal read or write operation. When at a high level, S forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables the data input buffers only. If this signal is not used, it must be connected to GND. W - Negative write enable, when at a low level, activates a write operation and holds the data output drivers in a high impedance state. When at a high level, W allows normal read operation. G - Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by S, W, and E. If this signal is not used it must be connected to GND. E - Chip enable, when at a high level allows normal operation. When at a low level, E forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the S input buffer. If this signal is not used, it must be connected to VDD. Truth Table Mode Write Read Standby Standby(3) Notes: Inputs(1),(2) E (4) High High X Low S Low Low High X W Low High X X G X Low X X I/O Data-In Data-Out High-Z High-Z 2 Power Active Active Standby Standby 1) VIN for don't care (X) inputs = VIL or VIH. 2) When G = high, I/O is high-Z. 3) To dissipate the minimum amount of standby power when in standby mode: S= VDD and E = GND. All other input levels may float. 4) E is tied high internally to the chip for the 28-DIP package. Absolute Maximum Ratings Applied Conditions(1) Storage Temperature Range (Ambient) Operating Temperature Range (TCASE) Positive Supply Voltage Input Voltage(2) Output Voltage(2) Minimum -65C Maximum +150C -55C -0.5 V +125C +7.0 V -0.5 V VDD+ 0.5 V VDD+ 0.5 V -0.5 V Power Dissipation(3) Lead Temperature (Soldering 5 sec) Electrostatic Discharge Sensitivity(4) 2.0 W +250C (Class II) Notes: 1) Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. All voltages are with reference to the module ground leads. 2) Maximum applied voltage shall not exceed +7.0 V. 3) Guaranteed by design; not tested. 4) Class as defined in MIL-STD-883, Method 3015. Recommended Operating Conditions Parameters(1) Supply Voltage Symbol VDD GND TC VIL VIH Minimum +4.5 Maximum +5.5 Supply Voltage Reference Case Temperature 0.0 -55 0.0 +125 Input Logic "Low" - CMOS 0.0 +1.5 Input Logic "Low" - TTL 0.0 Input Logic "High" - CMOS +3.5 +0.8 VDD Input Logic "High" - TTL +2.0 VDD Note: 1)All voltages referenced to GND. Power Sequencing The substrate of this module is connected directly to Ground. Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents: * Power-Up Sequence: GND, VDD, Inputs * Power-Down Sequence: Inputs, VDD, GND 3 Units Volt Volt Celsius Volt Volt DC Electrical Characteristics Test Symbol Device Type Test Conditions(1) Limits Minimum Maximum Units F = FMAX = 1/tAVAV(min) S = VIL = GND E = VIH = VDD No Output Load X3X 180 mA X4X X6X 130 mA IDD2 F = FMAX = 1/tAVAV(min) S = VIH = VDD E = VIL= GND X3X X4X X6X 2.0 1.2 2.0 mA mA mA Supply Current (Standby) IDD3 F = FMAX = 1/tAVAV(min) S = VIH = VDD E = VIL= GND X3X X4X X6X 2.0 1.2 2.0 mA mA mA Data Retention Current IDR VDD= 2.5 V X3X X4X X6X 1.0 0.4 1.0 mA mA mA High Level Output Voltage VOH Low Level Output Voltage VOL Data Retention Voltage VDR High Level Input Voltage VIH Supply Current (Cycling Selected) IDD1 Supply Current (Cycling De-Selected) Low Level Input Voltage IOH= -4 mA All IOH = -200 A IOL= 8 mA 4.2 VDD - 0.5 V 0.4 All IOL = 200 A VIL 0.05 All 2.5 CMOS 3.5 TTL CMOS 2.0 VDD = VDR V V V 1.5 TTL V 0.8 V Input Leakage IILK 0 V VIN 5.5 V All -5 5 A Output Leakage IOLK 0 V VOUT 5.5 V All -10 10 A Cin (2) By Design/ Verified By Characterization All 4 pF Cout (2) By Design/ Verified By Characterization All 7 pF Note: 1) Typical operating conditions: VDD = 5.0V; TA = 25 C, pre-radiation. -55C Tcase +125C; 4.5 V VDD 5.5 V; unless otherwise specified. 2) The worst case timing sequence of tWLZQ + tDUWH + tWHWL = tAVAV. Output Load Circuit 300 10% 2.8V 50 pF + 10% 4 Read Cycle AC Timing Characteristics(1) Worst Case By Speed -30 -40 -60 Symbol Minimum or Maximum Read Cycle Time tAVAV Minimum 30 40 60 ns Address Access Time tAVQV Maximum 30 40 60 ns Output Hold After Address Change tAXQX Minimum 5 5 5 ns Chip Select Access Time tSLQV Maximum 30 40 60 ns Chip Select to Output Active tSLQX Minimum 3 3 3 ns Chip Select to Output Disable tSHQZ Maximum CMOS - 10 TTL - 12 15 15 ns Chip Enable Access Time tEHQV Maximum 30 40 60 ns Chip Enable to Output Active tEHQX Minimum 3 3 3 ns Chip Disable to Output Disable tELQZ Maximum 15 ns Output Enable Access Time tGLQV Maximum 15 ns Output Enable to Output Active tGLQX Minimum 3 3 3 ns Maximum CMOS - 10 TTL - 12 15 15 ns Test Output Enable to Output Disable tGHQZ CMOS - 10 15 TTL - 12 CMOS - 12 CMOS - 15 TTL - 18 TTL - 15 Units Note: 1)Test conditions: input switching levels VIL/VIH = 0.5 V/VDD -0.5 V (CMOS), VIL/VIH = 0 V/3 V (TTL), input rise and fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL = 50 pF. For CL > 50 pF, derate access times by 0.02 ns/pF (typical). -55 C Tcase +125C; 4.5 V VDD 5.5 V; unless otherwise specified. Read Cycle Timing Diagram tAVAV Valid Address Address tAXQX tAVQV tSLQV S tSLQX tSHQZ tEHQV E tEHQX tELQZ tGLQV G tGLQX Data Out tSHQZ Valid Data High Impedance 5 Write Cycle AC Timing Characteristics(1) Worst Case By Speed -30 -40 -60 Units 35 40 40 ns Minimum 30 35 55 ns tSLWH Minimum 30 35 55 ns Data Setup to End of Write tDVWH Minimum 25 30 40 ns Address Setup to End of Write tAVWH Minimum 30 35 55 ns Data Hold After End of Write tWHDX Minimum 3 3 5 ns Address Setup to Start of Write tAVWL Minimum 0 0 0 ns Address Hold After End of Write tWHAX Minimum 0 0 0 ns Write Enable to Output Disable tWLQZ Maximum 12 15 15 ns Output Active After End of Write tWHQX Minimum 1 1 3 ns Write Pulse Width Access Time tWHWL Minimum 5 5 5 ns Chip Enable to End of Write tEHWH Minimum 30 35 55 ns Address Hold After End of Write tELWH Minimum 0 0 0 ns Symbol Minimum or Maximum Write Cycle Time tAVAV Minimum Write Pulse Width tWLWH Chip Select to End of Write Test Note: 1) Test conditions: input switching levels VIL/VIH = 0.5 V/VDD - 0.5 V (CMOS), VIL/VIH = 0 V/3 V (TTL), input rise and fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading = 50 pF. -55C Tcase +125C; 4.5 V VDD 5.5 V; unless otherwise specified. Write Cycle Timing Diagram tAVAV Valid Address Address tAVWH tSLWH tWHAX S E tEHWH tWLWH W tAVWL Data Out High Impedance tWHWL tWLQZ tWHQX High Impedance tDVWH tWHDX Data In High Impedance Valid Data 6 High Impedance Dynamic Electrical Characteristics Read Cycle The RAM is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (S), or chip enable (E) (refer to Read Cycle Timing diagram). To perform a valid read operation, both chip select and output enable (G) must be low and chip enable and write enable (W) must be high. The output drivers can be controlled independently by the G signal. Consecutive read cycles can be executed with S held continuously low, and with E held continuously high, and toggling the addresses. Write Cycle The write operation is synchronous with respect to the address bits, and control is governed by write enable (W), chip select (S), or chip enable (E) edge transitions (refer to Write Cycle Timing diagrams). To perform a write operation, both W and S must be low, and E must be high. Consecutive write cycles can be performed with W or S held continuously low, or E held continuously high. At least one of the control signals must transition to the opposite state between consecutive write operations. For an address-activated read cycle, S and E must be valid prior to or coincident with the activating address edge transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid tAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is tAVQV . When the RAM is operated at the minimum address-activated read cycle time, the data outputs will remain valid on the RAM I/O until tAXQX time following the next sequential address transition. The write mode can be controlled via three different control signals: W, S, and E. All three modes of control are similar except the S and E controlled modes actually disable the RAM during the write recovery pulse. Only the W controlled mode is shown in the table and diagram on the previous page for simplicity. However, each mode of control provides the same write cycle timing characteristics. Thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low. To control a read cycle with S, all addresses and E must be valid prior to or coincident with the enabling S edge transition. Address or E edge transitions can occur later than the specified setup times to S; however, the valid data access time will be delayed. Any address edge transition, that occurs during the time when S is low, will initiate a new read access, and data outputs will not become valid until tAVQV time following the address edge transition. Data outputs will enter a high impedance state tSHQZ time following a disabling S edge transition. To write data into the RAM, W and S must be held low and E must be held high for at least tWLWH /tSLSH /tEHEL time. Any amount of edge skew between the signals can be tolerated and any one of the control signals can initiate or terminate the write operation. For consecutive write operations, write pulses must be separated by the minimum specified tWHWL /tSHSL /tELEH time. Address inputs must be valid at least tAVWL /tAVSL /tAVEH time before the enabling W/S/E edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of tDVWH /tDVSH /tDVEL, and an address valid to end of write time of tAVWH /tAVSH /tAVEL also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling W/S/E edge transition must be a minimum of tWHAX /tSHAX /tELAX time and tWHDX /tSHDX /tELDX time, respectively. The minimum write cycle time is tAVAV. To control a read cycle with E, all addresses and S must be valid prior to or coincident with the enabling E edge transition. Address or S edge transitions can occur later than the specified setup times to E; however, the valid data access time will be delayed. Any address edge transition that occurs during the time when E is high will initiate a new read access, and data outputs will not become valid until tAVQV time following the address edge transition. Data outputs will enter a high impedance state tELQZ time following a disabling E edge transition. 7 Radiation Characteristics Total Ionizing Radiation Dose The SRAM will meet all stated functional and electrical specifications over the entire operating temperature range after a total ionizing radiation dose of 1x106 rad(Si). All electrical and timing performance parameters will remain within specifications after rebound at VDD = 5.5 V and T = 125C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and RAM product using 10 keV X-ray and Co60 radiation sources. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a dose rate of 1x105 rad(Si)/min at T = 25C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. The SRAM will meet any functional or electrical specification after exposure to a radiation pulse of 50 ns duration up to 1x1012 rad(Si)/s, when applied under recommended operating conditions. Note that the current conducted during the pulse by the RAM inputs, outputs, and power supply may significantly exceed the normal operating levels. The application design must accommodate these effects. Transient Pulse Ionizing Radiation The SRAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse of 50 ns duration up to 1x109 rad(Si)/s, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation is 10%), stiffening capacitance can be placed on the package between the package (chip) VDD and GND with the inductance between the package (chip) and stiffening capacitance kept to a minimum. If there are no operatethrough or valid stored data requirements, typical de-coupling capacitors should be mounted on the circuit board as close as possible to each device. Soft Error Rate The SRAM has a soft error rate (SER) performance of <1x10-11 upsets/bit-day, under recommended operating conditions. This hardness level is defined by the Adams 90% worst case cosmic ray environment. Neutron Radiation The SRAM will meet any functional or timing specification after a total neutron fluence of up to 1x1014 cm-2 applied under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV. Latchup The SRAM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Radiation Hardness Ratings (1),(2) Symbol Characteristics Conditions Minimum Maximum Units Total Dose MIL-STD-883, TM 1019.5 Condition A 1E + 06 rad(Si) Prompt Dose Upset 20 - 50 ns Pulse Width Tcase = 25C and 125C 1E + 09 rad(Si)/s Survivability 20 - 50 ns Pulse Width Tcase = 125C 1E + 12 rad(Si)/s SEU1 Single Event Upset(3) -55C Tcase 80C 1E - 11 Upsets/Bit-Day SEU2 Single Event Upset (3) -55C Tcase 125C 1E - 10 Upsets/Bit-Day RNF Neutron Fluence SEL Single Event Induced Latchup RTD RPRU RS 1E + 14 -55C Tcase 125C VDD = 5.5 V N/cm 2 Immune (4) Notes: 1) Measured at room temperature unless otherwise stated. Verification test per TRB approved test plan. 2) Device electrical characteristics are guaranteed for post irradiation levels at 25C. 3) 90% worst case particle environment, geosynchronous orbit, 0.025'' of aluminum shielding. Specification set using the CREME code upset rate calculation method with a 2 m epi thickness. 4) Immune for LET 120 MeV/mg/cm 2. 8 Tester AC Timing Characteristics TTL I/O Configuration Input Levels* CMOS I/O Configuration 3V . . . . . . . . . . . . . . . 1.5 V 0V........ VDD- 0.5 V . . . . . . . . . . . . . V /2 DD 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Sense Levels . . . . . . . . . . . . . V /2 DD . . . . . VDD- 0.4 V High Z . . . . . 0.4 V . . . . . VDD- 0.4 V High Z . . . . . 0.4 V 3.4 V . . . . 2.4 V . . . . High Z High Z 3.4 V . . . . 2.4 V . . . . High Z = 2.9 V High Z = 2.9 V *Input rise and fall times <5 ns Radiation Hardness Assurance Reliability BAE SYSTEMS provides a superior quality level of radiation hardness assurance for our products. The excellent product quality is sustained via the use of our qualified QML operation which requires process control with statistical process control, radiation hardness assurance procedures and a rigid computer controlled manufacturing operation monitoring and tracking system. BAE SYSTEMS' reliability starts with an overall product assurance system that utilizes a quality system involving all employees including operators, process engineers and product assurance personnel. An extensive wafer lot acceptance methodology, using in-line electrical data as well as physical data, assures product quality prior to assembly. A continuous reliability monitoring program evaluates every lot at the wafer level, utilizing test structures as well as product testing. Test structures are placed on every wafer, allowing correlation and checks within-wafer, wafer-to-wafer, and from lot-to-lot. The BAE SYSTEMS technology is built with resistance to radiation effects. Our product is designed to exhibit < 1e -11 fails/bit-day in a 90% worst case geosynchronous orbit under worst case operating conditions. Total dose hardness is assured by irradiating test structures on every lot and total dose exposure with Cobalt 60 testing performed quarterly on TCI lots to assure the product is meeting the QML radiation hardness requirements. Reliability attributes of the CMOS process are characterized by testing both irradiated and non-irradiated test structures. The evaluations allow design model and process changes to be incorporated for specific failure mechanisms, i.e., hot carriers, electromigration, and time dependent dielectric breakdown. These enhancements to the operation create a more reliable product. Screening Levels The process reliability is further enhanced by accelerated dynamic life tests of both irradiated and non-irradiated test structures. Screening and testing procedures from the customer are followed to qualify the product. BAE SYSTEMS has two QML screen levels (Q and V) to meet full compliant space applications. For limited performance and evaluation situations, BAE SYSTEMS offers an engineering screen level. A final periodic verification of the quality and reliability of the product is validated by a TCI (Technology Conformance Inspection). 9 Standard Screening Procedure QML Level Flow Comments Q V Wafer Lot Acceptance Serialization X X X X Alternate Method Used Die Traceability Destructive Bond Pull Sample X X X X Sample X MIL-STD-883, TM 2010 X X X X X X X X Internal Visual Temperature Cycle Constant Acceleration PIND Radiography Electrical Test Dynamic Burn-In Electrical Test Static Burn-In Final Electrical PDA X X Fine and Gross Leak External Visual X X X X X X X X 5.5 V, 125C, 144 Hours Meets Group A < 5% Fallout MIL-STD-883, TM 2009 Burn-In Circuit Stress Methodology There are two methods of burn-in defined. For "Static" burn-in, all possible addresses are written with a logic "1" for half of the burn-in duration and a logic "0" for the remaining half. For "Dynamic" burn-in, all possible addresses are written with alternating high and low data. V1 R R DQ0 E R R DIN W * * * * * G R R DQ7 A0 R S All I/O pins specified in the static and dynamic burn-in pin lists are driven through individual series resistors (1.6K 10%). The burn-in circuit diagram is shown at right. Voltage Levels * Vin(0): 0.0 V to + 0.4 V - VIL = Low level for all programmed signals *Vin(1): + 5.4 V to + 6.0 V - VIH = High level for all programmed signals * V1: + 5.5 V (-0% / +10%) - All VDD pins are tied to this level *Vsx: Float or GND - All GND pins are tied to this level Pin Listing The dynamic burn-in pin listing is shown at right. F = square wave, 100 KHz to 1.0 MHz. C1 = 0.1 F (10%) R = 1.6K (10%) C1 32K x 8 SRAM * * * A14 R Input A10 Signal F/2048 A6 A7 A8 Signal F/64 F/128 F/256 F/512 A11 A12 A13 F/4096 A9 F/1024 A14 Input A0 Signal F/2 Input A1 A2 A3 A4 F/4 F/8 F/16 F/32 A5 10 Input Signal W DIN F/65536 F/131072 F/8192 S F F/16384 F/32768 G E VIL VIH Packaging The 32K x 8 SRAM is offered in a custom 36-lead FP, 36-lead FPP or standard 28-lead DIP. All packages are constructed of multilayer ceramic (AI2O3) and feature internal power and ground planes. The FP also features a non-conductive ceramic tie bar on the lead frame. The purpose of the tie bar is to allow electrical testing of the device, while preserving the lead integrity during shipping and handling, up to the point of lead forming and insertion. Optional capacitors can be mounted to the package to maximize supply noise decoupling and increase board packing density. These capacitors attach directly to the internal package power and ground planes. This design minimizes resistance and inductance of the bond wire and package, both of which are critical in a transient radiation environment. All NC pins must be connected to either VDD, GND or an active driver to prevent charge build up in the radiation environment. (NC = no connect.) 36-Lead Flat Pack Pinout 28-Lead DIP Pinout GND VDD A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 NC VDD GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 Top View GND VDD W E A13 A8 A9 A11 G A10 S DQ7 DQ6 DQ5 DQ4 DQ3 VDD GND A14 1 28 VDD A12 2 A7 A6 3 4 27 26 W A13 25 A8 A5 5 A4 A3 6 7 24 23 A9 A11 A2 8 22 21 G A10 A1 A0 9 10 20 19 S DQ7 DQ0 11 18 DQ6 DQ1 DQ2 12 13 17 16 DQ5 DQ4 GND 14 15 DQ3 Top View 36-Lead Flat Pack H F G (2) Lead 18 J Lead 36 QML (USA) Date Code D Lead 1 B (Width) (1) Lead 19 A=.085 .010 B=.008 .002 C=.013 .004 D=.650 .010 E=.025 .002 F=.630 .007 G=.425 .004 H=1.490 J=.135 K=.080 L=.020 M=.285 N=.100 P=.040 Q=.130 R=.260 E (Pitch) M Notes: A 1) Part mark per device specification. C P K VDD VDD GND GND 2) "QML" may not be required per device specification. L 3) Dimensions are in inches. 4) Lead width: .008 .002. N Q 5) Lead height: .006 .002. 6) Unless otherwise specified, all R Lead 1 Indicator GND GND VDD VDD tolerances are .005". 11 36-Lead Flat Pack with Pedestal Package H F G (2) Lead 18 J Lead 36 QML (USA) Date Code D Lead 1 B (1) Lead 19 E L A=.137 .010 B=.008 .002 C=.013 .004 D=.650 .010 E=.025 .002 F=.630 .007 G=.425 .004 H=1.490 J=.135 K=.450 L=.285 Notes: 1) Part mark per device specification. 2) "QML" may not be required per device A C K specification. 3) Dimensions are in inches. 4) Lead width: .008 .002. VDD 5) Lead height: .006 .002. GND 6) Unless otherwise specified, all tolerances are .005". VDD 28-Lead DIP Lead 1 Indicator For 28-Lead DIP description, see MIL-STD-1835, type CDIP2-T28, configuration C, dimensions D-10. Ordering Information 32K x 8 CMOS Memory Device *Part Number 167A690 - X Y Z 32K x 8 TTL Memory Device *Part Number 182A934 - X Y Z X Package Designation 1 = 36-Lead FP 2 = 36-Lead FPP 3 = 28-Lead DIP Y Speed Designation 3 = 30 ns 4 = 40 ns 6 = 60 ns Z Screen Designation 1=QML VV 3=Engineering 4=QML VQ 5=QML QQ 7=Customer Specific Cleared for Public Domain Release BAE SYSTEMS reserves the right to make changes to any products herein to improve reliability, function or design. BAE SYSTEMS does not assume liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. BAE SYSTEMS An ISO 9001, AS9000, ISO 14001, and SEI CMM Level 4 Company 9300 Wellington Road, Manassas, VA 20110-4122 866-530-8104 http://www.iews.na.baesystems.com/space/ 0041_32K_8_SRAM.ppt (c)2001 BAE SYSTEMS, All Rights Reserved BAE SYSTEMS * 9300 Wellington Road * Manassas, Virginia 20110-4122