7
Dynamic Electrical Characteristics
Read Cycle
The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (S), or chip
enable (E) (refer to Read Cycle Timing diagram). To
perform a valid read operation, both chip select and output
enable (G) must be low and chip enable and write enable
(W) must be high. The output drivers can be controlled
independently by the G signal. Consecutive read cycles can
be executed with S held continuously low, and with E held
continuously high, and toggling the addresses.
For an address-activated read cycle, S and E must be valid
prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between
address edge transitions is permissible; however, data
outputs will become valid tAVQV time following the latest
occurring address edge transition. The minimum address
activated read cycle time is tAVQV . When the RAM is
operated at the minimum address-activated read cycle time,
the data outputs will remain valid on the RAM I/O until tAXQX
time following the next sequential address transition.
To control a read cycle with S, all addresses and E must be
valid prior to or coincident with the enabling S edge
transition. Address or E edge transitions can occur later
than the specified setup times to S; however, the valid data
access time will be delayed. Any address edge transition,
that occurs during the time when S is low, will initiate a new
read access, and data outputs will not become valid until
tAVQV time following the address edge transition. Data
outputs will enter a high impedance state tSHQZ time
following a disabling S edge transition.
To control a read cycle with E, all addresses and S must be
valid prior to or coincident with the enabling E edge
transition. Address or S edge transitions can occur later
than the specified setup times to E; however, the valid data
access time will be delayed. Any address edge transition
that occurs during the time when E is high will initiate a new
read access, and data outputs will not become valid until
tAVQV time following the address edge transition. Data
outputs will enter a high impedance state tELQZ time
following a disabling E edge transition.
Write Cycle
The write operation is synchronous with respect to the
address bits, and control is governed by write enable (W),
chip select (S), or chip enable (E) edge transitions (refer
to Write Cycle Timing diagrams). To perform a write
operation, both W and S must be low, and E must be
high. Consecutive write cycles can be performed with W
or S held continuously low, or E held continuously high. At
least one of the control signals must transition to the
opposite state between consecutive write operations.
The write mode can be controlled via three different
control signals: W, S, and E. All three modes of control
are similar except the S and E controlled modes actually
disable the RAM during the write recovery pulse. Only the
W controlled mode is shown in the table and diagram on
the previous page for simplicity. However, each mode of
control provides the same write cycle timing
characteristics. Thus, some of the parameter names
referenced below are not shown in the write cycle table or
diagram, but indicate which control pin is in control as it
switches high or low.
To write data into the RAM, W and S must be held low
and E must be held high for at least tWLWH /tSLSH /tEHEL time.
Any amount of edge skew between the signals can be
tolerated and any one of the control signals can initiate or
terminate the write operation. For consecutive write
operations, write pulses must be separated by the
minimum specified tWHWL /tSHSL /tELEH time. Address inputs
must be valid at least tAVWL /tAVSL /tAVEH time before the
enabling W/S/E edge transition, and must remain valid
during the entire write time. A valid data overlap of write
pulse width time of tDVWH /tDVSH /tDVEL, and an address valid to
end of write time of tAVWH /tAVSH /tAVEL also must be provided
for during the write operation. Hold times for address
inputs and data inputs with respect to the disabling W/S/E
edge transition must be a minimum of tWHAX /tSHAX /tELAX time
and tWHDX /tSHDX /tELDX time, respectively. The minimum write
cycle time is tAVAV.