Ultralow Power Step-Down Regulator
for Energy Harvesting
Data Sheet ADP5304
Rev. 0 Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Input supply voltage range: 2.15 V to 6.50 V
Operation down to 2.00 V typical
Ultralow, 260 nA typical quiescent current with no load
Selective output voltage from 1.2 V to 3.6 V (or 0.8 V to 5.0 V)
±2.5% output accuracy over the full temperature range
Output current up to 50 mA in hysteresis mode
VINOK flag to monitor the input voltage
100% duty cycle operation mode
Quick output discharge (QOD) option
Undervoltage lockout (UVLO), overcurrent protection (OCP),
and thermal shutdown (TSD) protection
10-lead, 3 mm × 3 mm LFCSP package
−40°C to +125°C operating junction temperature range
APPLICATIONS
Energy (gas, water) metering
Energy harvesting applications
Portable and battery-powered equipment
Medical applications
Keep-alive power supply
TYPICAL APPLICATION CIRCUIT
2.2µH
SW
PGND
FB
10µF
10µF
V
OUT
PVIN
MODE
EN
VID
V
IN
= 2.15V TO 6.5V
ADP5304
R0
OFF
ON
AGND VID0: 1.2V
VID1: 1.5V
VID2: 1.8V
VID3: 2.0V
VID4: 2.1V
VID5: 2.2V
VID6: 2.3V
VID7: 2.4V
VID8: 2.5V
VID9: 2.6V
VID10: 2.7V
VID11: 2.8V
VID12: 2.9V
VID13: 3.0V
VID14: 3.3V
VID15: 3.6V
EPAD
NC VINOK
13493-001
Figure 1.
GENERAL DESCRIPTION
The ADP5304 is a high efficient, ultralow quiescent current
step-down regulator that draws only 260 nA of quiescent
current to regulate the output at no load.
The ADP5304 runs from an input voltage range of 2.15 V to
6.50 V, allowing the use of the multiple alkaline, NiMH, and
Lithium cells, or the use of a high impedance power source. The
output voltage is selectable from 0.8 V to 5.0 V by an external
VID resistor to ground. The total solution requires only four
tiny external components.
The ADP5304 operates in hysteresis mode via connecting the
MODE pin to ground. In hysteresis mode, the regulator
achieves excellent efficiency at a power of less than 1 mW and
provides up to 50 mA of output load. The device enables very
efficient power management to achieve the collection of small
amounts of energy from the high impedance battery or the
energy harvester to charge up the conventional capacitor or
super capacitor.
The ADP5304 integrates an ultralow power comparator with a
factory programmable voltage reference to monitor the voltage
of the input power source. The voltage reference, with hysteresis, is
the threshold for the stopping and the starting of the switching,
allowing the use of the high impedance power source.
Other key features of the ADP5304 include separate enabling
and a QOD. Safety features, such as OCP, TSD, and input
UVLO are also included.
The ADP5304 is available in 10-lead, 3 mm × 3 mm LFCSP
package rated for the −40°C to +125°C junction temperature range.
ADP5304* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
EVALUATION KITS
•ADP5304 Evaluation Board
DOCUMENTATION
Data Sheet
•ADP5304: Ultralow Power Step-Down Regulator for
Energy Harvesting Data Sheet
User Guides
•UG-882: Evaluating the ADP5304 Ultralow Step-Down
Regulator
DESIGN RESOURCES
•ADP5304 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
View all ADP5304 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
ADP5304 Data Sheet
Rev. 0 | Page 2 of 17
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Detailed Functional Block Diagram .............................................. 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Buck Regulator Operational Mode .......................................... 11
Adjustable and Fixed Output Voltages .................................... 11
Undervoltage Lockout (UVLO) ............................................... 11
Enable/Disable ............................................................................ 11
VINOK Function ........................................................................ 11
Current Limit .............................................................................. 12
Short-Circuit Protection ............................................................ 12
Soft Start ...................................................................................... 12
Startup with Precharged Output .............................................. 12
100% Duty Operation ................................................................ 12
Active Discharge ......................................................................... 12
Thermal Shutdown .................................................................... 12
Applications Information .............................................................. 13
External Component Selection ................................................ 13
Selecting the Inductor ................................................................ 13
Output Capacitor ........................................................................ 13
Input Capacitor ........................................................................... 14
Layout Recommendations ........................................................ 14
Typical Application Circuits ......................................................... 15
Factory Programmable Options ................................................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
10/15—Revision 0: Initial Version
Data Sheet ADP5304
Rev. 0 | Page 3 of 17
DETAILED FUNCTIONAL BLOCK DIAGRAM
V
INO
K
INTERNAL
FEEDBACK
RESISTOR
DIVIDER
VINOK_TH
PVIN
CONTROL
LOGIC
I
LIM_HYS
STANDBY
0.808V
0A (HYS)
0.8V
DRIVER
PVIN PVIN
SW
PGND
FB
1.2V
0.4V
1.2V
0.4V
PVIN
UVLO
BAND GAP BIAS
AND
HOUSEKEEPING
KEEP ALIVE BLOCK
2.06V
2.00V
NC
EN
MODE
DRIVER
PVIN
VID
VINOK
AGND
2MHz
OSC
13493-002
Figure 2.
ADP5304 Data Sheet
Rev. 0 | Page 4 of 17
SPECIFICATIONS
VIN = 3.6 V, VOUT = 2.5 V, TJ = −40°C to +125°C for minimum and maximum specications, and TA = 25°C for typical specifications,
unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VIN 2.15 6.50 V
SHUTDOWN CURRENT ISHUTDOWN 18 40 nA VEN = 0 V, −40°C ≤ TJ ≤ +85°C
18 130 nA VEN = 0 V, −40°C ≤ TJ ≤ +125°C
QUIESCENT CURRENT
Operating Quiescent Current IQ 260 360 nA −40°C ≤ TJ ≤ +85°C
260 500 nA −40°C ≤ TJ ≤ +125°C
640 1500 nA 100% duty cycle operation, VIN = 3.0 V,
VOUT set as 3.3 V
UNDERVOLTAGE LOCKOUT UVLO
UVLO Threshold
Rising VUVLO_RISING 2.06 2.14 V
Falling VUVLO_FALLING 1.90 2.00 V
EN PIN
Input Voltage Threshold
High VIH 1.2 V
Low VIL 0.4 V
Input Leakage Current IEN_LEAKAGE 25 nA
FB PIN
Output Options by VID Resistor VOUT_OPT 0.8 5.0 V 0.8 V to 5.0 V in different factory option
Fixed VID Code Threshold Accuracy from Active
Mode to Standby Mode
VFB_FIX −0.75 +0.75 % TJ = 25°C
−2.5 +2.5 % −40°C ≤ TJ ≤ +125°C
Adjustable VID Code Threshold Accuracy from
Active Mode to Standby Mode
VFB_ADJ −3 +3 % −40°C ≤ TJ ≤ +125°C
Hysteresis of Threshold Accuracy from Active
Mode to Standby Mode
VFB (HYS) 1 %
Feedback Bias Current IFB 66 95 nA Output Option 0, VOUT = 2.5 V
25 45 nA Output Option 1, VOUT = 1.3 V
SW PIN
High-Side Power FET On Resistance RDS (ON) H 386 520 mΩ Pin to pin measurement
Low-Side Power FET On Resistance RDS (ON) L 299 470 mΩ Pin to pin measurement
Peak Current ILIM 265 mA
Minimum On Time tMIN_ON 40 70 ns
VINOK PIN
VINOK Monitor Threshold Range VVINOK (RISE) 2.05 5.15 V Factory programmable
VINOK Monitor Accuracy Range −1.5 +1.5 % TJ = 25°C
−3 +3 % −40°C ≤ TJ ≤ +125°C
VINOK Monitor Threshold Hysteresis VVINOK (HYS) 1.5 %
VINOK Rising Delay tVINOK_RISE 190 μs
VINOK Falling Delay tVINOK_FALL 130 μs
Leakage Current for the VINOK Pin IVINOK_LEAKAGE 0.1 1 μA
Output Low Voltage for the VINOK Pin VVINOK_LOW 50 100 mV IVINOK = 100 μA
SOFT START
Default Soft Start Time tSS 350 μs Factory trim, 1 bit (350 μs, 2800 μs)
Start-Up Delay tSTART_DELAY 2 ms Delay from the EN pin being pulled high
COUT DISCHARGE SWITCH ON RESISTANCE RDIS 290 Ω
THERMAL SHUTDOWN
Threshold TSHDN 142
C
Hysteresis THYS 127
C
Data Sheet ADP5304
Rev. 0 | Page 5 of 17
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
PVIN to PGND −0.3 V to +7 V
SW to PGND −0.3 V to PVIN + 0.3 V
FB to AGND −0.3 V to +7 V
VID to AGND −0.3 V to +7 V
EN to AGND −0.3 V to +7 V
VINOK to AGND −0.3 V to +7 V
MODE to AGND −0.3 V to +7 V
NC to AGND −0.3 V to +7 V
PGND to AGND −0.3 V to +0.3 V
Storage Temperate Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θ
JC Unit
10-Lead, 3 mm × 3 mm LFCSP 57 0.86 °C/W
ESD CAUTION
ADP5304 Data Sheet
Rev. 0 | Page 6 of 17
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
EN
NC
MODE
VID
FB
10
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LARGE
EXTERNAL COPPER GROUND PLANE UNDERNEATH THE
IC FOR THERMAL DISSIPATION.
9
8
7
6
PVIN
SW
PGND
AGND
VINOK
ADP5304
TOP VIEW
(Not to Scale)
13493-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 EN Enable Input for the Regulator. A logic low on this pin disables the regulator.
2 NC No Connect. Connect this pin to ground.
3 MODE Operating Mode Pin. Connect this pin to ground; the regulator operates in hysteresis mode.
4 VID Voltage Configuration Pin. Connect one resistor from this pin to ground to configure the output voltage of the
regulator.
5 FB Feedback Sensing Input for the Regulator.
6 VINOK Input Power-Good Signal. This open-drain output is the power-good signal for the input voltage.
7 AGND Analog Ground.
8 PGND Power Ground.
9 SW Switching Node Output for the Regulator.
10 PVIN Power Input for the Regulator.
EPAD
Exposed Pad. Solder the exposed pad to a large external copper ground plane underneath the IC for thermal
dissipation.
Data Sheet ADP5304
Rev. 0 | Page 7 of 17
TYPICAL PERFORMANCE CHARACTERISTICS
VIN =3.6 V, VOUT = 2.5 V, L1 = 2.2 µH, CIN = COUT = 10 F, fSW = 2 MHz, TA = 25°C, unless otherwise noted.
EFFICIENCY (%)
LOAD CURRENT (mA)
100
90
80
70
60
50
40
30
0.001 0.01 0.1 1 10
V
IN
= 2.5V
V
IN
= 3.0V
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.0V
V
IN
= 6.0V
13493-004
Figure 4. Hysteresis Efficiency vs. Load Current, VOUT = 1.2 V
EFFICIENCY (%)
LOAD CURRENT (mA)
100
90
80
70
60
50
40
0.001 0.01 0.1 1 10
V
IN
= 2.5V
V
IN
= 3.0V
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.0V
V
IN
= 6.0V
13493-005
Figure 5. Hysteresis Efficiency vs. Load Current, VOUT = 1.8 V
EFFICIENCY (%)
LOAD CURRENT (mA)
100
90
80
70
60
50
0.001 0.01 0.1 1 10
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.0V
V
IN
= 6.0V
13493-006
Figure 6. Hysteresis Efficiency vs. Load Current, VOUT = 3.3 V
EFFICIENCY (%)
LOAD CURRENT (mA)
100
90
80
70
60
50
40
0.001 0.01 0.1 1 10
V
IN
= 2.5V
V
IN
= 3.0V
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.0V
V
IN
= 6.0V
13493-007
Figure 7. Hysteresis Efficiency vs. Load Current, VOUT = 1.5 V
EFFICIENCY (%)
LOAD CURRENT (mA)
100
90
80
70
60
50
0.001 0.01 0.1 1 10
V
IN
= 3.6V
V
IN
= 3.0V
V
IN
= 4.2V
V
IN
= 5.0V
V
IN
= 6.0V
13493-008
Figure 8. Hysteresis Efficiency vs. Load Current, VOUT = 2.5 V
UVLO THRESHOLD (V)
TEMPERATURE (°C)
–40 25 85 125
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
RISING
FALLING
13493-022
Figure 9. UVLO Threshold, Rising and Falling vs. Temperature
ADP5304 Data Sheet
Rev. 0 | Page 8 of 17
SHUTDOWN CURRENT (nA)
V
IN
(V)
0
20
40
60
80
100
120
140
160
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
–40ºC
+25ºC
+85ºC
+125ºC
13493-012
Figure 10. Shutdown Current vs. VIN, EN = Low
HIGH-SIDE
R
DS (ON) H
(mΩ)
V
IN
(V)
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
100
200
300
400
500
600
700
–40ºC
+25ºC
+125ºC
13493-017
Figure 11. High-Side RDS (ON) H vs. VIN
FEEDBACK VOLTAGE (mV)
TEMPERATURE (°C)
–40 25 85 125
792
794
796
798
800
802
804
806
808
810
ACTIVE TO STANDBY
STANDBY TO ACTIVE
13493-019
Figure 12. Feedback Voltage vs. Temperature
QUIESCENT CURRENT (nA)
V
IN
(V)
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
–40ºC
+25ºC
+85ºC
+125ºC
100
150
200
250
300
350
13493-015
Figure 13. Quiescent Current vs. VIN
LOW-SIDE R
DS (ON) L
(mΩ)
V
IN
(V)
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
–40ºC
+25ºC
+125ºC
100
150
200
250
300
350
400
13493-020
Figure 14. Low-Side RDS (ON) L vs. VIN
CH4 140mA
4
1
2
CH2 2.00V
CH4 500mA Ω
CH1 100mV M 200µs A
T 39.60%
V
OUT
I
L
SW
13493-023
Figure 15. Steady Waveform, ILOAD = 1 mA (IL is the Inductor Current)
Data Sheet ADP5304
Rev. 0 | Page 9 of 17
1
2
4
3
V
IN
V
OUT
I
L
SW
CH1 1.40V
CH2 5.00V
CH4 500mA Ω
CH1 1.00V M 100µs A
T40.40%
CH3 2.00V
13493-016
Figure 16. Soft Start, ILOAD = 50 mA
1
4
V
OUT
(AC)
I
OUT
CH4 111mA
CH4 50.0mA Ω
CH1 50.0mV M 200µs A
T20.80%
13493-028
Figure 17. Load Transient, ILOAD from 0 mA to 50 mA
1
4
V
OUT
V
IN
I
L
CH3 4.80V
CH4 200mA Ω
CH1 1.00V M 10.0ms A
T40.20%
CH3 1.00V
13493-030
Figure 18. Input Voltage Ramp-Up and Ramp-Down
1
2
4
3
V
IN
V
OUT
I
L
SW
CH1 1.40V
CH2 5.00V
CH4 200mA Ω
CH1 1.00V M 100µs A
T40.40%
CH3 2.00V
13493-018
Figure 19. Soft Start with Precharge Function
1
2
4
V
OUT
(AC)
V
IN
I
L
SW
CH3 4.72V
CH2 5.00V
CH4 500mA Ω
CH1 50.0mV M 2.00ms A
T30.00%
CH3 2.00V
13493-029
Figure 20. Line Transient, ILOAD = 10 μA
1
2
3
CH3 980mVCH2 1.00V BW
CH1 2.00V BWM 4.00ms A
T20.20%
CH3 1.00V BW
13493-031
Figure 21. VINOK Function at a 3.0 V VINOK Threshold
ADP5304 Data Sheet
Rev. 0 | Page 10 of 17
1
2
4
V
OUT
I
L
SW
CH1 1.40V
CH2 5.00V
CH4 200mA Ω
CH1 1.00V M 10µs A
T40.40%
13493-041
Figure 22. Output Short Protection
1
2
3
V
IN
V
OUT
I
L
SW
CH2 1.56V
CH2 2.00V
CH4 2.00V Ω
CH1 1.00V M 20.0ms A
T40.20%
CH3 1.00V
13493-042
Figure 23. 260 μA Current Source Charge Up, 100 μF Output Capacitor with
100 μA Load Current, and 3.0 V VINOK Threshold
1
2
4
V
OUT
I
L
SW
CH2 1.68V
CH2 5.00V
CH4 200mV Ω
CH1 1.00V M 200µs A
T40.20%
13493-043
Figure 24. Output Short Recovery
3
1
2
EN
V
OUT
SW
CH3 1.64V
CH2 2.00V
CH1 1.00V M 4.00ms A
T 40.00%
CH3 2.00V
13493-037
Figure 25. Quick Output Discharge Function
Data Sheet ADP5304
Rev. 0 | Page 11 of 17
THEORY OF OPERATION
The ADP5304 is a high efficient, ultralow quiescent current
step-down regulator in a 10-lead LFCSP package, designed to
meet demanding performance and board space requirements.
The device enables direct connection to a wide input voltage
range of 2.15 V to 6.50 V, allowing the use of high impedance
power sources or energy harvester sources.
BUCK REGULATOR OPERATIONAL MODE
The ADP5304 buck regulator operates in hysteresis mode and
charges the output voltage slightly higher than its nominal
output voltage with PWM pulses via the regulation of constant
peak inductor current. When the output voltage increases until
the output sense signal exceeds the hysteresis upper threshold,
the regulator enters the standby mode. In standby mode, the
high-side and low-side MOSFET and a majority of the circuitry
are disabled to allow a low quiescent current, as well as high
efficiency performance. During standby mode, the output
capacitor supplies the energy into the load and the output
voltage decreases until it falls below the hysteresis comparator
lower threshold. Then, the buck regulator wakes up into active
mode and generates the PWM pulses to charge the output again.
The buck regulator is forced to operate in hysteresis mode via
connecting the MODE pin to ground. The regulator only draws
260 nA of quiescent current to regulate the output under zero load,
which allows the regulator to act as keep-alive power supply in
battery-powered applications or energy harvesting systems.
ADJUSTABLE AND FIXED OUTPUT VOLTAGES
The ADP5304 provides adjustable output voltage settings via
the connection of one resistor through the VID pin to AGND.
The VID detection circuitry works in the start-up period, and
the voltage ID code is sampled and held into the internal
register and does not change until the next power recycle.
Furthermore, the ADP5304 provides a fixed output voltage
programmed via the factory fuse. In this condition, connect
the VID pin to the PVIN pin.
For output voltage settings, the feedback resistor divider is built
in to the ADP5304, and the feedback pin (FB) must be tied
directly to the output. An ultralow power voltage reference and
an integrated high impedance (50 M, typical) feedback
divider network contribute to low quiescent current. Table 5
lists the output voltage options by the VID pin configurations. It
is recommended to use a 1% resistor.
Table 5. Output Voltage Options by the VID Pin
VID
Configuration
VOUT,
Factory Option 0 (V)
VOUT,
Factory Option 1 (V)
Short to ground 3.0 3.1
Short to PVIN 2.5 1.3
RVID = 499 kΩ 3.6 5.0
RVID = 316 kΩ 3.3 4.5
RVID = 226 kΩ 2.9 4.2
RVID = 174 kΩ 2.8 3.9
RVID = 127 kΩ 2.7 3.4
RVID = 97.6 kΩ 2.6 3.2
RVID = 76.8 kΩ 2.4 1.9
RVID = 56.2 kΩ 2.3 1.7
RVID = 43 kΩ 2.2 1.6
RVID = 32.4 kΩ 2.1 1.4
RVID = 25.5 kΩ 2.0 1.1
RVID = 19.6 kΩ 1.8 1.0
RVID = 15 kΩ 1.5 0.9
RVID = 11.8 kΩ 1.2 0.8
UNDERVOLTAGE LOCKOUT (UVLO)
The undervoltage lockout circuitry monitors the input voltage
level on the PVIN pin. If input voltage falls below 2.00 V
(typical), the regulator turns off. After the input voltage rises
above 2.06 V (typical), the soft start period initiates, and when
the EN pin is high, the regulator enables.
ENABLE/DISABLE
The ADP5304 includes a separate enable (EN) pin. A logic high
on the EN pin starts the regulator. Due to the low quiescent current
design, it is typical for the regulator to start switching after a
delay of a few milliseconds from the EN pin being pulled high.
A logic low on the EN pin immediately disables the regulator
and brings the regulator into extremely low current consumption.
VINOK FUNCTION
The ADP5304 includes an open-drain VINOK output that can
be used to indicate the input voltage status. The VINOK output
becomes active high when the input voltage on the PVIN pin is
above the reference threshold. When the input voltage falls below
the reference threshold, the VINOK pin goes low. Note that a
relatively long validation time of 130 µs typical exists for the
VINOK output status to change due to the ultralow power
comparator design.
ADP5304 Data Sheet
Rev. 0 | Page 12 of 17
The ADP5304 VINOK threshold also determines the time
when the buck regulator starts and stops switching. When the
input voltage is below the threshold, the regulator stops switching
in hysteresis mode. After the input source charges the input
capacitor voltage above a hysteresis from the threshold, the
regulator resumes switching. The regulator operates the input
voltage in a hysteresis window around the threshold considered
as the maximum power point tracking (MPPT). The high
impedance input power source or small input power application
employs the ADP5304 to charge the large output capacitor via
trickle charging.
Different VINOK thresholds are factory programmable from
2.05 V to 5.15 V in 50 mV steps. To order a device with options
other than the default options, contact your local Analog
Devices, Inc., sales or distribution representative.
CURRENT LIMIT
The buck regulators in the ADP5304 have protection circuitry
that limits the direction and the amount of current to a certain
level that flows through the high-side MOSFET and the low-side
MOSFET in cycle by cycle mode. The positive current limit on
the high-side MOSFET limits the amount of current that can
flow from the input to the output. The negative current limit on
the low-side MOSFET prevents the inductor current from
reversing direction and flowing out of the load.
SHORT-CIRCUIT PROTECTION
The buck regulators in the ADP5304 include frequency foldback to
prevent current runaway on a hard short. When the output voltage
at the feedback pin (FB) falls below 0.3 V typical, indicating the
possibility of a hard short at the output, the switching frequency
in active mode reduces to half of the internal oscillator frequency.
The reduction in the switching frequency allows more time for
the inductor to discharge, preventing a runaway of output current.
SOFT START
The ADP5304 has an internal soft start function that ramps the
output voltage in a controlled limitation upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the device. The typical soft start
time or the regulator is 350 μs.
A different soft start time (2800 μs) can be programmed for
ADP5304 via the factory fuse (see Table 11).
STARTUP WITH PRECHARGED OUTPUT
The buck regulators in the ADP5304 include a precharged
start-up feature to protect the low-side FETs from damage
during startup. If the output voltage is precharged before the
regulator is turned on, the regulator prevents reverse inductor
current—which discharges the output capacitor—until the
internal soft start reference voltage exceeds the precharged
voltage on the feedback pin.
100% DUTY OPERATION
When the input voltage approaches the output voltage, the
ADP5304 stops switching and enters 100% duty cycle operation. It
connects the output via the inductor and the internal high-side
power switch to the input. When the input voltage is charged
again and the required duty cycle falls to 95% typical, the buck
immediately restarts switching and regulation without allowing
overshoot on the output voltage. The ADP5304 draws an ultralow
quiescent current of only 640 nA typical during 100% duty cycle
operation.
ACTIVE DISCHARGE
The regulator in the ADP5304 integrates an optional, factory
programmable discharge switch from the switching node to
ground. This switch turns on when its associated regulator is
disabled, which helps discharge the output capacitor quickly.
The typical value of the discharge switch is 290 Ω for the regulator.
By default, the discharge function is not enabled. The active
discharge function can be enabled by the factory fuse
THERMAL SHUTDOWN
If the ADP5304 junction temperature exceeds 142C, the thermal
shutdown circuit turns the IC off, except for the internal linear
regulator. Extreme junction temperatures can be the result of
high current operation, poor circuit board design, or high ambient
temperature. A 15C hysteresis is included so that the ADP5304
does not return to operation after thermal shutdown until the
junction temperature falls below 127C. When the device exits
thermal shutdown, a soft start is initiated for each enabled channel.
Data Sheet ADP5304
Rev. 0 | Page 13 of 17
APPLICATIONS INFORMATION
This section describes the external components selection for the
ADP5304. The typical application circuit is shown in Figure 26.
2.2µH
SW
PGND
FB
10µF
MLCC
10µF
MLCC
V
OUT
= 1.8V
PVIN
MODE
EN
VID
V
IN
=
2.15V TO 6.50V
ADP5304
R1
19.6kΩ
VINOK
EPAD
NC
AGND
R2
1MΩ
13493-038
Figure 26. Typical Application Circuit
EXTERNAL COMPONENT SELECTION
The ADP5304 is optimized for operation with a 2.2 H inductor
and 10 F output capacitors for various output voltages using
the closed-loop compensation and adaptive slope compensation
circuits. The selection of components depends on the efficiency,
the load current transient, and other application requirements.
The trade-offs among performance parameters, such as
efficiency and transient response, are made by varying the
choice of external components.
SELECTING THE INDUCTOR
The high switching frequency of the ADP5304 allows the use of
small surface-mount power inductors. The dc resistance (DCR)
value of the selected inductor affects efficiency. In addition, it is
recommended to select a multilayer inductor rather than a
magnetic iron inductor because the high switching frequency
increases the core temperature rise and enlarges the core loss.
A minimum requirement of the dc current rating of the inductor
is for it to be equal to the maximum load current plus half of the
inductor current ripple (IL), as shown by the following equations:
SW
IN
OUT
OUTL fL V
V
VI –1
IPK = ILOAD (MAX) +
2L
I
where IPK is the peak inductor current.
Use the inductor series from the different vendors shown in Table 6.
OUTPUT CAPACITOR
Output capacitance is required to minimize the voltage overshoot,
the voltage undershoot, and the ripple voltage present on the
output. Capacitors with low equivalent series resistance (ESR)
values produce the lowest output ripple. Furthermore, use
capacitors such as X5R and X7R dielectric capacitors. Do not
use Y5V and Z5U capacitors, because they are unsuitable
choices due to their large capacitance variation over temperature
and their dc bias voltage changes. Because ESR is important,
select the capacitor using the following equation:
L
RIPPLE
COUT I
V
ESR
where:
ESRCOUT is the ESR of the chosen capacitor.
VRIPPLE is the peak-to-peak output voltage ripple.
Increasing the output capacitor value has no effect on stability
and may reduce output ripple and enhance load transient response.
ADP5304 can charge up the conventional capacitor or super
capacitor. When choosing the output capacitor value, it is
important to account for the loss of capacitance due to output
voltage dc bias.
Use the capacitor series from the different vendors shown in Table 7.
Table 6. Recommended Inductors
Vendor Model Inductance (μH) Dimensions (mm) DCR (mΩ) ISAT1 (A)
TDK MLP2016V2R2MT0S1 2.2 2.0 × 1.6 × 0.85 280 1.0
Wurth 74479889222 2.2 2.5 × 2.0 × 1.2 250 1.7
Coilcraft LPS3314-222MR 2.2 3.3 × 3.3 × 1.3 100 1.5
1 ISAT is the dc current at which the inductance drops 30% (typical) from its value without current.
Table 7. Input and Output Capacitors
Vendor Model Capacitance (μF) Size
Murata GRM188D71A106MA73 10 0603
Murata GRM21BR71A106KE51 10 0805
Murata GRM31CR60J107ME39 100 1206
ADP5304 Data Sheet
Rev. 0 | Page 14 of 17
INPUT CAPACITOR
An input capacitor is required to reduce the input voltage
ripple, input ripple current, and source impedance. Place the
input capacitor as close as possible to the PVIN pin. A low ESR
X7R or X5R capacitor is highly recommended to minimize the
input voltage ripple.
Use the following equation to determine the rms input current:
IN
OUTINOUT
MAXLOADRMS VVVV
II
)(
For most applications, a 10 µF capacitor is sufficient. The input
capacitor can be increased without any limit for better input
voltage filtering.
LAYOUT RECOMMENDATIONS
Figure 27 shows the typical printed circuit board (PCB) layout
for the ADP5304.
5.7
4.6
100kΩ
0201
EN 1
MODE3
PVIN
AGND
PGND
VID 4
ADP5304
TOP VIEW
FB 5
NC 2 SW
VINOK
10
7
8
9
6
10µF
10V/XR5
0603
L1
2.2µH
0603
10µF
6.3V/XR5
0603
13493-044
Figure 27. PCB Layout for the ADP5304
Data Sheet ADP5304
Rev. 0 | Page 15 of 17
TYPICAL APPLICATION CIRCUITS
The ADP5304 can be used as a keep-alive, ultralow power step-
down regulator to extend the battery life and load pulse current
capability with super capacitors (see Figure 28), and as a
battery-powered equipment or wireless sensor network
controlled by a microcontroller or a processor (see Figure 29).
The VINOK function can achieve the maximum power point
tracking.
2.2µH
SW
PGND
FB
1mF
R2
1MΩ
10µF
V
OUT
= 1.8V
ADC/RF/AFE
MCU
(ALWAYS ON)
PVIN
VID
EN
MODE
V
IN
= 2.0V TO 3.0V
ADP5304
R1
19.6kΩ
1% VINOK
AGND
NC
CR2032
13493-039
Figure 28. Typical ADP5304 Application with a Coin Cell Battery (CR2032)
2.2µH
SW
PGND
FB
10mF
R2
1MΩ
10µF
V
OUT
= 1.8V
ADC/RF/AFE
MCU
(ALWAYS ON)
PVIN
VID
EN
MODE
ADP5304
R1
19.6kΩ
1%
VINOK
AGND
NC
PIEZOELECTRI
C
HARVESTER
13493-040
Figure 29. Typical ADP5304 Application with a Piezoelectric Harvester
ADP5304 Data Sheet
Rev. 0 | Page 16 of 17
FACTORY PROGRAMMABLE OPTIONS
To order a device with options other than the default options,
contact your local Analog Devices sales or distribution
representative.
Table 8. Output Voltage VID Setting Options
Option Description
Option 0 VID resistor to set the output voltage as follows:
1.2 V, 1.5 V, 1.8 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V,
2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.3 V, 3.6 V, 3.3 V (default)
Option 1 VID resistor to set the output voltage as follows:
0.8 V, 0.9 V, 1.0 V, 1.1 V, 1.3 V, 1.4 V, 1.6 V, 1.7 V, 1.9 V,
3.1 V, 3.4 V, 3.9 V, 4.2 V, 4.5 V, 5.0 V
Table 9. VINOK Monitor Threshed Options
Option VINOK Monitor Threshold (V)
Option 0 2.05
Option 1 2.10
Option 2 2.15
Option 3 2.20
… …
Option 20 3.00 (default)
… …
Option 62 5.10
Option 63 5.15
Table 10. Output Discharge Functionality Options
Option Description
Option 0 Output discharge function disabled for buck
regulator (default)
Option 1 Output discharge function enabled form buck
regulator
Table 11. Soft Start Timer Options
Option Description
Option 0 350 μs (default)
Option 1 2800 μs
Data Sheet ADP5304
Rev. 0 | Page 17 of 17
OUTLINE DIMENSIONS
2.48
2.38
2.23
0.50
0.40
0.30
10
1
6
5
0.30
0.25
0.20
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0
2-05-2013-
C
TOP VIEW BOTTOM VIEW
0.20 MIN
Figure 30. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADP5304ACPZ-1-R7 −40°C to +125°C 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] Without
Output Discharge, VINOK Threshold = 3.00 V
CP-10-9
ADP5304ACPZ-2-R7 −40°C to +125°C 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] Without
Output Discharge, VINOK Threshold = 4.00 V
CP-10-9
ADP5304-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13493-0-10/15(0)
