Nonvolatile, I2C-Compatible
256-Position, Digital Potentiometer
AD5259
Rev. B
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113© 2005–2010 Analog Devices, Inc. All rights reserved.
FEATURES
Nonvolatile memory maintains wiper settings
256-position
Thin LFCSP-10 (3 mm x 3 mm x 0.8 mm) package
Compact MSOP-10 (3 mm × 4.9 mm x 1.1mm) package
I2C®-compatible interface
VLOGIC pin provides increased interface flexibility
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEPROM (0.1% accuracy)
Power-on EEPROM refresh time < 1ms
Software write protect command
Address Decode Pin AD0 and Pin AD1 allow
4 packages per bus
100-year typical data retention at 55°C
Wide operating temperature −40°C to +85°C
3 V to 5 V single supply
APPLICATIONS
LCD panel VCOM adjustment
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
Fiber to the home systems
Electronics level settings
GENERAL DESCRIPTION
The AD5259 provides a compact, nonvolatile LFCSP-10
(3 mm × 3 mm) or MSOP-10 (3 mm × 4.9 mm) packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function
as mechanical potentiometers1 or variable resistors, but
with enhanced resolution and solid-state reliability.
The wiper settings are controllable through an I2C-compatible
digital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM, providing an end-to-end tolerance accuracy of 0.1%.
A separate VLOGIC pin delivers increased interface flexibility. For
users who need multiple parts on one bus, Address Bit AD0 and
Address Bit AD1 allow up to four devices on the same bus.
FUNCTIONAL BLOCK DIAGRAMS
05026-001
RDAC
REGISTER
RDAC
DATA
CONTROL
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL LOGIC
AD5259
I
2
C
SERIAL
INTERFACE
POWER-
ON RESET
A
W
B
SCL
SDA
AD0
AD1
V
DD
V
LOGIC
GND
RDAC
EEPROM
8
8
Figure 1. Block Diagram
05026-003
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL
LOGIC
SCL
SDA
AD0
AD1
GND
EEPROM
I
2
C
SERIAL
INTERFACE
RDAC
REGISTER
AND
LEVEL
SHIFTER
A
W
B
V
LOGIC
V
DD
Figure 2. Block Diagram Showing Level Shifters
CONNECTION DIAGRAM
05026-002
AD5259
TOP VIEW
(Not to Scale)
W
1
AD0
2
AD1
3
SDA
4
SCL
5
A
B
V
DD
GND
V
LOGIC
10
9
8
7
6
Figure 3. Pinout
1 The terms digital potentiometer, VR (variable resistor), and RDAC are used
interchangeably.
AD5259
Rev. B | Page 2 of 24
TABLE OF CONTENTS
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 13
Theory of Operation ...................................................................... 14
Programming the Variable Resistor ......................................... 14
Programming the Potentiometer Divider ............................... 14
I2C-Compatible Interface............................................................... 15
Writing ......................................................................................... 15
Storing/Restoring ....................................................................... 15
Reading ........................................................................................ 15
I2C-Compatible Format ................................................................. 16
Generic Interface ........................................................................ 16
Write Modes ................................................................................ 16
Read Modes ................................................................................. 17
Store/Restore Modes .................................................................. 17
Tolerance Readback Modes ...................................................... 18
ESD Protection of Digital Pins and Resistor Terminals ........ 19
Power-Up Sequence ................................................................... 19
Layout and Power Supply Bypassing ....................................... 19
Multiple Devices on One Bus ................................................... 19
Evaluation Board ........................................................................ 19
Display Applications ...................................................................... 20
Circuitry ...................................................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
5/10—Rev. A to Rev. B
Changes to Figure 5 .......................................................................... 7
Changes to Storing/Restoring Section ......................................... 15
Changes to Table 7 .......................................................................... 16
Changes to Table 14 ........................................................................ 17
Updated Outline Dimensions ....................................................... 21
7/05—Rev. 0 to Rev. A
Added 10-Lead LFCSP ....................................................... Universal
Changes to Features Section and
General Description Section ........................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 and Added Figure 4 ........................................ 5
Changes to Table 4 ............................................................................ 7
Changes to Figure 27 Caption ....................................................... 11
Changes to Theory of Operation Section .................................... 14
Changes to I2C-Compatible Interface Section ............................ 15
Changes to Table 5 .......................................................................... 16
Changes to Multiple Devices on One Bus Section ..................... 19
Updated Figure 49 Caption ........................................................... 21
Changes to Ordering Guide .......................................................... 21
2/05—Revision 0: Initial Version
AD5259
Rev. B | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS:
RHEOSTAT MODE
Resistor Differential Nonlinearity R-DNL RWB, VA= no connect LSB
5 kΩ –1 ±0.2 +1
10 kΩ −1 ±0.1 +1
50 kΩ/100 kΩ −0.5 ±0.1 +0.5
Resistor Integral Nonlinearity R-INL RWB, VA= no connect LSB
5 kΩ –4 ±0.3 +4
10 kΩ −2 ±0.2 +2
50 kΩ/100 kΩ −1 ±0.4 +1
Nominal Resistor Tolerance ΔRAB T
A = 25°C, VDD = 5.5 V –30 +30 %
Resistance Temperature Coefficient (ΔRAB x 106)/
(RAB x ΔT)
Code = 0x00/0x80 500/15 ppm/°C
Total Wiper Resistance RWB Code = 0x00 75 350 Ω
DC CHARACTERISTICS:
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity DNL LSB
5 kΩ –1 ±0.2 +1
10 kΩ −0.5 ±0.1 +0.5
50 kΩ/100 kΩ −0.5 ±0.2 +0.5
Integral Nonlinearity INL LSB
5 kΩ –1 ±0.2 +1
10 kΩ −0.5 ±0.1 +0.5
50 kΩ/100 kΩ −0.5 ±0.1 +0.5
Full-Scale Error VWFSE Code = 0xFF LSB
5 kΩ −7 −3 0
10 kΩ −4 −1.5 0
50 kΩ/100 kΩ −1 −0.4 0
Zero-Scale Error VWZSE Code = 0x00 LSB
5 kΩ 0 2.5 4
10 kΩ 0 1 3
50 kΩ/100 kΩ 0 0.2 0.5
Voltage Divider Temperature
Coefficient
(∆VW x 106)/
(VW x ∆T)
Code = 0x00/0x80 60/5 ppm/°C
RESISTOR TERMINALS
Voltage Range VA, B, W GND VDD V
Capacitance A, B CA, B f = 1 MHz, measured to GND,
code = 0x80
45 pF
Capacitance W CW f = 1 MHz, measured to GND,
code = 0x80
60 pF
Common-Mode Leakage ICM V
A = VB = VDD/2 10 nA
AD5259
Rev. B | Page 4 of 24
Parameter Symbol Conditions Min Typ1 Max Unit
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH 0.7 × VL V
L + 0.5 V
Input Logic Low VIL −0.5 0.3 × VL V
Leakage Current IIL μA
SDA, AD0, AD1 VIN = 0 V or 5 V 0.01 ±1
SCL – Logic High VIN = 0 V −2.5 −1.3 +1
SCL – Logic Low VIN = 5 V 0.01 ±1
Input Capacitance CIL 5 pF
POWER SUPPLIES
Power Supply Range VDD 2.7 5.5 V
Positive Supply Current IDD 0.1 2 μA
Logic Supply VLOGIC 2.7 5.5 V
Logic Supply Current ILOGIC V
IH = 5 V or VIL = 0 V 3 6 μA
Programming Mode Current (EEPROM) ILOGIC(PROG) V
IH = 5 V or VIL = 0 V 35 mA
Power Dissipation PDISS V
IH = 5 V or VIL = 0 V, VDD = 5 V 15 40 μW
Power Supply Rejection Ratio PSRR VDD = +5 V ± 10%, code = 0x80 ±0.005 ±0.06 %/%
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB BW Code = 0x80
R
AB = 5 kΩ 2000 kHz
R
AB = 10 kΩ 800 kHz
R
AB = 50 kΩ 160 kHz
R
AB = 100 kΩ 80 kHz
Total Harmonic Distortion THDW RAB = 10 kΩ, VA = 1 V rms,
VB = 0, f = 1 kHz
0.01 %
VW Settling Time tS RAB = 10 kΩ, VAB = 5 V,
±1 LSB error band
500 ns
Resistor Noise Voltage Density eN_WB R
WB = 5 kΩ, f = 1 kHz 9 nV/√Hz
1 Typical values represent average readings at 25°C and VDD = 5 V.
AD5259
Rev. B | Page 5 of 24
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
I2C INTERFACE TIMING
CHARACTERISTICS1
SCL Clock Frequency fSCL 0 400 kHz
tBUF Bus Free Time Between Stop
and Start
t1 1.3 μs
tHD;STA Hold Time (Repeated Start) t2 After this period, the first clock pulse is
generated.
0.6 μs
tLOW Low Period of SCL Clock t3 1.3 μs
tHIGH High Period of SCL Clock t4 0.6 μs
tSU;STA Setup Time for Repeated
Start Condition
t5 0.6 μs
tHD;DAT Data Hold Time t6 0 0.9 μs
tSU;DAT Data Setup Time t7 100 ns
tF Fall Time of Both SDA and
SCL Signals
t8 300 ns
tR Rise Time of Both SDA and
SCL Signals
t9 300 ns
tSU;STO Setup Time for Stop Condition t10 0.6 μs
EEPROM Data Storing Time tEEMEM_STORE 26 ms
EEPROM Data Restoring Time at
Power On2
tEEMEM_RESTORE1 VDD rise time dependent. Measure without
decoupling capacitors at VDD and GND.
300 μs
EEPROM Data Restoring Time upon
Restore Command2
tEEMEM_RESTORE2 VDD = 5 V. 300 μs
EEPROM Data Rewritable Time3 t
EEMEM_REWRITE 540 μs
FLASH/EE MEMORY RELIABILITY
Endurance4 100 700 kCycles
Data Retention5 100 Years
1 Standard I2C mode operation guaranteed by design.
2 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
3 Delay time after power-on PRESET prior to writing new EEPROM data.
4 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
5 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature.
05026-004
t1
t2t3
t8
t8
t9
t9
t6
t4t7t5
t2
t10
PS S
SCL
SDA
P
Figure 4. I2C Interface Timing Diagram
AD5259
Rev. B | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Value
VDD, VLOGIC to GND −0.3 V to +7 V
VA, VB, VW to GND GND − 0.3 V, VDD + 0.3 V
IMAX
Pulsed1 ±20 mA
Continuous ±5 mA
Digital Inputs and Output Voltage
to GND
0 V to 7 V
Operating Temperature Range −40°C to +85°C
Maximum Junction Temperature
(TJMAX)
150°C
Storage Temperature −65°C to +150°C
Lead Temperature
(Soldering, 10 sec)
300°C
Thermal Resistance2
θJA: MSOP–10 200°C/W
1 Maximum terminal current is bounded by the maximum current handling
of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5259
Rev. B | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05026-002
AD5259
TOP V IEW
(No t to S cal e)
W
1
AD0
2
AD1
3
SDA
4
SCL
5
A
B
V
DD
GND
V
LOGIC
10
9
8
7
6
NOTES
1. THE EXPOSED PAD SHO ULD
BE CONNE CT ED TO GND OR
LEFT FLOATING.
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin Mnemonic Description
1 W W Terminal, GND ≤ VW ≤ VDD.
2 ADO Programmable Pin 0 for Multiple Package Decoding. State is registered on power-up.
3 AD1 Programmable Pin 1 for Multiple Package Decoding. State is registered on power-up.
4 SDA Serial Data Input/Output.
5 SCL Serial Clock Input. Positive edge triggered.
6 VLOGIC Logic Power Supply.
7 GND Digital Ground.
8 VDD Positive Power Supply.
9 B B Terminal, GND ≤ VB ≤ VDD.
10 A A Terminal, GND ≤ VA ≤ VDD.
AD5259
Rev. B | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = VLOGIC = 5.5 V, RAB = 10 kΩ, TA = +25°C; unless otherwise noted.
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
–0.1
–0.3
–0.50 256224192160128966432
05026-015
CODE (Decimal)
RHEOSTAT MODE INL (LSB)
2.7V
5.5V
Figure 6. R-INL vs. Code vs. Supply Voltage
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.50 256224192160128966432
05026-017
CODE (Decimal)
RHEOSTAT MODE DNL (LSB)
2.7V
5.5V
Figure 7. R-DNL vs. Code vs. Supply Voltage
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.250 256224192160128966432
05026-010
CODE (Decimal)
POTENTIOMETER MODE INL (LSB)
T
A
= –40
C
T
A
= +25
C
T
A
= +85
C
Figure 8. INL vs. Code vs. Temperature
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.250 256224192160128966432
05026-012
CODE (Decimal)
POTENTIOMETER MODE DNL (LSB)
–40
C
+25
C
+85
C
Figure 9. DNL vs. Code vs. Temperature
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.250 256224192160128966432
05026-011
CODE (Decimal)
POTENTIOMETER MODE INL (LSB)
5.5V
2.7V
Figure 10. INL vs. Supply Voltages
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.250 256224192160128966432
05026-013
CODE (Decimal)
POTENTIOMETER MODE DNL (LSB)
5.5V
2.7V
Figure 11. DNL vs. Code vs. Supply Voltage
AD5259
Rev. B | Page 9 of 24
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.50 256224192160128966432
05026-014
CODE (Decimal)
RHEOSTAT MODE INL (LSB)
–40
C
+85
C
+25
C
Figure 12. R-INL vs. Code vs. Temperature
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.50 256224192160128966432
05026-016
CODE (Decimal)
RHEOSTAT MODE DNL (LSB)
TA = –40C
TA = +85C
TA = +25C
Figure 13. R-DNL vs. Code vs. Temperature
0
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
–40 –20 806040200
05026-024
TEMPERATURE (C)
FSE (LSB)
FSE @ V
DD
= 2.7V
FSE @ V
DD
= 5.5V
Figure 14. Full-Scale Error vs. Temperature
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40 –20 806040200
05026-023
TEMPERATURE (C)
ZSE (LSB)
ZSE @ V
DD
= 2.7V
ZSE @ V
DD
= 5.5V
Figure 15. Zero-Scale Error vs. Temperature
1
0.1
–40 –20 806040200
05026-020
TEMPERATURE (C)
I
DD
, SUPPLY CURRENT (A)
V
DD
= 5.5V
Figure 16. Supply Current vs. Temperature
6
–1
0
1
2
3
4
5
–40 –20 806040200
05026-021
TEMPERATURE (C)
I
LOGIC
, LOGIC SUPPLY CURRENT (A)
V
DD
= 2.7V
V
DD
= 5.5V
Figure 17. Logic Supply Current vs. Temperature vs. VDD
AD5259
Rev. B | Page 10 of 24
400
–600
–500
–400
–300
–200
–100
0
100
200
300
0 256224192160128966432
05026-019
CODE (Decimal)
RHEOSTAT MODE TEMPCO (ppm/
C)
5k
10k
50k
100k
Figure 18. Rheostat Mode Tempco (ΔRAB x 106)/(RAB x ΔT) vs. Code
70
–40
–30
–20
–10
0
10
20
30
40
50
60
0 256224192160128966432
05026-018
CODE (Decimal)
POTENTIOMETER MODE TEMPCO (ppm/
C)
10k
50k5k
100k
Figure 19. Potentiometer Mode Tempco (ΔVW x 106)/(VW x ΔT) vs. Code
350
0
50
100
150
200
250
300
–40 –20 806040200
05026-022
TEMPERATURE (C)
R
WB
@ 0x00
R
WB
@ V
DD
= 5.5V
R
WB
@ V
DD
= 2.7V
Figure 20. RWB vs. Temperature
120
100
80
60
40
20
0
–40 –20 806040200
05026-025
TEMPERATURE (C)
TOTAL RESISTANCE (k
)
100k Rt @ V
DD
= 5.5V
50k Rt @ V
DD
= 5.5V
10k Rt @ V
DD
= 5.5V
5k Rt @ V
DD
= 5.5V
Figure 21. Total Resistance vs. Temperature
05026-026
80H
40H
20H
10H
08H
04H
02H
01H
1k 10M1M100k10k
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
FREQUENCY (Hz)
GAIN (dB)
Figure 22. Gain vs. Frequency vs. Code, RAB = 5 kΩ
1k 10M1M100k10k
05026-027
80H
40H
20H
10H
08H
04H
02H
01H
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
FREQUENCY (Hz)
GAIN (dB)
Figure 23. Gain vs. Frequency vs. Code, RAB = 10 kΩ
AD5259
Rev. B | Page 11 of 24
1k 1M100k10k
05026-028
80
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
FREQUENCY (Hz)
GAIN (dB)
Figure 24. Gain vs. Frequency vs. Code, RAB = 50 kΩ
1k 1M100k10k
05026-029
80
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
FREQUENCY (Hz)
GAIN (dB)
Figure 25. Gain vs. Frequency vs. Code, RAB = 100 kΩ
1k 10M1M100k10k
05026-050
50k
160kHz
100k
80kHz
5k
2MHz
10k
800kHz
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
FREQUENCY (Hz)
GAIN (dB)
Figure 26. −3 dB Bandwidth @ Code = 0×80
10k
1k
100
10012345
05026-055
V
IH
(V)
I
LOGIC
(
A)
V
DD
= V
LOGIC
= 5V
V
DD
= V
LOGIC
= 3V
Figure 27. Logic Supply Current vs. Input Voltage
80
60
40
20
0
100 1k 1M100k10k
05026-054
FREQUENCY (Hz)
PSRR (dB)
CODE = MIDSCALE, V
A
= V
LOGIC
, V
B
= 0V
PSRR @ V
LOGIC
= 5V DC
10% p-p AC
PSRR @ V
LOGIC
= 3V DC
10% p-p AC
Figure 28. PSRR vs. Frequency
05026-051
1
2
V
W
SCL
200mV/DIV
400ns/DIV
5V/DIV
Figure 29. Digital Feedthrough
AD5259
Rev. B | Page 12 of 24
05026-052
1
V
W
1s/DIV
50mV/DIV
Figure 30. Midscale Glitch, Code 0×7F to 0×80
05026-053
1
2
V
W
SCL
2V/DIV
200ns/DIV
5V/DIV
Figure 31. Large Signal Settling Time
AD5259
Rev. B | Page 13 of 24
TEST CIRCUITS
Figure 32 through Figure 37 illustrate the test circuits that define the test conditions used in the product Specifications tables.
05026-030
VMS
AW
B
DUT
V+
V+ = VDD
1LSB = V+/2N
Figure 32. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
05026-031
NO CONNECT
I
W
V
MS
AW
B
DUT
Figure 33. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
05026-032
V
MS2
V
MS1
V
W
AW
B
DUT I
W
= V
DD
/R
NOMINAL
R
W
= [V
MS1
– V
MS2
]/I
W
Figure 34. Test Circuit for Wiper Resistance
05026-033
V
MS
%
DUT
( )
AW
B
V+ V
DD
%
V
MS
V
DD
V
DD
V
A
V
MS
V+ = V
DD
10%
PSRR (dB) = 20 LOG
PSS (%/%) =
Figure 35. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
05026-034
+5V
–5V
W
A
+2.5V
BV
OUT
OFFSET
GND
DUT
AD8610
V
IN
Figure 36. Test Circuit for Gain vs. Frequency
05026-035
W
B
DUT
I
SW
I
SW
R
SW
GND TO V
DD
CODE = 0x00
=0.1V
0.1V
Figure 37. Test Circuit for Common-Mode Leakage Current
AD5259
Rev. B | Page 14 of 24
THEORY OF OPERATION
The AD5259 is a 256-position digitally-controlled variable
resistor (VR) device. EEPROM is pre-loaded at midscale from
the factory, and initial power-up is, accordingly, at midscale.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance (RAB) of the RDAC between Terminal A
and Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance of the VR has 256 contact points accessed
by the wiper terminal. The 8-bit data in the RDAC latch is
decoded to select one of 256 possible settings.
A
W
B
A
W
B
A
W
B
05026-036
Figure 38. Rheostat Mode Configuration
The general equation determining the digitally programmed
output resistance between Wiper W and Terminal B is
W
AB
WB RR
D
DR 2
256
)( (1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the ON resistance of
each internal switch.
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
05026-037
Figure 39. AD5259 Equivalent RDAC Circuit
In the zero-scale condition, there is a relatively low value finite
wiper resistance. Care should be taken to limit the current flow
between Wiper W and Terminal B in this state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation
or destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A produces a digitally
controlled complementary resistance, RWA . The resistance value
setting for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
ABWA RR
D
DR
2
256
256
)( (2)
Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. For this reason, resistance tolerance is
stored in the EEPROM, enabling the user to know the actual
RAB within 0.1%.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
Wiper W to Terminal B and Wiper W to Terminal A propor-
tional to the input voltage at Terminal A to Terminal B. Unlike
the polarity of VDD to GND, which must be positive, voltage
across Terminal A to Terminal B, Wiper W to Terminal A, and
Wiper W to Terminal B can be at either polarity.
A
VI
W
B
VO
05026-038
Figure 40. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at Wiper W to Terminal B starting
at 0 V up to 1 LSB less than 5 V. The general equation defining
the output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
B
A
WV
D
V
D
DV 256
256
256
)(
(3)
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
B
AB
WA
A
AB
WB
WV
R
DR
V
R
DR
DV )(
)(
)( (4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly
on the ratio of the Internal Resistors RWA and RWB and not
the absolute values.
AD5259
Rev. B | Page 15 of 24
I2C-COMPATIBLE INTERFACE
The master initiates data transfer by establishing a start condi-
tion, which is when a high-to-low transition on the SDA line
occurs while SCL is high (see Figure 4). The next byte is the
slave address byte, which consists of the slave address (first
7 bits) followed by an R/W bit (see Table 6). When the R/W bit
is high, the master reads from the slave device. When the R/W
bit is low, the master writes to the slave device.
The slave address of the part is determined by two configurable
address pins, Pin AD0 and Pin AD1. The state of these two pins
is registered upon power-up and decoded into a corresponding
I2C 7-bit address (see Table 5). The slave address corresponding
to the transmitted address bits responds by pulling the SDA
line low during the ninth clock pulse (this is termed the slave
acknowledge bit). At this stage, all other devices on the bus
remain idle while the selected device waits for data to be
written to, or read from, its serial register.
WRITING
In the write mode, the last bit (R/W) of the slave address byte is
logic low. The second byte is the instruction byte. The first three
bits of the instruction byte are the command bits (see Table 6).
The user must choose whether to write to the RDAC register,
EEPROM register, or activate the software write protect (see
Table 7 to Table 10). The final five bits are all zeros (see Table 13
to Table 14). The slave again responds by pulling the SDA line
low during the ninth clock pulse.
The final byte is the data byte MSB first. With the write protect
mode, data is not stored; rather, a logic high in the LSB enables
write protect. Likewise, a logic low disables write protect. The
slave again responds by pulling the SDA line low during the
ninth clock pulse.
STORING/RESTORING
In this mode, only the address and instruction bytes are
necessary. The last bit (R/W) of the address byte is logic
low. The first three bits of the instruction byte are the
command bits (see Table 6). The two choices are transfer
data from RDAC to EEPROM (store), or from EEPROM
to RDAC (restore). The final five bits are all zeros (see
Table 13 to Table 14). In addition, users should issue an
NOP command immediately after restoring the EEMEM
setting to RDAC, thereby minimizing supply current
dissipation.
READING
Assuming the register of interest was not just written to, it is
necessary to write a dummy address and instruction byte. The
instruction byte will vary depending on whether the data that
is wanted is the RDAC register, EEPROM register, or tolerance
register (see Table 11 and Table 16).
After the dummy address and instruction bytes are sent, a repeat
start is necessary. After the repeat start, another address byte is
needed, except this time the R/W bit is logic high. Following this
address byte is the readback byte containing the information
requested in the instruction byte. Read bits appear on the nega-
tive edges of the clock.
The tolerance register can be read back individually (see
Table 15) or consecutively (see Table 16). Refer to the Read
Modes section for detailed information on the interpretation
of the tolerance bytes.
After all data bits have been read or written, a stop condition is
established by the master. A stop condition is defined as a low-to-
high transition on the SDA line while SCL is high. In write mode,
the master pulls the SDA line high during the tenth clock pulse
to establish a stop condition (see Figure 46). In read mode, the
master issues a no acknowledge for the ninth clock pulse (that is,
the SDA line remains high). The master then brings the SDA line
low before the tenth clock pulse, and then raises SDA high to
establish a stop condition (see Figure 47).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowl-
edged its slave address and instruction bytes in the write mode,
the RDAC output is updated on each successive byte until a stop
condition is received. If different instructions are needed, the
write/read mode has to start again with a new slave address,
instruction, and data byte. Similarly, a repeated read function
of the RDAC is also allowed.
AD5259
Rev. B | Page 16 of 24
I2C-COMPATIBLE FORMAT
The following generic, write, read, and store/restore control
registers for the AD5259 all refer to the device addresses listed
in Table 5; the mode/condition reference key (S, P, SA, MA,
NA, W, R, and X) is listed below.
S = Start Condition
P = Stop Condition
SA = Slave Acknowledge
MA = Master Acknowledge
NA = No Acknowledge
W = Write
R = Read
X = Don’t Care
AD1 and AD0 are two-state address pins.
Table 5. Device Address Lookup
AD1 Address Pin AD0 Address Pin I2C Device Address
0 0 0011000
1 0 0011010
0 1 1001100
1 1 1001110
GENERIC INTERFACE
Table 6. Generic Interface Format
S
7-Bit Device Address
(See Table 5) R/W SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Slave Address Byte Instruction Byte Data Byte
Table 7. RDAC-to-EEPROM Interface Command Descriptions
C2 C1 C0 Command Description
0 0 0 Operation Between Interface and RDAC.
0 0 1 Operation Between Interface and EEPROM.
0 1 0 Operation Between Interface and Write Protection Register. See Table 10.
1 0 0 NOP.
1 0 1 Restore EEPROM to RDAC.1
1 1 0 Store RDAC to EEPROM.
1 This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state.
WRITE MODES
Table 8. Writing to RDAC Register
S
7-Bit Device Address
(See Table 5) 0 SA 0 0 0 0 0 0 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Slave Address Byte Instruction Byte Data Byte
Table 9. Writing to EEPROM Register
S
7-Bit Device Address
(See Table 5) 0 SA 0 0 1 0 0 0 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P
Slave Address Byte Instruction Byte Data Byte
Table 10. Activating/Deactivating Software Write Protect
S
7-Bit Device Address
(See Table 5) 0 SA 0 1 0 0 0 0 0 0 SA 0 0 0 0 0 0 0 WP SA P
Slave Address Byte Instruction Byte Data Byte
In order to activate the write protection mode, the WP bit in Table 10 must be logic high. To deactivate the write protection, the
command must be sent again, except with the WP in logic zero state. WP is reset to the deactivated mode if power is cycled off and on.
AD5259
Rev. B | Page 17 of 24
READ MODES
Read modes are referred to as traditional because the first two bytes for all three cases are dummy bytes, which function to place the
pointer towards the correct register; this is the reason for the repeat start. Theoretically, this step can be avoided if the user reads a register
previously written to. For example, if the EEPROM was just written to, the user can then skip the two dummy bytes and proceed directly
to the slave address byte, followed by the EEPROM readback data.
Table 11. Traditional Readback of RDAC Register Value
S
7-Bit Device Address
(See Table 5) 0 SA 0 0 0 0 0 0 0 0 SA S
7-Bit Device Address
(See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address Byte Instruction Byte Slave Address Byte Read Back Data
↑
Repeat start
Table 12. Traditional Readback of Stored EEPROM Value
S
7-Bit Device Address
(See Table 5) 0 SA 0 0 1 0 0 0 0 0 SA S
7-Bit Device Address
(See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address Byte Instruction Byte Slave Address Byte Read Back Data
↑
Repeat start
STORE/RESTORE MODES
Table 13. Storing RDAC Value to EEPROM
S
7-Bit Device Address
(See Table 5) 0 SA 1 1 0 0 0 0 0 0 SA P
Slave Address Byte Instruction Byte
Table 14. Restoring EEPROM to RDAC1
S
7-Bit Device Address
(See Table 5) 0 SA 1 0 1 0 0 0 0 0 SA P
Slave Address Byte Instruction Byte
1 User should issue an NOP command immediately after this command to conserve power.
AD5259
Rev. B | Page 18 of 24
TOLERANCE READBACK MODES
Table 15. Traditional Readback of Tolerance (Individually)
S
7-Bit Device Address
(See Table 5) 0 SA 0 0 1 1 1 1 1 0 SA S
7-Bit Device Address
(See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address Byte Instruction Byte Slave Address Byte Sign + Integer Byte
↑
Repeat start
S
7-Bit Device Address
(See Table 5) 0 SA 0 0 1 1 1 1 1 1 SA S
7-Bit Device Address
(See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address Byte Instruction Byte Slave Address Byte Decimal Byte
↑
Repeat start
Table 16.Traditional Readback of Tolerance (Consecutively)
S
7-Bit Device
Address
(See Table 5) 0 SA 0 0 1 1 1 1 1 0 SA S
7-Bit Device
Address
(See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 MA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address
Byte Instruction Byte
Slave Address
Byte
Sign + Integer Byte Decimal Byte
↑
Repeat start
Calculating RAB Tolerance Stored in Read-Only Memory
05026-005
A
AA
D7 D6 D5 D4 D3 D2 D1 D0
SIGN
SIGN 7 BITS FOR INTEGER NUMBER
2
6
2
5
2
4
2
3
2
2
2
1
2
0
D7 D6 D5 D4 D3 D2 D1 D0
8 BITS FOR DECIMAL NUMBER
2
–8
2
–1
2
–2
2
–3
2
–4
2
–5
2
–6
2
–7
Figure 41. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions.
(Unit is Percent. Only Data Bytes are Shown.)
The AD5259 features a patented RAB tolerance storage in the
nonvolatile memory. The tolerance is stored in the memory
during factory production and can be read by users at any time.
The knowledge of stored tolerance allows users to accurately
calculate RAB. This feature is valuable for precision, rheostat
mode, and open-loop applications where knowledge of abso-
lute resistance is critical.
The stored tolerance resides in the read-only memory and is
expressed as a percentage. The tolerance is stored in two memory
location bytes in sign magnitude binary form (see Figure 41).
The two EEPROM address bytes are 11110 (sign + integer)
and 11111 (decimal number). The two bytes can be indi-
vidually accessed with two separate commands (see Table 15).
Alternatively, readback of the first byte followed by the second
byte can be done in one command (see Table 16). In the latter
case, the memory pointer will automatically increment from
the first to the second EEPROM location (increments from
11110 to 11111) if read consecutively.
In the first memory location, the MSB is designated for the
sign (0 = + and 1= −) and the seven LSBs are designated for
the integer portion of the tolerance. In the second memory
location, all eight data bits are designated for the decimal
portion of tolerance. Note the decimal portion has a limited
accuracy of only 0.1%. For example, if the rated RAB = 10 kΩ
and the data readback from Address 11110 shows 0001 1100,
and Address 11111 shows 0000 1111, then the tolerance can
be calculated as
MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2–8 = 0.06
Tol eran ce = +28.06%
Rounded Tolerance = +28.1% and therefore,
RAB_ACTUAL = 12.810 kΩ
AD5259
Rev. B | Page 19 of 24
ESD PROTECTION OF DIGITAL PINS AND
RESISTOR TERMINALS
The AD5259 VDD, VLOGIC, and GND power supplies define the
boundary conditions for proper 3-terminal and digital input
operation. Supply signals present on Terminal A, Terminal B,
and Terminal W that exceed VDD or GND are clamped by the
internal forward biased ESD protection diodes (see Figure 42).
Digital Input SCL and Digital Input SDA are clamped by ESD
protection diodes with respect to VLOGIC and GND as shown in
Figure 43.
GND
A
W
B
V
DD
05026-039
Figure 42. Maximum Terminal Voltages Set by VDD and GND
GND
SCL
SDA
V
LOGIC
05026-040
Figure 43. Maximum Terminal Voltages Set by VLOGIC and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Term ina l A, Termi nal B, and Term ina l W (s ee Figure 42) , it
is important to power GND/VDD/VLOGIC before applying any
voltage to Terminal A, Terminal B, and Terminal W; otherwise,
the diode is forward biased, so the VDD and VLOGIC are powered
unintentionally and may affect the user’s circuit. The ideal power-
up sequence is in the following order: GND, VDD, VLOGIC, digital
inputs, and then VA, VB, VW. The relative order of powering
VA, VB, VW, and the digital inputs is not important as long as
they are powered after GND/VDD/VLOGIC.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to use compact, minimum lead length layout
design. The leads to the inputs should be as direct as possible
with minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic capaci-
tors of 0.01 μF to 0.1 μF. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 44). The digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
VDD
GND
V
DD C2
10FC1
0.1F
AD5259
+
05026-041
Figure 44. Power Supply Bypassing
MULTIPLE DEVICES ON ONE BUS
The AD5259 has two configurable address pins, Pin AD0 and
Pin AD1. The state of these two pins is registered upon power-
up and decoded into a corresponding I2C-compatible 7-bit
address (see Table 5). This allows up to four devices on the bus
to be written to or read from independently.
EVALUATION BOARD
An evaluation board, with all necessary software, is available
to program the AD5259 from any PC running Windows® 98/
2000/ XP. The graphical user interface, as shown in Figure 45,
is straightforward and easy to use. More detailed information
is available in the board’s user manual.
05026-042
Figure 45. AD5259 Evaluation Board Software
AD5259
Rev. B | Page 20 of 24
DISPLAY APPLICATIONS
CIRCUITRY
A special feature of the AD5259 is its unique separation of the
VLOGIC and VDD supply pins. The separation provides greater
flexibility in applications that do not always provide needed
supply voltages.
In particular, LCD panels often require a VCOM voltage in the
range of 3 V to 5 V. The circuit in Figure 46 is the rare excep-
tion in which a 5 V supply is available to power the digital
potentiometer.
05026-006
A
BW
R2
10k
R1
70k
R3
25k
V
DD
V
LOGIC
SCL
SDA
GND
–
+
U1
AD8565
3.5V < V
COM
< 4.5V
14.4VVCC (~3.3V) 5V
AD5259
MCU
C1
1FR5
10k
R6
10k
Figure 46. VCOM Adjustment Application
In the more common case shown in Figure 47, only analog 14.4 V
and digital logic 3.3 V supplies are available. By placing discrete
resistors above and below the digital potentiometer, VDD can
now be tapped off the resistor string itself. Based on the chosen
resistor values, the voltage at VDD in this case equals 4.8 V,
allowing the wiper to be safely operated all the way up to 4.8 V.
The current draw of VDD will not affect that node’s bias because
it is only on the order of microamps. VLOGIC is tied to the MCU’s
3.3 V digital supply because VLOGIC will draw the 35 mA which
is needed when writing to the EEPROM. It would be imprac-
tical to try and source 35 mA through the 70 kΩ resistor,
therefore, VLOGIC is not connected to the same node as VDD.
For this reason, VLOGIC and VDD are provided as two separate
supply pins that can either be tied together or treated inde-
pendently; VLOGIC supplying the logic/EEPROM with power,
and VDD biasing up the A, B, and W terminals for added
flexibility.
05026-007
A
BW
R2
10k
R1
70k
R3
25k
V
DD
V
LOGIC
SCL
SDA
GND
–
+
U1
AD8565
3.5V < V
COM
< 4.5V
14.4VVCC (~3.3V)
AD5259
MCU
C1
1FR5
10k
R6
10k
SUPPLIES POWER
TO BOTH THE
MICRO AND THE
LOGIC SUPPLY OF
THE DIGITAL POT
Figure 47. Circuitry When a Separate Supply is Not Available for VDD
For a more detailed look at this application, refer to the article,
“Simple VCOM Adjustment uses any Logic Supply Voltage” in
the September 30, 2004 issue of EDN magazine.
AD5259
Rev. B | Page 21 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
0.50
0.40
0.30
121009-A
TOP VIEW
10
1
6
5
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN1
INDICATOR
(R0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
AD5259
Rev. B | Page 22 of 24
ORDERING GUIDE
Model1 RAB (Ω) Temperature Package Description Package Option Branding
AD5259BRMZ5 5 k –40°C to +85°C 10-Lead MSOP RM-10 D4P
AD5259BRMZ5-R7 5 k –40°C to +85°C 10-Lead MSOP RM-10 D4P
AD5259BCPZ5-R7 5 k –40°C to +85°C 10-Lead LFCSP_WD CP-10-9 D4P
AD5259BRMZ10 10 k –40°C to +85°C 10-Lead MSOP RM-10 D4Q
AD5259BRMZ10-R7 10 k –40°C to +85°C 10-Lead MSOP RM-10 D4Q
AD5259BCPZ10-R7 10 k –40°C to +85°C 10-Lead LFCSP_WD CP-10-9 D4Q
AD5259BRMZ50 50 k –40°C to +85°C 10-Lead MSOP RM-10 D4R
AD5259BRMZ50-R7 50 k –40°C to +85°C 10-Lead MSOP RM-10 D4R
AD5259BCPZ50-R7 50 k –40°C to +85°C 10-Lead LFCSP_WD CP-10-9 D4R
AD5259BRMZ100 100 k –40°C to +85°C 10-Lead MSOP RM-10 D4S
AD5259BRMZ100-R7 100 k –40°C to +85°C 10-Lead MSOP RM-10 D4S
AD5259BCPZ100-R7 100 k –40°C to +85°C 10-Lead LFCSP_WD CP-10-9 D4S
AD5259EVAL Evaluation Board2
1 Z = RoHS Compliant Part.
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
AD5259
Rev. B | Page 23 of 24
NOTES
AD5259
Rev. B | Page 24 of 24
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
D05026-0-5/10(B)
