FDMA507PZ Single P-Channel PowerTrench(R) MOSFET -20 V, -7.8 A, 24 m Features General Description Max rDS(on) = 24 m at VGS = -5 V, ID = -7.8 A This device is designed specifically for battery charge or load switching in cellular handset and other ultraportable applications. It features a MOSFET with low on-stade resistance. Max rDS(on) = 25 m at VGS = -4.5 V, ID = -7 A Max rDS(on) = 35 m at VGS = -2.5 V, ID = -5.5 A The MicroFET 2X2 package offers exceptional thermal perfomance for its physical size and is well suited to linear mode applications. Max rDS(on) = 45 m at VGS = -1.8 V, ID = -4 A Low Profile - 0.8 mm maximum - in the package MicroFET 2X2 mm HBM ESD protection level > 3.2K V typical (Note3) Free from halogenated compounds and antimony oxides RoHS Compliant MOSFET Maximum Ratings TA = 25 C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage ID Drain Current -Continuous TA = 25 C (Note 1a) -Pulsed PD TJ, TSTG Ratings -20 Units V 8 V -7.8 -24 Power Dissipation TA = 25 C (Note 1a) 2.4 Power Dissipation TA = 25 C (Note 1b) 0.9 Operating and Storage Junction Temperature Range -55 to +150 A W C Thermal Characteristics RJA Thermal Resistance, Junction to Ambient (Note 1a) 52 RJA Thermal Resistance, Junction to Ambient (Note 1b) 145 C/W Package Marking and Ordering Information Device Marking 507 Device FDMA507PZ (c)2010 Fairchild Semiconductor Corporation FDMA507PZ Rev.C Package MicroFET 2X2 1 Reel Size 7 '' Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMA507PZ Single P-Channel PowerTrench(R) MOSFET May 2010 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = -250 A, VGS = 0 V BVDSS TJ Breakdown Voltage Temperature Coefficient ID = -250 A, referenced to 25 C IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V IGSS Gate to Source Leakage Current VGS = 8 V, VDS = 0 V -20 V -12 mV/C -1 A 10 A -1.5 V On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = -250 A VGS(th) TJ Gate to Source Threshold Voltage Temperature Coefficient ID = -250 A, referenced to 25 C rDS(on) gFS Drain to Source On Resistance Forward Transconductance -0.4 -0.5 3 mV/C VGS = -5 V, ID = -7.8 A 19 24 VGS = -4.5 V, ID = -7 A 20 25 VGS = -2.5 V, ID = -5.5 A 24 35 VGS = -1.8 V, ID = -4 A 29 45 VGS = -5 V, ID = -7.8 A, TJ = 125 C 26 34 VDS = -5 V, ID = -7.8 A 33 m S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = -10 V, VGS = 0 V, f = 1 MHz 1515 2015 pF 265 355 pF 240 360 pF Switching Characteristics td(on) Turn-On Delay Time tr Rise Time VDD = -10 V, ID = -7.8 A VGS = -5 V, RGEN = 6 6.4 13 ns 14 25 ns ns td(off) Turn-Off Delay Time 192 307 tf Fall Time 96 154 ns Qg(TOT) Total Gate Charge 30 42 nC Qgs Gate to Source Gate Charge Qgd Gate to Drain "Miller" Charge VDD = -10 V, ID = -7.8 A VGS = -5 V 2 nC 7.5 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = -2.0 A (Note 2) IF = -7.8 A, di/dt = 100 A/s -0.6 -1.2 V 66 106 ns 44 70 nC Notes: 1. RJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RJC is guaranteed by design while RCA is determined by the user's board design. a. 52 C/W when mounted on a 1 in2 pad of 2 oz copper. b. 145 C/W when mounted on a minimum pad of 2 oz copper. 2. Pulse Test: Pulse Width < 300s, Duty cycle < 2.0%. 3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. (c)2010 Fairchild Semiconductor Corporation FDMA507PZ Rev.C 2 www.fairchildsemi.com FDMA507PZ Single P-Channel PowerTrench(R) MOSFET Electrical Characteristics TJ = 25 C unless otherwise noted 2.5 24 VGS = -4.5 V -ID, DRAIN CURRENT (A) 20 VGS = -3 V VGS = -2.5 V 16 12 VGS = -1.8 V 8 4 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 0 0 PULSE DURATION = 80 s DUTY CYCLE = 0.5%MAX NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = -5 V 2.0 VGS = -1.8 V 1.5 1.0 VGS = -3 V 0 rDS(on), DRAIN TO SOURCE ON-RESISTANCE (m) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.4 1.2 1.0 0.8 -50 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) Figure 3. Normalized On Resistance vs Junction Temperature -IS, REVERSE DRAIN CURRENT (A) -ID, DRAIN CURRENT (A) 8 12 16 -ID, DRAIN CURRENT(A) 20 24 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX VDS = -5 V 16 12 TJ = 150 oC TJ = 25 oC 4 TJ = -55 oC 0.5 1.0 1.5 -VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 120 80 TJ = 125 oC 40 TJ = 25 oC 0 1 20 10 2 3 4 -VGS, GATE TO SOURCE VOLTAGE (V) 5 VGS = 0 V TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 2.0 Figure 5. Transfer Characteristics (c)2010 Fairchild Semiconductor Corporation FDMA507PZ Rev.C ID = - 7.8 A Figure 4. On-Resistance vs Gate to Source Voltage 24 0 0 4 160 ID = -7.8 A VGS = -5 V 8 VGS = -5 V Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 20 VGS = -4.5 V 0.5 0.2 0.4 0.6 0.8 1.0 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On Region Characteristics 0.6 -75 VGS = -2.5 V 0 0.2 0.4 0.6 0.8 1.0 -VSD, BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3 www.fairchildsemi.com FDMA507PZ Single P-Channel PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted -VGS, GATE TO SOURCE VOLTAGE(V) 5 10000 ID = -7.8 V CAPACITANCE (pF) 4 VDD = -8 V 3 VDD = -10 V 2 VDD = -12 V 1 0 0 10 20 30 Ciss 1000 Coss f = 1 MHz VGS = 0 V 100 0.1 40 Qg, GATE CHARGE(nC) Figure 7. Gate Charge Characteristics -1 20 50 -2 VGS = 0 V 10 -ID, DRAIN CURRENT (A) -Ig, GATE LEAKAGE CURRENT (A) 1 10 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 8. Capacitance vs Drain to Source Voltage 10 -3 10 -4 10 -5 TJ = 125 oC 10 -6 10 -7 10 -8 10 1 ms 1 0.1 3 6 10 ms THIS AREA IS LIMITEDBY rDS(on) 100 ms SINGLE PULSE TJ = MAX RATED RJA = 145 oC/W 1s 10 s DC TA = 25 oC -10 0 100 us 10 TJ = 25 oC -9 10 10 Crss 9 12 0.01 0.1 15 1 80 10 -VDS, DRAIN to SOURCE VOLTAGE (V) -VGS, GATE TO SOURCE VOLTAGE (V) Figure 9. Gate Leakage Current vs Gate to Source Voltage Figure 10. Forward Bias Safe Operating Area P(PK), PEAK TRANSIENT POWER (W) 1000 SINGLE PULSE RJA = 145 oC/W o 100 TA = 25 C 10 1 0.5 -4 10 -3 -2 10 10 -1 10 t, PULSE WIDTH (sec) 1 10 100 1000 Figure 11. Single Pulse Maximum Power Dissipation (c)2010 Fairchild Semiconductor Corporation FDMA507PZ Rev.C 4 www.fairchildsemi.com FDMA507PZ Single P-Channel PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted 2 1 NORMALIZED THERMAL IMPEDANCE, ZJA DUTY CYCLE-DESCENDING ORDER 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA SINGLE PULSE o RJA = 145 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) 10 100 1000 Figure 12. Junction-to-Ambient Transient Thermal Response Curve (c)2010 Fairchild Semiconductor Corporation FDMA507PZ Rev.C 5 www.fairchildsemi.com FDMA507PZ Single P-Channel PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted FDMA507PZ Single P-Channel PowerTrench(R) MOSFET Dimensional Outline and Pad Layout (c)2010 Fairchild Semiconductor Corporation FDMA507PZ Rev.C 6 www.fairchildsemi.com tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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