1
FEATURES
>400.0 Mbps (200 MHz) switching rates
+340mV differential signaling
3.3 V powe r supply
TTL compatible outputs
Cold spare all pins
Ultra low power CMOS technology
1.9ns maximum propagation delay
200ps maximum differential skew
Operational environment; total dose irradiati on testi ng to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
Packaging options:
- 16-lead flatpack (dual in-line)
Standard Microcircuit Drawing 5962-98652
- QML Q and V compliant part
INTRODUCTION
The UT54LVDS032LV Quad Receiver is a quad CMOS
differential line receiver designed for applications requiring
ultra low power dissipation and high data rates. The device is
designed to support data rates in excess of 400.0 Mbps (200
MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The UT54LVDS032LV accepts low voltage (340mV)
differential input signals and translates them to 3V CMOS
output levels. The receiver supports a three-state function that
may be used to multiplex outputs. The receiver also supports
OPEN, shorted and terminated (100 Ω) input fail-safe. Receiver
output will be HIGH for all fail-safe conditions.
The UT54LVDS032LV and companion quad line driver
UT54LVDS031LV provides new alternati ves to hig h power
pseudo-ECL devices for high speed point-to-point interface
applications.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
Standard Products
UT54LVDS032LV/E Low Voltage Quad Receiver
Data Sheet
December, 2008
www.aeroflex.com/lvds
Figure 1. UT54LVDS032LV Quad Receiver Block Diagram
+
R1
-
RIN1+
RIN1-
RIN2+
RIN2-
RIN3+
RIN3-
RIN4+
RIN4-
ROUT1
ROUT2
ROUT4
ROUT3
EN
EN
+
R2
-
+
R3
-
+
R4
-
2
TRUTH TABLE
PIN DESCRIPTION
APPLICATIONS INFORMATION
The UT54LVDS032LV receiver’s intended use is primarily in
an uncomplicated point-to-point configuration as is shown in
Figure 3. This configuration provides a clean signaling
environment for quick edge rates of the drivers. The receiver is
connected to the driver through a balanced media which may
be a standard twisted pair cable, a parallel pair cable, or simply
PCB traces. Typically, the characteristic impedance of the media
is in the range of 100Ω. A termination resistor of 100Ω should
be selected to match the media and is located as close to the
receiver input pins as possible. The termination resistor converts
the current sourced by the driver into voltages that are detected
by the receiver. Other configurations are possible such as a
multi-receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance
discontinuities, as well as ground shifting, noise margin limits,
and total termination loading must be taken into account.
The UT54LVDS032LV differential line receiver is capable of
detecting signals as low as 100mV, over a + 1V common-mode
range centered around +1.2V. This is related to the driver offset
voltage which is typically +1.2V. The driven signal is centered
around this voltage and may shift +1V around this center point.
The +1V shifting may be the result of a ground potential
difference between the driver’s ground reference and the
receiver’s ground reference, the common-mode effects of
coupled noise or a combination of the two. Both receiver input
pins should honor their specified operating input voltage range
of 0V to +2.4V (measured from each pin to ground).
Enables Input Output
EN EN RIN+ - RIN- ROUT
L H X Z
All other combinations
of ENABLE inputs VID > 0.1V H
VID < -0.1V L
Full Fail-safe
OPEN/SHORT or
Terminated
H
Pin No. Name Description
2, 6, 10, 14 RIN+ Non-inverting receiver input pin
1, 7, 9, 15 RIN- Inverting receiver input pin
3, 5, 1 1, 13 ROUT Receiver output pin
4EN Active high enable pin, OR-ed
with EN
12 EN Active low enable pin, OR-ed
with EN
16 VDD Power supply pin, +3.3 + 0.3V
8 VSS Ground pin
Figure 2. UT54LVDS032LV Pinout
UT54LVDS032LV
Receiver
16
15
14
13
12
11
10
9
VDD
RIN4-
RIN4+
ROUT4
EN
ROUT3
RIN3+
RIN3-
1
RIN1-
2
RIN1+ 3
ROUT1
4
EN 5
ROUT2 6
RIN2+ 7
RIN2-
8
VSS
ENABLE
DATA
INPUT
1/4 UT54LVDS031LV
1/4 UT54LVDS032LV
+
-DATA
OUTPUT
Figure 3. Point-to-Point Application
RT 100Ω
3
Receiver Fail-Safe
The UT54LVDS032LV receiver is a high gain, high speed
device that amplifies a small differential signal (20mV) to TTL
logic levels. Due to the high gain and tight threshold of the
receiver , care should be taken to prevent noise from appearing
as a valid signal.
The receiver’ s internal fail-safe circuitry is designed to source/
sink a small amount of current, providing fail-safe protection
(a stable known state of HIGH output voltage) for floating,
terminated or shorted receiver inputs.
1. Open Input Pins. The UT54LVD S0 32LV is a quad
receiver device, and if an application requires only 1, 2
or 3 receivers, the unused channel(s) inputs should be
left OPEN. Do not tie unused receiver inputs to ground
or any other voltages. The input is biased by internal
high value pull up and pull down resi st ors to set the
output to a HIGH state. This internal circuitry will
guarantee a HIGH, stable output state fo r open inputs.
2. T erminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a three-state or power-
off condition, the receiver output will again be in a
HIGH state, even with the end of cable 100Ω
termination resistor across the input pins. The
unplugged cable can become a floating antenna which
can pick up noise. If the cable picks up more than 10mV
of differential noise, the receiver may see the noise as
a valid signal and switch. To insure that any noise is
seen as common-mode and not differential, a balanced
interconnect should be used. Twisted pair cable offers
better balance than flat ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output remains
in a HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (VSS to
2.4V). It is only supported with inputs shorte d and no
external common-mode voltage applied.
4
OPERATIONAL ENVIRONMENT
Notes:
1. Guarnteed but not tested.
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperatu re may be incr eased to +175°C during burn-in and life test.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Ionizing Dose (TID) 1.0E6 rad(Si)
Single Event Latchup (SEL) >100 MeV-cm2/mg
Neutron Fluence11.0E13 n/cm2
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.3 to 4.0V
VI/O Voltage on any pin during operation -0.3 to (VDD + 0.3V)
Voltage on any pin during cold spare -.3 to 4.0V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissipation 1.25 W
TJMaximum junction te mperature2+150°C
ΘJC Thermal resistance, junction-to-case310°C/W
IIDC input current ±10mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 3.0 to 3.6V
TCCase temperature range -55 to +125°C
VIN DC input voltage, receiver inputs
DC input voltage, log ic inp uts 2.4V
0 to VDD for EN, EN
5
DC ELECTRICAL CHARACTERISTICS* 1
(VDD = 3.3V + 0.3V; -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed
maximum junction temperature specification.
3. Guaranteed by characterization.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (TTL) 2.0 V
VIL Low-level input voltage (TTL) 0.8 V
VOL Low-level output voltage IOL = 2mA, VDD = 3.0V 0.25 V
VOH High-level output voltage IOH = -0.4mA, VDD = 3.0V 2.7 V
IIN Logic input leakage current Enables = EN/EN = 0 and 3.6V,
VDD = 3.6 -10 +10 μA
IIReceiver input Current VIN = 2.4V -15 +15 μΑ
ICS Cold Spare Leakage Current VIN=3.6V, VDD=VSS -20 +20 μΑ
VTH3Differential Input High Threshold VCM = +1.2V +100 mV
VTL3Differential Input Low Threshold VCM = +1.2V -100 mV
IOZ3Output Three-State Current Disabled, VOUT = 0 V or VDD -10 +10 μΑ
VCL Input clamp voltage ICL = +18mA -1.5 V
IOS2, 3 Output Short Circuit Current Enabled, VOUT = 0 V2-15 -130 mA
ICC3Supply current, receivers enabled EN, EN = VDD or VSS
Inputs Open
15 mA
ICCZ3Supply current, receivers disabled EN = VSS, EN = VDD
Inputs Open 4mA
6
AC SWITCHING CHARACTERISTICS 1, 2, 3
(VDD = +3.3V + 0.3V, TC = -55 °C to +125 °C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019,
Condition A up to the maximum TID level procured.
1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.
2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z0 = 50Ω, tr and tf (0% - 100%) < 1ns for RIN and tr and tf < 1ns for EN or EN.
3. CL includes probe and jig capacitance.
4. Guaranteed by characterization.
5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
SYMBOL PARAMETER MIN MAX MIN MAX UNIT
UT54LVDS032LV UT54LVDS032LVE
tPHLD Differential Propagation Delay High to Low
CL = 10pf (figures 4 and 5) 1.0 4.0 1.0 1.9 ns
tPLHD Differential Propagation Delay Low to High
CL = 10pf (figures 4 and 5) 1.0 4.0 1.0 1.9 ns
tSKD Differential Skew (tPHLD - tPLHD) (figures 4 and 5) 0 350 0 210 ps
tSK1 Channel-to-Channel Skew1 (figures 4 and 5) 0 500 0 200 ps
tSK2 Chip-to-Chip Skew5 (figures 4 and 5) 3.0 0.9 ns
tTLH4Rise Ti me (figures 4 and 5) 1.2 1.2 ns
tTHL4Fall Time (figures 4 and 5) 1.2 1.2 ns
tPHZ Disable Time High to Z (figures 6 and 7) 12 3.8 ns
tPLZ Disable Time Low to Z (figures 6 and 7) 12 3.8 ns
tPZH Enable Time Z to High (figures 6 and 7) 12 3.8 ns
tPZL Enable Time Z to Low (figures 6 and 7) 12 3.8 ns
7
R
RIN+ ROUT
Receiver Enabled
Generator
50Ω
Figure 4. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit
RIN-
50Ω
40pF
RIN-
RIN+
ROUT
tPHLD
VOL
VOH
+1.1V
50%
+1.2V
tTHL
20%
80%
50%
20%
80%
tTLH
0V Differential
Figure 5. Receiver Propagation Delay and Transition Time Waveforms
tPLHD
VID = 200mV
+1.3V
8
Figure 6. Receiver Three-State Delay Test Circuit or Equivalent Circuit
RIN+
RIN-
EN VDD
2K
100Ω
40pf
EN when EN = VDD
EN when EN = VSS
Output when
VID = -100mV
Output when
VID = +100mV
tPHZ tPZH
0.5V 50%
VOH
VOZ
VOZ
0V
VDD
0V
VDD
1.5V
1.5V
1.5V
1.5V
0.5V
tPZL
tPLZ
Figure 7. Receiver Three-State Delay Waveform
50%
VOL
9
10
ORDERING INFORMATION
UT54LVDS032LV/E QUAD RECEIVER:
UT54************- * * * * *
Device Type:
LVDS032LV LVDS Receiver
LVDS032LVE LVDS Receiver Enhanced AC’s
Access T i me:
Not applicable
Package Type:
(U) = 16-lead Flatpack (dual-in-line)
Screening:
(C) = HiRel Temperature Range flow
(P) = Prototype flow
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. T ested at 25°C only . Lead finish is GOLD ONLY. Radiation neither
tested nor guaranteed.
4. HiRel T emperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.
Radiation neither tested nor guaranteed.
11
UT54LVDS032LV /E QUAD RECEIVER: SMD
5962 - ** *
Federal Stock Class Designator: No Options
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)
Drawing Number: 5962-98652
Device Type
02 = LVDS Receiver, 300k, 500k and 1M Rad(Si)
03 = LVDS Receiver, 100k Rad(Si)
04 = LVDS Receiver with enhanced ACs, 300K, 500K and 1Mrad(Si)
05 = LVDS Receiver with enhanced ACs, 100Krad(Si)
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Case Outline:
(Y) = 16 lead Flatpack (dual-in-line)
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
**
98652
Notes:
1.Lead finish (A,C, or X) must be specified.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
12
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changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
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Aeroflex Colordo Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel