1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• Internal control latches and address decoder
• Short set-up and hold times
• Wide operating voltage: 4.5 V to 13.2 V
• 12Vpp analog signal capability
•R
ON 65 max. @ VDD = 12 V, 25C
•RON 10 @ VDD = 12 V, 25C
• Full CMOS switch for low distortion
• Minimum feedthrough and crosstalk
• Separate analog and digital reference supplies
• Low power consumptio n ISO-CMOS technology
Applications
• Key systems
• PBX systems
• Mobile radio
• Test equipment/instrumentation
• Analog/digital multiplexers
• Audio/Video switching
Description
The Zarlink MT8816 is fabricated in Zarlink’s ISO-
CMOS technology providing low power dissipation and
high reliability. The device contains a 8 x 16 array of
crosspoint switches along with a 7 to 128 line decoder
and latch circuits. Any one of the 128 switches can be
addressed by selecting the appropriate seven address
bits. The selected switch can be turned on or off by
applying a logical one or zero to the DATA input. VSS is
the ground reference of the digital inputs. The range of
the analog signal is from VDD to VEE. Chip Select (CS)
allows the crosspoint array to be cascaded for matrix
expansion.
September 2011
Ordering Information
MT8816AP1 44 Pin PLCC* Tubes
MT8816APR1 44 Pin PLCC* Tape & Reel
MT8816AE1 40 Pin PDIP* Tubes
MT8816AF1 44 Pin TQFP* Trays
* Pb Free Matte Tin
-40C to +85C
MT8816
ISO-CMOS 8 x 16 Analog Switch Array
Data Sheet
Figure 1 - Functional Block Diagram
7 to 128
Decoder Latches
8 x 16
Switch
Array
CS STROBE DATA RESET VDD VEE VSS
Xi I/O
(i=0-15)
Yi I/O (i=0-7)
11
128128
• • • • • • • • • • • • • • • • • • •
• • • • • • • • • • • • • • • •
AX0
AX1
AY0
AY1
AY2
AX2
AX3
MT8816 Data Sheet
2
Zarlink Semiconductor Inc.
Change Summary
Changes from the January 2010 issue to the September 2011 issue.
Figure 2 - Pin Connections
Page Item Change
1 Ordering Information Removed leaded packag es as per PCN notice.
40 PIN PLASTIC DIP 44 PIN PLCC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
140
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
AY2
RESET
AX3
AX0
X14
X15
X6
X7
X8
X9
X10
X11
NC
Y7
VSS
Y6
STROBE
Y5
VEE
Y3 Y2
DATA
Y1
CS
Y0
NC
X0
X1
X2
X3
X4
X5
X12
X13
AY1
AY0
AX2
AX1
Y4
VDD
X14
X15
X6
X7
X8
X9
X10
X11
NC
NC
Y7
VSS
Y6
STROBE
Y5
VEE
AX1
AX2
AY0
AY1
NC
Y4
1
6 5 4 3 2 4443424140
7
8
9
10
11
12
13
14
15
16
39
38
37
36
35
34
33
32
31
30
231819202122 2425262728
17 29
Y0
NC
X0
X1
X2
X3
X4
X5
X12
X13
NC
CS
Y1
DATA
Y2
VDD
Y3
AY2
RESET
AX3
AX0
NC
44 PIN TQFP
VSS
Y6
STROBE
Y5
VEE
AX1
AX2
AY0
AY1
NC
Y4
CS
Y1
DATA
Y2
VDD
Y3
AY2
NC
RESET
AX3
AX0
NC
X14
X15
X6
X7
X8
X9
X10
X11
Y7
NC
NC
Y0
X0
X1
X2
X3
X4
X5
X12
X13
NC
2
3
4
5
6
7
8
9
10
11 12 13 141516 18 19 20
132
31
30
29
28
27
26
25
24
23
33
212217
44 43 424140 38 37 36353439
MT8816 Data Sheet
3
Zarlink Semiconductor Inc.
Pin Description
Pin # Name Description
TQFP PDIP PLCC
39 1 1 Y3 Y3 Analog (Input/Output): this is connecte d to the Y3 column of the
switch array.
40 2 2 AY2 Y2 Address Line (Input).
42 3 3 RESET Master RESET (Input): this is used to turn off all switche s regardless
of the condition of CS. Active High.
43,44 4,5 4,5 AX3,AX0 X3 and X0 Address Lines (Input s).
2, 3 6,7 7,8 X14, X15 X14 and X15 Analog (Inputs/Outputs): these are connected to the
X14 and X15 rows of the switch array.
4-9 8-13 9-14 X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-
X11 rows of the sw it ch array.
41,1,11 14 6,15,16 NC No Connection
10 15 17 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the
switch array.
12 16 18 VSS Digital Ground Reference.
13 17 19 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the
switch array.
14 18 20 STROBE STROBE (Input): enables function selected by address and data.
Address must be stable before STROBE goes high and DATA must
be stable on the falling edge of the STROBE. Active High.
15 19 21 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the
switch array.
16 20 22 VEE Negative Power Supply.
17 21 23 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the
switch array.
18,19 22, 23 24,25 AX1,AX2 X1 and X2 Address Lines (Inputs).
20,21 24, 25 26,27 AY0,AY1 Y0 and Y1 Address Lines (Inputs).
24,25 26, 27 30,31 X13, X12 X13 and X12 Analog (Inputs/Outputs): these are connected to the
X13 and X12 rows of the switch array.
26-31 28 - 33 32-37 X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0
rows of the switch array.
22,23,33 34 28,29,
38 NC No Connection.
32 35 39 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column o f the
switch array.
34 36 40 CS Chip Select (Input): this is used to select the device. Active High.
MT8816 Data Sheet
4
Zarlink Semiconductor Inc.
35 37 41 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column o f the
switch array.
36 38 42 DATA DATA (Input): a logic high input will turn on the selected switch an d a
logic low will turn off the selected switch. Active High.
37 39 43 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column o f the
switch array.
38 40 44 VDD Positive Power Supply.
Pin Description (continued)
Pin # Name Description
TQFP PDIP PLCC
MT8816 Data Sheet
5
Zarlink Semiconductor Inc.
Functional Description
The MT8816 is an analog switch matrix with an array size of 8 x 16. The switch array is arranged such that there
are 8 columns by 16 rows. The columns are referred to as the Y inputs/outputs and the rows are the X
inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and
provide a high degree of isolation when turned off. The control memory consists of a 128 bit write only RAM in
which the bits are selected by the address inputs (AY0-AY2, AX0-AX3). Data is presented to the memory on the
DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and STROBE inputs
are high and are latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the
corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches
corresponding to the addressed memory location are altered when data is written into memory. The remaining
switches retain their previous states. Any combination of X and Y inputs/outputs can be interconnected by
establishing appropriate patterns in the control memory. A logical “1” on the RESET input will asynchronously return
all memory locations to logical “0” turning off all crosspoint switches regardless of whether CS is high or low.
Two voltage reference pins (VSS and VEE) are provided for the MT8816 to enable switching of negative analog
signals. The range for digital signals is from VDD to VSS while the range for analog signals is from VDD to VEE. VSS
and VEE pins can be tied together if a single voltage reference is needed.
Address Decode
The seven address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable
signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To
write to a location, RESET must be low and CS must go high while the address and data are set up. Then the
STROBE input is set high and then low causing the data to be latc hed. The data can be changed while STROBE is
high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be
stable on the falling edge of STROBE in order for correct data to be written to the latch.
Applications
Figure 3 shows a typical Operating Circuit of a video surveillance system using analog crosspoint switches which
allow multiple video sources switched to multiple output devices, e.g., video monitor, video recorder etc.
Figure 3 - Typical Video Surveillance System
Analog Crosspoint Switch
Quad Video Drivers
NTSC
/ PA L
Cameras
Quad Video Amplifiers
Video
Monitors
MT8816 Data Sheet
6
Zarlink Semiconductor Inc.
Figure 4 illustrates the major components of a video surveillance system. In the center is the MT8816, a 16 x 8
analog cross-point IC. At the left are 16 video input buffers CLC2005 from Cadeka Microcircuits. At the right hand
side are 8 video output buffers CLC2005 and each buffer is capable of driving a 75 ohm video load directly. BNC
connectors are provided for all video inputs and video outputs.
A FT245R USB FIFO from Future Tec hnology Dev ices International (FTDI) provides a standard USB interface for a
PC. Through this USB connection the PC controls the switching of the video signals.
Figure 4 - Functional Block Diagram for a 16 x 8 Video Surveillance System using MT8816
Ca deka Input Buffers
C adeka Out
p
ut Bu ffe rs
MT8816
16 x 8
Switch
matrix
Vi deo In
(
1 of 16
)
FT DI FT245R
USB
From
PC
Video Out
(1 of 8 )
Contro l a n d I/ O
MT8816 Data Sheet
7
Zarlink Semiconductor Inc.
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
† DC Electrical Charac teristics are over recommended temperature range.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated.
Parameter Symbol Min. Max. Units
1 Supply Voltage VDD
VSS -0.3
-0.3 16.0
VDD+0.3 V
V
2 Analog Input Voltage VINA -0.3 VDD+0.3 V
3 Digital Input Voltage VIN VSS-0.3 VDD+0.3 V
4 Current on any I/O Pin I 15 mA
5 Storage Temperature TS-65 +150 C
6 Package Power Dissipation PLASTIC DIP PD0.6 W
Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated.
Characteristics Sym. Min. Typ. Max. Units Test Conditions
1 Operating Temperature TO-40 25 85 C
2 Supply Voltage VDD
VSS 4.5
VEE 13.2
VDD-4.5 V
V
3 Analog Input Voltage VINA VEE VDD V
4 Digital Input Voltage VIN VSS VDD V
DC Electrical Characteristics†- Voltages are with respect to VEE = VSS = 0 V, VDD =12 V unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Quiescent Supply Current IDD 1 100 A All digital inputs at VIN=VSS or
VDD
0.4 1.5 mA All digital inputs at VIN=2.4V +
VSS; VSS=7.0 V
5 15 mA All digital inputs at VIN=3.4 V
2 Off-state Leakage Current
(See G.9 in Appendix) IOFF 1500 nA IVXi - VYjI = VDD - VEE
See Appendix, Fig. A.1
3 Input Logic “0” level VIL 0.8+VS
SVV
SS=7.5V; VEE=0 V
4 Input Logic “1” level VIH 2.0+VSS VV
SS=6.5V; VEE=0 V
5 Input Logic “1” level VIH 3.3 V
6 Input Leakage (digital pins) ILEAK 0.1 10 A All di gital inputs at VIN = VSS
or VDD
MT8816 Data Sheet
8
Zarlink Semiconductor Inc.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measureme nts are for Plastic D IPS only, cr osstalk values for PLCC packages are a pproximately 5 dB better.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics Sym. 25C70C85C Units Test Conditions
Typ. Max. Typ. Max. Typ. Max.
1 On-state VDD=12V
Resistance VDD=10V
VDD= 5V
(See G.1, G.2, G.3 in
Appendix)
RON 45
55
120
65
75
185
75
85
215
80
90
225
VSS=VEE=0 V,VDC=VDD/2,
IVXi-VYjI = 0.4 V
See Appendix, Fig. A.2
2 Difference in on-state
resistance between
two switches
(See G.4 in Appendix)
RON 510 10 10VDD=12V, VSS=VEE=0,
VDC=VDD/2,
IVXi-VYjI = 0.4 V
See Appendix, Fig. A.2
AC Electrical Characteristics† - Crosspoint Performance-Voltages are with respect to VDD= 5 V, VSS= 0 V, VEE= -7 V, unless
otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Switch I/O Capacitance CS20 pF f=1 MHz
2 Feedthrough Capacitance CF0.2 pF f=1 MHz
3 Frequency Response
Channel “ON”
20LOG(VOUT/VXi)=-3 dB
F3dB 45 MHz Switch is “ON”; VINA = 2Vpp
sinewave; RL = 1 k
See Appendix, Fig. A.3
4 Total Harmonic Distortion
(See G.5, G.6 in Appendix) THD 0.01 % Switch is “ON”; VINA = 2Vpp
sinewave f= 1 kHz; RL=1 k
5 Feedthrough
Channel “OFF”
Feed.=20LOG (VOUT/VXi)
(See G.8 in Appendix)
FDT -95 dB All Switches “OFF”; VINA=
2Vpp sinewave f= 1 kHz;
RL= 1 k.
See Appendix, Fig. A.4
6 Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk=20LOG (VYj/VXi).
(See G.7 in Appendix).
Xtalk -45 dB VINA=2Vpp sine w a ve
f= 10 MHz; RL = 75 .
-90 dB VINA=2Vpp sine wave
f= 10 kHz; RL = 600 .
-85 dB VINA=2Vpp sine wave
f= 10 kHz; RL = 1 k.
-80 dB VINA=2Vpp sine wave
f= 1 kHz; RL = 10 k.
Refer to Appendix, Fig. A.5
for test circuit.
7 Propagation delay through
switch tPS 30 ns RL=1 k; CL=50 pF
MT8816 Data Sheet
9
Zarlink Semiconductor Inc.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5 ns.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
¿ Refer to Append ix, Fig. A.7 for test circuit.
AC Electrical Characteristics† - Control and I/O Timings- Voltages are with resp ect to VDD = 5 V, VSS = 0 V, VEE = -7V, unless
otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
CXtalk 30 mVpp VIN=3 V squarewave;
RIN=1 k, RL=10 k.
See Appendix, Fig. A.6
2 Digital Input Cap acitance CDI 10 pF f=1 MHz
3 Switching Frequency FO20 MHz
4 Setup Time DATA to STRO B E tDS 10 ns RL= 1 k, CL=50 pF ¿
5 Hold Time DATA to STROBE tDH 10 ns RL= 1 k, CL=50 pF ¿
6 Setup Time Address to
STROBE tAS 10 ns RL= 1 k, CL= 50pF ¿
7 Hold Time Address to STROBE tAH 10 ns RL= 1 k, CL=50 pF ¿
8 Setup Time CS to STROB E tCSS 10 ns RL= 1 k, CL=50 pF ¿
9 Hold Time CS to STROBE tCSH 10 ns RL= 1 k, CL=50 pF ¿
10 STROBE Pulse Width tSPW 20 ns RL= 1 k, CL=50 pF ¿
11 RESET Pulse Width tRPW 40 ns RL= 1 k, CL=50 pF ¿
12 STROBE to Switch Status Delay tS40 100 ns RL= 1 k, CL=50 pF ¿
13 DATA to Switch Status Delay tD50 100 ns RL= 1 k, CL=50 pF ¿
14 RESET to Switch Status Delay tR35 100 ns RL= 1 k, CL=50 pF ¿
MT8816 Data Sheet
10
Zarlink Semiconductor Inc.
Figure 5 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
tCSS tCSH
tRPW
tSPW
tAS
tAH
tDH
tDtStRtR
tDS
50% 50%
50% 50%
50%50%50%
50% 50%
50% 50%
CS
RESET
STROBE
ADDRESS
DATA
SWITCH* ON
OFF
MT8816 Data Sheet
11
Zarlink Semiconductor Inc.
Table 1 - Address Decode Truth Table
* Switch connections are not in ascending order
AX0 AX1 AX2 AX3 AY0 AY1 AY2 Connection*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X0-Y0
X1-Y0
X2-Y0
X3-Y0
X4-Y0
X5-Y0
X12-Y0
X13-Y0
X6-Y0
X7-Y0
X8-Y0
X9-Y0
X10-Y0
X11-Y0
X14-Y0
X15-Y0
0
1
0
1
0
1
0
1
1
1
0
0
0
0
X0-Y1
X15-Y1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
X0-Y2
X15-Y2
0
1
0
1
0
1
0
1
1
1
1
1
0
0
X0-Y3
X15-Y3
0
1
0
1
0
1
0
1
0
0
0
0
1
1
X0-Y4
X15-Y4
0
1
0
1
0
1
0
1
1
1
0
0
1
1
X0-Y5
X15-Y5
0
1
0
1
0
1
0
1
0
0
1
1
1
1
X0-Y6
X15-Y6
0
1
0
1
0
1
0
1
1
1
1
1
1
1
X0-Y7
X15-Y7
MT8816 Data Sheet
12
Zarlink Semiconductor Inc.
44 Pin TQFP
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Za rlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The pr oducts, their specifications, services a nd other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performan ce or su itability of any produ ct or servi ce. Inf ormatio n concerni ng po ssible meth ods of u se is p rovided a s a guide only and doe s not co nstitut e
any guarantee th at such methods of use will be satisfactory in a sp ecific piece of equip ment. It is the user ’s responsibili ty to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up t o date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or paramete rs. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user . All products and materials are sold and services provided subject to Zarlink’s conditions of sa le w hich are avai la ble on req ues t.
Purchase of Zarlink’s I2C components conveys a license un der the Philips I2C Patent rights to use thes e components in an I2C System, provided that the syste m
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
trademarks of Zarlink Semiconductor Inc.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
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