High Speed Deserialization Board (HSDB)
HSC-ADC-FPGA
Rev. C
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
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FEATURES FUNCTIONAL BLOCK DIAGRAM
FPGA
XILINX
XC2V250
+3.0V
REG
+3.0V
REG
USB
CTLR
+1.5V
REG
n
n n
n
STANDARD
USB 2.0
TIMING
CIRCUIT
CHA FIFO,
32k,
133MHz
CHB FIFO,
32k,
133MHz
120-PIN
CONNECTOR
HSC-ADC-EVALA/B-SC
OR
HSC-ADC-EVALA/B-DC
HSC-ADC-FPGA
SERIAL LVDS
HIGH SPEED ADC
EVALUATION BOARD
DATA
FCO
DCO
HIGH SPEED
CONNECTOR
FILTERED
ANALOG
INPUT
PS PS PSREG
SPI SPI
EPROM
CLOCK INPUT
CLOCK
CIRCUIT
ADC
05053-001
SPI
Used in tandem with buffer memory board for capturing and
converting high speed serial LVDS digital data to parallel
CMOS logic levels for both quad and octal ADCs
Used with high speed ADC evaluation boards that have serial
LVDS outputs
Features Xilinx® XC2V250-5FG256C FPGA, Virtex-II FPGA
Can switch up to 4/8 channels of output data (2 at a time)
Easily configurable, supporting 8-bit to 14-bit ADCs
Allows standard JTAG user connection for additional code
modifications
EQUIPMENT NEEDED
Any high speed ADC evaluation board that supports serial
LVDS digital output format
HSC-ADC-EVALA/B-DC, Analog Devices, Inc., data capture
FIFO board
Figure 1. Simplified Functional Block Diagram
GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
1. Easy to set up.
Connect the power supply and signal sources to the two
evaluation boards. Then connect to the PC and evaluate
the performance instantly.
The high speed deserialization board (HSDB) captures up to
four/eight channels of serial LVDS digital outputs and converts
the outputs to standard parallel CMOS format. It supports
quad/octal analog-to-digital converter (ADC) evaluation
boards, enabling the user to connect to the Analog Devices
FIFO board (HSC-ADC-EVALA/B-DC). Together, these boards
can be connected to a PC through a USB port and used with the
ADC Analyzer™ to evaluate the performance of high speed
quad/octal ADCs. Users can view both time and frequency
information for a specific analog input and encode rate and
analyze SNR, SINAD, SFDR, and harmonic information.
2. JTAG user interface.
With the supplied JTAG connection, users can implement
unique features in the FPGA.
3. Up to 840 Mbps available on each channel.
14-bit quad/octal ADCs with encode rates as high as
60 MSPS can be used with the deserialization board.
The evaluation kit, which includes a wall-mount switching
power supply, is easy to set up. Additional equipment required
includes an Analog Devices high speed quad/octal ADC
evaluation board, dual-channel FIFO board, a signal source,
and a clock source. Once the kit is connected and powered, the
evaluation is enabled instantly on the PC.
The HSC-ADC-FPGA supports up to four/eight ADC channels,
providing two parallel CMOS outputs simultaneously.
HSC-ADC-FPGA
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Equipment Needed........................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
HSDB Quick Start............................................................................. 3
Requirements ................................................................................ 3
Additional Information and Updates ........................................ 3
Quick Start Steps .......................................................................... 3
Deserialization Board....................................................................... 4
Supported ADC Evaluation Boards........................................... 4
Theory of Operation ........................................................................ 5
Code Description ......................................................................... 5
Manual Installation and Customization.................................... 5
Jumpers ...............................................................................................6
Resolution Settings........................................................................6
Channel Selection Settings...........................................................6
Data Alignment .............................................................................6
DCO Phase Alignment.................................................................6
SPI® Interface..................................................................................7
FIFO Jumper Settings ...................................................................7
Evaluation Board ...............................................................................8
Power Supplies...............................................................................8
HSDB Schematics and PCB Layout ................................................9
Ordering Information.................................................................... 18
Bill of Materials........................................................................... 18
Ordering Guide .......................................................................... 20
ESD Caution................................................................................ 20
REVISION HISTORY
10/06—Rev. B to Rev. C
Added Quad-/Octal-Channel High Speed Serial LVDS to
Parallel CMOS Converter (HSC-ADC-FPGA-8) .....Universal
Changes to Figure 2.......................................................................... 4
Changes to Table 1............................................................................ 4
Changes to Figure 3.......................................................................... 5
Changes to Channel Selection Settings Section ........................... 6
Changes to Table 3............................................................................ 6
Changes to Table 4............................................................................ 6
Changes to Figure 5 to Figure 14.................................................... 8
Changes to Table 6.......................................................................... 18
Changes to Ordering Guide .......................................................... 20
11/05—Rev. A to Rev B
Changed HSC-ADC-EVALA-DC to
HSC-ADC-EVALA/B-DC............................................Universal
Changes to Figure 1...........................................................................1
Changes to Table 1.............................................................................4
Changes to the Theory of Operation Section and Figure 3.........5
Added the SPI Interface Section......................................................7
Changes to Figure 5...........................................................................8
Changes to Figure 6...........................................................................9
Updated Schematic and Layout to Rev D ................................9-17
Changes to Table 6.......................................................................... 17
Changes to Ordering Guide.......................................................... 20
02/05—Rev. 0 to Rev. A
Updated Bill of Materials............................................................... 15
Changes to Ordering Guide.......................................................... 16
10/04—Revision 0: Initial Version
HSC-ADC-FPGA
Rev. C | Page 3 of 20
HSDB QUICK START
The HSDB is used to create an interface from a quad/octal ADC
evaluation board that has serial LVDS outputs to the FIFO
data capture board.
REQUIREMENTS
The following equipment is needed to set up the HSDB:
• FIFO evaluation board, ADC Analyzer, USB cable, and
FIFO data sheet
• High speed ADC evaluation board and ADC data sheet
• Power supply for ADC evaluation board, HSDB, and FIFO
• Analog signal source and appropriate filtering
• Low jitter clock source applicable for specific ADC
evaluation, typically <1 ps rms
• PC with Windows® 98 (2nd edition), Windows 2000,
Windows ME, or Windows XP for the ADC Analyzer
• PC with a USB 2.0 port recommended for FIFO
connection
ADDITIONAL INFORMATION AND UPDATES
For more information on the ADC Analyzer and the FIFO
data capture board, and for software updates, visit
www.analog.com/FIFO.
For more information on LVDS data output, see the LVD S D ata
Outputs for High Speed Analog-to-Digital Converters Application
Note (AN-586) on www.analog.com.
QUICK START STEPS
Connect the quad/octal ADC evaluation board to the high
speed backplane connector side of the HSDB. Then connect the
other side of the HSDB to the 120-pin connector header that
mates to the FIFO board.
1. Connect the USB cable to the FIFO evaluation board and
to a USB port on the PC.
2. Set the FIFO jumper settings in dual-channel configuration
as shown in the HSC-ADC-EVALA/B-DC data sheet,
located at www.analog.com/FIFO.
3. Verify and connect the appropriate power supplies to the
FIFO, HSDB, and ADC evaluation boards.
4. Apply power to the evaluation boards and check the
voltage levels at the board level. Separate supplies may be
necessary.
5. Connect the appropriate analog input (which should be
filtered with a band-pass filter) and low jitter clock signal.
6. Start the ADC Analyzer to begin the evaluation.
HSC-ADC-FPGA
Rev. C | Page 4 of 20
DESERIALIZATION BOARD
OPTION
A
L
POWER
CONNECTION
JTAG
CONNECTOR
120-CONNECTOR
(TO FIFO)
DLL RESET
SWITCH
ADC RESOLUTION
JUMPERS
ADC CHANNEL
SELECTION JUMPERS
CHANNELS A, B, C, D
HIGH SPEED
BACKPLANE
CONNECTOR
(FROM ADC
EVAL BOARD)
XILINX
X
C2V250-5FG256C
FPGA
XILINX
XCF02SV020C
EEPROM
DCO PHASE
SHIFTER CIRCUIT
6V SWITCHING
POWER SUPPLY
CONNECTION
05053-002
ADC CHANNEL
SELECTION JUMPERS
CHANNELS E, F, G, H
Figure 2. HSC-ADC-FPGA-8 Components
SUPPORTED ADC EVALUATION BOARDS
The evaluation boards in Table 1 can be used with the high speed ADC deserialization board.
Table 1. Supported ADC Evaluation Boards
Evaluation Board Model Description of ADC Comments
AD9289-65EB 8-bit, 65 MSPS quad ADC Requires HSC-ADC-FPGA-9289 and HSC-ADC-EVALA/B-DC (dual-channel)
AD9229-65EB 12-bit, 65 MSPS quad ADC Requires HSC-ADC-FPGA-4/-8 and HSC-ADC-EVALA/B-DC (dual-channel)
AD9287-100EB 8-bit, 100 MSPS quad ADC Requires HSC-ADC-FPGA-4/-8 and HSC-ADC-EVALA/B-DC (dual-channel)
AD9219-65EB 10-bit, 65 MSPS quad ADC Requires HSC-ADC-FPGA-4/-8 and HSC-ADC-EVALA/B-DC (dual-channel)
AD9228-65EB 12-bit, 65 MSPS quad ADC Requires HSC-ADC-FPGA-4/-8 and HSC-ADC-EVALA/B-DC (dual-channel)
AD9259-50EB 14-bit, 50 MSPS quad ADC Requires HSC-ADC-FPGA-4/-8 and HSC-ADC-EVALA/B-DC (dual-channel)
AD9212-65EB 10-bit, 65 MSPS quad ADC Requires HSC-ADC-FPGA-8 and HSC-ADC-EVALA/B-DC (dual-channel)
AD9222-50EB 12-bit, 50 MSPS quad ADC Requires HSC-ADC-FPGA-8 and HSC-ADC-EVALA/B-DC (dual-channel)
AD9252-50EB 14-bit, 50 MSPS quad ADC Requires HSC-ADC-FPGA-8 and HSC-ADC-EVALA/B-DC (dual-channel)
HSC-ADC-FPGA
Rev. C | Page 5 of 20
THEORY OF OPERATION
The HSDB, featuring the Xilinx Virtex-II FPGA, accepts
four/eight ADC channels of LVDS serial data and the data
output and frame align clocks (DCO and FCO). The FPGA
then converts all of these signals from LVDS to single-ended
CMOS signals.
The HSDB can support 8-bit to 14-bit ADCs. The DCO signal
is used to clock the incoming data through 14 shift registers.
Seven of these registers are clocked on the rising edge of DCO,
and the other seven are clocked on the falling edge (DDR), as
shown in Figure 3. The ADC resolution is selectable using
Jumper Connection JP101 and Jumper Connection JP102.
Both the DCO and FCO are used inside the FPGA to set up
all necessary clock edges to take the parallel data from the shift
registers to the output of the FPGA. The DLL/Timing Reset
button (PB101) is used to set the data capture timing to the
default setting (see Table 4).
Once the parallel data has been transferred completely to the
FCO clock domain, the data is multiplexed for use with the
2-channel FIFO board (HSC-ADC-EVALA/B-DC). ADC
Channel A and Channel B are selected using the JP104 jumper
connection. Channel C and Channel D are selected using the
JP103 jumper connection. Data clock outputs (CLK_AB and
CLK_CD) are also provided to clock the FIFO board.
CODE DESCRIPTION
The FPGA on the HSDB comes with Verilog code preinstalled
and tested. It is designed to help evaluate the performance of an
Analog Devices quad/octal ADC quickly and easily by
providing the user with familiar CMOS logic-level outputs.
MANUAL INSTALLATION AND CUSTOMIZATION
Users can manually customize or update the necessary code
through a JTAG connector provided on the deserialization
board, as shown in Figure 2. However, Analog Devices provides
no guarantee of performance if the code is customized.
A Zip file containing all of the necessary default configuration
files to implement manual changes or to add custom module
blocks for further computation is at www.analog.com/FIFO.
ASSEMBLE
DATA
MUX
SHIFT RISING
SHIFT FALLING
JP103
JP104
7
n
n
n
n
n
7
ASSEMBLE
DATA
SHIFT RISINGLVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOSFCO
CHB
CHA
CHC
CHD
OCTAL ADC
WITH SERIAL
LVDS OUTPUTS
DCO
CHF
CHE
CHG
CHH
JP101, JP102
JP, PB100, PB101
DATA OUT ABCD
CLK_ABCD
SHIFT FALLING
7
7
ASSEMBLE
DATA
SHIFT RISING
SHIFT FALLING
7
7
ASSEMBLE
DATA
SHIFT RISING
SHIFT FALLING
7
7
ASSEMBLE
DATA
SHIFT RISING
SHIFT FALLING
7
7
ASSEMBLE
DATA
SHIFT RISINGLVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
SHIFT FALLING
7
7
ASSEMBLE
DATA
SHIFT RISING
SHIFT FALLING
7
7
ASSEMBLE
DATA
SHIFT RISING
SHIFT FALLING
7
7
MUX
JP105
JP106
n
n
n
n
n
DATA OUT EFGH
CLK_EFGH
05053-003
Figure 3. Internal FPGA Functional Block Diagram
HSC-ADC-FPGA
Rev. C | Page 6 of 20
JUMPERS
RESOLUTION SETTINGS DCO PHASE ALIGNMENT
The HSDB supports ADCs with 8 bits to 14 bits of resolution.
Use Table 2 to configure the appropriate jumpers. In Table 2,
0 indicates an open jumper, and 1 indicates a shorted jumper.
The DCO Phase Shift button (PB100) can be used in
conjunction with the DCO Phase Shift jumper (JP100) to adjust
the phase relationship between the incoming DCO signal and
the FPGA DLL signal.
Table 2. Resolution Jumper Settings The output of the FPGA DLL is used to capture the incoming
serial data streams. The rising edge and falling edge of this
signal must be aligned, so that they occur during the center of
the data eye as shown in Figure 4.
Number of Bits JP101 JP102
8 0 0
10 0 1
12 1 0
05053-004
t
0
t
DATA
FPGA DLL–
FPGA DLL+
DCO–
DCO+
D–
D+
MSB MSB – 1 MSB – 2
14 1 1
CHANNEL SELECTION SETTINGS
The ADC Channel A through Channel D are associated with
the top IDT FIFO chip, the one closest to the Analog Devices
logo; Channel B; or ADC Analyzer Channel B. ADC Channel E
through Channel H are associated with the bottom IDT FIFO
chip, Channel A, or ADC Analyzer Channel A. Use Table 3 to
configure the jumper settings for channel selection. In Table 3,
0 indicates an open jumper, and 1 indicates a shorted jumper.
Figure 4. DCO Phase Shifting Alignment Example
Table 3. Channel Selection Jumper Settings After activating the DLL/Timing Reset button (PB101), the
phase of the DLL is set to its default value. If this phase
alignment setting is not compatible with the current
configuration of the ADC under test, it can be adjusted.
FIFO Channel/
ADC Analyzer Channel
ADC Channel Channel Select
A Channel B/Channel B JP103 = 0, JP104 = 0
B Channel B/Channel B JP103 = 0, JP104 = 1 The phase shift operation is activated by pressing the DLL
Phase Shift button (PB100). The direction of this adjustment is
determined by the setting of the DLL Phase Shift jumper
(JP100); see Table 5.
C Channel B/Channel B JP103 = 1, JP104 = 0
D Channel B/Channel B JP103 = 1, JP104 = 1
E Channel A/Channel A JP105 = 0, JP106 = 0
F Channel A/Channel A JP105 = 0, JP106 = 1
G Channel A/Channel A JP105 = 1, JP106 = 0 Table 5. DCO Phase Shift Alignment Settings
H Channel A/Channel A JP105 = 1, JP106 = 1 DCO Phase Shift JP100
Increment 0
DATA ALIGNMENT Decrement 1
The DLL/Timing Reset button (PB101) must be pressed to
operate the HSDB after initial power-up. Data alignment is
automatic; however, the DLL/Timing Reset button must be
pressed any time the ADC sample clock rate is changed, or data
outputs become corrupted.
While the DLL Phase Shift button is clicked, the phase is
adjusted continuously over the range of the PHASE_SHIFT
user constraint. The PHASE_SHIFT variable can be set to any
integer value between ±255. The actual setting of this variable is
lost when using this function. However, an out-of-range condition
is indicated by LED CR100. If the phase has gone out of range,
it can be set back in range either by using the DLL/Timing Reset
button (PB101) or by changing the adjustment direction using
Jumper JP100 and clicking the PB100 button again.
After pressing the DLL/Timing Reset button, the FPGA digital
clock manager (DCM) DLL is reset to its default setting. This
value (PHASE_SHIFT) is defined in the user constraints file of
the FPGA software and is shown in Table 4.
Table 4. Default PHASE_SHIFT User Constraint Settings The rate of phase change while the PB100 button is clicked
is determined by multiplying the FCO clock period by
227 (256 steps × 219). This gives the amount of time in seconds
that it takes to slew from PHASE_SHIFT = 0 to the minimum
or maximum value. For example, if FCO = 65 MHz, it takes
approximately 2 sec to slew from PHASE_SHIFT = 0 to out-of-
range (227 × 1/65M). Refer to the Xilinx Virtex-II data sheet for
further details on DCM phase shifting.
Product PHASE_SHIFT User Constraint
AD9289 +50
AD9229 −10
−10
AD9219/AD9228/
AD9259/AD9287
−10
AD9212/AD9222/
AD9252
HSC-ADC-FPGA
Rev. C | Page 7 of 20
SPI® INTERFACE
The HSDB fully supports ADCs that have an SPI interface. The
HSDB does not interact with any of the SPI signals; it provides a
path for the SPI interface to be connected from the HSC-ADC-
EVALB-DC data capture board to the corresponding product
evaluation board.
FIFO JUMPER SETTINGS
The HSDB requires the interface of the HSC-ADC-EVALA/B-
DC (dual-channel FIFO4 or FIFO4.1) for data to be captured
and displayed in the ADC Analyzer. The default settings for
the FIFO dual-channel configuration can be found in the
HSC-ADC-EVALA/B-DC data sheet at www.analog.com/FIFO.
To align the timing properly, some evaluation boards require
modifications to these settings. For proper operation, the FIFO
timing setting should be configured for dual-channel config-
uration. For more details, see the Theory of Operation section
in the HSC-ADC-EVALA/B-SC/HSC-ADC-EVALA/B-DC data
sheet at www.analog.com/FIFO.
Another easy way to determine if the proper jumper settings
between the HSDB, FIFO, and ADC Analyzer have already
been installed is to consult the help menu in the ADC Analyzer
software:
1. From the Help menu, select About HSC_ADC_EVALA.
2. Click Setup Default Jumper Wizard.
3. Click Dual Channel. A picture of the FIFO board for that
application appears, showing the correct jumper settings
already in place.
HSC-ADC-FPGA
Rev. C | Page 8 of 20
EVALUATION BOARD
POWER SUPPLIES
This section describes the optional settings or modes allowed
on the HSC-ADC-FPGA-8, Rev. A, HSDB. Note that when
using the HSC-ADC-FPGA-8 with a quad ADC, the data is
only captured on Channel B of the FIFO4.1 (HSC-ADC-
EVALA/B-DC) and displayed on Channel B of the ADC
Analyzer software. This is because of the way the first four
channels are routed through the PCB and FPGA.
The HSDB board is supplied with a wall mount switching
power supply that provides a 6 V, 2 A maximum output.
Connect the supply to the rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter
jack that connects to the PCB at J300. On the PC board, the 6 V
supply is then fused and conditioned before connecting to two
low dropout linear regulators that supply the proper bias to each
of the various sections on the board (see Figure 5).
The HSDB provides all of the support circuitry required to
accept quad/octal ADC digital serial LVDS outputs. Each of the
various functions and configurations can be selected by proper
connection of various jumpers (see Figure 6 to Figure 8). When
using this in conjunction with an ADC evaluation board and
FIFO, it is critical that the signal sources used for the analog
input and clock have very low phase noise (<1 ps rms jitter) to
realize the ultimate performance of the converter. Proper
filtering of the analog input signal to remove harmonics and
lower the integrated or broadband noise at the input is also
necessary to achieve the specified noise performance.
When operating the evaluation board in a nondefault condition,
L302 and L303 can be removed to disconnect the switching
power supply. This enables the user to bias each section of the
board individually. Use P301 to connect a different supply for
each section. The 3.3 V supply with a 1 A current capability is
needed to bias the input/output supply ring pins of the FPGA.
In addition to the 3.3 V supply, the 1.5 V supply is needed with
a 1 A current capability to bias the core supply pins of the FPGA.
See Figure 6 to Figure 8 for complete schematics and
layout plots.
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
BAND-PASS
FILTER
XFMR
INPUT
CLK
CHA–CHD
OR
CHE–CHH
SERIAL
LVDS
OUTPUTS
SPI SPI
2CH
8-BIT TO 14-BIT
PARALLEL
CMOS
USB
CONNECTION
EVALUATION
BOARD HSC-ADC-FPGA
HIGH SPEED
DESERIALIZATION
BOARD
05053-040
HSC-ADC-EVALB-DC
FIFO DATA
CAPTURE
BOARD
PC
RUNNING
ADC
ANALYZER
6VDC
2Amax
WALL OUTLET
100-240VAC
47-63Hz
SWITCHING
POWER
SUPPLY
3.3V –+–+
3.3V_D
1.5V_FPGA
GND
GND
1.5V
SPISPI
Figure 5. Example Setup Using Quad/Octal ADC Evaluation Board and FIFO Data Capture Board
HSC-ADC-FPGA
Rev. C | Page 9 of 20
HSDB SCHEMATICS AND PCB LAYOUT
05053-008
J200
SCLK_CHB
SDI_CHB
SDO_CHB
CSB3_CHB
CSB4_CHB
SCLK_CHA
SDI_CHA
SDO_CHA
CSB2_CHA
CSB1_CHA
C1
C3
C5
C7
C9
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
C39
C2
C4
C6
C8
C10
C12
C14
C16
C18
C20
C22
C24
C26
C28
C30
C32
C34
C36
C38
C40
J200
D1_17
D1_16
CTRL_A
CTRL_C
D2_17
D2_16
B1
B3
B5
B7
B9
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B35
B37
B39
B2
B4
B6
B8
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
B32
B34
B36
B38
B40
J200
DUTCLK1
CTRL_B
D1_15
D1_14
D1_13
D1_12
D1_11
D1_10
D1_9
D1_8
D1_7 CHB
D1_6
D1_5
D1_4
D1_3
D1_2
D1_1
D1_0
D2_0
D2_2
D2_1
D2_3
D2_5
D2_4
D2_6
D2_8
D2_7
D2_9
D2_11
D2_10
D2_12
D2_15
D2_14
D2_13
CTRL_D
DUTCLK2
A1
A3
A5
A7
A9
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
A33
A35
A37
A39
A2
A4
A6
A8
A10
A12
A14
A16
A18
A20
A22
A24
A26
A28
A30
A32
A34
A36
A38
A40
P
A
R
A
LLEL CMDS OUTPUTS TO FIFO BO
AR
D
J201
1
3
5
7
9
11
13
2
4
6
8
10
12
14
JTAG
CONNECTION
R201
1kΩ
R202
DNP
R204
1kΩ
R203
1kΩ
TMS
TCK
TDO
TDI
3.3V_D
SCLK_CHB
SDI_CHB
SDO_CHB
CSB3_CHB
CSB4_CHB
SCLK_CHA
SDI_CHA
SDO_CHA
CSB1_CHA
CSB2_CHA
DCO
FCO
CHA
CHB
CHC
CHD
DCO
FCO
CHA
CHB
CHC
CHD
LOCK
P200
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
60
59
58
57
56
55
54
53
52
51
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
10
9
8
7
6
5
4
3
2
1
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
GNDCD10
GNDCD9
GNDCD8
GNDCD7
GNDCD6
GNDCD5
GNDCD4
GNDCD3
GNDCD2
GNDCD1
GNDAB10
GNDAB9
GNDAB8
GNDAB7
GNDAB6
GNDAB5
GNDAB4
GNDAB3
GNDAB2
GNDAB1
50
49
48
47
46
45
44
43
42
41
20
19
18
17
16
15
14
13
12
11
CHH
CHE
CHF
CHG
CHH
CHE
CHF
CHG
SERIAL L
V
DS INPUTS FROM EVAL BOA
R
D
U201
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
D0D0
DNC1
CLKCCLK
TDI
TMS
TCK
TDI
TMS
TCK
CFPROG_B
OE/RESETBARINIT_B
DNC2
CE
VCCJ
VCCO
VCCINT
TDO
DNC3
DNC4
DNC5
CEO
DNC6
GND
3.3V_D
TDI_F
CR200
DONE
CONFIG
DONE
R200
261Ω
CH
A
XCF02SV020C
Figure 6. PCB Schematic
HSC-ADC-FPGA
Rev. C | Page 10 of 20
NC = B10, C10, D10, E10, E11, C4, B4
NC = B13, C13, D16, F12, G12, G16
NC = D5, C5, D6, C6, B6, E6, E7, D7, C7
NC = L5, K5, K4, K3, E4, E3, F4, F3, F5, G5
NC=R11,R10,R6,R5,C11,D11,T7,R7
NC = A9, A12, B9, B12, C9, C12, D9, D12
NC = B7, J14, K16, K12, L12, R12
NC = G4, G3, H4, H3, J1, J2, J3, J4, K1, K2
NC = M3, E14, P12, N5, T15, A13, A3, A4, A14
NC = P1, N1, N3, N2, M4, M2, M1, L4, L3, L2, L1
1.5V_FPGA : N13, N4, M12
3.3V_D : FB, E9, F10, F9, G11, H11, H12
3.3V_D : L8, M8, J5, J6, K6, G6, H5, H6
GND : F6, G10, G7, G8, G9, H10, H7, H8
GND : K9, L11, L6, P14, P3, R15, R2, T1, T16
1.5V_FPGA : M5, E12, E5, D13, D4
3.3V_D : B1, B16, R1, R16, E8, F7
3.3V_D : J11, J12, K11, L10, L9, M9, L7
GND : A1, A16, B15, B2, C14, C3, F11
GND : H9, J10, J7, J8, J9, K10, K7, K8
NC = T14, T4, T3, R4, R13, P4, M14, N12, P5
U100: A
IO_L01N_2
IO_L04N_2
IO_L06N_2
IO_L43N_2
IO_L91N_2
IO_L93N_2
IO_L94P_2
IO_L96P_2
IO_L96P_3
IO_L91P_3
IO_L93P_3
IO_L06N_3
IO_L43N_3
IO_L04P_3
IO_L01N_3
IO_L03N_2
IO_L04P_2
IO_L06P_2
IO_L43P_2
IO_L96P_0
IO_L96N_0
IO_L91P_2
IO_L94N_2
IO_L95N_0
IO_L95P_0
IO_L96N_2
IO_L94P_3
IO_L96N_3
IO_L91N_3
IO_L06P_3
IO_L43P_3
IO_L03P_3
IO_L04N_3
IO_L01P_3
DUTCLK1
D1_14
D1_12
D1_10
D1_8
D1_6
D1_4
D1_2
D2_15
D2_13
D2_11
D2_9
D2_7
D2_5
D2_3
D1_15
D1_13
D1_11
D1_9
D1_7
D1_5
D1_3
DUTCLK2
D2_14
D2_12
D2_10
D2_8
D2_6
D2_4
D2_2
C16
E15
F13
F15
G13
G15
H14
H16
J15
K13
K15
L14
L16
M15
N16
E13
E16
F14
F16
G14
H13
H15
J13
J16
K14
L13
A8
D8
B8
C8
L15
M13
M16
P16
SERIAL L
V
DS INPUTS FROM E
V
A
LBO
AR
D
R100
100Ω
DCO
DCO
R101
100Ω
FCO
FCO
IO_L04N_7
IO_L04P_7
E2
E1
IO_L43N_7
IO_L43P_7
IO_L93P_7
IO_L93N_7
F4
G1
F3
G2
R104
100Ω
CHC
CHC
R102
100Ω
CHA
CHA
R103
100Ω
CHB
CHB
IO_L96N_7
IO_L96P_7
H4
H3
R105
100Ω
CHD
CHD
SERIAL LVDS INPUTS
FROM EVAL BOARD
CHA
IO_L96N_6
IO_L96P_6
J1
J2
IO_L93N_6
IO_L93P_6
IO_L43P_6
IO_L43N_6
K3
L2
K4
L1
R108
100Ω
CHG
CHG
R106
100Ω
CHE
CHE
R107
100Ω
CHF
CHF
IO_L04N_6
IO_L04P_6
M3
M4
R109
100Ω
CHH
CHH
XC2V250-5FG256C
VRN4
VRP5
VRP2
VRN5
VRP4
VRP3
DONE
PROG_B
VRN2
CCLK
INIT_B
VRN3
DONE
PROG_B
CCLK
INIT_B
P11
P6
D14
N6
N11
N15
R14
A2
D15
P15
T13
N14
T2
P2
C2
A15
T11
R3
C15
B14
P13
T10
IO_L94P_4
M0
M1
TDI
TCK
IO_L91P_4
M2
TDO
TMS
IO_L02N_4
IO_L96P_5/GCLK6P
IO_L95N_4/GCLK3S
IO_L96N_5/GCLK1S
IO_L93N_4
IO_L92P_4
IO_L96N_5/GCLK7S
IO_L95P_5/GCLK2P
IO_L96P_4/GCLK0P
IO_L93P_3
IO_L92N_4
IO_L92P_5
IO_L93P_5
IO_L95P_5/GCLK4P
IO_L92N_5
IO_L93N_5
IO_L95N_5/GCLK5S
R8
N9
R9
N10
M10
T8
P9
T9
P10
M11
M6
N7
N8
M7
P7
P8
R8
N9
R9
N10
M10
T8
P9
T9
P10
M11
M6
N7
N8
M7
P7
P8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R11
R10
IO_L94P_4
IO_L91P_4
IO_L04P_4
IO_L05N_1
IO_L04N_5
IO_L91N_5
DCO_PHASE_0R
IO_L94P_0
IO_L94N_1
T12
A11
T5
T6
A6
A7
A10
R118
49.9Ω
R119
49.9Ω
R120
49.9Ω
R121
49.9Ω
R122
1kΩ
R123
1kΩ
R131
49.9Ω
R132
49.9Ω
R133
49.9Ω
R126
1kΩ
R127
1kΩ
3.3V_D
3.3V_D
R117
1kΩ
PB101
PB100
3.3V_D
3.3V_D
R115
1kΩ
R116
1kΩ
R114
261Ω
CTRL_CCTRL_D
R112
1kΩ
R113
1kΩ
R134
10kΩ
JP101
JP100
JP102
CR100
CR100 : DCO PHASE
OUT-OF-RANGE
INDICATOR
JP102
OPEN
CLOSED
OPEN
CLOSED
# ADC BITS
RESOL
8-BIT
10-BIT
12-BIT
14-BIT
JP101
OPEN
OPEN
CLOSED
CLOSED
SHIFT
DEC
CLOSED
DCO PHASE
INC
OPEN
PB100 :
JP100 :
PB101: DLL/TIMING RESET
PUSH TO RESET
CHANNEL SELECT
OPEN
CLOSED
OPEN
CLOSED
JP104JP103
OPEN
OPEN
CLOSED
CLOSED
CHANNE L A
CHANNE L B
CHANNE L C
CHANNE L D
OPEN
CLOSED
OPEN
CLOSED
JP106JP105
OPEN
OPEN
CLOSED
CLOSED
CHANNE L E
CHANNE L F
CHANNE L G
CHANNE L H
R137
1kΩ
R138
1kΩ
R111
1kΩ
TDO TMS
TCK
DO
TDI_F
CTRL_A
R135
1kΩ
R136
1kΩ
R139
1kΩ
R140
1kΩ
CTRL_B
CTRL_C
CTRL_D
3.3V_D
JP103
JP104
JP105
JP106
05053-009
LOCK
U100: B
XC2V250-5FG256C
R130
49.9Ω
Figure 7. PCB Schematic (Continued)
HSC-ADC-FPGA
Rev. C | Page 11 of 20
05053-011
DECOUPLING CAPACITORS
C311
0.1µF
C312
0.1µF
C309
0.1µF
C310
0.1µF
C315
1nF
C316
1nF
C313
1nF
C314
1nF
1.5V_FPGA
C325
0.1µF
C326
0.1µF
C327
0.1µF
C319
0.1µF
C320
0.1µF
C317
0.1µF
C318
0.1µF
C323
0.1µF
C324
0.1µF
C321
0.1µF
C322
0.1µF
3.3V_D
C330
1nF
C331
1nF
C336
1nF
C337
1nF
C338
1nF
C328
1nF
C329
1nF
C334
1nF
C335
1nF
C332
1nF
C333
1nF
3.3V_D
H1 H2
H3 H4
MOUNTING HOLES
CONNECTED TO GROUND
OPTIONAL POWER INPUT
C305
10µF
C306
0.1µF
1.5V_FPGA
L300
10µH
P1
P2
P3
P4
1
2
3
4
P301
DNP
3.3V
1.5V
C307
10µF
C308
0.1µF
3.3V_D
L301
10µH
U301
C303
1µF
C304
1µF
32
1
PWR_IN
4
ADP3339AKC-3.3-RL
OUT
OUT
IN
GND
3.3
V
L303
10µH
U300
C301
1µF
C302
1µF
32
1
PWR_IN
4
ADP3339AKC-1.5-RL
OUT
OUT
IN
GND
1.5V
L302
10µH
J300
C300
10µF
1
2
3
F300
6V, 2.2A
D300
50V, 5A
D301
30V, 3A
1
4
2
3
FER300
10µH, 5A
R300
261Ω
CR300
PWR_IN
PO
W
ER SUPPL
INPUT
6V
2A MAX
Figure 8. PCB Schematic (Continued)
HSC-ADC-FPGA
Rev. C | Page 12 of 20
05053-050
Figure 9. Layer 1—Primary Side (Top)
HSC-ADC-FPGA
Rev. C | Page 13 of 20
0
5053-051
Figure 10. Layer 2—Ground Plane
HSC-ADC-FPGA
Rev. C | Page 14 of 20
05053-052
Figure 11. Layer 3—+1.5 V Power Plane and Signal
HSC-ADC-FPGA
Rev. C | Page 15 of 20
05053-053
Figure 12. Layer 4—+3.3V Power Plane and Signal
HSC-ADC-FPGA
Rev. C | Page 16 of 20
05053-054
Figure 13. Layer 5—Ground Plane
HSC-ADC-FPGA
Rev. C | Page 17 of 20
05053-055
Figure 14. Layer 6—Secondary Side (Bottom)
HSC-ADC-FPGA
Rev. C | Page 18 of 20
ORDERING INFORMATION
BILL OF MATERIALS
Table 6. Component Listing1
Item Qty REFDES Device Package Value Manufacturer and Part No.
1 1 HSC-ADC-FPGA-8-EBZ PCB PCB Rev A
2 15
C309, C310, C311, C312, C317,
C318, C319, C320, C321, C322,
C323, C324, C325, C326, C327
Capacitor 402 0.1 F, ceramic, X5R, 10 V,
10% tolerance
Murata,
GRM155R71C104KA88D
3 2 C305, C307 Capacitor 805 10 F, 6.3 V ± 10%,
ceramic, X5R
Murata,
GRM219R60J106KE19D
4 2 C306, C308 Capacitor 603 0.1 F, ceramic, X7R, 16 V,
10% tolerance
Murata,
GRM188R71C104KA01D
5 15
C313, C314, C315, C316, C328,
C329, C330, C331, C332, C333,
C334, C335, C336, C337, C338
Capacitor 402 1 nF, ceramic, X7R,
25 V, 10% tolerance
Murata,
GRM155R71H102KA01D
6 1 C300 Capacitor 1206 10 F, tantalum, 16 V,
10% tolerance
Rohm, TCA1C106M8R
7 4 C301, C302, C303, C304 Capacitor 603 1 F, ceramic, X5R, 6.3 V,
10% tolerance
Panasonic, ECJ-1VB0J105K
8 3 CR100, CR200, CR300 LED SMT Green, 4 V, 5 m candela Panasonic, LNJ314G8TRA
9 1 D301 Diode DO-214AB 30 V, 3 A, SMC Micro Commercial Co., SK33-TP
10 1 D300 Diode DO-214AA 50 V, 2 A, SMC Micro Commercial Co., S2A-TP
11 1 F300 Fuse 1210 6.0 V, 2.2 A trip current
resettable fuse
Tyco/Raychem,
NANOSMDC110F-2
12 1 FER300 Ferrite bead 2020 10 H, 5 A, 50 V, 190 Ω
@ 100 MHz
Murata, DLW5BSN191SQ2L
13 1 J200 Connector HEADER TSW-140-08-G-T-RA,
120-pin header
assembly
Samtec, TSW-140-08-G-T-RA
14 1 J201 Connector HEADER 87832-1420, 14-pin dual
ROM shrouded header
Molex, 87832-1420
15 1 J300 Connector 0.1", PCMT power supply connector Switchcraft, RAPC722X
16 7 JP100, JP101, JP102, JP103,
JP104, JP105, JP106
Connector HEADER 100 mil header jumper,
2-pin
Samtec, TSW-102-07-G-S
17 4 L300, L301, L302, L303 Ferrite bead 1206 10 µH, 50 Ω @ 100 MHz, 3 A Murata, BLM31PG500SN1L
18 1 P200 Connector HEADER 6469028-1, right angle
2 pair, 25 mm, header
assembly
Tyco, 6469028-1
19 2 PB100, PB101 Switch SMT SPST, 20 mA, push-
button switch
Panasonic, EVQ-PHP03T
20 2 R100, R101 Resistor 402 100 Ω, 1/16 W,
5% tolerance
NIC Components,
NRC04F1000TRF
8
R102, R103, R104, R105,
R106, R107, R108, R109
Resistor 201 100 Ω, 1/20 W,
1% tolerance
NIC Components,
NRC02F1000TRF
21 1 R117 Resistor 603 1 kΩ, 1/10 W,
5% tolerance
NIC Components,
NRC06J102TRF
22 18
R111, R112, R113, R115, R116,
R122, R123, R126, R127, R135,
R136, R137, R138, R139, R140,
R201, R203, R204
Resistor 402 1 kΩ, 1/16 W,
1% tolerance
NIC Components,
NRC04F1001TRF
23 3 R114, R200, R300 Resistor 402 261 Ω, 1/16 W,
1% tolerance
NIC Components,
NRC04F2610TRF
24 8 R118, R119, R120, R121,
R130, R131, R132, R133
Resistor 402 49.9 Ω, 1/16 W,
1% tolerance
SUSUMU CO., RR0510R-49R9-D
25 1 R134 Resistor 402 10 kΩ, 1/16 W,
5% tolerance
NIC Components,
NRC04J103TRF
HSC-ADC-FPGA
Rev. C | Page 19 of 20
Item Qty REFDES Device Package Value Manufacturer and Part No.
26 1 U301 IC SOT-223 ADP3339AKC-3.3, 1.5 A,
3.3 V LDO regulator
Analog Devices,
ADP3339AKC-3.3-RL
27 1 U300 IC SOT-223 ADP3339AKC-1.5, 1.5 A,
1.5 V LDO regulator
Analog Devices,
ADP3339AKC-1.5-RL
28 1 U100 IC BGA XC2V250-5FG256C-2020,
FPGA
Xilinx, XC2V250-5FG256C
29 1 U201 IC SSOT XCF02SV020C, EPROM Xilinx, XCF02SV020C
30 4 MP101 to MP104 Part of
assembly
CBSB-14-01A-RT,
7/8" height, standoffs
for circuit board support
Richco, CBSB-14-01A-RT
31 7 MP105 to MP111 Part of
assembly
SNT-100-BK-G-H,
100 mil jumpers
Samtec, SNT-100-BK-G-H
1 The bill of materials is RoHS compliant.
HSC-ADC-FPGA
Rev. C | Page 20 of 20
ORDERING GUIDE
Model Package Description
HSC-ADC-FPGA-9289 Quad-Channel High Speed Serial LVDS to Parallel CMOS Converter for the AD9289 only
HSC-ADC-FPGA-4 Quad-Channel High Speed Serial LVDS to Parallel CMOS Converter for the AD9287, AD9219, AD9228, AD9229, AD9259
HSC-ADC-FPGA-8 Quad-/Octal-Channel High Speed Serial LVDS to Parallel CMOS Converter for the AD9287, AD9219, AD9228,
AD9229, AD9259, AD9212, AD9222, AD9252
ESD CAUTION
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
EB05053-0-10/06(C)