MKW39/38/37 Data Sheet
An ultra low-power, highly integrated Bluetooth® Low
Energy 5.0 wireless microcontroller
Multi-Standard Radio
2.4 GHz Bluetooth Low Energy (Bluetooth LE) version
5.0 compliant supporting up to 8 simultaneous
hardware connections and all optional features
including:
High speed (2M PHY)
Long range
Advertising Extension
High duty cycle non-connectable advertising
Channel selection algorithm #2
Typical Bluetooth LE Receiver Sensitivity
Bluetooth LE 2 Mbit/s: –95.5 dBm
Bluetooth LE 1 Mbit/s: –98 dBm
Bluetooth LE LR 500 kbit/s: –101 dBm
Bluetooth LE LR 125 kbit/s: –105 dBm
Generic FSK modulation
Data Rate: 250, 500, 1000 and 2000 kbit/s
Modulations: GFSK BT = 0.5, MSK
Modulation Index: 0.32, 0.5, 0.7, and 1.0
Typical Receiver Sensitivity (250 kbit/s GFSK-
BT=0.5, h=0.5) = –101 dBm
Programmable Transmitter Output Power: –30 dBm to
+5 dBm
Low external component count for low-cost application
On-chip balun with single ended bidirectional RF port
System peripherals
Nine MCU low-power modes to provide power
optimization based on application requirements
DC-DC Converter supporting Buck and Bypass
operating modes
Direct Memory Access (DMA) controller
Computer Operating Properly (COP) watchdog
Serial Wire Debug (SWD) Interface and Micro Trace
buffer
Bit Manipulation Engine (BME)
Timers
16-bit Low-power Timer (LPTMR)
3 Timer/PWM Modules(TPM): One 4 channel TPM
and two 2 channel TPMs
Programmable Interrupt Timer (PIT)
Real-Time Clock (RTC)
Communication interfaces
2 Serial Peripheral Interface (SPI) modules
2 Inter-integrated Circuit (I2C) modules
Low-power UART (LPUART) module with LIN
support (2x LPUART on KW38)
Carrier Modulator Timer (CMT)
FlexCAN module (with CAN FD support up to 3.2
Mbit/s baudrate) on KW38
MKW39A512VFT4
MKW38A512VFT4
MKW38Z512VFT4
MKW37A512VFT4
MKW37Z512VFT4
48 "Wettable" HVQFN
7x7 mm Pitch 0.5 mm
NXP Semiconductors MKW39A512
Data Sheet: Technical Data Rev. 7, 03/2020
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Analog Modules
16-bit Analog-to-Digital Converter (ADC)
6-bit High-Speed Analog Comparator (CMP)
1.2 V Voltage Reference (VREF)
MCU and Memories
256 KB program flash memory plus 256 KB FlexNVM
on KW39/38
512 KB program flash memory on KW37
8 KB FlexRAM supporting EEPROM emulation on
KW39/38
8 KB program acceleration RAM on KW37
On-chip 64 KB SRAM
Up to 48 MHz Arm® Cortex®-M0+ core
Low-power Consumption
Transceiver current (DC-DC buck mode, 3.6 V supply)
Typical Rx current: 6.3 mA
Typical Tx current: 5.7 mA
Low-power Mode (VLLS0) Current: 266.6 nA
Security
AES-128 Hardware Accelerator (AESA)
True Random Number Generator (TRNG)
Advanced flash security on Program Flash
80-bit unique identification number per chip
40-bit unique Media Access Control (MAC) sub-
address
LE Secure Connections
Clocks
26 and 32 MHz supported for Bluetooth LE and
Generic FSK modes
32.768 kHz Crystal Oscillator
Operating Characteristics
Voltage range: 1.71 V to 3.6 V
Ambient temperature range: –40 to 105 °C
AEC Q100 Grade 2 Automotive Qualification
Industrial Qualification
Human-machine Interface (HMI)
General-purpose input/output (GPIO)
KW39/38/37 Part Numbers
Device Qualification
Tier CAN FD 512 KB
P-Flash
256 KB P-
Flash/256
KB
FlexNVM
Second LPUART
with LIN
8 KB
FlexRAM
EEPROM
Package
MKW39A512VFT4 Auto AEC-Q100
Grade 2
N N Y N Y 7X7 mm 48-
pin "Wettable"
HVQFN
MKW38A512VFT4 Auto AEC-Q100
Grade 2
Y N Y Y Y
MKW38Z512VFT4 Industrial Y N Y Y Y
MKW37A512VFT4 Auto AEC-Q100
Grade 2
N Y N N N
MKW37Z512VFT4 Industrial N Y N N N
Related Resources
Type Description
Product Selector The Product Selector lets you find the right Kinetis part for your design.
Fact Sheet The Fact Sheet gives overview of the product key features and its uses.
Reference Manual The Reference Manual contains a comprehensive description of the structure and function
(operation) of a device.
Data Sheet The Data Sheet includes electrical characteristics and signal connections.
Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask
set.
Package drawing Package dimensions are available in package drawings.
2MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 3
NXP Semiconductors
Table of Contents
1 Introduction........................................................................... 5
2 Feature Descriptions............................................................. 6
2.1 Block Diagram............................................................... 6
2.2 Radio features............................................................... 8
2.3 Microcontroller features................................................. 9
2.4 System features.............................................................10
2.5 Peripheral features........................................................ 12
2.6 Security Features...........................................................17
3 Transceiver Description........................................................ 18
3.1 Transceiver Functions................................................... 18
3.2 Key Specifications......................................................... 19
3.3 Channel Map Frequency Plans .................................... 19
3.3.1 Channel Plan for Bluetooth Low Energy............19
3.3.2 Other Channel Plans ........................................ 21
4 Transceiver Electrical Characteristics................................... 21
4.1 Radio operating conditions............................................ 21
4.2 Receiver Feature Summary...........................................22
4.3 Transmit and PLL Feature Summary.............................26
5 System and Power Management.......................................... 31
5.1 Power Management.......................................................31
5.1.1 DC-DC Converter.............................................. 32
5.2 Modes of Operation....................................................... 32
5.2.1 Power modes.....................................................32
6 KW39/38/37 Electrical Characteristics.................................. 35
6.1 AC electrical characteristics...........................................35
6.2 Nonswitching electrical specifications............................35
6.2.1 Voltage and current operating requirements..... 35
6.2.2 LVD and POR operating requirements..............36
6.2.3 Voltage and current operating behaviors...........37
6.2.4 Power mode transition operating behaviors...... 38
6.2.5 Power consumption operating behaviors.......... 39
6.2.6 Diagram: Typical IDD_RUN operating behavior46
6.2.7 SoC Power Consumption.................................. 48
6.2.8 Designing with radiated emissions in mind........49
6.2.9 Capacitance attributes.......................................49
6.3 Switching electrical specifications..................................49
6.3.1 Device clock specifications................................49
6.3.2 General switching specifications....................... 50
6.4 Thermal specifications...................................................51
6.4.1 Thermal operating requirements....................... 51
6.4.2 Thermal attributes..............................................51
6.5 Peripheral operating requirements and behaviors.........52
6.5.1 Core modules.................................................... 52
6.5.2 System modules................................................ 53
6.5.3 Clock modules................................................... 54
6.5.4 Memories and memory interfaces..................... 57
6.5.5 Security and integrity modules.......................... 61
6.5.6 Analog............................................................... 61
6.5.7 Timers................................................................68
6.5.8 Communication interfaces................................. 68
6.5.9 Human-machine interfaces (HMI)......................73
6.6 DC-DC Converter Operating Requirements.................. 73
6.7 Ratings...........................................................................75
6.7.1 Thermal handling ratings................................... 75
6.7.2 Moisture handling ratings.................................. 75
6.7.3 ESD handling ratings.........................................76
6.7.4 Voltage and current operating ratings............... 76
7 Pin Diagrams and Pin Assignments......................................76
7.1 KW39/37 Signal Multiplexing and Pin Assignments...... 77
7.2 KW38 Signal Multiplexing and Pin Assignments........... 79
7.3 KW39/38/37 Pinouts......................................................82
7.4 Module Signal Description Tables................................. 83
7.4.1 Core Modules.................................................... 83
7.4.2 Radio Modules...................................................84
7.4.3 System Modules................................................ 85
7.4.4 Clock Modules................................................... 85
7.4.5 Analog Modules.................................................86
7.4.6 Timer Modules...................................................87
7.4.7 Communication Interfaces.................................87
7.4.8 Human-Machine Interfaces(HMI)...................... 89
8 Package Information............................................................. 89
8.1 Obtaining package dimensions......................................89
9 Part identification...................................................................90
9.1 Description.....................................................................90
9.2 Format........................................................................... 90
9.3 Fields............................................................................. 90
9.4 Example.........................................................................91
10 Revision History.................................................................... 91
4MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
1 Introduction
The KW39/38/37 wireless microcontrollers (MCU), which includes the KW39A,
KW38A/Z and KW37A/Z families of devices, are highly integrated single-chip
devices that enable Bluetooth Low Energy 5.0 and Generic FSK connectivity for
automotive, and industrial embedded systems. To meet the stringent requirements of
automotive applications, the KW39/38/37 is fully AEC Q100 Grade 2 Automotive
Qualified. The target applications center on wirelessly bridging the embedded world
with mobile devices to enhance the human interface experience, share embedded data
between devices and the cloud and enable wireless firmware updates. Leading the
automotive applications is the Digital Key, where a smartphone can be used by the
owner as an alternative to the key FOB for unlocking and personalizing the driving
experience. For a car sharing experience, the owner can provide selective, temporary
authorization for access to the car allowing the authorized person to unlock, start, and
operate the car using their mobile device using Bluetooth LE.
The KW39/38/37 Wireless MCU integrates an Arm® Cortex-M0+ CPU with up to
512 KB flash and 64 KB SRAM and a 2.4 GHz radio that supports Bluetooth LE 5.0
and Generic FSK modulations. The Bluetooth LE radio supports up to 8 simultaneous
connections in any master/slave combination.
The KW38 includes an integrated FlexCAN module enabling seamless integration
into a cars in-vehicle or an industrial CAN communication network, enabling
communication with external control and sensor monitoring devices over Bluetooth
LE. The FlexCAN module can support CAN’s flexible data-rate (CAN FD) protocol
for increased bandwidth and lower latency required by many automotive applications.
The KW39/38/37 devices can be used as a "BlackBox" modem to add Bluetooth LE
or Generic FSK connectivity to an existing host MCU or MPU (microprocessor). The
devices may also be used as a standalone smart wireless sensor with embedded
application where no host controller is required.
The RF circuit of the KW39/38/37 is optimized to require very few external
components, achieving the smallest RF footprint possible on a printed circuit board.
Extremely long battery life is achieved through the efficiency of code execution in the
Cortex-M0+ CPU core and the multiple low-power operating modes of the
KW39/38/37. For power critical applications, an integrated DC-DC converter enables
operation from a single coin cell or Li-ion battery with a significant reduction of peak
receive and transmit current consumption.
Introduction
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 5
NXP Semiconductors
2 Feature Descriptions
This section provides a simplified block diagram and highlights the KW39/38/37
features.
2.1 Block Diagram
IPS
(for RSIM) IPS
DCDC
VDCDC_IN
SRAM
Flash
Arm Cortex M0+ Core
NVIC WIC
IOPORT
DAP
MTB
GPIO
BME
Flash
AIPS-Lite
MDM
DWT
RTC
LPTMR
PIT
SIM
RCM
PMC
SMC LPUART
ADC
Unified Bus
M0
S0
S1
Serial Wire Debug
IPS
AHBLite
S2
Controller
FlexNVM
256 KB
S3
32K Osc
MCG
FLL IRC
32 kHz
IRC
4 MHz
DMA MUX
4ch DMA
AHBLite
CMP TPM x3
32M Osc
VREF
I2C x2
CMT
256 KB
64 KByte
TRNG SPI x2
M2A
Radio
LTC(AESA)
Data stream
M3
Crossbar-Lite Switch (AXBS)
FlexRAM
8 KB
Figure 1. KW39 Detailed Block Diagram
IPS
(for RSIM) IPS
DCDC
VDCDC_IN
SRAM
Flash
Arm Cortex M0+ Core
NVIC WIC
IOPORT
DAP
MTB
GPIO
BME
Flash
AIPS-Lite
MDM
DWT
RTC
LPTMR
PIT
SIM
RCM
PMC
SMC LPUART x2
ADC
Unified Bus
M0
S0
S1
Serial Wire Debug
IPS
AHBLite
S2
Controller
FlexNVM
256 KB
S3
32K Osc
MCG
FLL IRC
32 kHz
IRC
4 MHz
DMA MUX
4ch DMA
AHBLite
CMP TPM x3
32M Osc
VREF
I2C x2
CMT
FlexCAN
256 KB
64 KByte
TRNG SPI x2
M2A
Radio
LTC(AESA)
Data stream
M3
Crossbar-Lite Switch (AXBS)
FlexRAM
8 KB
Figure 2. KW38 Detailed Block Diagram
Feature Descriptions
6MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
IPS
(for RSIM) IPS
DCDC
VDCDC_IN
SRAM
Flash
Arm Cortex M0+ Core
NVIC WIC
IOPORT
DAP
MTB
GPIO
BME
Flash
AIPS-Lite
MDM
DWT
RTC
LPTMR
PIT
SIM
RCM
PMC
SMC LPUART
ADC
Unified Bus
M0
S0
S1
Serial Wire Debug
IPS
AHBLite
S2
Controller
Prg Acc RAM
8 KB
S3
32K Osc
MCG
FLL IRC
32 kHz
IRC
4 MHz
DMA MUX
4ch DMA
AHBLite
CMP TPM x3
32M Osc
VREF
I2C x2
CMT
512 KB
64 KByte
TRNG SPI x2
M2A
Radio
LTC(AESA)
Data stream
M3
Crossbar-Lite Switch (AXBS)
Figure 3. KW37 Detailed Block Diagram
Table 1. List of IPs in block diagrams
Acronym Definition
ADC Analog-to-Digital Converter
AESA Advanced Encryption Standard Accelerator
AIPS Peripheral Bridge
BME Bit Manipulation Engine
CMP Comparator
CMT Carrier Modulator Timer
DAP Debug Access Port
DMA Direct Memory Access
DMAMUX Direct Memory Access Multiplexer
DWT Data Watchpoint and Trace
FLL Frequency-Locked Loop
GPIO General Purpose Input/Output
I2C Inter-integrated Circuit
IRC Internal Reference Clock
LPTMR Low-Power Timer
LPUART Low-Power UART
LTC LP Trusted Cryptography
MCG Multipurpose Clock Generator
MDM Miscellaneous Debug Module
MTB Micro Trace Buffer
NVIC Nested Vectored Interrupt Controller
OSC Oscillator
PIT Periodic Interrupt Timer
Table continues on the next page...
Feature Descriptions
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 7
NXP Semiconductors
Table 1. List of IPs in block diagrams (continued)
Acronym Definition
PMC Power Management Control
PORT Port Control and Interrupt
Prg Acc RAM Flash Programming Acceleration RAM
RCM Reset Control Module
RSIM Radio System Integration Module
RTC Real-Time Clock
SIM System Integration Module
SMC System Mode Controller
SPI Serial Peripheral Interface
TRNG True Random Number Generator
VREF Voltage Reference
2.2 Radio features
Operating frequencies:
2.4 GHz ISM band (2400-2483.5 MHz)
Medical Body Area Network frequency band (MBAN) 2360-2400 MHz
Supported standards:
Bluetooth Low Energy Version 5.0 compliant radio supporting all mandatory and
optional features including:
Bluetooth LE 4.2 errata
2 Mbit/s high-speed mode
Long range coded PHY (125/500 kbit/s)
Advertising Extensions
High duty cycle non-connectable advertising
Channel selection algorithm #2
Support for up to 8 simultaneous Bluetooth LE hardware connections in any
master, slave combination
Bluetooth LE Application Profiles
Generic FSK modulation supporting data rates of 250, 500, 1000 and 2000 kbit/s
Other features:
Programmable transmit output power up to +5 dBm with greater than 30 dB power
control dynamic range
Feature Descriptions
8MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK
modes
Up to 26 devices supported by whitelist in hardware
Up to 8 private resolvable addresses supported in hardware
Supports DMA capture of IQ data and phase for localization applications
Support for distance estimation and direction finding applications
Integrated on-chip balun
Single ended bidirectional RF port shared by transmit and receive
Low external component count
Supports transceiver range extension using external PA and/or LNA
2.3 Microcontroller features
Arm Cortex-M0+ CPU
Up to 48 MHz CPU
As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline
microarchitecture for reduced power consumption and improved architectural
performance (cycles per instruction)
Supports up to 32 interrupt request sources
Binary compatible instruction set architecture with the Cortex-M0 core
Thumb instruction set combines high code density with 32-bit performance
Serial Wire Debug (SWD) reduces the number of pins required for debugging
Micro Trace Buffer (MTB) provides lightweight program trace capabilities using
system RAM as the destination memory
Nested Vectored Interrupt Controller (NVIC)
32 vectored interrupts, 4 programmable priority levels
Includes a single non-maskable interrupt
Wake-up Interrupt Controller (WIC)
Supports interrupt handling when system clocking is disabled in low-power
modes
Takes over and emulates the NVIC behavior when correctly primed by the NVIC
on entry to very-deep-sleep
A rudimentary interrupt masking system with no prioritization logic signals for
wake-up as soon as a non-masked interrupt is detected
Debug Controller
Feature Descriptions
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 9
NXP Semiconductors
Two-wire Serial Wire Debug (SWD) interface
Hardware breakpoint unit for 2 code addresses
Hardware watchpoint unit for 2 data items
Micro Trace Buffer for program tracing
On-Chip Memory
Up to 512 KB Flash
KW39/38 contains 256 KB program flash with ECC and 256 KB FlexNVM
enabling EEPROM emulation.
KW37 contains 512 KB program flash with ECC.
Flash implemented as two equal blocks each of 256 KB block. Code can
execute or read from one block while the other block is being erased or
programmed on KW37 only.
Firmware distribution protection. Program flash can be marked execute-only
on a per-sector (8 KB) basis to prevent firmware contents from being read by
third parties.
64 KB SRAM
KW39/38 contains 8 KB FlexRAM enabling EEPROM emulation.
KW37 contains 8 KB program acceleration RAM.
Security circuitry to prevent unauthorized access to RAM and flash contents
through the debugger
2.4 System features
Power Management Control Unit (PMC)
Programmable power saving modes
Available wake-up from power saving modes via internal and external sources
Integrated Power-on Reset (POR)
Integrated Low Voltage Detect (LVD) with reset (brownout) capability
Selectable LVD trip points
Programmable Low Voltage Warning (LVW) interrupt capability
Individual peripheral clocks can be gated off to reduce current consumption
Internal Buffered bandgap reference voltage
Factory programmed trim for bandgap and LVD
1 kHz Low-power Oscillator (LPO)
DC-DC Converters
Feature Descriptions
10 MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Internal switched mode power supply supporting Buck and Bypass operating
modes
Buck operation supports external voltage sources of 2.1 V to 3.6 V
When DC-DC is not used, the device supports an external voltage range of 1.5 V
to 3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_RF3 and
VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1, and VDDA pins)
An external inductor is required to support the Buck mode
The DC-DC Converter VDD_1P8OUT current drive for external devices (MCU
in RUN mode, Radio is enabled, other peripherals are disabled)
Up to 45 mA in buck mode with VDD_1P8OUT = 1.8 V
Up to 27 mA in buck mode with VDD_1P8OUT = 3.0 V
Direct Memory Access (DMA) Controller
All data movement via dual-address transfers: read from source, write to
destination
Programmable source and destination addresses and transfer size
Support for enhanced addressing modes
4-channel implementation that performs complex data transfers with minimal
intervention from a host processor
Internal data buffer, used as temporary storage to support 16- and 32-byte
transfers
Connections to the crossbar switch for bus mastering the data movement
Transfer Control Descriptor (TCD) organized to support two-deep, nested transfer
operations
32-byte TCD stored in local memory for each channel
An inner data transfer loop defined by a minor byte transfer count
An outer data transfer loop defined by a major iteration count
Channel activation via one of three methods:
Explicit software initiation
Initiation via a channel-to-channel linking mechanism for continuous
transfers
Peripheral-paced hardware requests, one per channel
Fixed-priority and round-robin channel arbitration
Channel completion reported via optional interrupt requests
One interrupt per channel, optionally asserted at completion of major iteration
count
Optional error terminations per channel and logically summed together to form
one error interrupt to the interrupt controller
Optional support for scatter/gather DMA processing
Support for complex data structures
Feature Descriptions
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DMA Channel Multiplexer (DMA MUX)
4 independently selectable DMA channel routers
2 periodic trigger sources available
Each channel router can be assigned to 1 of the peripheral DMA sources
COP Watchdog Module
Independent clock source input (independent from CPU/bus clock)
Choice between two clock sources
LPO oscillator
Bus clock
System Clocks
Both 26 MHz and 32 MHz crystal reference oscillator supported for Bluetooth LE
and Generic FSK modes
MCU can derive its clock either from the crystal reference oscillator or the
Frequency-locked Loop (FLL)1
32.768 kHz crystal reference oscillator used to maintain precise Bluetooth Low
Energy timing in low-power modes
Multipurpose Clock Generator (MCG)
Internal reference clocks — Can be used as a clock source for other on-chip
peripherals
On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 3% accuracy
across full temperature range
On-chip 4 MHz oscillator with 11% accuracy across full temperature range
Frequency-locked Loop (FLL) controlled by internal or external reference
20 MHz to 48 MHz FLL output
Unique Identifiers
80-bit Unique ID represents a unique identifier for each chip
40-bit unique Media Access Control (MAC) address, which can be used to build a
unique 48-bit Bluetooth Low Energy MAC address
2.5 Peripheral features
16-bit Analog-to-Digital Converter (ADC)
Linear successive approximation algorithm with 16-bit resolution
Output formatted in differential-ended 16-, 13-, 11-, and 9-bit mode
1. Clock options can have restrictions based on the chosen SoC configuration.
Feature Descriptions
12 MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Output formatted in single-ended 16-, 12-, 10-, and 8-bit mode
Single or continuous conversion
Configurable sample time and conversion speed/power
Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec
Input clock selection
Operation in low-power modes for lower noise operation
Asynchronous clock source for lower noise operation
Selectable asynchronous hardware conversion trigger
Automatic compare with interrupt for less-than, or greater than, or equal to
programmable value
Temperature sensor
Battery voltage measurement
Hardware average function
Selectable voltage reverence
Self-calibration mode
High-Speed Analog Comparator (CMP)
6-bit DAC programmable reference generator output
Up to eight selectable comparator inputs; each input can be compared with any
input by any polarity sequence
Selectable interrupt on rising edge, falling edge, or either rising or falling edges of
comparator output
Two performance modes:
Shorter propagation delay at the expense of higher power
Low-power, with longer propagation delay
Operational in all MCU power modes except VLLS0 mode
Voltage Reference(VREF1)
Programmable trim register with 0.5 mV steps, automatically loaded with factory
trimmed value upon reset
Programmable buffer mode selection:
Off
Bandgap enabled/standby (output buffer disabled)
High-power buffer mode (output buffer enabled)
1.2 V output at room temperature
VREF_OUT output signal
Low-power Timer (LPTMR)
One channel
Operation as timer or pulse counter
Feature Descriptions
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 13
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Selectable clock for prescaler/glitch filter
1 kHz internal LPO
External low-power crystal oscillator
Internal reference clock
Configurable glitch filter or prescaler
Interrupt generated on timer compare
Hardware trigger generated on timer compare
Functional in all power modes
Timer/PWM (TPM)
TPM0: 4 channels, TPM1 and TPM2: 2 channels each
Selectable source clock
Programmable prescaler
16-bit counter supporting free-running or initial/final value, and counting is up or
up-down
Input capture, output compare, and edge-aligned and center-aligned PWM modes
Input capture and output compare modes
Generation of hardware triggers
TPM1 and TPM2: Quadrature decoder with input filters
Global time base mode shares single time base across multiple TPM instances
Programmable Interrupt Timer (PIT)
Up to 2 interrupt timers for triggering ADC conversions
32-bit counter resolution
Clocked by bus clock frequency
Real-Time Clock (RTC)
32-bit seconds counter with 32-bit alarm
Can be invalidated on detection of tamper detect
16-bit prescaler with compensation
Register write protection
Hard Lock requires MCU POR to enable write access
Soft lock requires POR or software reset to enable write/read access
Capable of waking up the system from low-power modes
Inter-Integrated Circuit (I2C)
Two channels
Compatible with I2C bus standard and SMBus Specification Version 2 features
Up to 400 kHz operation
Feature Descriptions
14 MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Multi-master operation
Software programmable for one of 64 different serial clock frequencies
Programmable slave address and glitch input filter
Interrupt driven byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Bus busy detection broadcast and 10-bit address extension
Address matching causes wake-up when processor is in low-power mode
LPUART
One channel (2 channels on KW38)
Full-duplex operation
Standard mark/space Non-return-to-zero (NRZ) format
13-bit baud rate selection with fractional divide of 32
Programmable 8-bit or 9-bit data format
Programmable 1 or 2 stop bits
Separately enabled transmitter and receiver
Programmable transmitter output polarity
Programmable receive input polarity
13-bit break character option
11-bit break character detection option
Two receiver wake-up methods:
Idle line wake-up
Address mark wake-up
Address match feature in receiver to reduce address mark wake-up ISR overhead
Interrupt or DMA driven operation
Receiver framing error detection
Hardware parity generation and checking
Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise
detection
Operation in low-power modes
Hardware Flow Control RTS\CTS
Functional in Stop/VLPS modes
Break detect supporting LIN
Serial Peripheral Interface (SPI)
Two independent SPI channels
Master and slave mode
Full-duplex, three-wire synchronous transfers
Programmable transmit bit rate
Feature Descriptions
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 15
NXP Semiconductors
Double-buffered transmit and receive data registers
Serial clock phase and polarity options
Slave select output
Control of SPI operation during wait mode
Selectable MSB-first or LSB-first shifting
Support for both transmit and receive by DMA
Carrier Modulator Timer (CMT)
Four modes of operation
Time; with independent control of high and low times
Baseband
Frequency shift key (FSK)
Direct software control of CMT_IRO signal
Extended space operation in time, baseband, and FSK modes
Selectable input clock divider
Interrupt on end of cycle
Ability to disable CMT_IRO signal and use as timer interrupt
General Purpose Input/Output (GPIO)
Hysteresis and configurable pull up device on all input pins
Independent pin value register to read logic level on digital pin
All GPIO pins can generate IRQ and wake-up events
Configurable drive strength on some output pins
GPIO can be configured to function as a interrupt driven keyboard scanning matrix;
in the 48-pin package there are a total of 25 digital pins
FlexCAN (for KW38 only)
Full implementation of the CAN with Flexible Data Rate (CAN FD) protocol
specification and CAN protocol specification, Version 2.0 B
Flexible Message Buffers (MBs); there are total 32 MBs of 8 bytes data length
each, configurable as Rx or Tx, all supporting standard and extended messages
Programmable clock source to the CAN Protocol Interface, either peripheral clock
or oscillator clock
Capability to select priority between mailboxes and Rx FIFO during matching
process
Feature Descriptions
16 MKW39/38/37 Data Sheet, Rev. 7, 03/2020
NXP Semiconductors
Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either
128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual
masking capability
Each individual MB forms by 16, 24, 40, or 72 bytes, depending on the quantity
of data bytes allocated for the message payload: 8, 16, 32, or 64 data bytes,
respectively
2.6 Security Features
Advanced Encryption Standard Accelerator(AES-128 Accelerator)
The Advanced Encryption Standard Accelerator (AESA) module is a standalone
hardware coprocessor capable of accelerating the 128-bit advanced encryption
standard (AES) cryptographic algorithms.
The AESA engine supports the following cryptographic features.
LTC includes the following features:
Cryptographic authentication
Message Authentication Codes (MAC)
Cipher-based MAC (AES-CMAC)
Extended cipher block chaining message authentication code (AES-
XCBC-MAC)
Auto padding
Integrity Check Value(ICV) checking
Authenticated encryption algorithms
Counter with CBC-MAC (AES-CCM)
Symmetric key block ciphers
AES (128-bit keys)
Cipher modes:
AES-128 modes
Electronic Codebook (ECB)
Cipher Block Chaining (CBC)
Counter (CTR)
Secure scan
True Random Number Generator (TRNG)
True Random Number Generator (TRNG) is a hardware accelerator module that
constitutes a high-quality entropy source.
Feature Descriptions
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 17
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TRNG generates a 512-bit (4x 128-bit) entropy as needed by an entropy-consuming
module, such as a deterministic random number generator.
TRNG output can be read and used by a deterministic pseudo-random number
generator (PRNG) implemented in software.
TRNG-PRNG combination achieves NIST-compliant true randomness and
cryptographic-strength random numbers using the TRNG output as the entropy
source.
A fully FIPS 180 compliant solution can be realized using the TRNG together with
a FIPS-compliant deterministic random number generator and the SoC-level
security.
Flash Memory Protection
The on-chip flash memory controller enables the following useful features:
Program flash protection scheme prevents accidental program or erase of stored
data.
Automated, built-in, program and erase algorithms with verify.
Read access to one program flash block is possible while programming or erasing
data in the other program flash block.
3Transceiver Description
Direct Conversion Receiver (Zero IF)
Constant Envelope Transmitter
Low Transmit and Receive Current Consumption
Low bill of material (BOM) radio
3.1 Transceiver Functions
Receive
The receiver architecture is Zero IF (ZIF) where the received signal after passing
through RF front end is down-converted to a baseband signal. The signal is filtered and
amplified before it is fed to analog-to-digital converter. The digital signal then
decimates to a baseband clock frequency before it digitally processes, demodulates and
passes on to packet processing/link-layer processing.
Transmit
Transceiver Description
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The transmitter transmits GFSK/FSK modulation having power and channel selection
adjustment per user application. After the channel of operation is determined, coarse
and fine-tuning is executed within the Frac-N PLL to engage signal lock. After signal
lock is established, the modulated buffered signal is routed to a multi-stage amplifier
for transmission..
3.2 Key Specifications
KW39/38/37 meets or exceeds all Bluetooth Low Energy version 5.0 performance
specifications. The key specifications for the KW39/38/37 are:
Frequency Band:
ISM Band: 2400 to 2483.5 MHz
MBAN Band: 2360 to 2400 MHz
Full Bluetooth Low Energy version 5.0 modulation scheme:
Symbol rate: Uncoded PHY (1, 2 Mbit/s), Coded PHY (125, 500 kbit/s)
Modulation: GFSK BT=0.5, h=0.5
Receiver sensitivity: –98 dBm, typical for Bluetooth LE 1 Mbit/s, –105 dBm for
Bluetooth LE-LR 125 kbit/s; for all other modes, refer Receiver Feature
Summary.
Programmable transmitter output power: –30 dBm to +5 dBm
Generic FSK modulation scheme:
Symbol rate: 250, 500, 1000, and 2000 kbit/s
Modulation(s): GFSK (modulation index = 0.32, 0.5, 0.7, and 1.0, BT = 0.5), and
MSK
Receiver Sensitivity: Mode and data rate dependent. –101 dBm typical for GFSK
(r=250 kbit/s, BT = 0.5, h = 0.5)
3.3 Channel Map Frequency Plans
Transceiver Description
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 19
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3.3.1 Channel Plan for Bluetooth Low Energy
This section describes the frequency plan / channels associated with 2.4 GHz ISM and
MBAN bands for Bluetooth Low Energy.
2.4 GHz ISM Channel numbering:
Fc=2402 + k * 2 MHz, k=0,.........,39.
MBAN Channel numbering:
Fc=2360 + k in MHz, for k=0,.....,39
where k is the channel number.
Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations
2.4 GHz ISM1MBAN22.4GHz ISM + MBAN
Channel Freq (MHz) Channel Freq (MHz) Channel Freq (MHz)
0 2402 0 2360 28 2390
1 2404 1 2361 29 2391
2 2406 2 2362 30 2392
3 2408 3 2363 31 2393
4 2410 4 2364 32 2394
5 2412 5 2365 33 2395
6 2414 6 2366 34 2396
7 2416 7 2367 35 2397
8 2418 8 2368 36 2398
9 2420 9 2369 0 2402
10 2422 10 2370 1 2404
11 2424 11 2371 2 2406
12 2426 12 2372 3 2408
13 2428 13 2373 4 2410
14 2430 14 2374 5 2412
15 2432 15 2375 6 2414
16 2434 16 2376 7 2416
17 2436 17 2377 8 2418
18 2438 18 2378 9 2420
19 2440 19 2379 10 2422
20 2442 20 2380 11 2424
21 2444 21 2381 12 2426
22 2446 22 2382 13 2428
23 2448 23 2383 14 2430
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Transceiver Description
20 MKW39/38/37 Data Sheet, Rev. 7, 03/2020
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Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)
2.4 GHz ISM1MBAN22.4GHz ISM + MBAN
Channel Freq (MHz) Channel Freq (MHz) Channel Freq (MHz)
24 2450 24 2384 15 2432
25 2452 25 2385 16 2434
26 2454 26 2386 17 2436
27 2456 27 2387 18 2438
28 2458 28 2388 19 2440
29 2460 29 2389 20 2442
30 2462 30 2390 21 2444
31 2464 31 2391 22 2446
32 2466 32 2392 23 2448
33 2468 33 2393 24 2450
34 2470 34 2394 25 2452
35 2472 35 2395 26 2454
36 2474 36 2396 27 2456
37 2476 37 2397 37 2476
38 2478 38 2398 38 2478
39 2480 39 2399 39 2480
1. ISM frequency of operation spans from 2400.0 MHz to 2483.5 MHz
2. Per FCC guideline rules, Bluetooth Low Energy single mode operation is allowed in these channels.
3.3.2 Other Channel Plans
The RF synthesizer can be configured to use any channel frequency between 2.36 and
2.487 GHz.
4Transceiver Electrical Characteristics
4.1 Radio operating conditions
Table 3. Radio operating conditions
Characteristic Symbol Min Typ Max Unit
Input Frequency fin 2.360 2.480 GHz
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Transceiver Electrical Characteristics
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 21
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Table 3. Radio operating conditions (continued)
Characteristic Symbol Min Typ Max Unit
Ambient Temperature Range TA–40 25 105 °C
Maximum RF Input Power Pmax 10 dBm
Crystal Reference Oscillator Frequency
1
fref 26 MHz or 32 MHz
1. The recommended crystal accuracy is ±40 ppm including initial accuracy, mechanical, temperature, and aging factors.
4.2 Receiver Feature Summary
Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted)
Characteristic1Symbol Min. Typ. Max. Unit
Receiver General Specifications
Supply current power down on VDD_RFx supplies Ipdn 200 1000 nA
Supply current Rx On with DC-DC converter enable
(Buck; VDCDC_IN = 3.6 V) , 2IRxon 6.36 mA
Supply current Rx On with DC-DC converter disabled
(Bypass) 2IRxon 17.78 mA
Input RF Frequency fin 2.360 2.4835 GHz
GFSK Rx Sensitivity(250 kbit/s GFSK-BT=0.5, h=0.5) SENSGFSK –101 dBm
Max Rx RF Input Signal Level RFin,max 10 dBm
Noise Figure for maximum gain mode @ typical
sensitivity
NFHG 7.5 dB
Receiver Signal Strength Indicator Range3RSSIRange –100 54dBm
Receiver Signal Strength Indicator Resolution RSSIRes 1 dB
Typical RSSI variation over frequency –2 2 dB
Typical RSSI variation over temperature –2 2 dB
Narrowband RSSI accuracy5RSSIAcc –3 3 dB
Spurious Emission < 1.6 MHz offset (Measured with 100
kHz resolution and average detector. Device transmit on
RF channel with center frequency fc and spurious power
measured in 1 MHz at RF frequency f), where |f-fc|< 1.6
MHz
–54 dBc
Spurious Emission > 2.5 MHz offset (Measured with 100
kHz resolution and average detector. Device transmit on
RF channel with center frequency fc and spurious power
measured in 1 MHz at RF frequency f), where |f-fc|> 2.5
MHz6
–70 dBc
Bluetooth LE coded 125 kbit/s (Long Range, 8x Spreading)
Bluetooth LE LR 125 kbit/s Sensitivity7SENSBLELR125 –105 dBm
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Transceiver Electrical Characteristics
22 MKW39/38/37 Data Sheet, Rev. 7, 03/2020
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Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted) (continued)
Characteristic1Symbol Min. Typ. Max. Unit
Bluetooth LE LR 125 kbit/s Co-channel Interference
(Wanted signal at –67 dBm, BER <0.1%. Measurement
resolution 1 MHz).
COSELBLELR125 –2 dB
Adjacent/Alternate Channel Performance8
Bluetooth LE LR 125 kbit/s Adjacent +/–1 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR125, 1
MHz
10 dB
Bluetooth LE LR 125 kbit/s Adjacent +/–2 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR125, 2
MHz
50 dB
Bluetooth LE LR 125 kbit/s Alternate +/–3 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR125, 3
MHz
55 dB
Bluetooth LE LR 125 kbit/s Alternate > +/–5 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR125, 5+
MHz
60 dB
Bluetooth LE coded 500 kbit/s (Long Range, 2x Spreading)
Bluetooth LE LR 500 kbit/s Sensitivity7SENSBLELR500 –101 dBm
Bluetooth LE LR 500 kbit/s Co-channel Interference
(Wanted signal at –67 dBm, BER <0.1%. Measurement
resolution 1 MHz).
COSELBLELR500 –4 dB
Adjacent/Alternate Channel Performance8
Bluetooth LE LR 500 kbit/s Adjacent +/–1 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR500, 1
MHz
9 dB
Bluetooth LE LR 500 kbit/s Adjacent +/–2 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR500, 2
MHz
50 dB
Bluetooth LE LR 500 kbit/s Alternate +/–3 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR500, 3
MHz
55 dB
Bluetooth LE LR 500 kbit/s Alternate > +/–5 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 1 MHz.)
SELBLELR500, 5+
MHz
60 dB
Bluetooth LE uncoded 1 Mbit/s
Bluetooth LE 1 Mbit/s Sensitivity7SENSBLE1M –98 dBm
Bluetooth LE 1 Mbit/s Co-channel Interference (Wanted
signal at –67 dBm, BER <0.1%. Measurement resolution
1 MHz).
COSELBLE1M –7 dB
Adjacent/Alternate Channel Selectivity Performance8
Bluetooth LE 1 Mbit/s Selectivity +/–1 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 1 MHz.)
SELBLE1M, 1 MHz 0 dB
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Transceiver Electrical Characteristics
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 23
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Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted) (continued)
Characteristic1Symbol Min. Typ. Max. Unit
Bluetooth LE 1 Mbit/s Adjacent +/–2 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 1 MHz.)
SELBLE1M, 2 MHz 42 dB
Bluetooth LE 1 Mbit/s Selectivity +/–3 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 1 MHz.)
SELBLE1M, 3 MHz 50 dB
Bluetooth LE 1 Mbit/s Alternate ≥ +/–5 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 1 MHz.)
SELBLE1M, 5+ MHz 55 dB
Intermodulation Performance
Bluetooth LE 1 Mbit/s Intermodulation with continuous
wave interferer at ± 3 MHz and modulated interferer is at
± 6 MHz (Wanted signal at –67 dBm, BER<0.1%.)
IM3-6BLE1M –42 dBm
Bluetooth LE 1 Mbit/s Intermodulation with continuous
wave interferer at ±5 MHz and modulated interferer is at
±10 MHz (Wanted signal at –67 dBm, BER<0.1%.)
IM5-10BLE1M –23 dBm
Blocking Performance
Bluetooth LE 1 Mbit/s Out of band blocking from 30 MHz
to 1000 MHz and 4000 MHz to 5000 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.), 9, 10
3 dBm
Bluetooth LE 1 Mbit/s Out of band blocking from 1000
MHz to 2000 MHz and 3000 MHz to 4000 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.)
3 dBm
Bluetooth LE 1 Mbit/s Out of band blocking from 2001
MHz to 2339 MHz and 2484 MHz to 2999 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.)10
–12 dBm
Bluetooth LE 1 Mbit/s Out of band blocking from 5000
MHz to 12750 MHz (Wanted signal at –67 dBm,
BER<0.1%. Interferer continuous wave signal.)10
5 dBm
Bluetooth LE uncoded 2 Mbit/s (High Speed)
Bluetooth LE 2 Mbit/s Sensitivity7SENSBLE2M –95.5 dBm
Bluetooth LE 2 Mbit/s Co-channel Interference (Wanted
signal at –67 dBm, BER <0.1%. Measurement resolution
2 MHz).
COSELBLE2M –7 dB
Adjacent/Alternate Channel Performance8
Bluetooth LE 2 Mbit/s Adjacent +/–2 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 2 MHz.)
SELBLE2M, 2 MHz 3 dB
Bluetooth LE 2 Mbit/s Alternate +/–4 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 2 MHz.)
SELBLE2M, 4 MHz 42 dB
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Transceiver Electrical Characteristics
24 MKW39/38/37 Data Sheet, Rev. 7, 03/2020
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Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted) (continued)
Characteristic1Symbol Min. Typ. Max. Unit
Bluetooth LE 2 Mbit/s Selectivity +/–6 MHz Interference
offset (Wanted signal at –67 dBm, BER <0.1%.
Measurement resolution 2 MHz.)
SELBLE2M, 6 MHz 50 dB
Bluetooth LE 2 Mbit/s Selectivity ≥ +/–10 MHz
Interference offset (Wanted signal at –67 dBm, BER
<0.1%. Measurement resolution 2 MHz.)
SELBLE2M, 10+ MHz 55 dB
Intermodulation Performance
Bluetooth LE 2 Mbit/s Intermodulation with continuous
wave interferer at ± 6 MHz and modulated interferer is at
± 12 MHz (Wanted signal at –67 dBm, BER<0.1%.)
IM6-12BLE2M –23 dBm
Bluetooth LE 2 Mbit/s Intermodulation with continuous
wave interferer at ±10 MHz and modulated interferer is
at ±20 MHz (Wanted signal at –67 dBm, BER<0.1%.)
IM10-20BLE2M –24 dBm
Blocking Performance
Bluetooth LE 2 Mbit/s Out of band blocking from 30 MHz
to 1000 MHz and 4000 MHz to 5000 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.)9,10
3 dBm
Bluetooth LE 2 Mbit/s Out of band blocking from 1000
MHz to 2000 MHz and 3000 MHz to 4000 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.)
–6 dBm
Bluetooth LE 2 Mbit/s Out of band blocking from 2001
MHz to 2339 MHz and 2484 MHz to 2999 MHz (Wanted
signal at –67 dBm, BER<0.1%. Interferer continuous
wave signal.)10
–12 dBm
Bluetooth LE 2 Mbit/s Out of band blocking from 5000
MHz to 12750 MHz (Wanted signal at –67 dBm,
BER<0.1%. Interferer continuous wave signal.)10
5 dBm
1. All the Rx parameters are measured at the KW39/38/37 RF pins.
2. Transceiver power consumption.
3. Narrow-band RSSI mode.
4. With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.
5. With one point calibration over frequency and temperature.
6. Exceptions allowed for twice the reference clock frequency(fref) multiples.
7. Measured at 0.1% BER using 37 byte long packets in maximum gain mode and nominal conditions.
8. Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals.
9. Exceptions allowed for carrier frequency sub harmonics.
10. Exceptions allowed for carrier frequency harmonics.
Transceiver Electrical Characteristics
MKW39/38/37 Data Sheet, Rev. 7, 03/2020 25
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Table 5. Receiver Specifications with Generic FSK Modulations
Adjacent/Alternate channel selectivity (dB)1
Modulation
type
Data
rate
(kb/s)
Channel
BW (kHz)
Typical
sensitivity
(dBm)
Desired
signal
level
(dBm)
Interferer
at ±1*
channel
BW offset
Interferer
at ±2*
channel
BW offset
Interferer
at ±3*
channel
BW offset
Interferer
at ±4*
channel
BW offset
Co-
channel
GFSK BT =
0.5, h = 0.32
2000 2000 –90.5 –67 39 48 52 54 –9
1000 1000 –93.5 –67 36 47 50 53 –8
GFSK BT =
0.5, h = 0.5
2000 4000 –94 –67 46 56 59 60 –7
1000 2000 –97 –67 44 56 59 60 –7
500 1000 –98.5 –85 43 49 56 57 –6
250 500 –100 –85 39 43 46 50 –6
GFSK, BT =
0.5, h = 0.7
2000 4000 –95 –85 44 53 56 59 –6
1000 2000 –97.5 –85 47 55 59 61 –5
GFSK, BT =
0.5, h = 1.0
1000 1600 –96 –85 50 58 61 64 –4
1. Selectivity measured with an unmodulated blocker.
4.3 Transmit and PLL Feature Summary
Supports constant envelope modulation of 2.4 GHz ISM and 2.36 GHz MBAN
frequency bands
Fast PLL Lock time: < 25 µs
Reference Frequency:
26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK
modes
Table 6. Top-Level Transmitter Specifications (TA=25 °C, nominal process unless otherwise
noted)
Characteristic1Symbol Min. Typ. Max. Unit
Transmitter General Specifications
Supply current power down on VDD_RFx supplies Ipdn 200 nA
Supply current Tx On with PRF = 0 dBm and DC-DC
converter enabled (Buck; VDDDCDC_in = 3.6 V) , 2ITX0dBm 5.7 mA
Supply current Tx On with PRF = 0 dBm and DC-DC
converter disabled (Bypass) 2ITX0dBmb 16 mA
Supply current Tx On with PRF = +3.5 dBm and DC-DC
converter enabled (Buck; VDDDCDC_in = 3.6 V)2ITX3.5dBm 6.9 mA
Supply current Tx On with PRF = +3.5 dBm and DC-DC
converter disabled (Bypass)2ITX3.5dBmb 19 mA
Table continues on the next page...
Transceiver Electrical Characteristics
26 MKW39/38/37 Data Sheet, Rev. 7, 03/2020
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