Radiation Hardended Ultra Low Dropout IRUH330118AP
Fixed Positive Linear Regulator +3.3VIN to +1.8VOUT @3.0A
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Features
nSilicon On Insulator (SOI) CMOS Regulator
IC, CMOS Latch-Up Immune,
Inherently Rad Hard
n Total Dose Capability up to 300Krads(Si)
(Condition A); Tested to 500Krad (Si)
nELDRS up to 100Krad(Si) (Condition D)
nSEU Immune up to LET = 80 MeV*cm2/mg
nSpace Level Screened
nFast Transient Response
nTimed Latch-Off Over-Current Protection
nInternal Thermal Protection
nOn/Off Control via Shutdown Pin, Power
Sequencing Easily Implemented
nIsolated Hermetic 8-Lead Flat Pack
Ensures Higher Reliability
nThis part is also available in MO-078 Package
as IRUH330118BK / IRUH330118BP
The IRUH330118 is a space qualified, ultra low dropout
linear regulator designed specifically for applications
requiring high reliability, low noise and radiation hardness.
05/18/12
8-LEAD FLAT PACK
Description
IRUH330118AK
Ab
so
l
u
t
e
M
ax
i
mum
R
a
ti
ngs
Parameter S
y
mbol Min. Max. Units
Power Dissipation @ TC = 125°C PD-25W
Maximum Output Current @ Maximum
Power Dissipation with no Derating
Non-Operating Input Voltage VIN -0.3 +8.0
Operating Input Voltage VIN 2.9 6.4
Ground GND -0.3 0.3
Shutdown Pin Voltage VSHDN -0.3 VIN + 0.3
Output Pin Voltage VOUT -0.3 VIN + 0.3
Operating Case Temperature Range TO-55 +140
Storage Temperature Range TS-65 +150
Maximmum Junction Temperature TJ -+150
Lead Temperature (Soldering 10sec) TL -+300
Pass Transistor Thermal Resistance, Junction to Case RTHJC -1.0°C/W
°C
IOA- See Fig 4
V
Product
S
ummary
Part Number IOVIN VOUT
IRUH330118AK
IRUH330118AP
3.0A 3.3V 1.8V
(5962F1023503K)
PD-97530C
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Notes:
Connected as shown in Fig.1 and measured at the junction of VOUT and VSENSE Pins.
Under normal closed-loop operation. Guaranteed by design. Not tested in production.
Electrical Characteristics
c
Pre-Radiation @T
C
= 25°C, V
IN
= 3.3V
(Unless Otherwise Specified)
Parameter Test Conditions Symbol Min. Typ. Max. Units
2.8V ≤ V
IN
≤ 3.8V, 50mA ≤ I
OUT
≤ 3.0A 1.773 1.8 1.827
2.8V ≤ V
IN
≤ 3.8V, 50mA ≤ I
OUT
≤ 3.0A,
Output Voltage
c
-55°C to +125°C V
OUT
V
2.8V ≤ V
IN
≤ 3.8V, 50mA ≤ I
OUT
≤ 3.0A,
Post -Rad
Over-Current Latching, -55°C to +125°C,
Post -Rad
Over-Current Time-to-Latch I
O
> I
LATCH
t
LATCH
-10 - ms
Maximum Shutdown Temp.
d
T
LATCH
125 140 - °C
F= 120Hz, I
O
= 50mA, -55°C to +125°C 65 - -
F= 120Hz, I
O
= 50mA, Post -Rad 40 - -
V
SENSE
Pin Current
d
-55°C to +125°C I
SENSE
-1.6
-mA
Minimum SHDN Pin "On" I
SOURCE
= 200µA, -55°C to +125°C
Threshold Voltage Post -Rad
Maximum SHDN Pin "Off" I
SOURCE
= 200µA, -55°C to +125°C
Threshold Voltage Post -Rad
R
LOAD
= 36 Ohms, V
SHDN
= 3.3V
-55°C to +125°C, Post-Rad
SHDN Pin Leakage Current
d
V
SHDN
= 3.3V, -55°C to +125°C,Post-Rad I
SHDN
-10 - 10 µA
V
SHDN
= 0.4V -98 - -56
SHDN Pin Pull-Up Current
d
V
SHDN
= 0.4V, -55°C to +125°C I
SHDN
-140 - -30 µA
V
SHDN
= 0.4V, Post-Rad -98 - -56
P
ower
O
n
R
eset
Th
res
h
o
ld
d
Sweep V
IN
and Measure Output V
T-POR
-1.7
-V
No Load - - 15
Full Load - - 90
V Output Voltage at Shutdown V
OUT
-0.1 - 0.1
V
V
SHDN
1.2 - - V
V
SHDN
--0.8
Current Limit
Ripple Rejection
d
PSRR dB
I
LATCH
3.5 - -
I
Q
mA Quiescent Current
d
1.746 1.8 1.854
1.737 1.8 1.836
A
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Notes:
Tested to 500Krad (Si).
See Fig. 5.
Space Level Screening Requirements
TEST/INSPECTION SCREENING LEVEL MIL-STD-883
SPACE METHOD
Nondestructive Bond Pull 100% 2023
Internal Visual 100% 2017
Seal 100% 1014
Temperature Cycle 100% 1010
Constant Acceleration 100% 2001
Mechanical Shock 100% 2002
PIND 100% 2020
Pre Burn-In-Electrical 100%
Burn-In 100% 1015
Final Electrical 100%
Radiographic 100% 2012
External Visual 100% 2009
Radiation Performance Characteristics
Test Conditions Min T
y
pUnit
MIL-STD-883, Method 1019 (Condition A)
Operating Bias applied during exposure
Minimum Rated Load, Vin = 6.4V
MIL-STD-883, Method 1019 (Condition D)
Total Ionizing Dose (Gamma) (ELDRS) Operating Bias applied during 100
exposure Minimum Rated Load, Vin = 6.4V
Single Event effects Heavy Ions (LET)
SEU, SEL, SEGR, SEB Operating Bias applied during exposure
under varying operating conditions
300 Total Ionizing Dose (Gamma)
Neutron Fluence MIL-STD-883, Method 1017
84
Krads (Si)500
c
1.0e11
See
d
Neutrons/cm2
Krads (Si)
MeV*cm2/mg
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Application Information
IRUH3301xxxx
0.1uF and 1uF
Ceramic;
Two 100uF
Low ESR
Tantalum
VIN
GND
SHDN
VSENSE
VOUT
0.1uF and 1uF
Ceramic;
Two 100uF
Low ESR
Tantalum
Input
Voltage
Output
Voltage
Fig. 1. Typical Regulator Circuit; Note the SHDN Pin is hardwired in the “ON” position.
The VSENSE Pin is connected as noted in the “General Layout Rules” section.
Over-Current & Over-Temperature Protection
The IRUH3301 series provides over-current protection by means of a timed latch function. Drive
current to the internal PNP pass transistor is limited by an internal resistor (Rb in Fig. 3) between
the base of the transistor and the control IC drive FET. If an over-current condition forces the
voltage across this resistor to exceed 0.5V (nom), the latch feature will be triggered. The time-to-
latch (tLATCH) is nominally 10ms. If the over-current condition exists for less than tLATCH , the latch
will not be set. If the latch is set the drive current to the PNP pass transistor will be disabled. The
latch will remain set until one of the following actions occur:
1. The SHDN Pin voltage is brought above 1.2V and then lowered below 0.8V.
2. The VIN Pin voltage is lowered below 1.7V.
If the junction temperature of the regulator IC exceeds 140°C nominal, the thermal shutdown circuit
will set the internal latch and disable the drive current to the PNP pass transistor as described
above. After the junction temperature falls below a nominal 125°C, the latch can be reset using
either of the actions described above.
Under-Voltage Lock-Out
The under-voltage lock-out (UVLO) function prevents operation when VIN is less than 1.7V
(nominal). There is a nominal 100mV hysteresis about this point.
Input Voltage Range
Shutdown (SHDN)
The regulator can be shutdown by applying a voltage of >1.2V to the SHDN Pin. The regulator will
restart when the SHDN Pin is pulled below the shutdown threshold of 0.8V. If the remote shutdown
feature is not required, the SHDN Pin should be connected to GND.
The device functions fully when VIN is greater than 2.8V. It enters into under-voltage lock-out at VIN
< 1.7V (nominal). When 1.7V (nominal) < VIN < 2.8V, VOUT will track VIN and overshoot may occur.
A larger output capacitor should be used to slow down the VOUT rise rate for slow VIN ramp
applications.
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Input Capacitance
Input bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums (AVX
TPS or equivalent), placed very close to the VIN Pin are required for proper operation. When the
input voltage supply capacitance is more than 4 inches from the device, additional input
capacitance is recommended. Larger input capacitor values will improve ripple rejection further
improving the integrity of the output voltage.
Output Capacitance
Output bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums
(AVX TPS or equivalent) are required for loop stability. Faster transient performance can be
achieved with multiple additional 1µF ceramic capacitors. Ceramic capacitors greater than 1µF in
value are not recommended as they can cause stability issues.
Tantalum capacitor values larger than the suggested value are recommended to improve the
transient response under large load current changes. The upper capacitance value limit is
governed by the delayed over-current latch function of the regulator and can be as much as
10,000µF without causing the device to latch-off during start-up.
General Layout Rules
Low impedance connections between the regulator output and load are essential. Solid power and
ground planes are highly recommended. In those cases where the board impedances are not kept
very small, oscillations can occur due to the effect of parasitic series resistance and inductance
on loop bandwidth and phase margin.
The VSENSE Pin must be connected directly to the VOUT Pin using as short a trace as possible with
the connection inside the first bypass capacitor (see Fig. 2a).
Connect ceramic output capacitors directly across the VOUT and GND Pins with as wide a trace as
design rules allow (see Fig. 2a). Avoid the use of vias for these capacitors and avoid loops. Fig.2
shows the ceramic capacitors tied directly to the regulator output.
Fig. 2a. Layer 1 conductor.
Ground plane below layer 1
Fig. 2b. Layer 1 silkscreen
The input capacitors should be connected as close a possible to the VIN Pin.
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Fig. 3. Simplified Schematic Circuit
VSENSE
+
-
Error
Amp
GND
Thermal
Shutdown
VIN
SHDN
VREF
Input
Undervoltage
detect
Shutdown
& Over
Current
Latch
Disable
Latch
Timing
capacitor
VOUT
Rb
Maximum Output Current (A) with no derating at Maximum Dissipation
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
100 110 120 130 140 150 160 170
Mounting Surface Temperature (’C)
Output Current (A)
Fig. 4. Maximum Output Current versus Mounting Surface Temperature with no Derating at Maximum
Dissipation
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VOut
-0.500%
-0.250%
0.000%
0.250%
0.500%
1 10 100 1000 10000 100000
Total Dose (Rad (Si))
Delta-VOut (%)
ELDRS
TID
Fig. 5. Change in Output Voltage vs. Total Ionizing Dose Radiation Exposure at Both High and Low Dose Rates
Fig. 6. Typical Power Supply Ripple Rejection at 100mA and 1.6A using recommended layout
and capacitors. Results above 10KHz are influenced by testing setup and layout.
PSRR (Typical)
-5
5
15
25
35
45
55
65
75
85
95
105
0.1 1 10 100 1000 10000
Freq (KHz)
PSRR (dB)
Recomended Setup without Part Iout=100mA & 1.6A, 1.8Vout, 3.3Vin
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Fig 7. Case Outline and Dimensions - 8-Lead Flat Pack (Lead Form Down)
Pin Assi
g
nment
Pin # Pin Description
1GND
2GND
3 SHUTDOWN
4VSENSE
5VOUT
6VOUT
7VIN
8VIN
Pin Assi
g
nment
Pin # Pin Description
1GND
2GND
3 SHUTDOWN
4VSENSE
5VOUT
6VOUT
7V
IN
8VIN
Note:
1) All dimensions are in inches
Note:
1) All dimensions are in inches
Fig 8. Case Outline and Dimensions - 8-Lead Flat Pack (Lead Trimmed)
Warning: This Product contains BeO
Warning: This Product contains BeO
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Part Numbering Nomenclature
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 05/2012
IR U H3 301 18 A K
Linear Regulator
U = Ultra Low Dropout Regulator
Radiation Hardening
H3 = 300 Krads
Device indicator
301 = 3 Amp Positive Regulator
Output Voltage
18 = 1.8V
25 = 2.5V
33 = 3.3V
A1 = Adjustable Optimized for 3.3 V Input
A2 = Adjustable Optimized for 5.0V Input
Lead Form Options
Blank = Lead Form Down (Fig. 7)
B = Lead Form Up
C = Lead Trimmed (Fig. 8)
Screening Level
P = Unscreened. 25°C
Electrical Test Not for Qualification
K = Class K per MIL-PRF-38534
Package Type
A = 8 Lead Flat Pack
