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IS66WVE4M16ALL
IS67WVE4M16ALL
Rev. B | Feb. 2012 www.issi.com - SRAM@issi.com
Overview
The IS66WVE4M16ALL is an i ntegrated memory device containing 64Mbit Pseudo Static Random Access
Memory using a self-refresh DRAM array organize d as 4M words by 16 bits. The device includes several
power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and
Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power
rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Asynchronous and pag e mode interface
Dual voltage rails for optional performance
VDD 1.8V, VDDQ 1.8V
Page mode read acces s
Interpag e Read access : 70ns
Intrapage Read acce ss : 20ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 18mA
Standby < 180 uA (max.)
Deep power -down (DPD) < 3uA (Typ)
Lo w Power F eatu re
Temperature Controlled Refresh
Partial Array Refresh
Deep power -down (DPD) mode
Operating temperature Range
Industrial and Automotive, A1: -40°C~85°C
Package:
48-ba ll TFBGA, 48-pin TSOP-I
1.8V Core Async/Page PSRAM
Features
Copyright © 2012 Integrated Silic on Solution, Inc. All rights reserved. ISS I reserves the right to make changes to thi s specifi cation and its
products at any tim e without noti ce. ISSI ass umes no liabilit y arisi ng out of the appl i cation or use of any i nf ormati on, products or services
described herein. Custom ers are advised to obtain the latest version of this device specif ic ation before relying on any publi shed inf orm ati on
and before pl acing orders f or produc ts.
Integrated Sili con Solution, Inc. does not recommend the use of any of i ts products i n l i fe support appli cations where the failure or
malfunction of the product can reasonabl y be expected to cause f ai l ure of the l i f e support system or to signific antly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance t o
its satisfactio n, that:
a.) the risk of injury or damage has been minimized;
b.) the user ass ume all such risk s ; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Notes :
1. The 48-pin TSOP -I package option is not yet available. Please contact SRAM marketing at sram@issi.com for
additional information.