64K x 16 Static RAM
CY7C1021BV33
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05148 Rev. *A Revised September 13, 2002
021BV33
Features
•3.3V operation (3.0V–3.6V)
•High speed
—tAA = 10/12/15 ns
•CMOS for optimum speed/power
•Low Active Power (L version)
—576 mW (max.)
•Low CMOS Standby Power (L version)
—1.80 mW (max.)
•Automatic power-down when deselected
•Independent control of upper and lower bits
•Available in 44-pin TSOP II and 400-mil SOJ
•Available in a 48-Ball Mini BGA package
Functional Description[1]
The CY7C1021BV is a high-performance CMOS static RAM
organ iz ed a s 6 5,5 36 wo rds by 16 b its. Th is dev ic e h as an a u-
tomatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O1 to I/O8. If Byte Hig h En abl e (BHE) is L OW,
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), the BHE an d
BLE are disabled (BHE, BLE HIGH) , or d uri ng a w ri te op era -
tion (CE LOW, and WE LOW).
The CY7C1021BV is ava il abl e in 400 -mi l-wid e SO J, st andard
44-pin TSOP Type II, and 48-ball mini BGA packages.
WE
Logic Block Diagram Pin Configurati ons
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
SOJ / TS OP II
12
13
41
44
43
42
16
15 29
30
VCC
A15
A14
A13
A12
NC
A4
A3
OE
VSS
A5
I/O16
A2
CE
I/O3
I/O1
I/O2
BHE
NC
A1
A0
18
17
20
19
I/O4
27
28
25
26
22
21 23
24 NC
VSS
I/O7
I/O5
I/O6
I/O8
A6
A7
BLE
VCC
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
64K x 16
RAM Array I/O1–I/O8
ROW DECODER
A7
A6
A5
A4
A3
A0
COLUMN DECODER
A9
A10
A11
A12
A13
A14
A15
512 X 2048
SENSE AMPS
DATA IN DRIVERS
OE
A2
A1
I/O9–I/O16
CE
WE
BLE
BHE
A8
Selection Guide
7C1021BV-8 7C1021BV-10 7C1021BV-12 7C1021BV-15
Maximum Access Time (ns) 81012 15
Maximum Operating Current (mA) Commercial 170 160 150 140
Industrial 190 180 170 160
Maximum CMOS Standby Current
(mA) Commercial 555 5
L0.500 0.500 0.500 0.500
Shaded areas contain advance information.
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
CY7C1021BV33
Document #: 38-05148 Rev. *A Page 2 of 11
Pin Configurations
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State[2] ......................................–0.5V to VCC+0.5V
DC Input Voltage[2]...................................–0.5V to VCC+0.5V
Current into Outputs (LOW) ........................................ 20 mA
St atic Discha rge Vol tage..... ...... ..... ................. ...... .....>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Note:
2. Mimimum voltage is–2.0V for pulse durations of less than 20 ns.
Mini BGA
(Top View)
BLE OE
BHE
WE
A0
A4
A1A2
CE
VSS
I/O1
A3
I/O9
I/O11
I/O10 A6
A5I/O3
I/O2
I/O5
I/O12 NC A7I/O4VCC
NC
VSS
VCC I/O13 NC NC
I/O15 I/O14
I/O8
A8
A15
A14 I/O6I/O7
I/O16 NC A12 A13
NC
NC A9A10 A11
123456
A
B
C
D
E
F
G
H
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C3.3V ± 10%
CY7C1021BV33
Document #: 38-05148 Rev. *A Page 3 of 11
Electrical Characteristics Over the Operating Ran ge
Parameter Description Test Conditions 7C1021BV-8 7C1021BV-10 7C1021BV-12 7C1021BV-15 UnitMin. Max. Min. Max. Min. Max. Min. Max.
VOH Output HIGH
Voltage VCC = Min.,
IOH = –4.0 mA 2.4 2.4 2.4 2.4 V
VOL Output LOW
Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 0.4 V
VIH Input HIGH
Voltage 2.2 VCC+
0.3V 2.2 VCC+
0.3V 2.2 VCC+
0.3V 2.2 VCC+
0.3V V
VIL Input LOW
Voltage[2] −0.3 0.8 −0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Load
Current GND < VI < VCC −1+1 −1+1–1+1 –1+1 µA
IOZ Output Leakage
Current GND < VI < VCC,
Output D isa bl ed −1+1 −1+1–1+1 –1+1 µA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Com 170 160 150 140 mA
Ind 190 120 170 160 mA
ISB1 Automatic CE
Power-Down
Current
—TTL Inputs
Max. VCC,
CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
40 40 40 40 mA
ISB2 Automatic CE
Power-Down
Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V,
f = 0
55 5 5 mA
L500 500 500 500 µA
Shaded areas contain advance information.
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz 6pF
COUT Output C ap a ci t ance 8pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
R 317ΩR 317Ω
R2
351ΩR2
351Ω
167
Equivalent to: THÉVENIN
EQUIVALENT 1.73V
30 pF
Rise Time: 1 V/ns Fall Time: 1 V/ns
CY7C1021BV33
Document #: 38-05148 Rev. *A Page 4 of 11
Switching Characteristics[4] Over the Operating Range
Parameter Description
7C1021BV-8 7C1021BV-10 7C1021BV-12 7C1021BV-15
UnitMin. Max. Min. Max. Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time 810 12 15 ns
tAA Address to Data Valid 81012 15 ns
tOHA Data Hold from Address Change 3 3 3 3 ns
tACE CE LOW to Data Valid 81012 15 ns
tDOE OE LOW to Data Valid 446 7 ns
tLZOE OE LOW to Low Z 0 0 0 0 ns
tHZOE OE HIGH to High Z[5, 6] 456 7 ns
tLZCE CE LOW to Low Z[6] 3 3 3 3 ns
tHZCE CE HIGH to High Z[5, 6] 456 7 ns
tPU CE LOW to Power-Up 0 0 0 0 ns
tPD CE HIGH to Power-Down 12 12 12 15 ns
tDBE Byte Enable to Data Valid 4 5 6 7 ns
tLZBE Byte Enab le to Low Z 0 0 0 0 ns
tHZBE Byte Disable to High Z 456 7 ns
WRITE CYCLE[7]
tWC Write Cycle Time 810 12 15 ns
tSCE CE LO W to Write End 7 8 9 10 ns
tAW Address Set-Up to Write End 6 7 8 10 ns
tHA Address Hold from Write End 0 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 0 ns
tPWE WE Pulse Width 6 8 8 10 ns
tSD Data Set-Up to Write End 4 6 6 8 ns
tHD Data Hold from Write End 0 0 0 0 ns
tLZWE WE HIGH to Low Z[6] 3 3 3 3 ns
tHZWE WE LOW to High Z[5, 6] 456 7 ns
tBW Byte Enable to End of Write 8 8 8 9 ns
Shaded areas contain advance information.
Data Retenti on Characteristi cs Over the Operating Range (L version only)
Parameter Description Conditions[8] Min. Max. Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current Com’l VCC = VDR = 2.0V ,
CE > V CC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
100 µA
tCDR[9] Chip Deselect to Data Retention Ti me 0ns
tR[10] Operation Recovery Time tRC ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF loa d cap acit ance.
5. tHZOE, tHZBE, tHZCE, an d tHZWE are specifi ed with a load cap acita nce of 5 pF as in part (b) of AC Test Loads. T ransitio n is measured ±500 mV from st eady-s tat e volt age.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is les s than tLZOE, and t HZWE is less than tLZWE for any given device.
7. T he i n ter na l wr i t e tim e of th e me mo ry is de fi ne d by t h e ov e rla p of CE LOW , WE LOW and BHE / BLE LOW . CE, W E and BHE / BLE mus t be LOW to in itiate a write,
and the transition of these sig nals can termi nate the writ e. The input data set- up and hold tim ing shoul d be referenc ed to the l eading edge of the signal that termin ates the writ e.
8. No input may exceed VCC + 0.5V.
9. Tested initially and after any design or process changes that may affect these parameters.
10. tr < 3 ns for t he -12 and -15 speeds. tr < 5 ns f or the -20 and s lower speeds.
CY7C1021BV33
Document #: 38-05148 Rev. *A Page 5 of 11
Data Retenti on Waveform
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
Switching Waveforms
Notes:
11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
12. WE is HIGH f or read cycle .
13. Address valid prio r to or coincident with CE t ransiti on LOW.
Read Cycle No. 1
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
[11, 12]
Read Cycle No. 2 (OEControlled)
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPE D ANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE,BLE
[12, 13]
CURRENT
ICC
ISB
CY7C1021BV33
Document #: 38-05148 Rev. *A Page 6 of 11
Notes:
14. Data I/O is high impedance if OE or BHE a nd/or BL E= VIH.
15. If CE goes HIG H simulta neously with WE going H IGH, the outpu t remai ns in a high -impeda nce s tate.
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATA I/O
ADDRESS
CE
WE
BHE, BLE
[14, 15]
t
Write Cycle No. 2 (BLEorBHE Controlled)
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATA I/O
ADDRESS
BHE,BLE
WE
CE
CY7C1021BV33
Document #: 38-05148 Rev. *A Page 7 of 11
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled,LOW)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
DATA I/O
ADDRESS
CE
WE
BHE,BLE
tSA
tLZWE
tHZWE
Truth Table
CE OE WE BLE BHE I/O1–I/O8I/O9–I/O16 Mode Power
H X X X X High Z High Z Power-Down Sta ndb y (ISB)
L L H L L Data Out Data Out Read - All bits Active (ICC)
L H Data Out High Z Read - Lower bits only Active (ICC)
H L High Z Data Out Read - Upper bits only Active (ICC)
L X L L L Data In Data In Write - All bi ts Active (ICC)
L H Data In High Z Write - Lower bits only Active (ICC)
H L High Z Data In Write - Upper bits only Active (ICC)
L H H X X High Z Hi gh Z Selected, Outputs Disabled Active (ICC)
L X X H H High Z Hi gh Z Selected, Outputs Disabled Active (ICC)
CY7C1021BV33
Document #: 38-05148 Rev. *A Page 8 of 11
Ordering Information
Speed (ns) Ordering Code Package
Name Package Type Operating
Range
8CY7C1021BV33-8BAC BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Commercial
CY7C1021BV33-8VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021BV33L-8VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021BV33-8ZC Z44 44-Lead TSOP Type II
CY7C1021BV33L-8ZC Z44 44-Lead TSOP Type II
10 CY7C1021BV33-10BAC BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Commercial
CY7C1021BV33-10VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021 BV33L-10VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021 BV33-10ZC Z44 44-Lead TSOP Type II
CY7C1021BV33L-10ZC Z44 44-Lead TSOP Type II
12 CY7C1021BV33-12BAC BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Commercial
CY7C1021BV33-12VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021 BV33L-12VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021 BV33-12ZC Z44 44-Lead TSOP Type II
CY7C1021BV33L-12ZC Z44 44-Lead TSOP Type II
CY7C1021BV33-12BAI BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Industrial
CY7C1021BV33-12VI V34 44-Lead (400-Mil) Molded SOJ
15 CY7C1021BV33-15BAC BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Commercial
CY7C1021BV33L-15BAC BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm)
CY7C1021BV33-15VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021 BV33L-15VC V34 44-Lead (400-Mil) Molded SOJ
CY7C1021 BV33-15ZC Z44 44-Lead TSOP Type II
CY7C1021BV33L-15VC Z44 44-Lead TSOP Ty pe II
CY7C1021BV33-15BAI BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Industrial
CY7C1021BV33L-15BAI BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm)
CY7C1021BV33-15VI V34 44-Lead (400-Mil) Molded SOJ
CY7C1021BV33L-15ZI Z44 44-Lead TSOP Type II
Shaded areas contain advance information.
CY7C1021BV33
Document #: 38-05148 Rev. *A Page 9 of 11
Package Diagrams
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
CY7C1021BV33
Document #: 38-05148 Rev. *A Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
44-Lead (4 00-Mil) Mo lded SOJ V3 4
51-85082-*B
44-Pin TSOP II Z44
51-85087-A
CY7C1021BV33
Document #: 38-05148 Rev. *A Page 11 of 11
Document History Page
Document Title: CY7C1021BV33 64K x 16 Static RAM
Document Number: 38-05148
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 109892 09/22/01 SZV Change from Spec number: 38-00954 to 38-05148
*A 116474 09/16/02 CEA Add applications foot note to data sheet, page 1.
