ISL6754
FN6754 Rev 2.00 Page 12 of 20
June 2, 2016
average of CS. Figure 9 shows the dynamic behavior of the
current averaging circuitry when CS is modulated by an external
sine wave. Notice IOUT is updated by the sample and hold
circuitry at the termination of the active output pulse.
The average current signal on IOUT remains accurate provided
the output inductor current remains continuous (CCM operation).
Once the inductor current becomes discontinuous (DCM
operation), IOUT represents 1/2 the peak inductor current rather
than the average current. This occurs because the sample and
hold circuitry is active only during the on time of the switching
cycle. It is unable to detect when the inductor current reaches
zero during the off time.
If average overcurrent limit is desired, IOUT may be used with the
error amplifier of the ISL6754. Typically IOUT is divided down and
filtered as required to achieve the desired amplitude. The
resulting signal is input to the current error amplifier (IEA). The
IEA is similar to the voltage EA found in most PWM controllers,
except it cannot source current. Instead, VERR has a separate
internal 1mA pull-up current source.
Configure the IEA as an integrating (Type I) amplifier using the
internal 0.6V reference. The voltage applied at FB is integrated
against the 0.6V reference. The resulting signal, VERR, is applied
to the PWM comparator where it is compared to the sawtooth
voltage on RAMP. If FB is less than 0.6V, the IEA will be open loop
(can’t source current), VERR will be at a level determined by the
voltage loop, and the duty cycle is unaffected. As the output load
increases, IOUT will increase, and the voltage applied to FB will
increase until it reaches 0.6V. At this point the IEA will reduce
VERR as required to maintain the output current at the level that
corresponds to the 0.6V reference. When the output current
again drops below the average current limit threshold, the IEA
returns to an open loop condition, and the duty cycle is again
controlled by the voltage loop.
The average current control loop behaves much the same as the
voltage control loop found in typical power supplies except it
regulates current rather than voltage.
The EA available on the ISL6754 may also be used as the voltage
EA for the voltage feedback control loop rather than the current
EA as described above. An external op-amp may be used as
either the current or voltage EA providing the circuit is not
allowed to source current into VERR. The external EA must only
sink current, which may be accomplished by adding a diode in
series with its output.
The 4x gain of the sample and hold buffer allows a range of 150
to 1000mV peak on the CS signal, depending on the resistor
divider placed on IOUT. The overall bandwidth of the average
current loop is determined by the integrating current EA
compensation and the divider on IOUT.
The current EA cross-over frequency, assuming R6 >> (R4||R5),
is:
Where fCO is the cross-over frequency. A capacitor in parallel with
R4 may be used to provide a double-pole roll-off.
The average current loop bandwidth is normally set to be much
less than the switching frequency, typically less than 5kHz and
often as slow as a few hundred hertz or less. This is especially
useful if the application experiences large surges. The average
current loop can be set to the steady state overcurrent threshold
and have a time response that is longer than the required
transient. The peak current limit can be set higher than the
expected transient so that it does not interfere with the transient,
but still protects for short-term larger faults. In essence a 2-stage
overcurrent response is possible.
The peak overcurrent behavior is similar to most other PWM
controllers. If the peak current exceeds 1.0V, the active output
pulse is terminated immediately.
If voltage-mode control is used in a bridge topology, it should be
noted that peak current limit results in inherently unstable
operation. DC blocking capacitors used in voltage-mode bridge
topologies become unbalanced, as does the flux in the
transformer core. The average overcurrent circuitry prevents this
behavior by maintaining symmetric duty cycles for each
FIGURE 9. DYNAMIC BEHAVIOR OF CS vs IOUT
CHANNEL 1 (YELLOW): OUTLL
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTLR
CHANNEL 4 (GREEN): IOUT
FIGURE 10. AVERAGE OVERCURRENT IMPLEMENTATION
SS
OUTUR
OUTUL
OUTLR
OUTLL
VDD
VREF
GND
1
2
4
3
5
6
7
8
19
20
11
12
13
14
15
16
N/C
GND9
10
17
18
150 - 1000 mV
+
-
0.6V
S&H
4x
R6R5
R4
C10
CS
FB
IOUT
VERR
ISL6754
fCO
1
2R6C10
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=Hz (EQ. 6)