DATA SHEET Z8E001 1 FEATURE-RICH Z8PLUS ONE-TIME PROGRAMMABLE (OTP) MICROCONTROLLER FEATURES Part Number ROM (KB) RAM* (Bytes) Speed (MHz) 64 10 Z8E001 1 Note: * General-Purpose Microcontroller Core Features All Instructions Execute in one 1 s Instruction Cycle with a 10 MHz Crystal 1K x 8 On-Chip OTP EPROM Memory 64 x 8 General-Purpose Registers (SRAM) Includes Special Functionality: Stop-Mode Recovery Input, Comparator Inputs, Selectable Edge Interrupts, and Timer Output One Analog Comparator 16-Bit Programmable Watch-Dog Timer (WDT) Software Programmable Timers Configurable as: Two 8-Bit Standard Timers and One 16-Bit Standard Timer, or One 16-Bit Standard Timer and One 16-Bit Pulse Width Modulator (PWM) Timer Six Vectored Interrupts with Fixed Priority Additional Features Operating Speed: DC10 MHz On-Chip Oscillator that accepts an XTAL, Ceramic Resonator, LC, or External Clock Programmable Options: EPROM Protect 13 Total Input/Output Pins One 8-Bit I/O Port (Port A) I/O Bit Programmable Each Bit Programmable as Push-Pull or OpenDrain Power Reduction Modes: HALT Mode with Peripheral Units Active STOP Mode with all Functionality Shut Down CMOS/Technology Features One 5-Bit I/O Port (Port B) I/O Bit Programmable Six Addressing Modes: R, IR, X, D, RA, & IM Peripheral Features Low-Power Consumption 3.5V to 5.5V Operating Range @ 0C to +70C 4.5V to 5.5V Operating Range @ 40C to +105C 18-Pin DIP, SOIC, and 20-Pin SSOP Packages. GENERAL DESCRIPTION Allowing easy software development, debug, and prototyping, ZiLOGOs new Z8E001 Microcontroller (MCU) offers a cost-effective One-Time Programmable (OTP) solution to its single-chip Z8Plus MCU family. For applications demanding powerful I/O capabilities, the Z8E001Os dedicated input and output lines are grouped into two ports, and are configurable under software control. Both 8-bit and 16-bit on-chip timers, with a large number of user-selectable modes, offload the system of administer- DS001101-Z8X0400 1 Z8E001 Z8Plus OTP Microcontroller ZiLOG GENERAL DESCRIPTION (Continued) ing real-time tasks such as counting/timing and I/O data communications. Power connections follow conventional descriptions below: Note: All signals with an overline, O O, are active Low. For example, B/ W (WORD is active Low, only); B /W (BYTE is active Low, only). VCC Connection Circuit Device Power VCC VDD Ground GND VSS GND Two 8-bit Timers or One 16-bit PWM Timer XTAL RESET Machine Timing ALU One 16-bit Std. Timer FLAG OTP Prg. Mem- Interrupt Control Register Pointer One Analog Comparator Program Counter RAM Register Port A Port B I/O I/O Figure 1. Functional Block Diagram 2 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG D70 AD90 Z8E001 MCU AD90 ADDRESS MUX ADDRESS GENERATOR AD90 EPROM D70 DATA MUX Z8E001 D70 PORT ROM PROT OPTION BIT A PGM + TEST MODE LOGIC PGM ADCLR/VPP ADCLK XTAL1 Figure 2. EPROM Programming Mode Block Diagram DS001101-Z8X0400 PRELIMINARY 3 Z8E001 Z8Plus OTP Microcontroller ZiLOG PIN DESCRIPTION PGM GND GND GND ADCLR/VPP D7 D6 D5 D4 1 18 18-Pin DIP 9 10 ADCLK XTAL1 NC GND VDD D0 D1 D2 D3 Figure 3. 18-Pin DIP/SOIC Pin Identification/EPROM Programming Mode EPROM Programming Mode Pin # Symbol Function Direction 1 24 5 PGM GND ADCLR/VPP Prog Mode Ground Clear Clk./Prog Volt. Input 6-9 1013 14 D7D4 D3D0 VDD Data 7,6,5,4 Data 3,2,1,0 Power Supply 15 16 17 18 GND NC XTAL1 ADCLK Ground No Connection 1MHz Clock Address Clock 4 PRELIMINARY Input Input/Output Input/Output Input Input DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG PB1 PB2 PB3 PB4 RST PA7 PA6 PA5 PA4 1 18 DIP 18-Pin 9 10 PBO XTAL1 XTAL2 VSS VCC PA0 PA1 PA2 PA3 Figure 4. 18-Pin DIP/SOIC Pin Identification Standard Mode Pin # Symbol Function Direction 14 5 6-9 1013 14 PB1PB4 RESET PA7PA4 PA3PA0 VCC Port B, Pins 1,2,3,4 Reset Port A, Pins 7,6,5,4 Port A, Pins 3,2,1,0 Power Supply Input/Output Input Input/Output Input/Output 15 VSS Ground 16 17 18 XTAL2 XTAL1 PB0 Crystal Osc. Clock Crystal Osc. Clock Port B, Pin 0 DS001101-Z8X0400 PRELIMINARY Output Input Input/Output 5 Z8E001 Z8Plus OTP Microcontroller ZiLOG PIN DESCRIPTION (Continued) PB1 PB2 PB3 PB4 RESET NC PA7 PA6 PA5 PA4 1 20 SSOP 20-Pin 10 11 PBO XTAL1 XTAL2 VSS VCC NC PA0 PA1 PA2 PA3 Figure 5. 20-Pin SSOP Pin Identification Standard Mode Pin # Symbol Function Direction 14 5 6 710 1114 15 16 PB1PB4 RESET NC PA7PA4 PA3PA0 NC VCC Port B, Pins 1,2,3,4 Reset No Connection Port A, Pins 7,6,5,4 Port A, Pins 3,2,1,0 No Connection Power Supply Input/Output Input 17 VSS Ground 18 19 20 XTAL2 XTAL1 PB0 Crystal Osc. Clock Crystal Osc. Clock Port B, Pin 0 6 PRELIMINARY Input/Output Input/Output Output Input Input/Output DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG PGM GND GND GND ADCLR/VPP NC D7 D6 D5 D4 1 20 SSOP 20-Pin 10 11 ADCLK XTAL1 NC GND VDD NC D0 D1 D2 D3 Figure 6. 20-Pin SSOP Pin Identification/EPROM Programming Mode EPROM Programming Mode Pin # Symbol Function Direction 1 24 5 PGM GND ADCLR/VPP Prog Mode Ground Clear Clk./Prog Volt. Input 6 710 1114 15 16 NC D7D4 D3D0 NC VDD No Connection Data 7,6,5,4 Data 3,2,1,0 No Connection Power Supply 17 18 19 20 GND NC XTAL1 ADCLK Ground No Connection 1MHz Clock Address Clock DS001101-Z8X0400 PRELIMINARY Input Input/Output Input/Output Input Input 7 Z8E001 Z8Plus OTP Microcontroller ZiLOG ABSOLUTE MAXIMUM RATINGS Parameter Min Max Units Note Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS 40 65 0.6 +105 +150 +7 C C V 1 Voltage on VDD Pin with Respect to VSS 0.3 +7 V Voltage on RESET Pin with Respect to VSS 0.6 VDD+1 V Total Power Dissipation Maximum Allowable Current out of VSS 880 80 mW mA Maximum Allowable Current into VDD 80 mA +600 +600 25 mA mA mA 25 40 40 40 40 mA mA mA mA mA Maximum Allowable Current into an Input Pin Maximum Allowable Current into an Open-Drain Pin Maximum Allowable Output Current Sunk by Any I/O Pin 600 600 Maximum Allowable Output Current Sourced by Any I/O Pin Maximum Allowable Output Current Sunk by Port A Maximum Allowable Output Current Sourced by Port A Maximum Allowable Output Current Sunk by Port B Maximum Allowable Output Current Sourced by Port B 2 3 4 Notes: 1. Applies to all pins except the RESET pin and where otherwise noted. 2. There is no input protection diode from pin to VDD. 3. Excludes XTAL pins. 4. Device pin is not at an output Low state. Stresses greater than those listed under Absolute Maximum Ratings can cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period can affect device reliability. Total power dissipation should 8 not exceed 880 mW for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [IDD (sum of IOH)] + sum of [(VDD VOH) x IOH] + sum of (V0L x I0L) PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 7). From Output Under Test 150 pF Figure 7. Test Load Diagram CAPACITANCE TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance DS001101-Z8X0400 Min Max 0 0 0 12 pF 12 pF 12 pF PRELIMINARY 9 Z8E001 Z8Plus OTP Microcontroller ZiLOG DC ELECTRICAL CHARACTERISTICS Table 1. DC Electrical Characteristics pF TA = 0C to +70C Standard Temperatures Typical2 @ 25C Units Conditions Sym Parameter VCC1 VCH Clock Input High Voltage 3.5V 0.7VCC VCC+0.3 1.3 V 5.5V 0.7VCC VCC+0.3 2.5 V 3.5V VSS0.3 0.2VCC 0.7 V 5.5V VSS0.3 0.2VCC 1.5 V VCL Clock Input Low Voltage Min Max Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator VIH Input High Voltage 3.5V 5.5V 0.7VCC 0.7VCC VCC+0.3 VCC+0.3 1.3 2.5 V V VIL Input Low Voltage 3.5V 5.5V VSS0.3 VSS0.3 0.2VCC 0.2VCC 0.7 1.5 V V VOH Output High Voltage 3.5V VCC0.4 3.1 V IOH = 2.0 mA 5.5V VCC0.4 4.8 V IOH = 2.0 mA VOL1 Output Low Voltage Notes 3.5V 0.6 0.2 V IOL = +4.0 mA 5.5V 0.4 0.1 V IOL = +4.0 mA 1.2 0.5 V IOL = +6 mA IOL = +12 mA VOL2 Output Low Voltage 3.5V 1.2 0.5 V VRH Reset Input High Voltage 3.5V 0.5VCC VCC 1.1 V 5.5V 0.5VCC VCC 2.2 V 3.5V VSS0.3 0.2VCC 0.9 V 5.5V VSS0.3 0.2VCC 1.4 V 3.5V 5.5V 3.5V 1.0 25.0 25.0 2.0 10.0 10.0 0.064 mV mV mA VIN = 0V, VCC 5.5V 1.0 2.0 0.064 mA VIN = 0V, VCC 3.5V 1.0 2.0 0.114 A VIN = 0V, VCC 5.5V 1.0 2.0 0.114 A VIN = 0V, VCC 3.5V VSS0.3 VCC1.0 V 3 5.5V VSS0.3 VCC1.0 V 3 3.5V 5.5V 10 20 60 180 5.5V VRL Reset Input Low Voltage VOFFSET Comparator Input Offset Voltage IIL IOL VICR IIR 10 Input Leakage Output Leakage Comparator Input Common Mode Voltage Range Reset Input Current PRELIMINARY 30 100 A A DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG Table 1. DC Electrical Characteristics (Continued) pF TA = 0C to +70C Standard Temperatures 1 Typical2 @ 25C Units Conditions Sym Parameter VCC ICC Supply Current ICC1 Standby Current 3.5V 5.5V 3.5V 2.5 6.0 2.0 2.0 3.5 1.0 mA mA mA @ 10 MHz @ 10 MHz HALT Mode VIN = 0V, VCC @ 10 MHz 4,5 4,5 4,5 5.5V 4.0 2.5 mA HALT Mode VIN = 0V, VCC @ 10 MHz 4,5 3.5V 500 150 nA STOP Mode VIN = 0V, VCC 6 ICC2 Standby Current Min Max Notes Notes: 1. The VCC voltage specification of 3.5V guarantees 3.5V and the VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V. 2. Typical values are measured at VCC = 3.3V and VCC = 5.0V; VSS = 0V = GND. 3. For analog comparator input when analog comparator is enabled. 4. All outputs unloaded and all inputs are at VCC or VSS level. 5. CL1 = CL2 = 22 pF. 6. Same as note 4 except inputs at VCC. DS001101-Z8X0400 PRELIMINARY 11 Z8E001 Z8Plus OTP Microcontroller ZiLOG DC ELECTRICAL CHARACTERISTICS (Continued) Table 2. DC Electrical Characteristics TA = 40C to +105C Extended Temperatures Sym Parameter VCC VCH Clock Input High Voltage VCL VIH VIL VOH VOL1 VOL2 VRH Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage Reset Input High Voltage VOFFSET Comparator Input Offset Voltage 1 Typical2 @ 25C Units Conditions Min Max Notes 4.5V 0.7 VCC VCC+0.3 2.5 V 5.5V 0.7 VCC VCC+0.3 2.5 V 4.5V VSS0.3 0.2 VCC 1.5 V 5.5V VSS0.3 0.2 VCC 1.5 V 4.5V 0.7 VCC VCC+0.3 2.5 V 5.5V 0.7 VCC VCC+0.3 2.5 V 4.5V VSS0.3 0.2 VCC 1.5 V 5.5V VSS0.3 0.2 VCC 1.5 V 4.5V VCC0.4 4.8 V IOH = 2.0 mA 5.5V VCC0.4 4.8 V IOH = 2.0 mA Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator 4.5V 0.4 0.1 V IOL = +4.0 mA 5.5V 0.4 0.1 V IOL = +4.0 mA 4.5V 1.2 0.5 V IOL = +12 mA 5.5V 1.2 0.5 V IOL = +12 mA 4.5V 0.5VCC VCC 1.1 V 5.5V 0.5VCC VCC 2.2 V 1.0 25.0 25.0 2.0 10.0 10.0 <1.0 mV mV A IIL Input Leakage 4.5V 5.5V 4.5V 5.5V 1.0 2.0 <1.0 A VIN = 0V, VCC IOL Output Leakage 4.5V 1.0 2.0 <1.0 A VIN = 0V, VCC 5.5V 1.0 2.0 <1.0 A VIN = 0V, VCC 4.5V 0 VCC 1.5V V 3 5.5V 0 VCC 1.5V V 3 4.5V 5.5V 18 18 180 180 VICR IIR 12 Comparator Input Common Mode Voltage Range Reset Input Current 112 112 PRELIMINARY VIN = 0V, VCC mA mA DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG Table 2. DC Electrical Characteristics (Continued) TA = 40C to +105C Extended Temperatures 1 Typical2 @ 25C Units Conditions Sym Parameter VCC ICC Supply Current ICC1 Standby Current 4.5V 5.5V 4.5V 7.0 7.0 2.0 4.0 4.0 1.0 mA mA mA @ 10 MHz @ 10 MHz HALT Mode VIN = 0V, VCC @ 10 MHz 4,5 4,5 4,5 5.5V 2.0 1.0 mA HALT Mode VIN = 0V, VCC @ 10 MHz 4,5 4.5V 700 250 nA STOP Mode VIN = 0V,VCC 6 5.5V 700 250 nA STOP Mode VIN = 0V,VCC 6 ICC2 Standby Current Min Max Notes Notes: 1. The VCC voltage specification of 4.5V and 5.5V guarantees 5.0V 0.5V. 2. Typical values are measured at VCC = 3.3V and VCC = 5.0V; VSS = 0V = GND. 3. For analog comparator input when analog comparator is enabled. 4. All outputs unloaded and all inputs are at VCC or VSS level. 5. CL1 = CL2 = 22 pF. 6. Same as note 4 except inputs at VCC. DS001101-Z8X0400 PRELIMINARY 13 Z8E001 Z8Plus OTP Microcontroller ZiLOG AC ELECTRICAL CHARACTERISTICS 1 3 CLOCK 2 3 2 IRQN 4 5 Figure 8. AC Electrical Timing Diagram Table 3. Additional Timing TA = 0C to +70C TA = 40C to +105C @ 10 MHz No Symbol Parameter VCC1 Min Max Units Notes 1 TpC Input Clock Period 100 100 2 TrC,TfC Clock Input Rise and Fall Times DC DC 15 15 3 TwC Input Clock Width 4 TwIL Int. Request Input Low Time ns ns ns ns ns ns ns ns 5 TwIH Int. Request Input High Time 2 2 2 2 2 2 2 2 2 2 6 Twsm STOP Mode Recovery Width Spec. 7 Tost Oscillator Start-Up Time 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 50 50 70 70 5TpC 5TpC 12 12 ns ns 5TpC 5TpC Notes: 1. The VDD voltage specification of 3.5V guarantees 3.5V. The VDD voltage specification of 5.5V guarantees 5.0V 0.5V. 2. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 14 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG Z8PLUS CORE The Z8E001 is based on the ZiLOG Z8Plus Core Architecture. This core is capable of addressing up to 64KBytes of program memory and 4KBytes of RAM. Register RAM is accessed as either 8 or 16 bit registers using a combination of 4, 8, and 12 bit addressing modes. The architecture sup- ports up to 15 vectored interrupts from external and internal sources. The processor decodes 44 CISC instructions using six addressing modes. See the Z8Plus UserOs Manual for more information. RESET This section describes the Z8E001 reset conditions, reset timing, and register initialization procedures. Reset is generated by the Reset Pin, Watch-Dog Timer (WDT), and Stop-Mode Recovery (SMR). are reset to their default conditions after a reset from the RESET pin. The control registers and ports are not reset to their default conditions after wakeup from Stop Mode or WDT timeout. A system reset overrides all other operating conditions and puts the Z8E001 into a known state. To initialize the chipOs internal logic, the RESET input must be held Low for at least 30 XTAL clock cycles. The control registers and ports During RESET, the program counter is loaded with 0020H. I/O ports and control registers are configured to their default reset state. Resetting the Z8E001 does not affect the contents of the general-purpose registers. RESET PIN OPERATION The Z8E001 hardware RESET pin initializes the control and peripheral registers, as shown in Table 4. Specific reset values are shown by 1 or 0, while bits whose states are unchanged or unknown from Power-Up are indicated by the letter U. RESET must be held Low until the oscillator stabilizes, for an additional 30 XTAL clock cycles, in order to be sure that the internal reset is complete. The RESET pin has a SchmittTrigger input with a trip point. There is no High side protection diode. The user should place an external diode from RESET to VCC. A pull-up resistor on the RESET pin is approximately 500 K, typical. Program execution starts 10 XTAL clock cycles after RESET has returned High. The initial instruction fetch is from location 0020H. Figure 9 indicates reset timing. After a reset, the first routine executed must be one that initializes the TCTLHI control register to the required system configuration, followed by initialization of the remaining control registers. Table 4. Control and Peripheral Registers Bits Register (HEX) Register Name 7 6 5 4 3 2 1 0 Comments FF Stack Pointer 0 0 U U U U U U Stack pointer is not affected by RESET FE FD Reserved Register Pointer U U U U 0 0 0 0 FC Flags U U U U U U * * FB FA Interrupt Mask Interrupt Request 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register pointer is not affected by RESET Only WDT & SMR flags are affected by RESET All interrupts masked by RESET All interrupt requests cleared by RESET F9F0 EFE0 Reserved Virtual Copy DFD8 Reserved DS001101-Z8X0400 Virtual Copy of the Current Working Register Set PRELIMINARY 15 Z8E001 Z8Plus OTP Microcontroller ZiLOG RESET PIN OPERATION (Continued) Table 4. Control and Peripheral Registers (Continued) Bits Register (HEX) Register Name 7 6 5 4 3 2 1 0 Comments D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 Port B Special Function Port B Directional Control Port B Output U U U U U U U U D4 Port B Input U U U U U U U U D3 Port A Special Function 0 0 0 0 0 0 0 0 Deactivates all port special functions after RESET Defines all bits as inputs in PortB after RESET Output register not affected by RESET Current sample of the input pin following RESET Deactivates all port special functions after RESET D2 0 0 0 0 0 0 0 0 D1 Port A Directional Control Port A Output U U U U U U U U D0 Port A Input U U U U U U U U CF CE CD CC CB CA C9 C8 C7 C6 C5 C4 C3 C2 C1 Reserved Reserved T1VAL T0VAL T3VAL T2VAL T3AR T2AR T1ARHI T0ARHI T1ARLO T0ARLO WDTHI WDTLO TCTLHI U U U U U U U U U U 1 1 1 U U U U U U U U U U 1 1 1 U U U U U U U U U U 1 1 1 U U U U U U U U U U 1 1 1 U U U U U U U U U U 1 1 1 U U U U U U U U U U 1 1 0 U U U U U U U U U U 1 1 0 U U U U U U U U U U 1 1 0 0 0 D6 C0 TCTLLO 0 0 0 0 0 0 Note: *The SMR and WDT flags are set indicating the source of the RESET. 16 PRELIMINARY Defines all bits as inputs in PortA after RESET Output register not affected by RESET Current sample of the input pin following RESET WDT Enabled in HALT Mode, WDT timeout at maximum value, STOP Mode disabled All standard timers are disabled DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG Table 5. Flag Register Bit D1, D0 D1 D0 Reset Source 0 0 1 1 0 1 0 1 RESET Pin SMR Recovery WDT Reset Reserved First Machine Cycle Clock RESET Hold Low For 30 XTAL Periods (Minimum) 10 XTAL CLOCK CYCLES First Instruction Fetch Figure 9. Reset Timing VCC VCC 100 K1/2 500 K1/2 RESET 1K1/2 1 F Z8E001 Figure 10. Example of External Power-On Reset (POR) Circuit DS001101-Z8X0400 PRELIMINARY 17 Z8E001 Z8Plus OTP Microcontroller ZiLOG RESET PIN OPERATION (Continued) TCTLHI D6,D5,D4 3 WDT TAP SELECT XTAL /64 16-BIT TIMER WDTRST WDTRST WATCHDOG TIMER SMR (PB0) SMR LOGIC SMR RECOVERY Figure 11. Z8E001 Reset Circuitry with WDT and SMR 18 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG Z8E001 WATCH-DOG TIMER (WDT) The WDT is a retriggerable one-shot 16-bit timer that resets the Z8E001 if it reaches its terminal count. The WDT is driven by the XTAL2 clock pin. To provide the longer timeout periods required in applications, the watchdog timer is only updated every 64th clock cycle. When operating in the RUN or HALT Modes, a WDT timeout reset is functionally equivalent to an interrupt vectoring the PC to 0020H and setting the WDT flag to a one state. Coming out of RESET, the WDT is fully enabled with its timeout value set at the maximum value, unless otherwise programmed during the first instruction. Subsequent executions of the WDT instruction, reinitialize the watchdog timer registers (C2H and C3H), to their initial values as defined by bits D6, D5, and D4 of the TCTLHI register. The WDT cannot be disabled except on the first cycle after RESET, and if the device enters Stop mode. get near 0. Because the WDT timeout periods are relatively long, a WDT reset will occur in the unlikely event that the WDT times out on exactly the same cycle that the WDT instruction is executed. The WDT and SMR flags are the only flags that are affected by the external RESET pin. RESET clears both the WDT and SMR flags. A WDT timeout sets the WDT flag. The STOP instruction sets the SMR flag. This behavior enables software to determine whether a pin RESET occurred, or whether a WDT timeout occurred, or whether a return from STOP Mode occurred. Reading the WDT and SMR flags does not reset it to zero, the user must clear it via software. Note: Failure to clear the SMR flag can result in undefined behavior. The WDT instruction should be executed often enough to provide some margin before allowing the WDT registers to 0C1 TCTLHI D7 D6 D5 D4 D3 D2 D1 D0 RESERVED (MUST BE 0) 0 = STOP MODE ENABLED 1 = STOP MODE DISABLED* D6 ---0 0 0 0 1 1 1 1 D5 ---0 0 1 1 0 0 1 1 D4 ---0 1 0 1 0 1 0 1 WDT TIMEOUT VALUE -------------------------------DISABLED 65,536 TpC 131,072 TpC 262,144 TpC 524,288 TpC 1,048,576 TpC 2,097,152 TpC 4,194,304 TpC* (XTAL CLOCKS TO TIMEOUT) 1 = WDT ENABLED IN HALT MODE* 0 = WDT DISABLED IN HALT MODE *Designates Default Value after RESET Figure 12. Z8E001 TCTLHI Register for Control of WDT DS001101-Z8X0400 PRELIMINARY 19 Z8E001 Z8Plus OTP Microcontroller ZiLOG Note: The WDT can only be disabled via software if the first instruction out of RESET performs this function. Logic within the Z8E001 detects that it is in the process of executing the first instruction after the part leaves RESET. During the execution of this instruction, the upper five bits of the TCTLHI register can be written. After this first instruction, hardware does not allow the upper five bits of this register to be written. STOP MODE (D3). Coming out of RESET, the Z8E001 STOP Mode is disabled. If an application requires use of STOP Mode, bit D3 must be cleared immediately upon leaving RESET. If bit D3 is set, the STOP instruction executes as a NOP. If bit D3 is cleared, the STOP instruction enters Stop Mode. Whenever the Z8E001 wakes up after having been in STOP Mode, the STOP Mode is again disabled. Bits 2, 1 and 0. These bits are reserved and must be 0. Table 6. WDT Time-Out The TCTLHI bits for control of the WDT are described below: WDT Time Select (D6, D5, D4). Bits 6, 5, and 4 determine the time-out period. Table 6 indicates the range of timeout values that can be obtained. The default values of D6, D5, and D4 are all 1, thus setting the WDT to its maximum timeout period when coming out of RESET. WDT During HALT (D7). This bit determines whether or not the WDT is active during HALT Mode. A 1 indicates active during HALT. A 0 prevents the WDT from resetting the part while halted.Coming out of reset, the WDT is enabled during HALT Mode. D6 D5 D4 Crystal Clocks* to Timeout Time-Out Using a 10 MHZ Crystal 0 0 0 Disabled Disabled 0 0 1 65,536 TpC 6.55 ms 0 1 0 131,072 TpC 13.11 ms 0 1 1 262,144 TpC 26.21 ms 1 0 0 524,288 TpC 52.43 ms 1 0 1 1,048,576 TpC 104.86 ms 1 1 0 2,097,152 TpC 209.72 ms 1 1 1 4,194,304 TpC 419.43 ms Note: *TpC=XTAL clock cycle. The default on reset is D6=D5=D4=1. POWER-DOWN MODES In addition to the standard RUN mode, the Z8E001 MCU supports two Power-Down modes to minimize device current consumption. The two modes supported are HALT and STOP. HALT MODE OPERATION The HALT Mode suspends instruction execution and turns off the internal CPU clock. The on-chip oscillator circuit remains active so the internal clock continues to run and is applied to the timers and interrupt logic. The HALT Mode can be exited by servicing an interrupt (either externally or internally) generated. Upon completion of the interrupt service routine, the user program continues from the instruction after the HALT instruction. To enter the HALT Mode, the Z8E001 only requires a HALT instruction. It is NOT necessary to execute a NOP instruction immediately before the HALT instruction. The HALT Mode can also be exited via a RESET activation or a Watch-Dog Timer (WDT) timeout. In these cases, program execution restarts at the reset restart address 0020H. 7F 20 HALT ; enter HALT Mode PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG STOP MODE OPERATION The STOP Mode provides the lowest possible device standby current. This instruction turns off the on-chip oscillator and internal system clock. To enter the STOP Mode, the Z8E001 only requires a STOP instruction. It is NOT necessary to execute a NOP instruction immediately before the STOP instruction. 6F STOP The Z8E001 provides a dedicated STOP-Mode Recovery (SMR) circuit. In this case, a low-level applied to input pin PB0 triggers an SMR. To use this mode, pin PB0 (I/O Port B, bit 0) must be configured as an input before the STOP Mode is entered. The Low level on PB0 must be held for a minimum pulse width TWSM plus any oscillator startup time. Program execution starts at address 20Hex after PB0 is raised back to a high level. ;enter STOP Mode The STOP Mode is exited by any one of the following resets: RESET pin or a STOP-Mode Recovery source. Upon reset generation, the processor always restarts the application program at address 0020H, and the STOP Mode Flag is set. Reading the STOP Mode Flag does not clear it. The user must clear the STOP Mode Flag with software. Notes: Use of the PB0 input for the stop mode recovery does not initialize the control registers. The STOP Mode current (ICC2) is minimized when: * VCC is at the low end of the devices operating range. * Output current sourcing is minimized. * All inputs (digital and analog) are at the Low or High rail voltages. Note: Failure to clear the STOP Mode Flag can result in undefined behavior. CLOCK The Z8E001 MCU derives its timing from on-board clock circuitry connected to pins XTAL1 and XTAL2. The clock circuitry consists of an oscillator, a glitch filter, a divideby-two shaping circuit, a divide-by-four shaping circuit, and a divide-by-eight shaping circuit. Figure 13 illustrates the clock circuitry. The oscillatorOs input is XTAL1 and its output is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock, or an external clock source. XTAL1 XTAL2 Glitch Filter /2 Machine Clock (5 cycles per instruction) /4 Timer Clock /8 WDT Clock Figure 13. Z8E001 Clock Circuit DS001101-Z8X0400 PRELIMINARY 21 Z8E001 Z8Plus OTP Microcontroller ZiLOG OSCILLATOR OPERATION The Z8E001 MCU uses a Pierce oscillator with an internal feedback resistor (Figure 14). The advantages of this circuit are low-cost, large output signal, low-power level in the crystal, stability with respect to VCC and temperature, and low impedances (not disturbed by stray effects). or components except at the Z8E001 device VSS pin. The objective is to prevent differential system ground noise injection into the oscillator (Figure 15). Z8E001 One draw back is the requirement for high gain in the amplifier to compensate for feedback path losses. The oscillator amplifies its own noise at start-up until it settles at the frequency that satisfies the gain/phase requirements (A x B = 1; where A = Vo/Vi is the gain of the amplifier and B = Vi/Vo is the gain of the feedback element). The total phase shift around the loop is forced to zero (360 degrees). VIN must be in phase with itself; therefore, the amplifier/inverter provides a 180-degree phase shift, and the feedback element is forced to provide the other 180-degree phase shift. R1 is a resistive component placed from output to input of the amplifier. The purpose of this feedback is to bias the amplifier in its linear region and provide the start-up transition. Capacitor C2, combined with the amplifier output resistance, provides a small phase shift. It also provides some attenuation of overtones. Capacitor C1, combined with the crystal resistance, provides an additional phase shift. C1 and C2 can affect the start-up time if they increase dramatically in size. As C1 and C2 increase, the start-up time increases until the oscillator reaches a point where it does not start up any more. It is recommended for fast and reliable oscillator start-up (over the manufacturing process range) that the load capacitors be sized as low as possible without resulting in overtone operation. Layout Traces connecting crystal, caps, and the Z8E001 oscillator pins should be as short and wide as possible, to reduce parasitic inductance and resistance. The components (caps, crystal, resistors) should be placed as close as possible to the oscillator pins of the Z8E001. The traces from the oscillator pins of the IC and the ground side of the lead caps should be guarded from all other traces (clock, VCC, address/data lines, system ground) to reduce cross talk and noise injection. Guarding is usually accomplished by keeping other traces and system ground trace planes away from the oscillator circuit, and by placing a Z8E001 device VSS ground ring around the traces/components. The ground side of the oscillator lead caps should be connected to a single trace to the Z8E001 VSS (GND) pin. It should not be shared with any other system ground trace 22 VSS A RI V1 XTAL1 V0 XTAL2 C1 C2 Figure 14. Pierce Oscillator with Internal Feedback Circuit Indications of an Unreliable Design There are two major indicators that are used in working designs to determine their reliability over full lot and temperature variations. They are: Start-up Time. If start-up time is excessive, or varies widely from unit to unit, there is probably a gain problem. To fix the problem, the capacitors C1/C2 require reduction. The amplifier gain is either not adequate at frequency, or the crystal Rs are too large. Output Level. The signal at the amplifier output should swing from ground to VCC to indicate adequate gain in the amplifier. As the oscillator starts up, the signal amplitude grows until clipping occurs. At that point, the loop gain is effectively reduced to unity, and constant oscillation is achieved. A signal of less than 2.5 volts peak-to-peak is an indication that low gain can be a problem. Either C1 or C2 should be made smaller, or a low-resistance crystal should be used. Circuit Board Design Rules The following circuit board design rules are suggested: To prevent induced noise, the crystal and load capacitors should be physically located as close to the Z8E001 as possible. Signal lines should not run parallel to the clock oscillator inputs. In particular, the crystal input circuitry and the internal system clock output should be separated as much as possible. PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG VCC power lines should be separated from the clock oscillator input circuitry. Resistivity between XTAL1 or XTAL2 (and the other pins) should be greater than 10 M. XTAL1 17 C1 Z8E001 XTAL2 16 C2 VSS 15 Clock Generator Circuit Signals A B Z8E001 (Parallel Traces Must Be Avoided) PB0 Signal C X1 XTAL1 17 X2 Z8E001 VSS VCC XTAL2 16 Board Design Example (Top View) Figure 15. Circuit Board Design Rules Crystals and Resonators Crystals and ceramic resonators (Figure 16) should have the following characteristics to ensure proper oscillation: Crystal Cut Mode Crystal Capacitance Load Capacitance Resistance DS001101-Z8X0400 Depending on the operation frequency, the oscillator can require additional capacitors, C1 and C2, as shown in Figure 16 and Figure 17. The capacitance values are dependent on the manufacturerOs crystal specifications. AT (crystal only) Parallel, Fundamental Mode <7pF 10pF < CL < 220 pF, 15 typical 100 ohms max PRELIMINARY 23 Z8E001 Z8Plus OTP Microcontroller ZiLOG OSCILLATOR OPERATION (Continued) tal/ceramic resonator manufacturer. The RD can be increased to decrease the amount of drive from the oscillator output to the crystal. It can also be used as an adjustment to avoid clipping of the oscillator signal to reduce noise. The RF can be used to improve the start-up of the crystal/ceramic resonator. The Z8E001 oscillator already has an internal shunt resistor in parallel to the crystal/ceramic resonator. VSS Z8E001 XTAL1 XTAL2 RF RD XTAL1 C2 C1 Z8E001 VSS Figure 16. Crystal/Ceramic Resonator Oscillator N/C Figure 18. External Clock XTAL1 C1 L XTAL2 Figure 16, Figure 17, and Figure 18 recommend that the load capacitor ground trace connect directly to the VSS (GND) pin of the Z8E001. This requirement assures that no system noise is injected into the Z8E001 clock. This trace should not be shared with any other components except at the VSS pin of the Z8E001. Z8E001 VSS XTAL2 C2 Note: A parallel resonant crystal or resonator data sheet specifies a load capacitor value that is a series combination of C1 and C2, including all parasitics (PCB and holder). Figure 17. LC Clock In most cases, the RD is 0 Ohms and RF is infinite. These specifications are determined and specified by the crys- 24 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG LC OSCILLATOR The Z8E001 oscillator can use a LC network to generate a XTAL clock (Figure 17). The frequency stays stable over VCC and temperature. The oscillation frequency is determined by the equation: Frequency = 1/ CT = 1/C1 + 1/C2 If C1 = C2 1/CT = 2 C1 C1 = 2CT 1 2 (LCT) 1/2 where L is the total inductance including parasitics, and CT is the total series capacitance including parasitics. Simple series capacitance is calculated using the equation at the top of the next column. A sample calculation of capacitance C1 and C2 for 5.83 MHz frequency and inductance value of 27 H is displayed as follows: 5.83 (10^6) = 1 2 [2.7 (10-6) CT] CT = 27.6 pF Thus C1 = 55.2 pF and C2 = 55.2 pF. TIMERS For the Z8E001, 8-bit timers (T0 and T1) are available to function as a pair of independent 8-bit standard timers, or they can be cascaded to function as a 16-bit PWM timer. In addition to T0 and T1, extra 8-bit timers (T2 and T3) are provided, but they can only operate in cascade to function as a 16-bit standard timer. OSC/8 Enable TCTLL0 (D5) IRQ5 (T23) 16-bit Down Counter T3VAL T3AR T2AR T2VAL Internal Data Bus Figure 19. Z8E001 16-Bit Standard Timer DS001101-Z8X0400 PRELIMINARY 25 Z8E001 Z8Plus OTP Microcontroller ZiLOG TIMERS (Continued) 8-bit Standard Timer Internal Data Bus T1ARHI T1ARLO T1VAL (Not used in this mode) 8-bit Down Counter IRQ2 (T1) Enable TCTLL0 (D2-D0) 8-bit Down Counter (Not used in this mode) 8-bit Standard Timer OSC/8 T0ARHI T0ARLO T0VAL Enable TCTLL0 (D2-D0) IRQ2 (T0) OSC/8 Internal Data Bus Figure 20. 8-Bit Standard Timers Internal Data Bus T1ARHI T1ARLO T1VAL T1 High Side PWM Low Side T0 16-bit Down Counter Edge Detect Logic IRQ0 IRQ2 T OUT OSC/8 T0ARHI T0ARLO T0VAL Internal Data Bus Figure 21. 16-bit Standard PWM Timer 26 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG 0C0 D7 TCTLLO D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 ---- ---- --0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 TIMER STATUS T0 T1 T01 ------------ ------------ --------------DISAB. DISAB. ENAB. DISAB. DISAB. ENAB. ENAB. ENAB. ENAB.(*) ENAB.(*) DISAB. DISAB. ENAB.(*) ENAB.(*) ENAB.(*) (NOTE: (*) INDICATES AUTO-RELOAD IS ACTIVE.) RESERVED (MUST BE 0) 1 = T23 16-BIT TIMER ENABLED WITH AUTO-RELOAD ACTIVE 0 = T2 AND T3 TIMERS DISABLED RESERVED (MUST BE 0) Note: Timer T01 is a 16-bit PWM Timer formed by cascading 8-bit timers T1 (MSB) and T0 (LSB). T23 is a standard 16-bit timer formed by cascading 8-bit timers T3 (MSB) and T2 (LSB). Figure 22. TCTLLO Register Each 8-bit timer is provided a pair of registers, which are both readable and writable. One of the registers is defined to contain the auto-initialization value for the timer, while the second register contains the current value for the timer. When a timer is enabled, the timer decrements whatever value is currently held in its count register, and then continues decrementing until it reaches 0. At this time, an interrupt is generated and the contents of the auto-initialization register optionally copy into the count value register. If auto-initialization is not enabled, the timer stops counting upon reaching 0, and control logic clears the appropriate control register bit to disable the timer. This operation is referred to as Osingle-shotO. If auto-initialization is enabled, the timer continues counting from the initialization value. Software should not attempt to use registers that are defined as having timer functionality. Software is allowed to write to any register at any time, but care should be taken if timer registers are updated while the timer is enabled. If software updates the count value while the timer is in operation, the timer continues counting based upon the software-updated value. DS001101-Z8X0400 Note: Strange behavior can result if the software update occurred at exactly the point that the timer was reaching 0 to trigger an interrupt and/or reload. Similarly, if software updates the initialization value register while the timer is active, the next time that the timer reaches 0, it initializes using the updated value. Note: Strange behavior could result if the initialization value register is being written while the timer is in the process of being initialized. Whether initialization is done with the new or old value is a function of the exact timing of the write operation. In all cases, the Z8E001 prioritizes the software write above that of a decrementer writeback; however, when hardware clears a control register bit for a timer that is configured for single-shot operation, the clearing of the control bit overrides a software write. Reading either register can be done PRELIMINARY 27 Z8E001 Z8Plus OTP Microcontroller ZiLOG TIMERS (Continued) at any time, and will have no effect on the functionality of the timer. If a timer pair is defined to operate as a single 16-bit entity, the entire 16-bit value must reach 0 before an interrupt is generated. In this case, a single interrupt is generated, and the interrupt corresponds to the even 8-bit timer. Example: Timers T2 and T3 are cascaded to form a single 16bit timer, so the interrupt for the combined timer is defined to be that of timer T2 rather than T3. When a timer pair is specified to act as a single 16-bit timer, the even timer registers in the pair (timer T0 or T2) is defined to hold the timerOs least significant byte. In contrast, the odd timer in the pair holds the timerOs most significant byte. In parallel with the posting of the interrupt request, the interrupting timerOs count value is initialized by copying the contents of the auto-initialization value register to the count value register. It should be noted that any time that a timer pair is defined to act as a single 16-bit timer, that the autoreload function is performed automatically. All 16-bit timers continue counting while their interrupt requests are active, and each operates in a free-running manner. If interrupts are disabled for a long period of time, it is possible for the timer to decrement to 0 again before its initial interrupt has been responded to. This condition is termed a degenerate case, and hardware is not required to detect it. When the timer control register is written, all timers that are enabled by the write begins counting using the value that is held in the count register. In this case, an auto-initialization is not performed. All timers can receive an internal clock source only. Each timer that is enabled is updated every 8th XTAL clock cycle. If T0 and T1 are defined to work independently, then each works as an 8-bit timer with a single auto-initialization register (T0ARLO for T0, and T1ARLO for T1). Each timer asserts its predefined interrupt when it times out, optionally performing the auto-initialization function. If T0 and T1 are cascaded to form a single 16-bit timer, then the single 16bit timer is capable of performing as a Pulse-Width Modulator (PWM). This timer is referred to as T01 to distinguish it as having special functionality that is not available when T0 and T1 act independently. When T01 is enabled, it can use a pair of 16-bit auto-initialization registers. In this mode, one 16-bit auto-initialization value is composed of the concatenation of T1ARLO and T0ARLO. The second auto-initialization value is composed of the concatenation of T1ARHI and T0ARHI. When 28 T01 times out, it alternately initializes its count value using the LO auto-init pair, followed by the HI auto-init pair. This functionality corresponds to a PWM, where the T1 interrupt defines the end of the HI section of the waveform, and the T0 interrupt marks the end of the LO portion of the PWM waveform. To use the cascaded timers as a PWM, one must initialize the T0 and T1 count registers to work in conjunction with the port pin. The user should initialize the T0 and T1 count registers to the PWM_HI auto-init value to obtain the required PWM behavior. The PWM is arbitrarily defined to use the LO autoreload registers first, implying that it had just timed out after beginning in the HI portion of the PWM waveform. As such, the PWM is defined to assert the T1 interrupt after the first timeout interval. After the auto-initialization has been completed, decrementing occurs for the number of counts defined by the PWM_LO registers. When decrementing again reaches 0, the T0 interrupt is asserted; and auto-init using the PWM_HI registers occurs. Decrementing occurs for the number of counts defined by the PWM_HI registers until reaching 0. From there, the T1 interrupt is asserted, and the cycle begins again. The internal timers can be used to trigger external events by toggling the PB1 output when generating an interrupt. This functionality can only be achieved in conjunction with the port unit defining the appropriate pin as an output signal with the timer output special function enabled. In this mode, the appropriate port output is toggled when the timer count reaches 0, and continues toggling each time that the timer times out. TOUT Mode The PortB special function register PTBSFR (0D7H) (Figure 23) is used in conjunction with the Port B directional control register PTBDIR (0D6) (Figure 24) to configure PB1 for TOUT operation for timer0. In order for TOUT to function, PB1 must be defined as an output line by setting PTBDIR bit 1 to 1. Configured in this way, PB1 has the capability of being a clock output for timer0, toggling the PB1 output pin on each timer0 timeout. At end-of-count, the interrupt request line IRQ0, clocks a toggle flip-flop. The output of this flip-flop drives the TOUT line, PB1. In all cases, when timer0 reaches its end-of-count, TOUT toggles to its opposite state (Figure 25). If, for example, timer0 is in Continuous Counting Mode, TOUT has a 50 percent duty cycle output. This duty cycle can easily be controlled by varying the initial values after each endof-count. PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG 0D7 PTBSFR D7 D6 D5 D4 D3 D2 D1 D0 1 = ENABLE BIT 0 AS SMR INPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE BIT 1 AS TIMER0 OUTPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE BIT 2 AS INT1 INPUT 0 = NO SPECIAL FUNCTIONALITY D4 D3 COMPAR. INTERRUPTS --- --- -------------- ------------------0 0 DISABLED DISABLED 0 1 ENABLED DISABLED 1 0 DISABLED ENABLED 1 1 ENABLED ENABLED BIT 3: COMP. REF. INPUT BIT 4: COMP. SIGNAL INPUT/ INT0/INT2 RESERVED (MUST BE 0) Figure 23. PortB Special Function Register (Tout Operation) 0D6 D7 PTBDIR D6 D5 D4 D3 D2 D1 D0 1 = BIT N SET AS OUTPUT 0 = BIT N SET AS INPUT RESERVED (MUST BE 0) Figure 24. Port B Directional Control Register IRQ0 (T0 End-of-Count) /2 PB1 TOUT Figure 25. Timer T0 Output Through TOUT DS001101-Z8X0400 PRELIMINARY 29 Z8E001 Z8Plus OTP Microcontroller ZiLOG RESET CONDITIONS After a hardware RESET, the timers are disabled. See Table 4 for timer control, value, and auto-initialization register status after RESET. I/O PORTS The Z8E001 has 13 lines dedicated to input and output. These lines are grouped into two ports known as Port A and Port B. Port A is an 8-bit port, bit programmable as either inputs or outputs. Port B can be programmed to provide standard input/output or the following special functions: timer0 output, comparator input, SMR input, and external interrupt inputs. All ports have push-pull CMOS outputs. In addition, the outputs of Port A on a bit-wise basis can be configured for open-drain operation.The ports operate on a bit-wise basis. As such, the register values for/at a given bit position only affect the bit in question. Table 7. Z8E001 I/O Ports Registers Register Address Identifier Port B Special Function Port B Directional Control Port B Output Value Port B Input Value Port A Special Function Port A Directional Control Port A Output Value Port A Input Value OD7H 0D6H 0D5H 0D4H 0D3H 0D2H 0D1H 0D0H PTBSFR PTBDIR PTBOUT PTBIN PTASFR PTADIR PTAOUT PTAIN Each port is defined by a set of four control registers. See Figure 27. Input and Output Value Registers Directional Control and Special Function Registers Each port has an Output Value Register and a pF Input Value Register. For port bits configured as an input by means of the Directional Control Register, the Input Value Register for that bit position contains the current synchronized input value. Each port on the Z8E001 has a dedicated Directional Control Register that determines (on a bit-wise basis) whether a given port bit operates as either an input or an output. Each port on the Z8E001 has a Special Function Register that, in conjunction with the Directional Control Register, implements (on a bit-wise basis), any special functionality that can be defined for each particular port bit. For port bits configured as an output by means of the Directional Control Register, the value held in the corresponding bit of the Output Value Register is driven directly onto the output pin. The opposite register bit for a given pin (the output register bit for an input pin and the input register bit for an output pin) holds their previous value. These bits are not changed and donOt have any effect on the hardware. READ/WRITE OPERATIONS The control for each port is done on a bit-wise basis. All bits are capable of operating as inputs or outputs, depending upon the setting of the portOs Directional Control Register. If configured as an input, each bit is provided a Schmitttrigger. The output of the Schmitt-trigger is latched twice to perform a synchronization function, and the output of the synchronizer is fed to the port input register, which can be read by software. A write to a port input register has the effect of updating the contents of the input register, but subsequent reads do not necessarily return the same value that was written. If the bit in question is defined as an input, the input register for 30 that bit position contains the current synchronized input value. Thus, writes to that bit position is overwritten on the next clock cycle with the newly sampled input data. However, if the particular port bit is programmed as an output, the input register for that bit retains the software-updated value. The port bits that are programmed as outputs do not sample the value being driven out. Any bit in either port can be defined as an output by setting the appropriate bit in the directional control register. If such is the case, the value held in the appropriate bit of the port output register is driven directly onto the output pin. PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG Note: The preceding result does not necessarily reflect the actual output value. If an external error is holding an output pin either High or Low against the output driver, the software read returns the required value, not the actual state caused by the contention. When a bit is defined as an output, the Schmitt-trigger on the input is disabled to save power. Updates to the output register takes effect based upon the timing of the internal instruction pipeline, but is referenced to the rising edge of the clock. The output register can be read at any time, and returns the current output value that is held. No restrictions are placed on the timing of reads and/or writes to any of the port registers with respect to the others; however, care should be taken when updating the directional control and special function registers. When updating a Directional Control Register, the Special Function Register should first be disabled. If this precaution is not taken, spurious events could take place as a result of the change in port I/O status. This precaution is especially important when defining changes in Port B, as the spurious event referred to above could be one or more interrupts. Clearing of the SFR register should be the first step in configuring the port, while setting the SFR register should be the final step in the port configuration process. To ensure deterministic behavior, the SFR register should not be written until the pins are being driven appropriately, and all initialization has been completed. PORT A Port A is a general-purpose port. Figure 26 features a block diagram of Port A. Each of its lines can be independently programmed as input or output via the Port A Directional Control Register (PTADIR at 0D2H) as seen in Figure 27. A bit set to a 1 in PTADIR configures the corresponding bit in Port A as an output, while a bit cleared to 0 configures the corresponding bit in Port A as an input. The input buffers are Schmitt-triggered. Bits programmed as outputs can be individually programmed as either pushpull or open drain by setting the corresponding bit in the Special Function Register (PTASFR, Figure 27). Register 0D2H PTADIR Register D7 D6 D5 D4 D3 D2 D1 D0 1 = Output 0 = Input Figure 26. Port A Directional Control Register PTASFR.bitN N = 0...7 PTADIR.bitN N = 0...7 PA0PA7 PIN PTAOUT.bitN N = 0...7 PTAIN.bitN N = 0...7 Figure 27. Port A Configuration with Open-Drain Capability and Schmitt-Trigger DS001101-Z8X0400 PRELIMINARY 31 Z8E001 Z8Plus OTP Microcontroller ZiLOG PORT A REGISTER DIAGRAMS Register 0D0H D7 D6 PTAIN D5 D4 D3 D2 D1 D0 PORT A BIT N CURRENT INPUT VALUE (only updated for pins in input mode) Figure 28. Port A Input Value Register Register 0D1H D7 D6 PTAOUT D5 D4 D3 D2 D1 D0 PORT A BIT N CURRENT OUTPUT VALUE Figure 29. Port A Output Value Register 32 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG Register 0D2H D7 D6 PTADIR D5 D4 D3 D2 D1 D0 1 = BIT N SET AS AN OUTPUT 0 = BIT N SET AS AN INPUT Figure 30. Port A Directional Control Register Register 0D3H D7 D6 PTASFR D5 D4 D3 D2 D1 D0 1 = BIT N IN OPEN-DRAIN MODE 0 = BIT N IN PUSH-PULL MODE Figure 31. Port A Special Function Register DS001101-Z8X0400 PRELIMINARY 33 Z8E001 Z8Plus OTP Microcontroller ZiLOG PORT B Port B Description Table 8. Port B Special Functions Port B is a 5-bit (bidirectional), CMOS-compatible I/O port. These five I/O lines can be configured under software control to be an input or output, independently. Input buffers are Schmitt-triggered. See Figure 33 through Figure 36 for diagrams of all five Port B pins. Port Pin PB0 In addition to standard input/output capability on all five pins of Port B, each pin provides special functionality as shown in the following table: PB1 PB2 PB3 Special functionality is invoked via the Port B Special Function Register. See Figure 32 for the arrangement and control conventions of this register. PB4 Register 0D7H D7 D6 Input Special Function Stop Mode Recovery Input None IRQ3 Comparator Reference Input Comparator Signal Input/IRQ1/IRQ4 Output Special Function None Timer0 Output None None None PTBSFR D5 D4 D3 D2 D1 D0 1 = ENABLE PB0 AS SMR INPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE PB1 AS TIMER0 OUTPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE PB2 AS IRQ3 INPUT 0 = NO SPECIAL FUNCTIONALITY 1 = Analog Comparator on PB3 & PB4 0 = Digital Inputs on PB3 & PB4 1 = PB4 Interrupts Enabled 0 = PB4 Interrupts Disabled RESERVED (MUST BE 0) Figure 32. Port B Special Function Register 34 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG PORT BNPIN 0 CONFIGURATION PTBDIR.bit0 PTBIN.bit0 SMR RESET PTBSFR.bit0 SMR Flag PTBDIR.bit0 PB0 PIN PTBOUT.bit0 Figure 33. Port B Pin 0 Diagram DS001101-Z8X0400 PRELIMINARY 35 Z8E001 Z8Plus OTP Microcontroller ZiLOG PORT BNPIN 1 CONFIGURATION PTBDIR.bit1 PTBIN.bit1 PTBDIR.bit1 PB1 PIN PTBOUT.bit1 TIMER0 Output M U X PTBSFR.bit1 Figure 34. Port B Pin 1 Diagram 36 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG PORT BNPIN 2 CONFIGURATION PTBDIR.bit2 PTBIN.bit2 IRQ3 EDGE DETECT LOGIC PTBSFR.bit2 PTBDIR.bit2 PB2 PIN PTBOUT.bit2 Figure 35. Port B Pin 2 Diagram DS001101-Z8X0400 PRELIMINARY 37 Z8E001 Z8Plus OTP Microcontroller ZiLOG PORT BNPINS 3 AND 4 CONFIGURATION PTBDIR.bit4 PTBIN.bit4 IRQ1 IRQ4 EDGE DETECT LOGIC M U X PTBSFR.bit4 + - PTBSFR.bit3 AN IN REF PTBDIR.bit3 PTBIN.bit3 PTBDIR.bit3 PB3 PIN PTBOUT.bit3 PTBDIR.bit4 PB4 PIN PTBOUT.bit4 Figure 36. Port B Pins 3 and 4 Diagram 38 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG PORT B CONTROL REGISTERS Register 0D4H D7 D6 PTBIN D5 D4 D3 D2 D1 D0 PORT B BIT N CURRENT INPUT VALUE (only updated for pins in input mode) RESERVED (MUST BE 0) Figure 37. Port B Input Value Register Register 0D5H D7 D6 PTBOUT D5 D4 D3 D2 D1 D0 PORT B BIT N CURRENT OUTPUT VALUE RESERVED (MUST BE 0) Figure 38. Port B Output Value Register Register 0D6H D7 D6 PTBDIR D5 D4 D3 D2 D1 D0 1 = BIT N SET AS OUTPUT 0 = BIT N SET AS INPUT RESERVED (MUST BE 0) Figure 39. Port B Directional Control Register DS001101-Z8X0400 PRELIMINARY 39 Z8E001 Z8Plus OTP Microcontroller ZiLOG PORT B CONTROL REGISTERS (Continued) Register 0D7H D7 D6 PTBSFR D5 D4 D3 D2 D1 D0 1 = ENABLE PB0 AS SMR INPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE PB1 AS TIMER0 OUTPUT 0 = NO SPECIAL FUNCTIONALITY 1 = ENABLE PB2 AS IRQ3 INPUT 0 = NO SPECIAL FUNCTIONALITY 1 = Analog Comparator on PB3 & PB4 0 = Digital Inputs on PB3 & PB4 1 = PB4 Interrupts Enabled 0 = PB4 Interrupts Disabled RESERVED (MUST BE 0) Figure 40. Port B Special Function Register 40 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG I/O PORT RESET CONDITIONS Full Reset Port A and Port B output value registers are not affected by RESET. On RESET, the Port A and Port B directional control registers is cleared to all zeros, which defines all pins in both ports as inputs. On RESET, the directional control registers redefine all pins as inputs, and the Port A and Port B input value registers overwrites the previously held data with the current sample of the input pins. On RESET, the Port A and Port B special function registers is cleared to all zeros, which deactivates all port special functions. Note: The SMR and WDT timeout events are NOT full device resets. The port control registers are not affected by either of these events. ANALOG COMPARATOR The Z8E001 includes one on-chip analog comparator. Pin PB4 has a comparator front end. The comparator reference voltage is on pin PB3. Comparator Description The on-chip comparator can process an analog signal on PB4 with reference to the voltage on PB3. The analog function is enabled by programming the Port B Special Function Register bits 3 and 4. When the analog comparator function is enabled, bit 4 of the input register is defined as holding the synchronized output of the comparator, while bit 3 retains a synchronized sample of the reference input. If the interrupts for PB4 are enabled when the comparator special function is selected, the output of the comparator generates interrupts. COMPARATOR OPERATION The comparator output reflects the relationship between the analog input to the reference input. If the voltage on the analog input is higher than the voltage on the reference input, then the comparator output is at a High state. If the voltage on the analog input is lower than the voltage on the reference input, then the analog output will be at a Low state. VOFFSET The absolute value of the voltage between the positive input and the reference input required to make the comparator output voltage switch is the input offset voltage (VOFFSET). IIO For the CMOS voltage comparator input, the input offset current (IIO) is the leakage current of the CMOS input gate. Comparator Definitions VICR The usable voltage range for the positive input and reference input is called the common mode voltage range (VICR). Note: The comparator is not guaranteed to work if the input is outside of the VICR range. HALT Mode The analog comparator is functional during HALT Mode. If the interrupts are enabled, an interrupt generated by the comparator will cause a return from HALT Mode. STOP Mode The analog comparator is disabled during STOP Mode. The comparator is powered down to prevent it from drawing any current. DS001101-Z8X0400 PRELIMINARY 41 Z8E001 Z8Plus OTP Microcontroller ZiLOG INPUT PROTECTION All I/O pins on the Z8E001 have diode input protection. There is a diode from the I/O pad to VCC and VSS (Figure 41). However, on the Z8E001, the RESET pin has only the input protection diode from pad to VSS (Figure 42). VCC PIN RESET VSS PIN Figure 42. RESET Pin Input Protection The high-side input protection diode was removed on this pin to allow the application of high voltage during the OTP programming mode. VSS Figure 41. I/O Pin Diode Input Protection 42 For better noise immunity in applications that are exposed to system EMI, a clamping diode to VCC from this pin can be required to prevent entering the OTP programming mode or to prevent high voltage from damaging this pin. PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG PACKAGE INFORMATION Figure 43. 18-Pin DIP Package Diagram Figure 44. 18-Pin SOIC Package Diagram DS001101-Z8X0400 PRELIMINARY 43 Z8E001 Z8Plus OTP Microcontroller ZiLOG PACKAGE INFORMATION (Continued) Figure 45. 20-Pin SSOP Package Diagram 44 PRELIMINARY DS001101-Z8X0400 Z8E001 Z8Plus OTP Microcontroller ZiLOG ORDERING INFORMATION Standard Temperature 18-Pin DIP 18-Pin SOIC 20-Pin SSOP Z8E00110SSC Z8E00110HSC Z8E00110PSC Extended Temperature 18-Pin DIP 18-Pin SOIC 20-Pin SSOP Z8E00110PEC Z8E00110SEC Z8E00110HEC For fast results, contact your local ZiLOG sales office for assistance in ordering the part(s) required. Codes Preferred Package Longer Lead Time P = Plastic DIP S = SOIC H = SSOP Preferred Temperature S = 0C to +70C E = 40C to +105C Speed 10 = 10 MHz Environmental C = Plastic Standard Example: Z 8E001 10 P S C is a Z86E001, 10 MHz, DIP, 0 to +70C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number ZiLOG Prefix DS001101-Z8X0400 PRELIMINARY 45 Z8E001 Z8Plus OTP Microcontroller ZiLOG Pre-Characterization Product: The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or non-conformance with some aspects of the document may be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues. Development Projects: Customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems and delays. No production release is authorized or committed until the Customer and ZiLOG have agreed upon a Product Specification for this project. Low Margin: Customer is advised that this product does not meet ZiLOG's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on ZiLOG liability stated on the front and back of the (c)1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. 46 acknowledgement, ZiLOG makes no claim as to quality and reliability under the document. The product remains subject to standard warranty for replacement due to defects in materials and workmanship. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. ZiLOG, Inc. 910 East Hamilton Avenue, Suite 110 Campbell, CA 95008 Telephone (408) 558-8500 FAX 408 558-8300 Internet: http://www.zilog.com PRELIMINARY DS001101-Z8X0400