CPC7582BC - IXYS Corporation - Datasheet.Directory

DS-CPC7582-R3.0 10/4/2002 www.clare.com 1

Features

•Small 16-pin SOIC or micro- leadf r ame package

•MLP package printed-circuit board f ootp rint is 60

percent smaller than the SOI C version, 70 percent

smaller than 4th generation EMR solutions .

•Monolithic IC reliability

•Low matched R ON

•Eliminates the need for zero cross switching

•Fle xible s witch timing to transition from ringing mode

to talk mode.

•Clean, bounce-free switching

•Tertiary protection consisting of integrate d current

limiting, voltage clamping, and thermal shutdown for

SLIC protection

•5 V operation with power consumption < 10 mW

•Intelligent battery monitor

•Latched logic-lev el inputs, no ex ternal drive circuitry

required

•SOIC version is pin compatible with Agere product

Applications

•Central office (CO)

•Digital Loop Carrier (DLC)

•PBX Systems

•Digitally Added Main Line (DAML)

•Hybrid Fiber Coax (HFC)

•Fiber in the Loop (FITL)

•P air Gain System

•Channel Banks

Description

The CPC7582 is a monolithic solid-state switch in a

16-pin SOIC or MLP surface-mount pac kage. It

provides the necessary functions to replace two

2-F orm-C electro-mechanical relays on traditional

analog and integrated voice and data (IVD) line cards

f oun d in Cent ral Office, Access , and PBX equipment.

The de vice contains solid st ate switches for tip and

ring line break, ringing injection/ringing return and test

access. The CPC7582 requires only a +5V supply and

off ers break- before-make or mak e-before-break

s witch oper ation using simple logic-lev el input control.

The CPC7582xC logic states differ from the

CPC7582xA/B. See “Functional Description” on

page 9 f or more information. The CPC7582xC also

has a higher trigger and hold current f or the protect ion

SCR. Specify CPC7582Bx for SOIC or specify

CPC7582Mx for MLP package shipped in tubes. Add

-TR to the part number for tape and reel packaging.

Ordering Information

Figure 1. CPC7582 Bloc k Diagram

Part Number Description

CPC7582xA 6-pole LCAS with protection SCR

CPC7582xB 6-pole LCAS without protection SCR

CPC7582xC 6-pole LCAS with protection SCR and added

logic state

CPC7582

TLINE

RLINE

TBAT

VDD

RBAT

DGND

VBAT

FGND

VREF INACCESS

INRINGING

TSD

LATCH

78161

Switch

Control

Logic

SCR and

Trip Circuit

(CPC7582xB/C)

Secondary

Protection

+5 Vdc

Tip

Ring

SLIC

XSW5

SW6

SW2

SW4

TTEST

VBAT

RINGING

300

(min.)

Ω

RTEST

TRING

SW3

SW1

CPC7582

Line Card Access Switch

CPC7582

2 www.clare.com R3.0 10/4/2002

1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Absolute Maximum Ratings (at 25° C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Electrical Characteristics, TA = -40° C to +85° C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4.3 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4.4 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4.5 Test Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.5 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.6 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.7 CPC7582xA/B Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.8 CPC7582xC Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1 CPC7582xA/B Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.2 CPC7582xC Logic States: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 Make-Before-Break Operation - All Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.2 Make-Before-Break Operation for All Versions (Ringing to Talk Transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.3 Break-Before-Make Operation - CPC7582xA/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.4 Break-Before-Make Operation CPC7582xA/B (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.5 Break-Before-Make Operation - All Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.6 Break-Before-Make Operation for all Version (Ringing to Talk Transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 TSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.6 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.7 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.8 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.8.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.8.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.9 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.10 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CPC7582

Rev. 3.0 10/4/2002 www.clare.com 3

1. Specifications

1.1 Package Pinout 1.2 Pinout

CPC7582

116

215

314

413

512

611

710

TBAT

FGND

TLINE

TRINGING

TTEST

VDD

DGND

VBAT

RBAT

RLINE

RRINGING

RTEST

LATCH

INRINGING

INTEST

Pin Name Description

1FGND Fault ground

2TBAT Connect to tip on SLIC side

3TLINE Connect to tip on line side

4TRINGING Connect to ringing generator return

5TTEST Connect to test bus tip lead

6VDD +5 V supply

7TSD

Temperature shutdown pin. Bi-directional

I/O with internal pullup to VDD. Output

function indicates status of thermal

shutdown circuitry. Input function can be

used to set the ‘all off’ mode using an

open-drain type output.

8DGND Digital ground

9INTEST Logic-level switch control input

10 INRINGING Logic-level switch control input

11 LATCH Data latch control, active high, transparent

low

12 RTEST Connect to test bus ring lead

13 RRINGING

Connect to ringing generator current

limiting resistor

14 RLINE Connect to ring on the line side

15 RBAT Connect to ring on the SLIC side

16 VBAT

Battery voltage supply. Must be capable of

sourcing the trigger current for proper

operation of the protection SCR.

CPC7582

4 www.clare.com Rev. 3.0 10/4/2002

1.3 Absolute Maximum Ratings (at 25° C)

1.4 Electrical Characteristics, T A = -40° C to +85° C

Unless otherwise specified, minimum and maxim um

v alu es ar e production testing r equir ements. Typical

v alues are char acteristic of the device and are the

result of engineering evaluations. Typical v alues are

provided for information purposes only and are not

part of the testing requirements .

Absolute maximum ratings are stress ratings. Stresses in

excess of these ratings can cause permanent damage to

the device. Functional operation of the device at these or

any other conditions beyond those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to the absolute maximum r a tin gs

for an extended period may degrade the device and affect

its reliability.

1.4.1 Power Supply Specifications

1.4.2 Break Switches, SW1 and SW2

Parameter Minimum Maximum Unit

Operating temperature -40 +110 °C

Storage temperature -40 +150 °C

Operating relative humidity 5 95 %

Pin soldering temperature

(10 seconds max) - +220 °C

+5 V power supply (VDD)-0.3 7 V

Battery Supply - -85 V

Logic input voltage -0.3 VDD + 0.3 V

Logic input to switch output

isolation -330V

Switch open contact

isolation (SW1, SW2, SW3,

SW5, SW6)

-330V

Switch Open Contact

Isolation (SW4)* -480V

*Ringing supply side of switch limited to ±210 V with respect to ground

Supply Minimum Typical Maximum Unit

VDD +4.5 +5.0 +5.5 V

VBAT

1-19 - -72 V

1VBAT is used only for internal protection circuitry. If VBAT rises above

-10 V, the device will enter the all-off state and will remain in the all-off

state until the battery drops below -15 V.

ESD Rating (Human Body Model)

1000 V

Parameter Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C VSW (differential) = -320 V to GND

VSW (differential) = +260 V to -60 V

ISW -

0.1

1µA+85° C

VSW (differential) = -330 V to GND

VSW (differential) = +270 V to -60 V 0.3

-40° C

VSW (differential) = -310 V to GND

VSW (differential) = +250 V to -60 V 0.1

RON

+25° C ISW = ±10 mA, ±40 mA,

RBAT and TBAT = -2 V RON

14.5 -

Ω

+85° C 20.5 28

-40° C 10.5 -

RON match

Per on-resistance test condition of

SW1, SW2.

Magnitude RON SW1 - RONSW2

∆ RON 0.15 0.8

CPC7582

Rev. 3.0 10/4/2002 www.clare.com 5

1.4.3 Ringing Return Switch, SW3

DC current limit

+25° C

VSW (on) = ±10 V

ISW

- 300 -

mA+85° C 80 160 -

-40° C - 400 425

Dynamic current limit

(t = <0.5 µs)

Break switches on, all other switches

off, apply ±1 kV 10/1000 µs pulse, with

appropriate protection in place.

-2.5- A

Logic input to switch output isolation

+25° C VSW (TLINE, RLINE) = ±320 V, logic

inputs = gnd

ISW -

0.1

1µA+85° C VSW (TLINE, RLINE) = ±330 V, logic

inputs = gnd 0.3

-40° C VSW (TLINE, RLINE) = ±310 V, logic

inputs = gnd 0.1

dv/dt sensitivity - - 200 - V/µs

Parameter Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C VSW (differential) = -320 V to GND

VSW (differential) = +260 V to -60 V

ISW -

0.1

1µA+85° C VSW (differential) = -330 V to GND

VSW (differential) = +270 V to -60 V 0.3

-40° C VSW (differential) = -310 V to GND

VSW (differential) = +250 V to -60 V 0.1

RON

+25° C

ISW (on) = ±0 mA, ±10 mA RON -

60 -

Ω+85° C 85 100

-40° C 45 -

DC current limit

+25° C

VSW (on) = ±10 V

ISW

- 135

mA+85° C 70 85

-40° C

210

Dynamic current limit

(t = <0.5 µs)

Ringing switches on, all other switches

off, apply ±1 kV 10/1000 µs pulse, with

appropriate protection in place.

2.5 A

Logic input to switch output isolation

+25° C VSW (TRINGING, TLINE) = ±320 V, logic

inputs = gnd

ISW -

0.1

1µA+85° C VSW (TRINGING, TLINE) = ±330 V, logic

inputs = gnd 0.3

-40° C VSW (TRINGING, TLINE) = ±310 V, logic

inputs = gnd 0.1

dv/dt sensitivity - - 200 - V/µs

Parameter Conditions Symbol Minimum Typical Maximum Unit

CPC7582

6 www.clare.com Rev. 3.0 10/4/2002

1.4.4 Ringing Switch, SW4

1.4.5 Test Switches, SW5 and SW6

Parameter Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C VSW (differential) = -255 V to +210 V

VSW (differential) = +255 V to -210 V

ISW

0.05

1µA+85° C VSW (differential) = -270 V to +210 V

VSW (differential) = +270 V to -210 V 0.1

-40° C VSW (differential) = -245 V to +210 V

VSW (differential) = +245 V to -210 V 0.05

On Voltage ISW (on) = ± 1 mA -1.53V

Ringing generator

current to ground during

ringing

VDD = 5 V, inputs set for ringing mode IRINGING 0.1 0.25 mA

Surge current*

Ringing switches on, all other switches

off, apply ±1 kV 10/1000 µs pulse, with

appropriate protection in place.

--2A

On steady-state current* Inputs set for ringing mode ISW - 150 mA

Release current - IRINGING 300 - µA

RON ISW (on) = ±70 mA, ±80 mA RON 10 15 Ω

Logic input to switch output isolation

+25° C VSW (RRINGING, RLINE) = ±320 V, logic

inputs = gnd

ISW -

0.1

1µA+85° C VSW (RRINGING, RLINE) = ±330 V, logic

inputs = gnd 0.3

-40° C VSW (RRINGING, RLINE) = ±310 V, logic

inputs = gnd 0.1

dv/dt sensitivity - - 200 - V/µs

*Secondary protection and ringing source current limiting must prevent exceeding this parameter.

Parameter Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C

VSW (differential) = -320 V to GND

VSW (differential) = +260 V to -60 V

ISW -

0.1

1µA+85° C VSW (differential) = -330 V to GND

VSW (differential) = +270 V to -60 V 0.3

-40° C VSW (differential) = -310 V to GND

VSW (differential) = +250 V to -60 V 0.1

CPC7582

Rev. 3.0 10/4/2002 www.clare.com 7

1.5 Additional Electrical Characteristics

RON

+25° C ISW(ON) = ±10 mA, ±40 mA,

TBAT = -2 V RON -

38 -

Ω+85° C 46 70

-40° C 28 -

DC current limit

+25° C

VSW (on) = ±10 V

ISW

- 175 -

mA+85° C 80 110 -

-40° C - 210 250

Dynamic current limit

(t = <0.5 µs)

Test switches on, all other switches off,

apply ±1 kV at 10/1000 µs pulse, with

appropriate protection in place.

-2.5- A

Logic input to switch output isolation

+25° C VSW (TTEST

, TLINE) = ±320 V,

logic inputs = gnd

ISW -

0.1

1µA+85° C VSW (TTEST

, TLINE) = ±330 V,

logic inputs = gnd 0.3

-40° C VSW (TTEST

, TLINE) = ±310 V,

logic inputs = gnd 0.1

Parameter Conditions Symbol Minimum Typical Maximum Unit

Digital input characteristics

Input low voltage - VIL --1.5

Input high voltage - VIH 3.5 - -

Input leakage current

(high) VDD = 5.5 V, VBAT = -75 V, VIH = 5 V IIH -0.11µA

Input leakage current

(low) VDD = 5.5 V, VBAT = -75 V, VIL = 0 V IIL -0.11

Power requirements

Power consumption in

talk and all-off states VDD = 5 V, VBAT = -48 V, measure IDD

and IBAT

-5.510

Power consumption in

all other states 6.5 10

VDD current in talk and

all-off states VDD = 5 V, VBAT = -48 V

IDD -1.12.0

VDD current in all other

states

IDD -1.32.0

VBAT current in any

state VDD = 5 V, VBAT = -48 V IBAT -0.110µA

Temperature Shutdown Requirements (temperature shutdown flag is active low)

Shutdown activation

temperature - - 110 125 150 °C

Shutdown circuit

hysteresis --10-25°C

CPC7582

8 www.clare.com Rev. 3.0 10/4/2002

1.6 Protection Circuitry Electrical Specifi cations

1.7 CPC7582xA/B Truth Table

Parameter Conditions Symbol Minimum Typical Maximum Unit

Parameters Related to the Diodes in the Diode Bridge

Voltage drop at

continuous current

(50/60 Hz)

Apply ± dc current limit of break

switches

Forward

Voltage -2.13

Voltage drop at surge

current

Apply ± dynamic current limit of

break switches

Forward

Voltage -5-

Parameters Related to the Protection SCR

Surge current

-- - *A

Trigger current (+25° C)

ITRIG

-60 (CPC7582xA, xB)

70 (CPC7582xC) -

Trigger current (+85° C) - 35 (CPC7582xA, xB)

40 (CPC7582xC) -

Hold current (+25° C)

IHOLD

-100 (CPC7582xA, xB)

135 (CPC7582xC) -

Hold current (+85° C) 60 (CPC7582xA, xB)

110 (CPC7582xC)

70 (CPC7582xA, xB)

115 (CPC7582xC) -

Gate trigger voltage IGATE = ITRIGGER** VTBAT or

VRBAT

VBAT -4 -VBAT -2 V

Reverse leakage

current VBAT = -48 V IVBAT --1.0µA

On-state voltage

0.5 A, t = 0.5 ms VTBAT or

VRBAT

--3-V

2.0 A, t = 0.5 ms

VTBAT or

VRBAT

--5-V

*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.

**VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate.

State INRINGING INTEST LATCH TSD

Break

Switches

Ringing

Switches

Test

Switches

Ta l k 0 0

01 or

Floating1

On Off Off

Te s t 0 1 O f f O f f On

Ringing 1 0 Off On Off

All Off 1 1 Off Off Off

Latched X X 1 Unchanged

All off XXX

02Off Off Off

1If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally.

2Forcing TSD to ground overrides the logic input pins and forces an all off state.

CPC7582

Rev. 3.0 10/4/2002 www.clare.com 9

1.8 CPC7582xC Truth Table

2. Functional Description

2.1 Introduction

2.1.1 CPC7582xA/B Logic States

•Talk. Break s witches SW1 and SW2 closed, ringing

switches SW3 and SW4 open, and test switches

SW5 and SW6 open.

•Ringing. Break switches SW1 and SW2 open,

ringing swit ches SW3 and SW4 closed, and test

switches SW5 and SW6 open.

•Test. Break switches SW1 and SW2 open, ringing

switches SW3 and SW4 open, and loop test

switches SW5 and SW6 closed.

•All off . Break switches SW1 and SW2 open, ringing

switches SW3 and SW4 open, and test switches

SW5 and SW6 open.

2.1.2 CPC7582xC Logic States:

•Talk. Break s witches SW1 and SW2 closed, ringing

switches SW3 and SW4 open, and test switches

SW5 and SW6 open.

•Ringing. Break switches SW1 and SW2 open,

ringing swit ches SW3 and SW4 closed, and test

switches SW5 and SW6 open.

•Test/Monitor. Break switches SW1 and SW2

closed, ringing switches SW3 and SW4 open , and

test s witches SW5 and SW6 closed.

•Ringing Test. Break switches SW1 and SW2 open,

ringing swit ches SW3 and SW4 closed, and test

switches SW5 and SW6 closed.

•All off . Break switches SW1 and SW2 open, ringing

switches SW3 and SW4 open, and test switches

SW5 and SW6 open.

The CPC7582 offers break-bef ore-make and make-

before-break switching from the ringing st ate t o the

talk state with simple logic- level input control. Solid-

state switch construction means no impulse noise is

generated when s w itching during ring cadence or ring

trip, eliminat in g the need for external zero-cross

s wit ching cir cuitry. State control is via log ic-level input

so no additional driver circu itry is required. The linear

break s witches SW1 a nd SW2 have exceptionally low

RON and excellent matching characteristics. The

ringing switch SW4 has a minimum open contact

breakdown voltage of 480 V. This is sufficiently high,

with proper protection, to prevent breakdown in the

presence of a transient f ault condition ( i.e., passing

the transient on t o t he ringing generator) .

Integrat ed into the CPC7582 is an over voltage

clamping circuit, active current limiting, and a thermal

shutdown mechanism to provide protection to the

SLIC de vice during a faul t condition. Positive and

negative surges are reduced by the current limiting

circuitry and hazardous potentials are diverted to

ground via diodes and, in xA/C parts, an integr ated

SCR. Power-cross potent ials are also reduced by the

current limiting and thermal shutdown circuits .

To protect the CPC7582 from an overvoltage fault

condition, use of a secondary protector is required.

The secondary protector must limit the v oltage seen at

the tip and ring terminals to a le vel below the

maximum breakdown voltage of the switches. To

minimize the stress o n the solid-state cont acts, use of

a foldback or cro wbar type secondary protector is

recommended. With proper selection of the secondary

protector, a line card using the CPC7582BC will meet

all relevant ITU, LSSGR, TIA/EIA and IEC protection

requirements.

The CPC7582 operates from a +5 V supply only. This

gives the device extremely low idle and active power

consumption and allows use wi th virtually any range of

State INRINGING INTEST LATCH TSD

Break

Switches

Ringing

Switches

Test

Switches

Ta l k 0 0

01 or

Floating1

On Off Off

Test/Monitor 0 1 On Off On

Ringing 1 0 Off On Off

Ringing Test 1 1 Off On On

Latched X X 1 Unchanged

All off XXX

02Off Off Off

1If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally.

2Forcing TSD to ground overrides the logic input pins and forces an all off state.

CPC7582

10 www.clare.com Rev. 3.0 10/4/2002

battery voltage. Battery voltage is also used by the

CPC7582 as a reference for the int egrated protection

circuit. In the event of a loss of bat tery volt age, the

CPC7582 enters the all-off state.

2.2 Switch Logic

The CPC7582 prov ides, when switching from the

ringing state to the talk sta te , th e ability t o control the

release timing of the ringing s witche s SW3 and SW4

relativ e t o the sta te of the break switches SW1 and

SW2 using simple logic-le v el inputs . This is ref erred to

as make-before-break or break-before-make

operation. When the break switch contacts (SW1 and

SW2) are closed (or made) before the ringing s witch

contacts (SW3 and SW4) are ope ned (or brok en), this

is ref erred to as mak e-before-break operation. Break-

before-make operat ion occurs when t he ringing

contacts (SW3 and SW4) are opened ( broken) bef ore

the break switch contacts (SW1 and SW2) are closed

(made). With the CPC7582, t he make-bef ore-break

and break-bef ore- mak e oper ations can easily be

selected by applying logic-level inputs to the device.

The logic sequences f or these modes of operation are

given in “Make-Bef ore-Break Operation for All

Versions (Ringing to Talk Transition)” on page 10,

“Break-Before-Make Oper ation CPC7582xA/B

(Ringing to Talk Transition)” on page 11, and “Break-

Bef ore-Mak e Operat ion for all Version (Ringing to Talk

Transition)” on page 11. Logic states and input control

settings are given in “CPC7582xA/B Truth Table” on

page 8 and “CPC7582xC Truth Table” on page 9.

2.2.1 Make-Before-Break Operation - All Versions

To use make-bef ore-break oper ation, change the logic

inputs to the talk state immediately following the

ringing state. Applicat ion of the talk state opens the

ringing return swit ch (SW3) as the break s wit ches

(SW1 and SW2) close . The ringing switch (SW4)

remains open until the next zero-crossing of the

ringing supply current. While in the make-bef ore-break

state, ringing potentials in excess of the CPC7582

protection circuitry trigger le vels will be diverted to

ground.

2.2.2 Make-Before-Break Operation for All Versions (Ringing to Talk Transition)

2.2.3 Break-Before-Make Operation - CPC7582xA/B

Break-before-make oper ation of the CPC7582xA/ B

can be achieved using tw o different techniques.

The first method uses manipulation of the I NRINGING

and INTEST logic inputs as shown in “Break-Before-

Make Oper ation CPC7582xA/ B (Ringing to Talk

Transition)” on page 11.

1. At the end of the ringing state apply the all off

state (0, 0). This releases the ringing return

switch (SW3) while the ringing switch remains

on, waiting for the next zero current event.

2. Hold the all off state for at least one-half of a

ringing cycle to assure that a z ero crossing e v ent

occurs and that the ringing switch (SW4) has

opened.

Break-bef ore-mak e operation occurs when the ringing

s w itch opens before the break switches ( SW1 and

SW2) close.

State INRINGING INTEST LATCH TSD Timing Break

Switches

Ringing

Return

Switch

(SW3)

Ringing

Switch

(SW4)

Test

Switches

Ringing 1 0

0 Floating

-Off

On On Off

Make-

before-

break

SW4 waiting for next zero-current

crossing to turn off. Maximum time is

one-half of the ringing cycle. In this

transition state, current that is limited to

the dc break switch current limit value

will be sourced from the ring node of the

SLIC.

On Off On Off

Talk 0 0 Zero-cross current has occurred On Off Off Off

CPC7582

Rev. 3.0 10/4/2002 www.clare.com 11

2.2.4 Break-Before-Make Operation CPC7582xA/B (Ringing to Talk Transition)

2.2.5 Break-Before-Make Operation - All Versions

The second break-bef ore-make method for the

CPC7582xA/B is also the only method available f or

the CPC7582xC. As shown in “CPC7582xA/B Truth

Table” on page 8 and “CPC7582xC Truth Tab l e” o n

page 9, the bi-directional TSD interf ace disables all of

the CPC7582 switches when pulled to a logic lo w.

Although logically disab led, if the ringing switch (SW4)

is activ e (closed), it will remain closed until the next

current zero crossing event.

As shown in the t able “Break-Bef ore-Make Operation

for all Version (Ringing to Talk Transition)” on

page 11, this operation is similar t o the one shown in

“Break-Before-Make Operat ion - All Versions” on

page 11, except in the method used to select the all off

state, and in when the IN RINGING and INTEST input s

are reconfigured for the talk state .

1. Pull TSD to a logic low to end the ringing state.

This opens the ringing return switch (SW3) and

prevents any other switches from closing.

2. Keep TSD lo w f or at least one-h alf the dur ation of

the ringing cycle period to allow sufficient time f or

a zero cro ssing current e ven t to occur and f or the

circuit to enter the break before make state.

3. During the TSD low period, set the INRINGING and

INTEST inputs to the talk state (0, 0).

4. Release TSD, allowing the internal pull-up to

activate the break switches.

When using TSD as an input, the two recommended

states are 0 (o verrides logic input pins and f orces an

all off state) and float (allo ws switch control via logic

input pins and the thermal shutdown mechanism is

activ e). This requires the use of an open-collector type

buffer.

F orcing TSD t o a logic high disables the thermal

shutdown circuit and is theref ore not recommended as

this could lead to device damage or destruction in the

presence of ex cessiv e tip or ring potentials.

2.2.6 Break-Before-Make Operation for all Version (Ringing to Talk Transition)

State INRINGING INTEST LATCH TSD Timing Break

Switches

Ringing

Return

Switch

(SW3)

Ringing

Switch

(SW4)

Test

Switches

Ringing 1 0

0 Floating

-Off

On On Off

All-Off 1 1

Hold this state for at least one-half of the

ringing cycle. SW4 waiting for zero

current to turn off.

Off Off On Off

Break-

Before-

Make

1 1 SW4 has opened Off Off Off Off

Talk 0 0 Close Break Switches On Off Off Off

State INRINGING INTEST LATCH TSD Timing Break

Switches

Ringing

Return

Switch

(SW3)

Ringing

Switch

(SW4)

Test

Switches

Ringing 1 0

Floating - Off On On Off

All-Off 0 0

Hold this state for at least one-half of the

ringing cycle. SW4 waiting for zero

current to turn off.

Off Off On Off

Break-

Before-

Make

0 0 SW4 has opened Off Off Off Off

Talk 0 0 Floating Close Break Switches On Off Off Off

CPC7582

12 www.clare.com Rev. 3.0 10/4/2002

2.3 Data Latch

The CPC7582 has an integrated data latch. The latch

operation is controlled by logic-le vel input pin 11

(LATCH). The data input of the latch is pin 10

(INRINGING) and pin 9 (I NTEST) of the device while the

output of the data latch is an internal node used for

state control. When LATCH cont rol pin is at logic 0,

the data latch is tr ansparent and da ta control sign als

flow directly through to state control. A change in input

will be reflected in the switch state. When LATCH

control pin is at logic 1, the dat a latch is active and a

change in input control will not aff ect switch state. The

switches will remain in the position they w er e in when

the LATCH changed from logic 0 to logic 1 and will not

respond to changes in input as long as the lat ch is at

logic 1. The TSD input is not tied to t he dat a latch.

Theref ore , TSD is not aff ected b y the LATCH input and

the TSD input will o verride state control.

2.4 TSD

Setting TSD to +5 V allows switch contr ol using t he

logic inputs. This setting, however, also disables the

thermal shutdown circuit and is therefore not recom-

mended. When using logic cont rols via the input pins,

pin 7 (TSD) should be allowed to float. As a result , the

two recommended states when using pin 7 (TSD) as a

control are 0, which forces the device to the all-off

state, or f loat, which allows logic inputs to remain

active. This requires the use of an open-collector type

buffer.

2.5 Ringing Switc h Zer o-Cr oss Current Turn Off

After the application of a logic input t o turn SW4 off,

the ringing switch is designed to delay the change in

state until the next zero-crossing. Once on, the switch

requires a zero-current cross to tu rn off, and therefore

should not be used to switch a pure DC signal. The

switch will remain in the on state no matter the logic

input until the next zero crossing. These switching

characteristics will reduce and possib ly eliminate

ov erall system impulse noise normally associated with

ringing swit ches . See application note AN-144,

Impulse Noise Benefits of Line Card Access Switches. The

attributes of ringing switch SW4 ma y make it possible

to eliminate the need f or a zero-cross switching

scheme. A minim um impedance of 300 Ω in series

with the ringing generator is recommended.

2.6 Power Suppli es

Both a +5 V supply and battery v oltage are connected

to the CPC7582. CPC7582 switch state control is

pow ered exclusively b y the +5 V supply. As a result,

the CPC7582BC e xhibits extremely low pow er

dissipation during both active and idle states.

The battery voltage is not u sed for switch control but

rather as a su pply for the integrated secondary

protection circuitry. The integrated SCR is designed to

trigger when pin 2 (TBAT) or pin 15 (RBAT) drops 2 to

4 V below the voltage on pin 16 (VBAT). This trigger

pre v ents a f ault in duced overvoltage e v ent at the T BAT

or RBAT nodes.

2.7 Battery Voltage Monito r

The CPC7582 also uses the VBAT voltage to monitor

battery v oltage. If battery voltage is lost, the CPC7582

immediately enters the all-off st ate. It remains in this

state until the battery voltage is rest ored. The device

also enters the all-off state if t he bat tery volt age rises

above –10 V and remains in the all-off st ate unt il the

battery v oltag e drops belo w –15 V. This batt ery

monitor f eature dr aws a small current from the battery

(less than 1 µA typical) and will add slightly t o t he

de vice’s overall power dissipation.

2.8 Protection

2.8.1 Diode Bridge/SCR

The CPC7582 uses a combination of current limited

break s witches, a diode bridge/SCR clamping circuit,

and a thermal shutdown mechanism to protect the

SLIC device or other associated circuitry from damage

during line transient e v ents such as lightning. During a

positive transient condition, the fault current is

conducted through the diod e bridge to g r ound via

FGND. Voltage is clamped to a diod e drop abo ve

ground. During a negative tr ansient of 2 to 4 V more

negative than the volta ge at VBAT, the SCR conducts

and f aults are shunted to FGND via the SCR or the

diode bridge.

In order f or the SCR to crowbar or f oldback, the on

v olt age (see “Protection Circuitry Electrical

Specifications” on page 8) of the SCR must be less

negative than the VBAT v oltage. If the VBAT voltage is

less negativ e than the SCR on voltage or if the VBAT

supply is unab le to source the trigger current, the SCR

will not crowbar.

F or po w er induction or po w er-cross fault conditions,

the positive cycle of the transient is clamped to the

diode drop abov e ground and the f ault current directed

to ground. The negative cycle of the transient will

cause the SCR to conduct when the voltage e xceeds

CPC7582

Rev. 3.0 10/4/2002 www.clare.com 13

the VBAT voltage b y two to four volts, steering the

current to ground.

2.8.2 Current Limiting function

If a lightning strike transient occurs when the device is

in the talk state, the current is passed along the line to

the integr ated protection circuit ry and limited by th e

dynamic current limit response of the active switches

during the talk state. During the talk state, when a

1000V 10/1000 µs pulse (GR-1089-CORE lightning) is

applied to the line though a properly clamped e xternal

protector, the current seen at pins 2 (TBAT) and pin 15

(RBAT) will be a pulse with a typical magnitude of 2.5 A

and a duration of less t han 0.5 µs.

If a power-cross fault occurs with the device in the talk

state, the current is passed though break switches

SW1 and SW2 on to the integ rated protection circuit

and is limited by the dynamic DC current limit

response of the tw o break switches. The DC current

limit, specified over temperature, is betw een 80 mA

and 425 mA, and the circuitry has a negative

temperature coeff icien t. As a re sult, if th e device is

subjected to ex tended heating due to a pow er cross

f ault , the measured current at pin 3 (TLINE) and pin 14

(RLINE) will decrease as the device temperature

increases. If the device temperature rises sufficiently,

the temperature shutdown mechanism will activate

and the device will enter the all-off state .

2.9 Temperature Shutdown

The thermal shutdown mechanism will activate when

the de vice temperature reaches a minimum of 110° C ,

placing the device in the all-off state regardless of

logic input. During thermal shutdown mode, pin 7

(TSD) will read 0 V. Normal output of TSD is +VDD.

If presented with a sh ort duration transient such as a

lightning e vent, the thermal shutdown feature will

typically not activate. But in an extended power-cross

transient, the device temperature will rise and the

thermal shutdown will activ ate forcing the s witches to

the all-off state. At this point the current measured at

pin 3 (TLINE) and pin 14 (RLINE) will drop to zero . Once

the device enters thermal shutdown it will remain in

the all-off state unt il t he temperature of the de vice

drops below the de-activation level of the thermal

shutdown circuit. This will permit the de vice t o return

to normal operation. If the transient has not passe d,

current will flow at the v alue allow ed b y the dynamic

DC current limiting of the switches and heating will

begin again, reactivating the thermal shutdown

mechanism. This cycle of entering and exiting the

thermal shutdown mode will continue as long as the

f ault condition persists. If the magnitude of the fault

condition is great enough, the external secondary

protector could activate and shunt all current to

ground.

The thermal shutdown mechanism of the CPC7582

can be disab l e by applying a logic high to pin 7 (TSD).

2.10 External Protection Elements

The CPC7582 requires only o verv olt age secondary

protection on the loop side of t he device. The

integrated pr otection featu re described abov e negates

the need f or protection on the line side. The secondary

protector limits voltage transients to levels that do not

e xceed t he breakdo wn voltage or input-output

isolation barrier of the CPC7582. A foldback or

crowbar t ype protect or is recommended to minimiz e

stresses on the de vice .

Consult Clare’s application note, AN-100, “Designing

Surge and Power Fault Protection Circuits for Solid

State Subscriber Line Interf aces” for equations related

to the specifications of external secondary protectors,

fused resistors and PTCs.

CPC7582

14 www.clare.com Rev. 3.0 10/4/2002

3. Manufacturing Information

3.1 Mechanical D ime ns io n s

3.1.1 SOIC

3.1.2 MLP

7.40 MIN / 7.60 MAX

(.291 MIN / .299 MAX)

0.23 MIN / 0.32 MAX

(.0091 MIN / .0125 MAX)

1.27

(.050)

2.44 MIN / 2.64 MAX

(.096 MIN / .104 MAX)

0.51 MIN / 1.01 MAX

(.020 MIN / .040 MAX)

10.11 MIN / 10.51 MAX

(.398 MIN / .414 MAX)

0.36 MIN / 0.46 MAX

(.014 MIN / .018 MAX)

10.11 MIN / 10.31 MAX

(.398 MIN / .406 MAX)

16 Pin SOIC (JEDEC Package)

0.55

0.80

0.23

0.55

0.33

(+0.07, -0.05)

0.2

0.80

(±0.10)

0.02

(+0.05, -0)

Terminal Tip

INDEX AREA

SEATING

PLANE

EXPOSED PAD

TOP VIEW

SIDE VIEW

BOTTOM VIEW

4.0

(±0.05)

6.0

(±0.05)

0.55

(±0.1)

Dimensions in mm

CPC7582

Rev. 3.0 10/4/2002 www.clare.com 15

3.2 Printed-Circuit Board Layout

3.2.1 SOIC

3.2.2 MLP

NOTE: For optimum solder joint size , MLP package

printed-circuit board pads should extend no more than

.05 mm past the chip post on t he sh ort sides, and no

more than .025 mm past the chip posts on the long

sides.

As the metallic pad on the bott om of the MLP pac kage

is connected to the substr ate of the die, Clare

recommends that no printed circuit board traces or

vias be placed under this area to maintain minimum

creepage and clearance values.

PC Board Pattern

(Top View)

1.193

(.047)

9.728 ± .051

(.383 ± .002)

.787

(.031)

1.270

(.050)

0.65

6.1

0.38

0.65

0.38

0.47

0.66

5.75

6.13

0.75 on center

5.35 on center

Detail A

All dimensions in mm

Not drawn to scale

CPC7582

16 www.clare.com Rev. 3.0 10/4/2002

3.3 Tape and Reel Packaging

3.3.1 SOIC

3.3.2 MLP

16.00

7.50

R = .50

2.30

1.30

6.80

3.00

2.00

4.00

2.00

1.50

12.00

6.50

2.70

A0 =

B0 =

K0 =

K1 =

NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA

STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS

LISTED ON PAGE 5 OF EIA-481-2.

6.5 mm

10.3 mm

2.3 mm

2.7 mm

16.00

R = .50

1.4

7.40

4.00

2.00

1.50

12.00

6.4

1.4

A0 =

B0 =

K0 =

K1 =

NOTES:1.ALL DIMENSIONS ARE IN MILLIMETERS AND CARRYTOLERANCES OF EIA

STANDARD 481-2. 2.THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS

LISTED ON PAGE 5 OF EIA-481-2.

6.4 mm

7.4 mm

1.4 mm

3.4 Soldering

3.4.1 Moisture Reflow Sensitivity

Clare has characterized the moist ure reflow sensitivity

of LCAS products using IPC/JEDEC standard

J-STD-020A. Moisture uptak e from atmosph eric

humidity occurs b y dif fusion. During the solder reflow

process, in which the component is at tached to the

PCB, the whole body of the component is e xposed to

high process temperatures. The combination of

moisture uptak e and high r eflow soldering

temperatures may lead to moisture induced

delamination and cracking of the component. To

pre vent this, this component must be handled in

accordance with IPC/JEDEC standard J-STD-020A

per the labelled moisture sensitivity level (MSL), level

1 for the SOIC package, and level 3 for the MLP

package.

3.4.2 Reflow Profile

The maximum ramp rates , dwell times , and

temperatures of the assemb ly reflow profile should no t

e xceed those specif ied in IPC standard IPC-9502,

tabl e 2. Soldering processes are limited to 220 °C

component body temperature.

3.5 Wash i ng

Clare does not recommend ultrasonic cleaning of

LCAS parts.

For additional information please visit www.clare.com

Clare, Inc. makes no representations or warran ties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make

changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implie d. Except as set

forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied w arranty relating to its

products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.

The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into

the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a

person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.

Specifications: DS-CPC7582-R3.0

10/4/2002