CPC7582 Line Card Access Switch Features Description * Small 16-pin SOIC or micro-leadframe package * MLP package printed-circuit board footprint is 60 percent smaller than the SOIC version, 70 percent smaller than 4th generation EMR solutions. * Monolithic IC reliability * Low matched RON * Eliminates the need for zero cross switching * Flexible switch timing to transition from ringing mode to talk mode. * Clean, bounce-free switching * Tertiary protection consisting of integrated current limiting, voltage clamping, and thermal shutdown for SLIC protection * 5 V operation with power consumption < 10 mW * Intelligent battery monitor * Latched logic-level inputs, no external drive circuitry required * SOIC version is pin compatible with Agere product The CPC7582 is a monolithic solid-state switch in a 16-pin SOIC or MLP surface-mount package. It provides the necessary functions to replace two 2-Form-C electro-mechanical relays on traditional analog and integrated voice and data (IVD) line cards found in Central Office, Access, and PBX equipment. The device contains solid state switches for tip and ring line break, ringing injection/ringing return and test access. The CPC7582 requires only a +5V supply and offers break-before-make or make-before-break switch operation using simple logic-level input control. Applications * * * * * * * * The CPC7582xC logic states differ from the CPC7582xA/B. See "Functional Description" on page 9 for more information. The CPC7582xC also has a higher trigger and hold current for the protection SCR. Specify CPC7582Bx for SOIC or specify CPC7582Mx for MLP package shipped in tubes. Add -TR to the part number for tape and reel packaging. Ordering Information Central office (CO) Digital Loop Carrier (DLC) PBX Systems Digitally Added Main Line (DAML) Hybrid Fiber Coax (HFC) Fiber in the Loop (FITL) Pair Gain System Channel Banks Part Number CPC7582xA CPC7582xB Description 6-pole LCAS with protection SCR 6-pole LCAS without protection SCR 6-pole LCAS with protection SCR and added logic state CPC7582xC Figure 1. CPC7582 Block Diagram +5 Vdc TTEST 4 TRING 5 SW5 Tip TLINE SW3 X 3 6 VDD CPC7582 X 2 TBAT X SW1 Secondary Protection Ring SLIC X SW6 SW4 12 VBAT SCR and Trip Circuit (CPC7582xB/C) X X RTEST 15 RBAT SW2 RLINE 14 13 300 (min.) 1 FGND VREF L A T C H Switch Control Logic 16 VBAT 8 DGND 9 10 11 INACCESS INRINGING LATCH 7 TSD RINGING DS-CPC7582-R3.0 10/4/2002 www.clare.com 1 CPC7582 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Absolute Maximum Ratings (at 25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Electrical Characteristics, TA = -40 C to +85 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.5 Test Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 CPC7582xA/B Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 CPC7582xC Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 4 4 4 4 5 6 6 7 8 8 9 2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 CPC7582xA/B Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.2 CPC7582xC Logic States: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 Make-Before-Break Operation - All Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 Make-Before-Break Operation for All Versions (Ringing to Talk Transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.3 Break-Before-Make Operation - CPC7582xA/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 Break-Before-Make Operation CPC7582xA/B (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.5 Break-Before-Make Operation - All Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.6 Break-Before-Make Operation for all Version (Ringing to Talk Transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 TSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.9 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.10 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 www.clare.com 14 14 14 14 15 15 15 16 16 16 17 17 17 17 R3.0 10/4/2002 CPC7582 1. Specifications 1.1 Package Pinout 1.2 Pinout CPC7582 Pin Name FGND 1 16 VBAT 1 FGND Fault ground TBAT 2 15 RBAT 2 TBAT Connect to tip on SLIC side TLINE 3 14 RLINE 3 TLINE Connect to tip on line side TRINGING 4 13 RRINGING TTEST 5 12 RTEST VDD 6 11 LATCH TSD 7 10 INRINGING DGND 8 9 INTEST 4 TRINGING Connect to ringing generator return 5 TTEST 6 VDD +5 V supply 7 TSD Temperature shutdown pin. Bi-directional I/O with internal pullup to VDD. Output function indicates status of thermal shutdown circuitry. Input function can be used to set the `all off' mode using an open-drain type output. 8 DGND Digital ground 9 INTEST Logic-level switch control input 10 Rev. 3.0 10/4/2002 Description Connect to test bus tip lead INRINGING Logic-level switch control input 11 LATCH Data latch control, active high, transparent low 12 RTEST Connect to test bus ring lead 13 RRINGING 14 RLINE Connect to ring on the line side 15 RBAT Connect to ring on the SLIC side 16 VBAT Battery voltage supply. Must be capable of sourcing the trigger current for proper operation of the protection SCR. www.clare.com Connect to ringing generator current limiting resistor 3 CPC7582 values are characteristic of the device and are the result of engineering evaluations. Typical values are provided for information purposes only and are not part of the testing requirements. 1.3 Absolute Maximum Ratings (at 25 C) Parameter Minimum Maximum Unit Operating temperature -40 +110 C Storage temperature -40 +150 C Operating relative humidity 5 95 % Pin soldering temperature (10 seconds max) - +220 C +5 V power supply (VDD) -0.3 7 V - -85 V -0.3 VDD + 0.3 V - 330 V Battery Supply Logic input voltage Logic input to switch output isolation Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability. 1.4.1 Power Supply Specifications Supply Switch open contact isolation (SW1, SW2, SW3, SW5, SW6) - Switch Open Contact Isolation (SW4)* - 330 480 V V Minimum Typical Maximum Unit VDD +4.5 +5.0 +5.5 V VBAT1 -19 - -72 V 1 VBAT is used only for internal protection circuitry. If VBAT rises above -10 V, the device will enter the all-off state and will remain in the all-off state until the battery drops below -15 V. *Ringing supply side of switch limited to 210 V with respect to ground 1.4 Electrical Characteristics, TA = -40 C to +85 C Unless otherwise specified, minimum and maximum values are production testing requirements. Typical ESD Rating (Human Body Model) 1000 V 1.4.2 Break Switches, SW1 and SW2 Parameter Conditions Symbol Minimum Typical Maximum Unit 1 A Off-state leakage current +25 C VSW (differential) = -320 V to GND VSW (differential) = +260 V to -60 V +85 C VSW (differential) = -330 V to GND VSW (differential) = +270 V to -60 V -40 C VSW (differential) = -310 V to GND VSW (differential) = +250 V to -60 V 0.1 ISW - 0.3 0.1 RON +25 C +85 C -40 C RON match 4 ISW = 10 mA, 40 mA, RBAT and TBAT = -2 V RON - Per on-resistance test condition of SW1, SW2. Magnitude RON SW1 - RONSW2 RON www.clare.com 14.5 - 20.5 28 10.5 - 0.15 0.8 Rev. 3.0 10/4/2002 CPC7582 Parameter Conditions Symbol Minimum Typical Maximum Unit DC current limit +25 C +85 C VSW (on) = 10 V -40 C ISW Dynamic current limit (t = <0.5 s) Break switches on, all other switches off, apply 1 kV 10/1000 s pulse, with appropriate protection in place. - 300 - 80 160 - - 400 425 - 2.5 - A 1 A 200 - V/s Typical Maximum Unit 1 A mA Logic input to switch output isolation +25 C VSW (TLINE, RLINE) = 320 V, logic inputs = gnd +85 C VSW (TLINE, RLINE) = 330 V, logic inputs = gnd -40 C VSW (TLINE, RLINE) = 310 V, logic inputs = gnd dv/dt sensitivity - 0.1 ISW - 0.3 0.1 - 1.4.3 Ringing Return Switch, SW3 Parameter Conditions Symbol Minimum Off-state leakage current +25 C VSW (differential) = -320 V to GND VSW (differential) = +260 V to -60 V +85 C VSW (differential) = -330 V to GND VSW (differential) = +270 V to -60 V -40 C VSW (differential) = -310 V to GND VSW (differential) = +250 V to -60 V 0.1 ISW - 0.3 0.1 RON +25 C +85 C ISW (on) = 0 mA, 10 mA RON - -40 C 60 - 85 100 45 - DC current limit +25 C +85 C VSW (on) = 10 V -40 C Dynamic current limit (t = <0.5 s) - 135 70 85 210 ISW Ringing switches on, all other switches off, apply 1 kV 10/1000 s pulse, with appropriate protection in place. - mA - 2.5 A Logic input to switch output isolation +25 C VSW (TRINGING, TLINE) = 320 V, logic inputs = gnd +85 C VSW (TRINGING, TLINE) = 330 V, logic inputs = gnd -40 C VSW (TRINGING, TLINE) = 310 V, logic inputs = gnd dv/dt sensitivity - Rev. 3.0 10/4/2002 0.1 ISW - 0.3 1 A - V/s 0.1 - www.clare.com 200 5 CPC7582 1.4.4 Ringing Switch, SW4 Parameter Conditions Symbol Minimum Typical Maximum Unit 1 A 1.5 3 V 0.1 0.25 mA - - 2 A ISW - 150 mA IRINGING 300 - A RON 10 15 1 A 200 - V/s Typical Maximum Unit 1 A Off-state leakage current +25 C VSW (differential) = -255 V to +210 V VSW (differential) = +255 V to -210 V +85 C VSW (differential) = -270 V to +210 V VSW (differential) = +270 V to -210 V -40 C VSW (differential) = -245 V to +210 V VSW (differential) = +245 V to -210 V On Voltage ISW (on) = 1 mA Ringing switches on, all other switches off, apply 1 kV 10/1000 s pulse, with appropriate protection in place. On steady-state current* Inputs set for ringing mode Release current - RON ISW (on) = 70 mA, 80 mA ISW 0.1 0.05 - Ringing generator current to ground during VDD = 5 V, inputs set for ringing mode ringing Surge current* 0.05 - IRINGING Logic input to switch output isolation +25 C VSW (RRINGING, RLINE) = 320 V, logic inputs = gnd +85 C VSW (RRINGING, RLINE) = 330 V, logic inputs = gnd -40 C VSW (RRINGING, RLINE) = 310 V, logic inputs = gnd dv/dt sensitivity - 0.1 ISW - 0.3 0.1 - *Secondary protection and ringing source current limiting must prevent exceeding this parameter. 1.4.5 Test Switches, SW5 and SW6 Parameter Conditions Symbol Minimum Off-state leakage current +25 C VSW (differential) = -320 V to GND VSW (differential) = +260 V to -60 V +85 C VSW (differential) = -330 V to GND VSW (differential) = +270 V to -60 V -40 C VSW (differential) = -310 V to GND VSW (differential) = +250 V to -60 V 6 0.1 ISW www.clare.com - 0.3 0.1 Rev. 3.0 10/4/2002 CPC7582 Parameter Conditions Symbol Minimum Typical Maximum Unit 38 - 46 70 28 - - 175 - 80 110 - - 210 250 - 2.5 - A 1 A Unit RON +25 C +85 C -40 C ISW(ON) = 10 mA, 40 mA, TBAT = -2 V RON - DC current limit +25 C +85 C VSW (on) = 10 V -40 C ISW Dynamic current limit (t = <0.5 s) Test switches on, all other switches off, apply 1 kV at 10/1000 s pulse, with appropriate protection in place. mA Logic input to switch output isolation +25 C VSW (TTEST, TLINE) = 320 V, logic inputs = gnd +85 C VSW (TTEST, TLINE) = 330 V, logic inputs = gnd -40 C VSW (TTEST, TLINE) = 310 V, logic inputs = gnd 0.1 ISW - 0.3 0.1 1.5 Additional Electrical Characteristics Parameter Conditions Symbol Minimum Typical Maximum Digital input characteristics Input low voltage - VIL - - 1.5 Input high voltage - VIH 3.5 - - Input leakage current (high) VDD = 5.5 V, VBAT = -75 V, VIH = 5 V IIH - 0.1 1 Input leakage current (low) VDD = 5.5 V, VBAT = -75 V, VIL = 0 V IIL V A - 0.1 1 - 5.5 10 6.5 10 Power requirements Power consumption in talk and all-off states Power consumption in all other states VDD current in talk and all-off states VDD current in all other states VBAT current in any state VDD = 5 V, VBAT = -48 V, measure IDD and IBAT P mW IDD - 1.1 2.0 IDD - 1.3 2.0 IBAT - 0.1 10 A VDD = 5 V, VBAT = -48 V VDD = 5 V, VBAT = -48 V mA Temperature Shutdown Requirements (temperature shutdown flag is active low) Shutdown activation temperature - - 110 125 150 C Shutdown circuit hysteresis - - 10 - 25 C Rev. 3.0 10/4/2002 www.clare.com 7 CPC7582 1.6 Protection Circuitry Electrical Specifications Parameter Conditions Symbol Minimum Typical Maximum 2.1 3 Unit Parameters Related to the Diodes in the Diode Bridge Voltage drop at continuous current (50/60 Hz) Apply dc current limit of break switches Forward Voltage - Voltage drop at surge current Apply dynamic current limit of break switches Forward Voltage - 5 - - - - * - 60 (CPC7582xA, xB) 70 (CPC7582xC) - - 35 (CPC7582xA, xB) 40 (CPC7582xC) - - 100 (CPC7582xA, xB) 135 (CPC7582xC) - 60 (CPC7582xA, xB) 70 (CPC7582xA, xB) 110 (CPC7582xC) 115 (CPC7582xC) - V Parameters Related to the Protection SCR Surge current Trigger current (+25 C) ITRIG Trigger current (+85 C) - Hold current (+25 C) IHOLD Hold current (+85 C) A mA VTBAT or VRBAT VBAT -4 - VBAT -2 V IVBAT - - 1.0 A 0.5 A, t = 0.5 ms VTBAT or VRBAT - -3 - V 2.0 A, t = 0.5 ms VTBAT or VRBAT - -5 - V Gate trigger voltage IGATE = ITRIGGER** Reverse leakage current VBAT = -48 V On-state voltage *Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place. **VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate. 1.7 CPC7582xA/B Truth Table INRINGING INTEST Talk 0 0 State Test 0 1 Ringing 1 0 All Off 1 1 Latched X X All off X X LATCH 0 TSD 1 or Floating1 Break Switches Ringing Switches Test Switches On Off Off Off Off On Off On Off Off Off Off 1 X Unchanged 2 0 Off Off Off 1 If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally. 2Forcing T to ground overrides the logic input pins and forces an all off state. SD 8 www.clare.com Rev. 3.0 10/4/2002 CPC7582 1.8 CPC7582xC Truth Table INRINGING INTEST Talk 0 0 Test/Monitor 0 1 Ringing 1 0 State LATCH 0 Ringing Test 1 1 Latched X X 1 All off X X X TSD 1 or Floating1 Break Switches Ringing Switches Test Switches On Off Off On Off On Off On Off On On Off Unchanged 02 Off Off Off 1If T is tied high, thermal shutdown is disabled. If T is left floating, the thermal shutdown mechanism functions normally. SD SD 2Forcing T to ground overrides the logic input pins and forces an all off state. SD 2. Functional Description 2.1 Introduction 2.1.1 CPC7582xA/B Logic States * Talk. Break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open. * Ringing. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test switches SW5 and SW6 open. * Test. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and loop test switches SW5 and SW6 closed. * All off. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open. 2.1.2 CPC7582xC Logic States: * Talk. Break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open. * Ringing. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test switches SW5 and SW6 open. * Test/Monitor. Break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 closed. * Ringing Test. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test switches SW5 and SW6 closed. * All off. Break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open. The CPC7582 offers break-before-make and makebefore-break switching from the ringing state to the talk state with simple logic-level input control. Solidstate switch construction means no impulse noise is Rev. 3.0 10/4/2002 generated when switching during ring cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State control is via logic-level input so no additional driver circuitry is required. The linear break switches SW1 and SW2 have exceptionally low RON and excellent matching characteristics. The ringing switch SW4 has a minimum open contact breakdown voltage of 480 V. This is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator). Integrated into the CPC7582 is an over voltage clamping circuit, active current limiting, and a thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and hazardous potentials are diverted to ground via diodes and, in xA/C parts, an integrated SCR. Power-cross potentials are also reduced by the current limiting and thermal shutdown circuits. To protect the CPC7582 from an overvoltage fault condition, use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the maximum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7582BC will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. The CPC7582 operates from a +5 V supply only. This gives the device extremely low idle and active power consumption and allows use with virtually any range of www.clare.com 9 CPC7582 battery voltage. Battery voltage is also used by the CPC7582 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7582 enters the all-off state. 2.2 Switch Logic The CPC7582 provides, when switching from the ringing state to the talk state, the ability to control the release timing of the ringing switches SW3 and SW4 relative to the state of the break switches SW1 and SW2 using simple logic-level inputs. This is referred to as make-before-break or break-before-make operation. When the break switch contacts (SW1 and SW2) are closed (or made) before the ringing switch contacts (SW3 and SW4) are opened (or broken), this is referred to as make-before-break operation. Breakbefore-make operation occurs when the ringing contacts (SW3 and SW4) are opened (broken) before the break switch contacts (SW1 and SW2) are closed (made). With the CPC7582, the make-before-break and break-before-make operations can easily be selected by applying logic-level inputs to the device. The logic sequences for these modes of operation are given in "Make-Before-Break Operation for All Versions (Ringing to Talk Transition)" on page 10, "Break-Before-Make Operation CPC7582xA/B (Ringing to Talk Transition)" on page 11, and "BreakBefore-Make Operation for all Version (Ringing to Talk Transition)" on page 11. Logic states and input control settings are given in "CPC7582xA/B Truth Table" on page 8 and "CPC7582xC Truth Table" on page 9. 2.2.1 Make-Before-Break Operation - All Versions To use make-before-break operation, change the logic inputs to the talk state immediately following the ringing state. Application of the talk state opens the ringing return switch (SW3) as the break switches (SW1 and SW2) close. The ringing switch (SW4) remains open until the next zero-crossing of the ringing supply current. While in the make-before-break state, ringing potentials in excess of the CPC7582 protection circuitry trigger levels will be diverted to ground. 2.2.2 Make-Before-Break Operation for All Versions (Ringing to Talk Transition) State INRINGING INTEST Ringing 1 0 Makebeforebreak 0 0 Talk 0 0 LATCH TSD Ringing Ringing Return Break Test Switch Switches Switch Switches (SW4) (SW3) Timing - 0 SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of the ringing cycle. In this Floating transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. Zero-cross current has occurred 2.2.3 Break-Before-Make Operation - CPC7582xA/B Off On On Off On Off On Off On Off Off Off opened. Break-before-make operation of the CPC7582xA/B can be achieved using two different techniques. The first method uses manipulation of the INRINGING and INTEST logic inputs as shown in "Break-BeforeMake Operation CPC7582xA/B (Ringing to Talk Transition)" on page 11. Break-before-make operation occurs when the ringing switch opens before the break switches (SW1 and SW2) close. 1. At the end of the ringing state apply the all off state (0, 0). This releases the ringing return switch (SW3) while the ringing switch remains on, waiting for the next zero current event. 2. Hold the all off state for at least one-half of a ringing cycle to assure that a zero crossing event occurs and that the ringing switch (SW4) has 10 www.clare.com Rev. 3.0 10/4/2002 CPC7582 2.2.4 Break-Before-Make Operation CPC7582xA/B (Ringing to Talk Transition) State INRINGING INTEST Ringing 1 0 - Off On On Off All-Off 1 1 Hold this state for at least one-half of the ringing cycle. SW4 waiting for zero current to turn off. Off Off On Off LATCH 0 TSD Ringing Ringing Return Break Test Switch Switches Switch Switches (SW4) (SW3) Floating Timing BreakBeforeMake 1 1 SW4 has opened Off Off Off Off Talk 0 0 Close Break Switches On Off Off Off 2.2.5 Break-Before-Make Operation - All Versions The second break-before-make method for the CPC7582xA/B is also the only method available for the CPC7582xC. As shown in "CPC7582xA/B Truth Table" on page 8 and "CPC7582xC Truth Table" on page 9, the bi-directional TSD interface disables all of the CPC7582 switches when pulled to a logic low. Although logically disabled, if the ringing switch (SW4) is active (closed), it will remain closed until the next current zero crossing event. As shown in the table "Break-Before-Make Operation for all Version (Ringing to Talk Transition)" on page 11, this operation is similar to the one shown in "Break-Before-Make Operation - All Versions" on page 11, except in the method used to select the all off state, and in when the INRINGING and INTEST inputs are reconfigured for the talk state. 1. Pull TSD to a logic low to end the ringing state. This opens the ringing return switch (SW3) and prevents any other switches from closing. 2. Keep TSD low for at least one-half the duration of the ringing cycle period to allow sufficient time for a zero crossing current event to occur and for the circuit to enter the break before make state. 3. During the TSD low period, set the INRINGING and INTEST inputs to the talk state (0, 0). 4. Release TSD, allowing the internal pull-up to activate the break switches. When using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces an all off state) and float (allows switch control via logic input pins and the thermal shutdown mechanism is active). This requires the use of an open-collector type buffer. Forcing TSD to a logic high disables the thermal shutdown circuit and is therefore not recommended as this could lead to device damage or destruction in the presence of excessive tip or ring potentials. 2.2.6 Break-Before-Make Operation for all Version (Ringing to Talk Transition) State INRINGING INTEST Ringing 1 0 All-Off 0 0 0 BreakBeforeMake 0 0 Talk 0 0 Rev. 3.0 10/4/2002 LATCH Ringing Ringing Return Break Test Switch Switches Switch Switches (SW4) (SW3) TSD Timing Floating - Off On On Off Hold this state for at least one-half of the ringing cycle. SW4 waiting for zero current to turn off. Off Off On Off SW4 has opened Off Off Off Off Close Break Switches On Off Off Off 0 Floating www.clare.com 11 CPC7582 2.3 Data Latch The CPC7582 has an integrated data latch. The latch operation is controlled by logic-level input pin 11 (LATCH). The data input of the latch is pin 10 (INRINGING) and pin 9 (INTEST) of the device while the output of the data latch is an internal node used for state control. When LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected in the switch state. When LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. The TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and the TSD input will override state control. 2.4 TSD Setting TSD to +5 V allows switch control using the logic inputs. This setting, however, also disables the thermal shutdown circuit and is therefore not recommended. When using logic controls via the input pins, pin 7 (TSD) should be allowed to float. As a result, the two recommended states when using pin 7 (TSD) as a control are 0, which forces the device to the all-off state, or float, which allows logic inputs to remain active. This requires the use of an open-collector type buffer. 2.5 Ringing Switch Zero-Cross Current Turn Off After the application of a logic input to turn SW4 off, the ringing switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See application note AN-144, Impulse Noise Benefits of Line Card Access Switches. The attributes of ringing switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 in series with the ringing generator is recommended. 2.6 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7582. CPC7582 switch state control is powered exclusively by the +5 V supply. As a result, 12 the CPC7582BC exhibits extremely low power dissipation during both active and idle states. The battery voltage is not used for switch control but rather as a supply for the integrated secondary protection circuitry. The integrated SCR is designed to trigger when pin 2 (TBAT) or pin 15 (RBAT) drops 2 to 4 V below the voltage on pin 16 (VBAT). This trigger prevents a fault induced overvoltage event at the TBAT or RBAT nodes. 2.7 Battery Voltage Monitor The CPC7582 also uses the VBAT voltage to monitor battery voltage. If battery voltage is lost, the CPC7582 immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the battery voltage rises above -10 V and remains in the all-off state until the battery voltage drops below -15 V. This battery monitor feature draws a small current from the battery (less than 1 A typical) and will add slightly to the device's overall power dissipation. 2.8 Protection 2.8.1 Diode Bridge/SCR The CPC7582 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground via FGND. Voltage is clamped to a diode drop above ground. During a negative transient of 2 to 4 V more negative than the voltage at VBAT, the SCR conducts and faults are shunted to FGND via the SCR or the diode bridge. In order for the SCR to crowbar or foldback, the on voltage (see "Protection Circuitry Electrical Specifications" on page 8) of the SCR must be less negative than the VBAT voltage. If the VBAT voltage is less negative than the SCR on voltage or if the VBAT supply is unable to source the trigger current, the SCR will not crowbar. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to the diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds www.clare.com Rev. 3.0 10/4/2002 CPC7582 fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. the VBAT voltage by two to four volts, steering the current to ground. 2.8.2 Current Limiting function If a lightning strike transient occurs when the device is in the talk state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of the active switches during the talk state. During the talk state, when a 1000V 10/1000 s pulse (GR-1089-CORE lightning) is applied to the line though a properly clamped external protector, the current seen at pins 2 (TBAT) and pin 15 (RBAT) will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 s. If a power-cross fault occurs with the device in the talk state, the current is passed though break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to a power cross fault, the measured current at pin 3 (TLINE) and pin 14 (RLINE) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will enter the all-off state. The thermal shutdown mechanism of the CPC7582 can be disable by applying a logic high to pin 7 (TSD). 2.10 External Protection Elements The CPC7582 requires only overvoltage secondary protection on the loop side of the device. The integrated protection feature described above negates the need for protection on the line side. The secondary protector limits voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7582. A foldback or crowbar type protector is recommended to minimize stresses on the device. Consult Clare's application note, AN-100, "Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces" for equations related to the specifications of external secondary protectors, fused resistors and PTCs. 2.9 Temperature Shutdown The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110 C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, pin 7 (TSD) will read 0 V. Normal output of TSD is +VDD. If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross transient, the device temperature will rise and the thermal shutdown will activate forcing the switches to the all-off state. At this point the current measured at pin 3 (TLINE) and pin 14 (RLINE) will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the de-activation level of the thermal shutdown circuit. This will permit the device to return to normal operation. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the Rev. 3.0 10/4/2002 www.clare.com 13 CPC7582 3. Manufacturing Information 3.1 Mechanical Dimensions 3.1.1 SOIC 16 Pin SOIC (JEDEC Package) 10.11 MIN / 10.31 MAX (.398 MIN / .406 MAX) 1.27 (.050) 0.23 MIN / 0.32 MAX (.0091 MIN / .0125 MAX) 2.44 MIN / 2.64 MAX (.096 MIN / .104 MAX) 7.40 MIN / 7.60 MAX (.291 MIN / .299 MAX) 10.11 MIN / 10.51 MAX (.398 MIN / .414 MAX) 0.51 MIN / 1.01 MAX (.020 MIN / .040 MAX) 0.36 MIN / 0.46 MAX (.014 MIN / .018 MAX) 3.1.2 MLP 7 6 INDEX AREA TOP VIEW 0.2 0.80 (0.10) SEATING PLANE SIDE VIEW 0.02 (+0.05, -0) 0.23 0.55 0.33 (+0.07, -0.05) 1 2 EXPOSED PAD 0.55 4.0 (0.05) 0.55 (0.1) 16 6.0 (0.05) 0.80 Terminal Tip BOTTOM VIEW Dimensions in mm 14 www.clare.com Rev. 3.0 10/4/2002 CPC7582 3.2 Printed-Circuit Board Layout 3.2.1 SOIC PC Board Pattern (Top View) 1.270 (.050) 9.728 .051 (.383 .002) 1.193 (.047) .787 (.031) 3.2.2 MLP 5.75 0.75 on center 0.65 0.38 5.35 on center 6.1 Detail A 6.13 Detail A All dimensions in mm Not drawn to scale 0.66 0.47 0.65 0.38 NOTE: For optimum solder joint size, MLP package printed-circuit board pads should extend no more than .05 mm past the chip post on the short sides, and no more than .025 mm past the chip posts on the long sides. As the metallic pad on the bottom of the MLP package is connected to the substrate of the die, Clare recommends that no printed circuit board traces or vias be placed under this area to maintain minimum creepage and clearance values. Rev. 3.0 10/4/2002 www.clare.com 15 CPC7582 3.3 Tape and Reel Packaging 3.3.1 SOIC A0 6.50 3.00 R = .50 2.00 K1 B0 2.30 6.80 1.30 16.00 K0 2.70 7.50 12.00 4.00 2.00 1.50 A0 = 6.5 mm B0 = 10.3 mm 2.3 mm 2.7 mm K0 = K1 = NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS LISTED ON PAGE 5 OF EIA-481-2. 3.3.2 MLP A0 6.4 R = .50 K1 B0 7.40 16.00 K0 1.4 1.4 12.00 4.00 1.50 A0 = 16 6.4 mm B0 = 7.4 mm K0 = 1.4 mm K1 = 1.4 mm 2.00 NOTES:1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS LISTED ON PAGE 5 OF EIA-481-2. www.clare.com Rev. 3.0 10/4/2002 3.4 Soldering 3.4.1 Moisture Reflow Sensitivity Clare has characterized the moisture reflow sensitivity of LCAS products using IPC/JEDEC standard J-STD-020A. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-020A per the labelled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 3 for the MLP package. 3.4.2 Reflow Profile The maximum ramp rates, dwell times, and temperatures of the assembly reflow profile should not exceed those specified in IPC standard IPC-9502, table 2. Soldering processes are limited to 220 C component body temperature. 3.5 Washing Clare does not recommend ultrasonic cleaning of LCAS parts. For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specifications: DS-CPC7582-R3.0 (c) Copyright 2002, Clare, Inc. All rights reserved. Printed in USA. 10/4/2002