SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus+
Family
D
State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Released as DSCC SMD 5962-9557801NXD
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include 100-Pin Plastic
Thin Quad Flat (PZ) Package With
14 × 14-mm Body Using 0.5-mm Lead Pitch
and Space-Saving 100-Pin Ceramic Quad
Flat (HS) Package†
767778798081828384858687888990919293949596979899100
494847464544434241403938373635343332313029282726
’ABTH32543 ...PZ PACKAGE
(TOP VIEW)
1A9
1A10
GND
1A11
1A12
1A13
1A14
GND
1A15
1A16
1A17
1A18
VCC
2A1
2A2
2A3
2A4
GND
2A5
2A6
2A7
2A8
GND
2A9
2A10
1B9
1B10
GND
1B11
1B12
1B13
1B14
GND
1B15
1B16
1B17
1B18
VCC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
2B8
GND
2B9
2B10
1A8
1A7
1A6
VCC
GND
2A14
2A11
2A12
2A13
1A5
1A4
1A3
1A2
1A1
1CEBA
1OEBA
1LEBA
1LEAB
1OEAB
1CEAB
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
GND
2A18
2A15
2A16
2A17
2LEAB
2OEAB
2CEBA
2OEBA
2B16
2B15
2CEAB
2B18
2B17
GND
2B13
2B14
2B12
2B11
VCC
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2LEBA
†The HS package is not production released.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GND
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1B7
1B8
1B10
1B11
1B12
1B13
1B14
GND
1B15
1B16
1B17
1B18
2B1
2B4
GND
2B5
2B6
2B7
2B8
1A6
1A8
1A9
1A10
1A11
1A12
1A13
1A14
1A15
1A16
1A18
2A1
2A2
2A3
2A4
GND
2A5
2A7
2A8
GND
1A5
1A3
1A2
1A1
1B2
1B3
1B4
1B5
GND
GND
2A14
2A15
2A16
2A17
2A18
2CEBA
2B18
2B17
2B16
2B14
GND
2B15
1A7
1CEAB
1B9
2B3
GND
2A6
2A9
2A10
2A11
2A12
GND
2B9
2B10
2B11
2B12
1B1
1A4
SN54ABTH32543 . . . HS PACKAGE†
(TOP VIEW)
1A17
VCC
2OEBA
2LEBA
CC
V
2LEAB
2OEAB
2CEAB
2B2
VCC
GND
1OEAB
1LEAB
CC
V
1LEBA
1OEBA
1CEBA
GND
2A13
2B13
1B6
†For HS package availability, please contact the factory or your local TI Field Sales Office.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
description
The ’ABTH32543 are 36-bit registered transceivers that contain two sets of D-type latches for temporary storage
of data flowing in either direction. These devices can be used as two 18-bit transceivers or one 36-bit
transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided
for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low , the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and
OEBA inputs.
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH32543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH32543 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE†
(each 18-bit section)
INPUTS OUTPUT
CEAB LEAB OEAB AB
H X X X Z
XXHXZ
LHLXB
0‡
LLLLL
L L L H H
†A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
‡Output level before the indicated steady-state
input conditions were established
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1 1B1
To 17 Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1 2B1
To 17 Other Channels
Pin numbers shown are for the PZ package.
90
91
89
86
85
87
92
36
35
37
40
41
39
14
84
62
C1
1D
C1
1D
C1
1D
C1
1D
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABTH32543 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABTH32543 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): PZ package 50°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH32543 SN74ABTH32543
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ABTH32543 SN74ABTH32543
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = – 3 mA 2.5 2.5
VOH
VCC = 5 V, IOH = – 3 mA 3 3
V
V
OH
VCC =45V
IOH = – 24 mA 2
V
V
CC =
4
.
5
V
IOH = – 32 mA 2
VOL
VCC =45V
IOL = 48 mA 0.55 0.55
V
V
OL
V
CC =
4
.
5
V
IOL = 64 mA 0.55
V
Vhys 100 100 mV
Control inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1
I
A or B ports VCC = 2.1 V to 5.5 V, VI = VCC or GND ±20
µA
I
IControl inputs
VCC =55V
VI=V
CC or GND
±1µ
A
A or B ports
V
CC =
5
.
5
V
,
V
I =
V
CC
or
GND
±20
II(h ld)
AorB
p
orts
VCC =45V
VI = 0.8 V 100
µA
I
I(hold)
A
or
B
ports
V
CC =
4
.
5
V
VI = 2 V –100 µ
A
IOZPU‡VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA
IOZPD‡VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA
Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 µA
ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 µA
IO§VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –100 –180 mA
V55VI0
Outputs high 3 3
ICC VCC = 5.5 V, IO = 0,
VI=V
CC or GND
Outputs low 20 20 mA
VI
=
VCC
or
GND
Outputs disabled 2 2
∆ICC¶VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND 1 1 mA
CiControl inputs VI = 2.5 V or 0.5 V 3.5 3.5 pF
Cio A or B ports VO = 2.5 V or 0.5 V 9.5 9.5 pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡This parameter is specified by characterization.
§Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C#SN54ABTH32543 SN74ABTH32543 UNIT
MIN MAX MIN MAX MIN MAX
twPulse duration, LEAB or LEBA low 3.3 3.3 3.3 ns
t
Setu
p
time
Data before LEAB↑ or LEBA↑2.1 2.6 2.1
ns
t
su
Set
u
p
time
Data before CEAB↑ or CEBA↑1.7 2 1.7
ns
th
Hold time
Data after LEAB↑ or LEBA↑0.6 1.1 0.6
ns
t
h
Hold
time
Data after CEAB↑ or CEBA↑0.9 1.2 0.9
ns
#These limits apply only to the SN74ABTH32543.
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C†SN54ABTH32543 SN74ABTH32543 UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
tPLH
AorB
BorA
1 3.5 5.2 0.5 6.3 1 5.9
ns
tPHL
A
or
B
B
or
A
1 3.5 5.1 0.5 5.9 1 5.7
ns
tPLH
LE
AorB
1.9 4.6 6.3 0.8 7.9 1.9 7.5
ns
tPHL
LE
A
or
B
1.9 4.3 5.9 0.8 6.9 1.9 6.6
ns
tPZH
CE
AorB
1.7 4.3 6.7 0.8 8.3 1.7 8
ns
tPZL
CE
A
or
B
2.6 5.2 8 1 8.8 2.6 8.8
ns
tPHZ
CE
AorB
1.6 3.8 6.6 0.5 7.4 1.6 7.1
ns
tPLZ
CE
A
or
B
2.4 4.6 7 1 7.9 2.4 7.5
ns
tPZH
OE
AorB
1.4 3.8 6.1 0.5 7.6 1.4 7.3
ns
tPZL
OE
A
or
B
2.3 4.7 7.4 1 8.2 2.3 8.1
ns
tPHZ
OE
AorB
1.3 3.4 6.1 0.5 6.7 1.3 6.5
ns
tPLZ
OE
A
or
B
2 4.2 6.6 0.8 7.2 2 6.9
ns
†These limits apply only to the SN74ABTH32543.
SN54ABTH32543, SN74ABTH32543
36-BIT REGISTERED BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS230F – JUNE 1992 – REVISED MAY 1997
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 . 5 n s, t f≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 1998, Texas Instruments Incorporated
