Enpirion® Power Evaluation Board User Guide
EP53x7xQI PowerSoC
Enpirion EP53x7xQI DC/DC Converter
Module Evaluation Boar d
Introduction
Thank you for c hoosing Alte ra Enpirion power produc ts!
T his applicat ion not e describes how t o t est t he following EP53x7xQI convert ers using the
Altera Enpirion 3x3 Module EVAL BOARD shown in Fig. 1: EP 5367LQI, EP 5367HQI,
EP5387LQI, EP5387HQI, EP53A7LQI, and EP53A7HQI. In a ddition to this document
you will also ne ed the devic e da ta shee t.
T he EP53x7xQ I converters are part of a new cl ass o f DC/DC converter products, a
complet e power system on silicon:
• These devices are complete modules including magnetics, and re quire only
cer amic input and output capacit ors.
• T he evaluat ion board is designed to offer a wide range of engineering evaluation
cap abilities. This includes the base configur at ion of an 0603 input ca pac itor and
an 0805 output capacitor.
• Pads ar e available to add up t o one additional input capacit or and up t o two
addit ional out put capacit ors to allow f or evaluat ion of per formance over a wide
r ange of input / output capacitor combinat ions.
• Pads are available to populate an external divider if desired.
• E asy jumpers are provided for t he following signals:
o Adaptive-biased light load mode (LLM)
o Enable
o VS0-VS3 output voltage select
• Numer ous test point s are pr ovided as well as clip leads for input and out put
connections
• T he board comes wit h input decoupling, and input reverse pol ari ty protecti on to
safeguard the devic e from common se tup mishaps.
Quick Start Guide
STEP 1: Se t the “ENA BLE” jumper to the Disable Position.
CAUTION: t he signal pins LLM, ENA, VS0, VS1, VS2, and
VS3 mus t be connected t o a logic “high”, jumper to t he lef t, or a
logic “low”, jumper to the right. If l eft fl oati n g th e state i s
indeterminate.
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ST E P 2: Connect a power supply t o t he input test points, TP8 (+ ) and T P5 (-) a s
indicat ed in F igure 1. T he same t est points can also be used t o measure t he input volt age.
CAUTION: be mindful of the polar ity and the volt age magnit ude. I f VIN is
gr eater than 6V, the board may get damaged. I f t he input volt age polarit y is
wr ong, diode D1 will conduct, and dr aw excessive input curr ent .
STEP 3: Set t he out put volt age select pins for t he desired out put voltage. Refer to Tables
1 a nd 2 to det ermine the set ting.
CAUTION: the external resistor divider is not popula ted in
the s tanda rd boa rd configura tion. Choosing the “EXT” option
f or t he E P53x7LQI without the exte rna l resis tors R1 a nd R2
will result in unpredictable behavior.
ST E P 4: Connect t he load to the out put connectors TP7 (+) a nd TP6 (-), as i ndi cated i n
Figure 1.The same test points are also used t o measure the DC output volt age.
ST E P 5: Connect t he L L M jumper as needed. A voltage greater
than 1.4V will enable LLM, and less tha n 0.4V will disable it.
LLM
LLM Enabled
LLM
LLM
LLM Di sabled
LLM
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EP53x7xQI PowerSoC
Figure 1. Evaluation Board L ayout.
STEP 6: Move t he E NABLE jumper to the enabled position, and power up t he board.
T he EP53x7xQ I should now be operat ional.
C
IN
COUT
Decoupling Cap
(to decouple supply cables)
Rever se polarity diode
Output V oltage Select
Out put E nable
Light-Load Mode
Enable
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EP53x7xQI PowerSoC
Output Voltage Select
T ab l e 1. EP53x7LQ I O utput Voltage Select Truth Table
VS3
VS2
VS1
VS0
VOUT
0
0
0
0
1.50
0
0
0
1
1.45
0
0
1
0
1.40
0
0
1
1
1.35
0
1
0
0
1.30
0
1
0
1
1.25
0
1
1
0
1.20
0
1
1
1
1.15
1
0
0
0
1.10
1
0
0
1
1.05
1
0
1
0
1.00
1
0
1
1
0.95
1
1
0
0
0.90
1
1
0
1
0.85
1
1
1
0
0.80
1
1
1
1
EXT
Table 2. EP53x7HQI Output Volt age Select Truth Table
VS3
VS2
VS1
VS0
VOUT
0
0
0
0
3.3
0
0
0
1
3.2
0
0
1
0
3.1
0
0
1
1
3.0
0
1
0
0
2.9
0
1
0
1
2.8
0
1
1
0
2.7
0
1
1
1
2.6
1
0
0
0
2.5
1
0
0
1
2.4
1
0
1
0
2.3
1
0
1
1
2.2
1
1
0
0
2.1
1
1
0
1
2.0
1
1
1
0
1.9
1
1
1
1
1.8
T he E P53x7xQI utilizes a 4 pin out put volt age select scheme. T he out put volt age is
pr ogrammed by set t ing t he VSx jumpers to eit her a logic “1” or a logic “0” as described
in t he Quick St ar t section
Tables 1 and 2 show t he t ruth table f or VOUT selection. There are fifteen preset output
volt age levels f or t he EP53x7LQI, and sixt een pr eset levels f or t he EP53x7H QI.
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Test Recommend atio ns
Recommendations
T o guarantee measurement accur acy, the following precaut ions should be observed:
1. Make all input and output voltage measurements at t he board using the t est
points provided. This will eliminate voltage drop across the line and load
cables that can produce false readings.
2. Measure input and out put curr ent with series ammet ers or accurat e shunt
resistors. This is especially important when mea suring efficie ncy.
3. Use a balan ced imp ed an ce p ro b e tip a s s hown in Figure 2, and through-hole
t est point pair T P2 to measure the output voltage ripple to avoid noise
coupling int o t he pr obe ground lead.
Figur e 2: Balanced-impedance oscilloscope probe. W rap bare w ire ar ound
the ground shaf t and br ing the w ire close to the pr obe tip. This minimizes
probe loop inductance and stray noise pickup by the probe.
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Enpirion® Power Evaluation Board User Guide
EP53x7xQI PowerSoC
Using The External Voltage Divider
T he E P53x7xQI evaluation board is designed t o provide a great deal of flexibi l ity in
evaluating t he perf ormance of the Altera Enpirion DC/DC modul e.
Pre-tinned pads are provided t o place 0805 sized 1% resis tors on the board to imple ment
an e xte rnal resistor divide r for t he EP53x7LQI to choose a n output voltage other than one
of the pre-set voltages available on t he VID. See Figure 3 for the basic circuit.
VIN
VSense
Vin
VS1
VS2
VS0
EP53x7LQI
10µF
2.2uF
V
OUT
V
out
GND
ENABLE
R1
R2
V
FB
Figure 3. External divider s chematic for the EP53x7L QI .
T he output volt age is select ed by t he following formula:
( )
2
1
16.0 R
R
OUT VV +=
R1 mus t be chosen as 237kΩ t o maint ain control loop stability. Then R2 is give n a s:
Ω
−
=6.0
102.142 3
2OUT
Vx
R
The external voltage divider option is chosen by set t ing t he jumpers V S 0 – VS3 to a l ogi c
“high”. Light-loa d mode (LLM) is not ope rationa l whe n using exte rna l re sistor dividers.
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Enpirion® Power Evaluation Board User Guide
EP53x7xQI PowerSoC
Dynamically Adjustable Output
The EP53x7xQI is designed to a llow for dynamic switching bet ween the predef ined
voltage levels by t oggling t he VI D pins . T he int er-voltage sle w rate is optimized to
prevent excess undershoot or overshoot as the output voltage levels transition. The slew
rate is defined in the datasheet.
T his feat ure can be t est ed by connect ing t he VSx jumper center pins to logic driver to
t oggle between the various VOUT states.
Input and Output Capacitors
The input capacitance is a single 0603 X5R MLCC. P lease see the part datasheet for the
ex act v alu e. There are pre-tinned pads that allows for one additional 0603 capacitor to
experiment with input filter performance.
The output capacitance requirement is a s ingle X5R MLCC. Please see t h e d at ash eet for
t h e ex act v alu e. The board has pr e-t inned pads for up to 2 additional 0805 output
capacitors.
NOTE: Ca pacitors must be X5R or X7R die le ctric formulations. D o not use Y5V
or any sim ilar dielectric.
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EP53x7xQI PowerSoC
C3
C4 N/U
C10
FB1
C5 N/U
TP2
1
2
TP1
1
2
0805
0603
J1
ASP12192002
1
2
3
5
6
7
9
10
11
13
14
15
17
18
19
Vin
Vout
Vin
TP6 1
TP81
TP5
1
ENABLE
VS0
VS1
VS2
R1
N/U
R2
N/U
J3
1
2
3
LLM
+
C8
U2
N/U
Vin
TP71
D1
C1 N/U
C2
0805
0805 0805
0603
0805
U1
Enpirion 3x 3 Module
NC(SW)
1
PGND
2
LLM
3
Vfb
4
Vsense
5
AGND
6
VOUT
7
VOUT
8
VS3 9
VS2 10
VS1 11
VS0 12
Enable 13
Vin 14
NC(SW) 15
NC(SW) 16
C9
N/U
0805
0805
VS3
Input Protection
F i gu re 4: 3x3 Mod u l e Eval u at ion Boa rd S ch em a t i c
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EP53x7xQI PowerSoC
Contact Information
Alt era Corporation
101 Innova tion Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Alter a C or por ati on —Confidential. All rights res erved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY,
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in accor danc e with Al ter a' s standar d w ar r anty , but r eser ves the r ight to make c hanges to any pr oducts and ser vices at an y
time w ithout noti ce. Alter a assumes no r esponsibility or lia bi l ity ar ising out of the app li cati on or use of any infor ma ti on,
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