High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
1 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
Revision History
Rev. No. History Issue Date
2.0 Initial issue with new naming rule Dec. 29, 2004
2.1 Update the WRITE CYCLE1 (Write Enable Controlled) waveform Mar. 31, 2005
2.2 Revise VIL from 1.5V to 0.8V Apr. 08, 2005
2.3
2.4
2.5
2.6
Revise VIH, VOH, IOL, ICC, ICCSB, ICCSB1, VDR, ICCDR, tDW
Add 28L PDIP 300mil
Revise ICCSB, ICCSB1 & ICCDR
Revise page 7 data retention waveform (VDR: 1.5V to 2V)
May. 26, 2005
Jul. 04, 2005
Oct. 06, 2005
May. 16, 2006
2.7 Revise DC characteristics Dec. 13, 2006
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
2 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
GENERAL DESCRIPTION
The CS18LV02565 is a high performance, high speed and super low power CMOS Static Random
Access Memory organized as 32,768 words by 8bits and operates for a single 4.5 to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high speed, super low power features
and maximum access time of 55/70ns in 5.0V operation. Easy memory expansion is provided by an
active LOW chip enable (/CE) and active LOW output enable (/OE).
The CS18LV02565 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV02565 is available in JEDEC standard 28-pin TSOP I
(8x13.4 mm), SOP (330 mil), PDIP (600 mil) and PDIP (300 mil) packages.
FEATURES
Wide operation voltage : 4.5 ~ 5.5V
Ultra low power consumption : 2mA＠1MHz (Max.) , Vcc=5.0V.
10 uA (Max.) CMOS standby current
High speed access time : 55/70ns.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 2.0V.
Easy expansion with /CE and /OE options.
PRODUCT FAMILY
Product Family Operating Temp. Vcc Range Speed (ns)
Standby Current(typ.)
ICCSB1
Package Type
28 SOP
28 TSOP I
28 PDIP
0~70oC 55/70
1.5 uA
(Vcc = 5.0V)
Dice
28 SOP
28 TSOP I
28 PDIP
CS18LV02565
-40~85oC
4.5~5.5V
55/70 2.0 uA
(Vcc= 5.0V)
Dice
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
3 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
PIN CONFIGURATIONS
OE A10
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
27
20
15
16
17
18
19
21
22
23
24
25
26
28
2
9
12
14
13
11
10
6
8
7
5
4
3
1
28TSOP(I)-8x13.4mm
FUNCTIONAL BLOCK DIAGRAM
Address
Input
Buffer
Row
Decoder 512x512
Memory Array
Data Output
Buffer
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
Control
Column I/O
Data Input
Buffer
A6
A7
A8
A9
A11
A12
A13
DQ0
DQ7
18 512
88
88
512
64
12
A0 A1 A2 A3 A4 A10
/WE
/OE
/CE
VCC
GND
A5
A14
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
4 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
PIN DESCRIPTIONS
Name Type Function
A0 – A14 Input Address inputs for selecting one of the 32,768 x 8 bit words in the RAM
/CE Input
/CE is active LOW. Chip enable must be active when data read from or write to the
device. If chip enable is not active, the device is deselected and in a standby power
mode. The DQ pins will be in high impedance state when the device is deselected.
/WE Input
The Write enable input is active LOW. It controls read and write operations. With the
chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the
DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
/OE Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when /OE is inactive.
DQ0~DQ7 I/O These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc Power Power Supply
Gnd Power Ground
TRUTH TABLE
Mode /CE /WE /OE DQ0~7 Vcc Current
Standby H X X High Z ICCSB, ICCSB1
Output Disabled L H H High Z ICC
Read L H L DOUT I
CC
Write L L X DIN I
CC
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
5 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Rating Unit
VCC Supply voltage, Vcc -0.5 to +7 V
VTERM Terminal Voltage with Respect to GND -0.5 to +7 V
TBIAS Temperature Under Bias -40 to +125 OC
TSTG Storage Temperature -60 to +150 OC
PT Power Dissipation 1.0 W
IOUT DC Output Current 20 mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Ambient Temperature Vcc
Commercial 0~70oC 4.5~5.5V
Industrial -40~85oC 4.5~5.5V
CAPACITANCE(1)(TA=25℃,f=1.0MHz)
Symbol Parameter Conduction MAX. Unit
CIN Input Capacitance VIN=0V 6 pF
CDQ Input/Output Capacitance VI/O=0V 8 pF
1. This parameter is guaranteed, and not 100% tested.
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
6 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
DC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V)
Name Parameter Test Condition MIN MAX Unit
VIL Guaranteed Input Low
Voltage
Vcc=5.0V -0.5(1) 0.8
V
VIH Guaranteed Input High
Voltage
Vcc=5.0V 2.2 Vcc+0.2(2) V
IIL Input Leakage Current VCC=MAX, VIN=0 to VCC -1 1
uA
IOL Output Leakage Current
VCC=MAX, /CE=VIN, or /OE=VIN ,
VIO=0V to VCC
-1 1
uA
VOL Output Low Voltage VCC=MAX, IOL = 2.1mA 0.4
V
VOH Output High Voltage VCC=MIN, IOH = -1mA 2.4
V
ICC Operating Power Supply
Current
/CE=VIL, IDQ=0mA,
F=FMAX =1/ tRC 30
mA
ICCSB TTL Standby Supply /CE=VIH, IDQ=0mA, 2.0
mA
ICCSB1 CMOS Standby Current
/CE≧VCC-0.2V, VIN≧VCC-0.2V or
VIN≦0.2V, 10
uA
1. Undershoot : -2.0V in case of pulse width ≤ 20ns
2. Overshoot : Vcc +2.0V in case of pulse width ≤ 20ns
DATA RETENTION CHARACTERISTICS ( TA = 0o ~70oC)
Name Parameter Test Condition MIN Typ (2) MAX Unit
VDR VCC for Data Retention /CE ≧VCC-0.2V, VIN ≧
VCC-0.2V or VIN≦0.2V 2.0 V
ICCDR Data Retention Current /CE≧VCC-0.2V, VCC=2V
VIN≧VCC-0.2V or VIN≦0.2V 0.5 2.0 uA
TCDR Chip Deselect to Data
Retention Time 0 ns
tR Operation Recovery Time
Refer to
Retention Waveform
t
RC (1) ns
1. tRC= .Read Cycle Time.
2. TA=25 OC
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
7 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled )
AC TEST CONDITIONS KEY TO SWITCHING WAVEFORMS
Input Pulse Levels Vcc/0V WAVEFORMS INPUTS OUTPUTS
Input Rise and Fall Times 5ns MUST BE STEADY MUST BE STEADY
Input and Output Timing
Reference Level 0.5Vcc MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
TO L
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
PERMITTED
CHANGE STATE
UNKNOWN
DOES NOT APPLY CENTER LINE IS HIGH
IMPEDANCE OFF STATE
AC TEST LOADS AND WAVEFORMS
FIGURE 1A
FIGURE 1B
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
8 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
AC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V )
< READ CYCLE >
-55 -70 JEDEC
Name Symbol Description MIN MAX MIN MAX Unit
tAVAX t
RC Read Cycle Time 55 70 ns
tAVQV t
AA Address Access Time 55 70
ns
tELQV t
ACE Chip Select Access Time 55 70
ns
tGLQV t
OE Output Enable to Output
Valid
30 50
ns
tELQX t
CLZ Chip Select to Output Low Z 10 10 ns
tGLQX t
OLZ Output Enable to Output in
Low Z
5 5 ns
tEHQZ t
CHZ Chip Deselect to Output in
High Z
0 35 0 35 ns
tGHQZ t
OHZ Output Disable to Output in
High Z
0 30 0 30 ns
tAXOX t
OH Address Change to Out
Disable
10 10 ns
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tAA
tOH tOH
tRC
ADDRESS
DOUT
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
9 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
READ CYCLE2 (1,3,4)
READ CYCLE3 (1,4)
t
AA
t
OH
t
RC
ADDRESS
t
CE
t
CLZ
(5)
t
CHZ
(5)
CE
D
OUT
OE
t
OHZ
(1,5)
t
OE
t
OLZ
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. /OE = VIL.
5. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input
pulse levels of 0V to VCC and output loading specified in Figure 1A.
6. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
10 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
AC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V )
< WRITE CYCLE >
-55 -70 JEDEC
Name Symbol Description MIN MAX MIN MAX Unit
tAVAX t
WC Write Cycle Time 55 70 ns
tE1LWH t
CW Chip Select to End of Write 55 70 ns
tAVW L t
AS Address Setup Time 0 0 ns
tAVW H t
AW Address Valid to End of Write 55 70 ns
tWLWH t
WP Write Pulse Width 40 50 ns
tWHAX t
WR Write Recovery Time 0 0 ns
tWLQZ t
WHZ Write to Output in High Z 25 35 ns
tDVWH t
DW Data to Write Time Overlap 20 30 ns
tWHDX t
DH Data Hold for Write End 0 0 ns
tGHQZ t
OHZ Output Disable to Output in
High Z
0 30 0 30 ns
tWHOX t
OW End of Write to Output Active 5 5 ns
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
11 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (Write Enable Controlled)
WRITE CYCLE2 (Chip Enable Controlled)
High Speed Super Low Power SRAM
32K-Word By 8 Bit CS18LV02565
12 Rev. 2.7
Chiplus reserves the right to change product or specification without notice.
NOTES:
1. /WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active
to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold
timing should be referenced to the second transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of /CE or /WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output
remain in a high impedance state.
6. It’s recommended to keep /OE at high (/OE = VIH ) as /WE Controlled WRITE CYCLE.
7. DOUT is the read data of next address.
8. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
9. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input pulse
levels of 0V to VCC and output loading specified in Figure 1A.
10. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
11. TCW is measured from the later of /CE going low to the end of write.
ORDER INFORMATION
Note: Package material code “R” meets ROHS
