RECORDS OF REVISION Type NoLQ0DZC2291 SPEC No. Date NO. LCY-09033A 2009. 06.05 LCY09033B 2009.12.8 PAGE SUMMARY NOTE - - 1st Issue 22 Connection of terminal STHR/STHL and 2nd Issue LCD. Note: In this ASIC Specification, binary notation, decimal notation and hexadecimal notation are described according to the rules below. Binary notation: Double quotation marks are used, e.g., "111000" or "1001". Otherwise, `b' is appended, e.g., 111000b. Hexadecimal notation: `0x' is used, e.g., 0x3F or 0x2D. Otherwise, `H' is appended, e.g., 20H or 1000H. Decimal notation: Unless binary notation and hexadecimal notation are used, decimal notation is used. LCY-09033B-1 - CONTENTS - Overview and Features of Product ...................................................................................................................................... 3 1. 1.1. Product Overview.................................................................................................................................................... 3 1.2. Main Features ......................................................................................................................................................... 3 1.3. Block diagram ......................................................................................................................................................... 3 2. Pin Description .................................................................................................................................................................... 5 2.1. Pin Layout............................................................................................................................................................... 5 2.2. Pin Settings............................................................................................................................................................. 7 3. Absolute Maximum Ratings ..................................................................................................................................................... 8 4. Electrical Specification ............................................................................................................................................................. 8 4.1. Recommended Operating Range...................................................................................................................................... 8 4.2. DC Electrical Specification ................................................................................................................................................ 9 4.3. AC Electrical Specification................................................................................................................................................. 9 5. Register Map ......................................................................................................................................................................... 10 6. Conditions for Input Signal ................................................................................................................................................ 11 6.1. Conditions for Image Signal Input ......................................................................................................................... 11 6.2. Horizontal timing 1 HENAB = Active input............................................................................................................. 13 6.3. Horizontal timing 2 HENAB = Fixed to Lo ............................................................................................................. 13 6.4. Vertical timing 1 HENAB = Active input................................................................................................................. 14 6.5. Vertical timing 2 HENAB = Fixed to Lo.................................................................................................................. 14 6.6. Horizontal/Vertical Data Capture Position ............................................................................................................. 14 7. Serial Input Conditions (I2C) ............................................................................................................................................. 15 7.1. Protocol................................................................................................................................................................. 15 7.2. Serial Interface AC Characteristics ....................................................................................................................... 16 7.3. Instruction to Write/Read to/from ASIC ................................................................................................................. 17 8. Description of Function and Supported Register ............................................................................................................... 18 8.1. Outline of Loading................................................................................................................................................. 18 8.2. Description of Register Regarding Loading .......................................................................................................... 18 9. Power ON Sequence......................................................................................................................................................... 19 10. I/O Format ......................................................................................................................................................................... 20 11. FreeRun Display................................................................................................................................................................ 21 11.1. Overview of FreeRun Display ............................................................................................................................... 21 11.2. Conditions for Transition to FreeRun .................................................................................................................... 21 11.3. Conditions for Recovery from FreeRun................................................................................................................. 21 12. Horizontal/Vertical Reverse Display................................................................................................................................... 22 13. RGB Independent Gamma Correction............................................................................................................................... 23 13.1. Overview of RGB Independent Gamma Correction .............................................................................................. 23 13.2. Description of Register Regarding RGB Independent Gamma Correction ........................................................... 23 13.3. Flow of Use of Independent Gamma Function...................................................................................................... 23 14. EEPROM........................................................................................................................................................................... 24 14.1. EEPROM .............................................................................................................................................................. 24 14.2. Recommended EEPROM ..................................................................................................................................... 24 14.3. Description of Register Regarding EEPROM........................................................................................................ 24 14.4. How to Write/Read to/from EEPROM ................................................................................................................... 24 14.5. ROM_Map of EEPROM ........................................................................................................................................ 25 15. Control of D/A Converter (hereinafter referred to as "DAC").............................................................................................. 26 15.1. Overview of DAC Control...................................................................................................................................... 26 Page 1 LCY-09033B-2 15.2. Recommended Component for DAC .................................................................................................................... 26 15.3. Description of Register Regarding DAC Control ................................................................................................... 26 15.4. Actual Usage......................................................................................................................................................... 27 16. Control of A/D Converter (hereinafter referred to as "ADC").............................................................................................. 28 16.1. Overview of ADC Control ...................................................................................................................................... 28 16.2. Recommended Component for ADC..................................................................................................................... 28 17. Output I/F to LCD .............................................................................................................................................................. 29 17.1. Example of Horizontal Timing ............................................................................................................................... 29 17.1.1. Horizontal Timing for Horizontal Resolution 800 Dots (WVGA) ........................................................................29 17.1.2. Horizontal Timing for Horizontal Resolution 480 Dots (WEGA1/WEGA2).........................................................30 17.1.3. Horizontal Timing for Horizontal Resolution 400 Dots (WQVGA)......................................................................31 17.2. Example of Vertical Timing.................................................................................................................................... 32 17.2.1. Vertical Timing for Vertical Resolution 480 Lines (WVGA)................................................................................32 17.2.2. Vertical Timing for Vertical Resolution 240 Lines (WQVGA/WEGA2) ...............................................................34 17.2.3. Vertical Timing for Vertical Resolution 272 Lines (WEGA1)..............................................................................36 18. Cautions on storage............................................................................................................................................................. 37 18.1. Storage environment ..................................................................................................................................................... 37 18.2. Storage methods ........................................................................................................................................................... 37 18.3. Long-term storage ......................................................................................................................................................... 37 19. Recommended soldering condition of infrared reflow .......................................................................................................... 39 20. Outline drawings .................................................................................................................................................................. 40 21. Marking ................................................................................................................................................................................ 41 22. Tray container ...................................................................................................................................................................... 42 23.Packing outline drawing ........................................................................................................................................................ 43 24. Carton .................................................................................................................................................................................. 44 Page 2 LCY-09033B-3 1. Overview and Features of Product 1.1. Product Overview This product is a timing controller for liquid crystal module to display four kinds of resolutions, i.e., WVGA (800RGB[H] x 480[V], WQVGA (400RGB[H] x 240[V]), WEGA1 (480RGB[H] x 272[V]) and WEGA2 (480RGB[H] x 240[V]). Moreover, RGB independent gamma can be controlled by adding external EEPROM. This controller has an auto-loading function. After resetting, the controller reads the register set values/independent gamma parameters from the external EEPROM and works according to the set values. 1.2. Main Features a) Timing controller (for WVGA, WQVGA, WEGA1 and WEGA2) contained b) ROMOFF setting (It can be specified whether external EEPROM should be disabled or enabled.) c) HSY/VSY input monitoring function. ("Free Run" is shown when HSY/VSY has not yet been input and when an error has been occurred in input.) d) Free Run Display (Blue background screen 1H = 1200 clk or more/1V = 700 Lines or more e) Horizontal/vertical reverse display available. f) Independent gamma setting (supported only for ROMOFF = 0) g) External D/A Converter 8ch control output supported (only for ROMOFF = 0) h) External A/D Converter 2ch control output supported (only for ROMOFF = 0) i) Internal register control with I2C (only for ROMOFF = 0) 1.3. Block diagram Figure 1-1 shows a simplified block diagram of LQ0DZC2291. DCLK RGB control signal Input I/F Gamma correction Waveform shaping/judgment LUT Blue background display Video signal Synchronization signal CMOS I/F CMOS LCD LCD control signal T-CON Internal control uCom Register I2C LUT/Reg Loader Slave DAC Ctrl ADC Ctrl DAC ADC I2C Master EEPROM Figure 1-1: Simplified Block Diagram of LQ0DZC2291 Page 3 LCY-09033B-4 Overview of block diagram is described below. (1) Input I/F Receives 18-bit parallel data input externally and passes it to the image processing block stated below. Waveform shaping (Hsy/Vsy phase difference absorption), pulse noise elimination (pulse of 2 clk or less) from control signal and synchronization signal input judgment are performed here. (2) Blue background display A block to generate the blue background display when Input I/F of (1) has judged that there is no synchronization signal input. (3) Gamma correction The gamma correction function allows to process input video data per RGB data and adjust the gamma curve per R, G and B. (This is available only for ROMOFF = `0'.) (4) T-CON A block of timing controller to drive a panel of four kinds of resolutions, i.e., WVGA, WQVGA, WEGA1 and /WEGA2. (5) LUT/Reg_Loader A block to read a data from the external EEPROM, which is connected to have an initial value of an ASIC's internal register and internal LUT, and to update the data for the register and LUT. (6) DAC Ctrl External D/C converter can be connected and controlled to set up the liquid crystal display gradation and specify the COM signal. In this block, a control signal to DAC is generated to control DAC. (7) ADC Ctrl External A/D converter can be connected and controlled. This block receives a signal from ADC and stores a data in the internal register of ASIC. Thermistor and photo sensor can be connected and monitored, by way of example. Page 4 LCY-09033B-5 2. Pin Description 2.1. Pin Layout Table 2-1 describes all the pins. Table 2-1: Pin Description I/O Attribute Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 - I I I I I I I I I I I I Id VDD IG0 IG1 IG2 IG3 IG4 IG5 IB0 IB1 IB2 IB3 IB4 IB5 ROMOFF 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Iu Iu Id Id O I Id Iu Id Iu - - I - Isu - Id Id Id Id Id - Iou Iu O O O - O O IOu - O O IOu - VRVC HRVC SMC GMDSEL SOUT TMC AMC VSY HENAB HSY VDD GND DCLK GND FRESET VDD S_SEL G_SEL DSEL1 DSEL2 TEST1 GND SERDIO SERCK ADCCK ADCCS ADCDI ADCDO DACDI DACLD DACCK GND ROMCK ROMWC ROMDIO GND PIN No. Drive Power Description of Function Green data input pin (LSB) Green data input pin Green data input pin Green data input pin Green data input pin Green data input pin (MSB) Blue data input pin (LSB) Blue data input pin Blue data input pin Blue data input pin Blue data input pin Blue data input pin (MSB) Setting whether external EEPROM should be disabled or enabled Vertical scan reversal Horizontal scan reversal ASIC test pin Gate start pulse output setting ASIC test pin ASIC test pin ASIC test pin Vertical synchronization signal input pin Horizontal data enable input pin Horizontal synchronization signal input pin Operation when it is not be used OPEN/GND OPEN OPEN/GND OPEN/GND Clock input pin ASIC reset pin Source driver setting pin Gate driver setting pin Resolution setting pin 1 Resolution setting pin 2 ASIC test pin GND 3mA 3mA 3mA Serial data I/O pin Serial clock input pin ADC clock output pin ADC chip select output pin ADC control data output pin ADC data input pin DAC data output pin DAC load output pin DAC clock output pin OPEN OPEN/VDD OPEN OPEN OPEN OPEN/VDD OPEN OPEN OPEN 3mA 3mA 3mA EEPROM clock output pin EEPROM write protect output pin EEPROM data I/O pin OPEN OPEN OPEN 3mA 3mA 3mA 3mA Page 5 LCY-09033B-6 PIN No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I: Input pin I/O Attribute Pin Name - O O O O O O - O O O O O O - O O O O O O - IO IO - - O - O O O O IO O IO O O I Id O O O - I I I I I I - VDD OR0 OR1 OR2 OR3 OR4 OR5 GND OG0 OG1 OG2 OG3 OG4 OG5 VDD OB0 OB1 OB2 OB3 OB4 OB5 GND STHR STHL VDD GND CLK GND STB REV FS REVC LBR GSPOI MODE2 R/L GSPIO SPS GOE MODE1 GCK CLS TEB TEST2 ALLON DCON G_SLP VDD IR0 IR1 IR2 IR3 IR4 IR5 GND O: Output pin IO: I/O pin Drive Power Operation when it is not be used Description of Function 6mA 6mA 6mA 6mA 6mA 6mA Red data output pin (LSB) Red data output pin Red data output pin Red data output pin Red data output pin Red data output pin (MSB) 6mA 6mA 6mA 6mA 6mA 6mA Green data output pin (LSB) Green data output pin Green data output pin Green data output pin Green data output pin Green data output pin (MSB) 6mA 6mA 6mA 6mA 6mA 6mA Blue data output pin (LSB) Blue data output pin Blue data output pin Blue data output pin Blue data output pin Blue data output pin (MSB) 6mA 6mA * Start pulse I/O signal 1 * Start pulse I/O signal 12mA Source driver sampling clock 6mA 6mA 6mA 3mA 3mA 3mA 3mA 3mA 3mA Source driver latch pulse output Source driver polarity reversal control output * Offset cancel / COM polarity reversal signal output Source driver horizontal reversal control output * Gate start pulse / Gate mode setting pin Gate driver vertical reversal control output * Gate start pulse * Gate driver control output * Gate driver shift clock ASIC test pin ASIC test pin Full gate output ON setting output Power supply circuit control output Gate slope control pin 3mA 3mA 3mA 1 VDD GND OPEN OPEN Red data input pin (LSB) Red data input pin Red data input pin Red data input pin Red data input pin Red data input pin (MSB) d: Pull-down for input pin 1 * Table 12-3 on page 22. 2 * Refer to Table 2-2 on page 10. Page 6 u: Pull-up for input pin su: Schmitt input pin LCY-09033B-7 2.2. Pin Settings Table 2-2 describes the pin settings. Table 2-2: Pin Settings Pin name S_SEL (*) G_SEL (*) VRVC HRVC Function Source setting pin For how to set this pin, ask the person in charge of Sharp Corporation. Gate setting pin For how to set this pin, ask the person in charge of Sharp Corporation. Gate driver scan direction setting Refer to Chapter 11 "Horizontal/Vertical Reverse Display". Source driver scan direction setting Refer to Chapter 11 "Horizontal/Vertical Reverse Display". Gate start pulse output setting GMDSEL Lo: Normal mode Hi: Interlacing two-pulse mode D_SEL1 (*) Input resolution switch setting pin Resolution D_SEL2 (*) D_SEL1 D_SEL2 WVGA 0 0 WQVGA 1 0 WEGA1 0 1 WEGA2 1 1 EEPROM setting pin Lo: EEPEOM is enabled. ROMOFF (*) Hi: EEPEOM is disabled. If ROMOFF is set to `1', this ASIC is used as a timing controller. Therefore, register control, DAC control, etc. cannot be performed. FRESET Reset pin (Lo-Active) * Time constant shall be 10 ms or less. Refer Figure 2-1. Do not change any setting of pins marked with *, after the ASIC power supply turns ON. 3.3 V 90% FRESET 0V 10% T 10 ms Figure 2-1 FREST Time Constant Page 7 LCY-09033B-8 3. Absolute Maximum Ratings Table 3-1: Absolute Maximum Ratings Parameter Symbol Supply voltage Rating Unit VDD -0.5 to +4.6 V Input voltage VI -0.5 to +4.6 V Output voltage VO -0.5 to +4.6 V Operating temperature TA -40 to +85 Storage temperature Tstg -65 to +150 4. Electrical Specification 4.1. Recommended Operating Range Table 4-1: Recommended Operating Range Parameter Symbol 1 Supply voltage* Min. Typ. Max. Unit VDD 2.7 3.15 3.6 V TA -40 85 1 VIH 2.00 VDD V Input voltage, low* VIL 0 0.8 V Positive trigger voltage VP 1.4 2.4 V Negative trigger voltage VN 0.8 1.6 V Hysteresis voltage VH 0.3 1.5 V Input rise time tri 0 200 ns Input fall time tfi 0 200 ns Input rise time tri 0 10 ms Input fall time tfi 0 10 ms Ambient temperature Input voltage, high* * Condition Schmitt Buffer Schmitt Buffer The following Supply voltage conditions operate. Condition1 Parameter Symbol Min. Supply voltage VDD Input voltage, high Input voltage, low Typ. Max. Unit 3.0 3.6 V VIH 0.7VDD VDD V VIL 0 0.3VDD V Symbol Min. Max. Unit Supply voltage VDD 2.7 3.0 V Input voltage, high VIH 0.75VDD VDD V Input voltage, low VIL 0 0.25VDD V Condition2 Parameter Page 8 Typ. LCY-09033B-9 4.2. DC Electrical Specification Table 4-2: DC Electrical Specification Parameter Symbol Condition Static current consumption IDDS VI=VDD or GND 300 A Off-state output current IOZ V0=VDD or GND 10 A Output short-circuit current IOS V0=GND -250 mA II VI=VDD or GND 1.0 A II VI=GND (pull-up 50k) -28 -83 -190 A II VI=VDD (pull-down 50k) 28 83 190 A Pull-up resistor (50k) RPU VI=GND 18.9 39.8 107.1 k Pull-down resistor (50k) RPD VI=VDD 18.9 39.8 107.1 k Output current,low IOL VOL=0.4V (IOL=3mA type) 3.0 mA VOL=0.4V (IOL=6mA type) 6.0 mA VOL=0.4V (IOL=12mA type) 12.0 mA VOH=2.4V (IOL=3mA type) -3.0 mA VOH=2.4V (IOL=6mA type) -6.0 mA VOH=2.4V (IOL=12mA type) -12.0 mA Input leakage current Output current,high IOH Min. Typ. Max. Unit 4.3. AC Electrical Specification Table 4-3: AC Electrical Specification Parameter Symbol Condition Output rise time tr Output buffer CL=15pF 2 10 ps Output fall time tr Output buffer CL=15pF 2 10 ps Page 9 Min. Typ. Max. Unit LCY-09033B-10 5. Register Map Table 5-1 shows the register map list of LQ0DZC2291. Table 5-1: Register Map List address bit7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh gamma_enb 0Fh 10h bit6 20h 21h 22h 23h 24h 25h 30h 31h 32h 33h 34h 35h bit5 bit4 bit3 bit2 da_0ch[7:0] da_1ch[7:0] da_2ch[7:0] da_3ch[7:0] da_4ch[7:0] da_5ch[7:0] da_6ch[7:0] da_7ch[7:0] henab[7:0] venab[7:0] rsel stb_hl[6:0] gck_hl[7:0] slp_ctrl[6:0] test test - bit1 bit0 vrvc hrvc r_read r_write jinput allon als jenable rom_adrs[7:0] rom_data[7:0] test test test ready test adc_data1 adc_data2 : Register for auto-loading als register value 0: Inaccessible. als register value 1: Write/Read can be done from a host. : Register not for auto-loading als register value 0: Inaccessible als register value 1: Write/Read can be done from a host. : Register not for auto-loading Regardless of the als register value, Write/Read can be done. : Read-Only register Regardless of the als register value, Read only can be done. Page 10 Initial value 0000_0000b 0000_0000b 0000_0000b 0000_0000b 0000_0000b 1111_1111b 0111_1000b 0000_0000b 1100_0010b 0010_0011b 0000_0000b 0100_0101b 1010_1010b 0100_0011b 0000_0000b 0000_0000b 0000_0000b LCY-09033B-11 6. Conditions for Input Signal 6.1. Conditions for Image Signal Input Table 6-1 to Table 6-4 and Figure 6-1 to Figure 6-4 show the input range specifications for the WVGA, WQVGA, WEGA1 and WEGA2 modes. Also, Table 6-5 shows the horizontal/vertical display data capture position list in the WVGA, WQVGA, WEGA1 and WEGA2 display modes. Table 6-1: WVGA Input Timing Specifications WVGA [D_SEL1=0, D_SEL2=0] ITEM Frequency DCLK Hi_Time Low Width Setup time Data[I* 0-5] Hold time Symbol tCLK tWCH tWCL tDS tDH tH(t) tH(clk) tHPW tV tVPW fV tHA tHC tVH tVFP Min. Typ. 26.62 33.26 5 5 5 5 31.45 31.75 Cycle 1024 1056 Hsy 5 Pulse Width 520 525 Cycle Vsy 2 Pulse Width 50 60 frame rate 800 Horizontal display period A-8 A Hsy_DCLK phase defference -10 0 Hsy_Vsy phase defference 5 Vertical fromt porch 35 Vertical back porch tVBP 10 28 480 Vertical display porch tVA 5 Setup time tES 5 Enable signal[HENAB] Hold time tEH Pulse Width 800 tEP Horizontal front porch 2 tHFP 194 tHBP Horizontal display starting position tHBP 20 *1: This spec is appied for HENAB Lo mode and W/O EEPROM mode *2: This spec is applied for HENAB active mode or W/EEPROM mode Max. 34.60 38.46 1088 tH-5 635 TV-2 60 A+8 10 35 222 UNIT MHz ns ns ns ns s ck ck line line Hz ck ns ck line line line line ns ns ck ck Remark Frequency:1/(tV/tH(clk)) A=tWCH(1/2(DCLK)) In case ROMOFF='1' In case ROMOFF='0' *1 *2 Table 6-2: WQVGA Input Timing Specifications WQVGA [D_SEL1=1, D_SEL2=0] ITEM Frequency DCLK Hi_Time Low Width Setup time Data[I* 0-5] Hold time Symbol tCLK tWCH tWCL tDS tDH tH(t) tH(clk) tHPW tV tVPW fV tHA tHC tVH tVFP Min. Typ. 6.96 7.99 5 5 5 5 61.3 63.6 Cycle 491 508 Hsy 5 Pulse Width 258 262 Cycle Vsy 2 Pulse Width 50 60 frame rate 400 Horizontal display period A-8 A Hsy_DCLK phase defference -10 0 Hsy_Vsy phase defference 5 Vertical fromt porch 20 Vertical back porch tVBP 9 240 Vertical display porch tVA 5 Setup time tES 5 Enable signal[HENAB] Hold time tEH Pulse Width 400 tEP Horizontal front porch 2 tHFP 87 tHBP Horizontal display starting position tHBP 20 *1: This spec is appied for HENAB Lo mode and W/O EEPROM mode *2: This spec is applied for HENAB active mode or W/EEPROM mode Page 11 Max. 9.19 70.5 563 TH-5 284 TV-2 60 A+8 10 20 126 UNIT MHz ns ns ns ns s ck ck line line Hz ck ns ck line line line line ns ns ck ck Remark Frequency:1/(tV/tH(clk)) A=tWCH(1/2(DCLK)) In case ROMOFF='1' In case ROMOFF='0' *1 *2 LCY-09033B-12 Table 6-3: WEGA1 Input Timing Specifications WEGA1 [D_SEL1=0, D_SEL2=1] ITEM Frequency DCLK Hi_Time Low Width Setup time Data[I* 0-5] Hold time frame rate Horizontal display period Hsy_DCLK phase defference Hsy_Vsy phase defference Vertical fromt porch Symbol tCLK tWCH tWCL tDS tDH tH(t) tH(clk) tHPW tV tVPW fV tHA tHC tVH tVFP Vertical back porch tVBP Hsy Vsy Cycle Pulse Width Cycle Pulse Width Min. 8.58 5 5 5 5 58.8 571 5 283 2 50 A-8 -10 2 9 Typ. 9.70 Max. 10.99 - - 64.1 622 66.5 646 tH-5 344 TV-2 60 312 50 480 A 0 31 272 tVA 5 tES 5 tEH 480 tEP 2 tHFP 116 tHBP Horizontal display starting position tHBP 20 *1: This spec is appied for HENAB Lo mode and W/O EEPROM mode *2: This spec is applied for HENAB active mode or W/EEPROM mode Vertical display porch Setup time Enable signal[HENAB] Hold time Pulse Width Horizontal front porch A+8 10 41 164 UNIT MHz ns ns ns ns s ck ck line line Hz ck ns ck line line line line ns ns ck ck Remark Frequency:1/(tV/tH(clk)) A=tWCH(1/2(DCLK)) In case ROMOFF='1' In case ROMOFF='0' *1 *2 Table 6-4: WEGA2 Input Timing Specifications WEGA2 [D_SEL1=1, D_SEL2=1] ITEM Frequency DCLK Hi_Time Low Width Setup time Data[I* 0-5] Hold time Symbol tCLK tWCH tWCL tDS tDH tH(t) tH(clk) tHPW tV tVPW fV tHA tHC tVH tVFP Min. Typ. 8.35 9.59 5 5 5 5 61.3 63.6 Cycle 589 610 Hsy 5 Pulse Width 258 262 Cycle Vsy 2 Pulse Width 50 60 frame rate 480 Horizontal display period A-8 A Hsy_DCLK phase defference -10 0 Hsy_Vsy phase defference 2 Vertical fromt porch 20 Vertical back porch tVBP 9 240 Vertical display porch tVA 5 Setup time tES 5 Enable signal[HENAB] Hold time tEH Pulse Width 480 tEP Horizontal front porch 2 tHFP 104 tHBP Horizontal display starting position tHBP 20 *1: This spec is appied for HENAB Lo mode and W/O EEPROM mode *2: This spec is applied for HENAB active mode or W/EEPROM mode Page 12 Max. 11.17 70.5 685 TH-5 284 TV-2 60 A+8 10 20 152 UNIT MHz ns ns ns ns s ck ck line line Hz ck ns ck line line line line ns ns ck ck Remark Frequency:1/(tV/tH(clk)) A=tWCH(1/2(DCLK)) In case ROMOFF='1' In case ROMOFF='0' *1 *2 LCY-09033B-13 6.2. Horizontal timing 1 HENAB = Active input tH HSY 0.7HVDD tWHL 0.3HVDD tCLK tWCH tHC tHC DCLK tES tHBP tWCH tHFP tEH HENAB tDH tHA tDS InData Figure 6-1: WVGA/WQVGA/WEGA1/WEGA2 Input Data Format (HENAB active/horizontal timing) "InData" above shows the image signal bus of IR0-5, IG0-5 and IB0-5 collectively. This applies to any "InData" after this. 6.3. Horizontal timing 2 HENAB = Fixed to Lo tH HSY 0.7HVDD tWHL 0.3HVDD tCLK tWCH tHC tHC DCLK tWCH tHBP tHFP HENAB tDH tHA tDS InData Figure 6-2: WVGA/WQVGA/WEGA1/WEGA2 Input Data Format (HENAB_Lo fixed/horizontal timing) Page 13 LCY-09033B-14 6.4. Vertical timing 1 HENAB = Active input tV tWVL 0.7HVDD VSY 0.3HVDD tVH tVH HSY 0.7HVDD tVFP tVBP HENAB tVA InData Figure 6-3: WVGA/WQVGA/WEGA1/WEGA2 Input Data Format (HENAB active/vertical timing) 6.5. Vertical timing 2 HENAB = Fixed to Lo tWVL 0.7HVDD VSY 0.3HVDD tVH tVH HSY tVBP tVFP HENAB tVA InData Figure 6-4: WVGA/WQVGA/WEGA1/WEGA2 Input Data Format (HENAB_Lo fixed/vertical timing) 6.6. Horizontal/Vertical Data Capture Position Table 6-5: Horizontal/Vertical Data Capture Position in WVGA/WQVGA/WEGA1/WEGA2 Display Mode HENAB input type Fixed to Lo Active input ROMOFF setting tHBP tVBP 0 A B 1 Each condition for input signal 0 DENAB 1 DENAB A: Decided according to a henab register set value. B: Decided according to a venab register set value. Page 14 tHBP Each condition for input signal tVBP B Each condition for input signal tVBP LCY-09033B-15 7. Serial Input Conditions (I2C) 7.1. Protocol Figure 7-1 shows the protocol for I2C used for LQ0DZC2291. SERCK SERDIO START Condition SDA Input SERCK 1 SERDIO MSB SDA Change 2 STOP Condition 3 7 9 8 ACK START Condition SERCK SERDIO 1 2 3 7 8 9 ACK MSB STOP Condition Figure 7-1: I2C Protocol Page 15 LCY-09033B-16 7.2. Serial Interface AC Characteristics Figure 7-2 and Table 5-1 show the specifications for AC characteristics of I2C serial I/F. tLOW tHIGH SERCK tTAhd SERDIO_in tTAsu tDIhd START Condition SDA Input tDIsu tTOsu SDA Change tBUF START STOP Condition Condition SERCK SERDIO_in tW Write Cycle tTOsu tTAsu STOP Condition START Condition SERCK tpd tDOhd Data Valid SERDIO_out 0.8Vcc SERCK 0.2Vcc tF1 tR1 0.8Vcc SERDIO tR2 0.2Vcc TF2 Figure 7-2: AC Specifications for Serial I/F Table 7-1: AC Specifications for Serial I/F Item Clock frequency Data clock "Hi" time Data clock "Lo" time Clock rise time Clock fall time Data rise time Data fall time Input data setup time Input data hold time Output data hold time Output data delay time Start condition setup time Start condition hold time Stop condition setup time Bus release time before transfer start Writing time Symbol fSCK tHIGH tLOW tR1 tF1 tR2 tF2 tDIsu tDIhd tDOhd tpd tTAsu tTAhd tTOsu tBUF tW Page 16 Min. Max. 400 600 1200 40 40 40 40 100 0 200 200 600 600 600 1300 900 10 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms LCY-09033B-17 7.3. Instruction to Write/Read to/from ASIC Figure 7-3 shows how to Write/Read to/from ASIC with I2C of LQ0DZC2291. (When writing) ACK ACK START BYTE ADDR R/W ACK ACK DEV SEL BYTE ADDR ACK ACK DATA IN1 DA ACK DATA IN3 ACK DATA IN N STOP TA IN2 START PAGEWRITE DATA IN STOP DEV SEL BYTEWRITE ACK R/W (When reading) R/W START RANDOM READ BYTE ADDR R/W ACK DEV SEL START DEV SEL DATA OUT R/W ACK ACK SEQUENTIAL DEV SEL NO ACK STOP START ADDRESS READ BYTE ADDR START DEV SEL RANDOM ACK ACK DATA OUT1 R/W * DEV_SEL of this ASIC is "1000111". Figure 7-3: How to Write/Read with I2C Page 17 ACK DATA OUT NO ACK DATA OUT N STOP ACK ACK LCY-09033B-18 8. Description of Function and Supported Register 8.1. Outline of Loading This ASIC can transfer the initial values of ASIC's internal register and the parameters for gamma correction, which are stored in EEPROM, to ASIC, when external EEPROM is connected and the ROMOFF pin is set to "0". Transfer EEPROM data from EEPROM into ASIC's internal register and LUT is referred to as "loading" in this document. There are two types of loading in this ASIC, as described below. (1) Initial loading This refers to transferring a data in EEPROM as ASIC's initial value into the internal register and LUT after canceling ASIC reset (FREST). This allows to fix an initial operation of ASIC. (2) Auto-loading For address 0x31[0]:als = `0', this ASIC transfers a data in EEPROM into ASIC's internal register and LUT once a 64V period. For the ASIC's internal register, all the registers are not always loaded from EEPROM. Refer to the register map of Table 5-1 and Table 8-1 below and check whether the register should be loaded or not. Table 8-1: Enabling/Disabling Loading and Access from Host Register to be loaded ALS="0" ALS="1" Access prohibited Write/Read can be done Access prohibited Write/Read can be done Write/Read can be done Write/Read can be done Read can be done Read can be done (Marked with in the register map) Register not to be loaded (Marked with in the register map) Register not to be loaded (Marked with in the register map) Read-Only register (Marked with 8.2. in the register map) Description of Register Regarding Loading Table 8-2 shows the registers regarding loading. Table 8-2: Registers Regarding Loading address bit7 bit5 bit4 bit3 bit2 bit1 - 31h als=0 als=1 32h bit6 bit0 Initial value als xxxx_xxx0b Auto-loading enabled: Any access from I2C to a register area to be loaded is prohibited. Auto-loading disabled: Register access functions completely. ready jinput ready Hi: Initial EEPROM loading completed. Lo: Initial EEPROM loading in process. jinput Hi: When HSY/VSY has not yet been input Lo: At a normal input operation jenable Hi: When Henable has been input Lo: when Henable has not yet been input Page 18 jenable LCY-09033B-19 9. Power ON Sequence Figure 9-1 below shows the power ON sequence. LSI power supply (3.3 V) Less than 10ms DCLK Data in FRESET 1650ck DCON (internal counter reset cancel timing) 11 2 3 4 5 6 7 8 9 10 Internal VSY Initial EEPROM loading period Ready REV REVC GOE MODEx RGB Out Other LCD signal output Figure 9-1: Power ON Sequence Procedure: (1) (2) When ASIC has turned on, change the reset pin (FRESET) of this ASIC from "Lo" to "Hi" and cancel the reset. When the reset has been cancelled, ASIC loads the initial values of internal register and LUT from EEPROM (for a maximum period of approximately 2 V). * In this period, access with I2C from an external CPU to a register to be loaded is prohibited. When making access, check that the ready register is "1" (i.e., initial loading has been completed). (3) Power ON sequence starts with VsyActive immediately after DCON has become "Hi". (4) REV reversal starts according to the Vsy(6) timing. (Polarity reversal starts.) (5) Data output starts according to the Vsy(7) timing. (6) The liquid crystal display enters a normal operation state at Vsy(8). Page 19 LCY-09033B-20 10. I/O Format Table 10-1 below describes the registers regarding I/O of timing controller (T-CON). Table 10-1: Registers for I/O format address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 henab[7:0] 08h 09h - Initial value 0010_0011b 0010_0011b venab[5:0] henab venab Horizontal display start position specified when the HENABLE signal is fixed to Lo. Vertical display start position specified. * Available only when ROMOFF = `0' is set. - 0Ah rsel hrvc vrvc 0000_0000b Scan direction change setting rsel, vrvc ,hrvc * Refer to "Chapter 12: Horizontal/Vertical Reverse Display". 0Bh - stb_hl[6:0] 0100_0101b stb_l Adjustment of STB in Hi period. Pulse width of STB is adjusted and charge share time is adjusted. * Refer to the set values listed in Table 10-2. gck_hl[7:0] 0Ch 1010_1010b Adjustment of CLS in Hi period. gck_hl * Refer to the set values listed in Table 10-2. 0Dh - slp_ctrl slp_ctrl[6:0] 0100_0011b Adjustment of G_SLP in Lo period. * Refer to the set values listed in Table 10-2. : Auto-loading register For the initial setting of stb_hl / gck_hl / slp_ctrl when ROMOFF = `0' has been specified, refer to Table 10-2. Table 10-2: Setting for stb_hl / gckhl / slp_ctrl stb_hl gck_hl WVGA 69 70 WQVGA 16 40 WEGA1 20 49 WEGA2 20 49 slp_ctrl 67 16 19 19 Perform the gate driver pulse output setting through the GMDSEL pin. Refer to Table 10-3. Table 10-3: Gate Start Pulse Output Setting GMDSEL Pin Gate start pulse output setting 0 Normal mode 1 Interlacing two-pulse mode Page 20 LCY-09033B-21 11. 11.1. FreeRun Display Overview of FreeRun Display This ASIC shows the blue background stored internally when a synchronization signal (Hsy/Vsy) input externally has been disappeared. 11.2. Conditions for Transition to FreeRun This ASIC counts Hsy/Vsy input externally. If the conditions below are met, this ASIC shows the blue background judging that there is no external input or an input error has occurred. A value of clk of 1H 1200 clk A value of clk of 1H tHA The number of lines of 1V 700 lines The number of lines of 1V tVA 11.3. Conditions for Recovery from FreeRun The ASIC counts Hsy/Vsy input externally in the FreeRun state. When the conditions below have been met and the same count value is obtained twice continuously, the ASIC shows the external input signal display judging that there is an external input. (tHA < a value of clk of 1H < 1200 clk) & the same count value obtained twice continuously (tVA < the number of lines of 1V < 700 line) & the same count value obtained twice continuously Page 21 LCY-09033B-22 12. Horizontal/Vertical Reverse Display This ASIC can reverse the display horizontally/vertically. The source/gate driver scan direction is set through an input pin, i.e., the HRCV pin/VRVC pin, or a register. The settings are described below. Table 12-1: Horizontal/Vertical Reverse Display Settings With or without ROM ROMOFF=`0' EEPROM setting ROMOFF=`1' rsel=`0' rsel=`1' Gate/source scan 15 pin VRVC/ 0x0a 15pin VRVC/ direction setting 16 pin HRVC vrvc/hrvc register value 16pin HRVC 0x0a rsel value Table 10-2: Register Regarding Horizontal/Vertical Reverse Display address bit7 bit6 bit5 0Ah bit4 bit3 - bit2 bit1 bit0 Initial value rsel vrvc hrvc 0000_0000b rsel For 0' setting, the vertical/horizontal reverse display is set by the input pins VRVC and HRVC. For 1' setting, the vertical/horizontal reverse display is set by the register values vrvc and hrvc. vrvc If the rsel register value is `1', the vertical reverse display is set. hrvc If the rsel register value is `1', the horizontal reverse display is set. The HRVC pin/hrvc register setting and the I/O of LBR/STHR/STHL are shown below. Table 12-3: I/O Related to Horizontal Reverse Display HRVC pin/ hrvc register LBR STHR STHL 0 0 Input Output 1 1 Output Input Please confirm the I/O relation described in specifications of LCD, and connect it with LQ0DZC2291. The VRVC pin/vrvc register setting and the I/O of RL/GSPOI_MODE2/GSPIO_SPS are shown below. Table 12-4: I/O Related to Vertical Reverse Display G_SEL=`0' VRVC/ vrvc register R/L 0 0 1 1 G_SEL=`1' GSPOI_ GSPIO_ MODE2 SPS Output Input (GSPOI) (GSPIO) Input Output (GSPOI) (GSPIO) Page 22 R/L 1 0 GSPOI_ GSPIO_ MODE2 SPS Output Output (MODE2) (SPS) Output Output (MODE2) (SPS) LCY-09033B-23 RGB Independent Gamma Correction 13. 13.1. Overview of RGB Independent Gamma Correction By mapping an input 6-bit data to a 8-bit signal based on the parameter stored in EEPROM, the 6-bit data is converted into 8-bit data in ASIC. This allows to control the gamma characteristics of input data per R, G and B independently. This ASIC is for 6-bit liquid crystal panel. So, the data is converted into 8-bit data in a pseudo way by the FRC technology and is displayed on the 6-bit panel. For turning ON/OFF the independent gamma conversion, refer to the register Map. (This is available only for ROMOFF = `0'.) 13.2. Description of Register Regarding RGB Independent Gamma Correction Table 13-1 shows the register regarding RGB independent gamma correction. Table 13-1: Register Regarding RGB Independent Gamma Correction address bit7 0Eh gamma_en gamma_en 13.3. bit6 bit5 bit4 bit3 bit2 bit1 bit0 - Initial value 0***_****b Setting to turn ON/OFF RGB independent gamma gamma_en=`0': Independent gamma correction is disabled. (The gamma correction is omitted.) gamma_en=`1': Independent gamma correction is enabled. Flow of Use of Independent Gamma Function As described above, the independent gamma parameters are loaded from EEPROM. Those independent gamma parameters are stored in the 192 addresses from 0x40 to 0xFF in EEPROM. Therefore, to use the independent gamma function, (1) write the set values corresponding to input gradations in advance and (2) store the data of 0x80 in the address 0x0E (gamma_enb) where is an auto-loading area in EEPROM. Page 23 LCY-09033B-24 14. EEPROM 14.1. EEPROM When using this ASIC, "256wordx8bitEEPROM" can be connected externally. Connect it to Pin (47: ROMCK, 48: ROMWC, 49: ROMDIO) of ASIC. This allows to load the ASIC register set values and independent gamma parameters from EEPROM. EEPROM is controlled by ASIC. So, any access from an external CPU to EEPROM must be performed through ASIC's internal register. 14.2. Recommended EEPROM Rohm "BR24L02-W" can be recommended as EEPROM that connection verification was executed. * Slave address "1010_000" 14.3. Description of Register Regarding EEPROM Table 14-1 shows the register regarding EEPROM. Table 14-1: Description of Register Regarding EEPROM address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rom_adrs[7:0] 20h rom_adrs Initial value 0000_0000b An address to access EEPROM is specified. rom_data[7:0] 21h rom_data 0000_0000b To write a data into EEPROM, specify an target address (in which the data is written) in the rom_adrs register and the target data (to be written) in this register and write the data into EEPROM through the rom_write register. To read a data from EEPROM, specify an target address (which stores the data to be read) in the rom_adrs and read the data from EEPROM through rom_read register. Then, the data stored in the specified address is stored in this register. When reading this register, confirm rom_head = 0 in advance. - 22h rom_read rom_write xxxx_xx00b rom_read ='0' rom_read ='1' The contents of EEPROM address specified in the rom_adrs register are read and then stored in the rom_data register. During reading from EEPROM, this register remains "1". When reading has been completed and the values have been stored in the rom_data register, this register becomes "0". rom_write ='0' rom_write ='1' A value of the rom_data register is written into an address in EEPROM, which is specified in the rom_adrs register. During writing into EEPROM, this register remains "1". When writing has been completed, this register becomes "0". You can not set both of rom_read = `1' and rom_write = `1' simultaneously. Your operation is ignored. 14.4. How to Write/Read to/from EEPROM (How to write) (1) Read the address 0x22 to check that it is 0x00. (If the Read data in this address is 0x01or0x02, any instruction from an external CPU is ignored because access to EEPROM is in process.) (2) Specify an EEPROM address to be written into the 0x20 address. (3) Write a data to be written into the address specified in step (2) in the address 0x21. (4) When 0x01 has been written into the address 0x22, the data specified in the step (3) is written into the EEPROM address specified in the step (2). (When the operation has been completed, ASIC changes the address 0x22 to 0x00 automatically.) (5) Unless the address 0x22 changes to 0x00 as stated in the step (1), any more writing/reading to/from EEPROM cannot be executed. (How to read) (1) Read the address 0x22 to check that it is 0x00. (If the Read data in this address is 0x01or0x02, any instruction from an external CPU is ignored because access to EEPROM is in process.) (2) Specify an EEPROM address to be read out to the 0x20 address. (3) When 0x02 has been written into the address 0x22, reading out from EEPROM to the address specified in the step (2) starts and the read data is written into the address 0x21. (When the operation has been completed, ASIC changes the address 0x22 to 0x00 automatically.) (4) Check that a data in the address 0x22 is 0x00 and then read out the data written into the address 0x21. Page 24 LCY-09033B-25 14.5. ROM_Map of EEPROM Table 14-2 shows mapping in EEPROM of this ASIC. Technique to storage in EEPROM is described below individually in detail. Table 14-2: ROM_Map of EEPROM ADRS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F (1) (2) Content dac_0ch dac_1ch dac_2ch dac_3ch dac_4ch dac_5ch dac_6ch dac_7ch Horizontal display start position adjustment Vertical display start position adjustment Scan direction change setting Charge share adjustment CLS_Hi period adjustment Gate slope adjustment Gamma control Test register Test register Gate output mode setting ADRS 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 Content Independent gamma (R)_00 Independent gamma (R)_01 Independent gamma (R)_02 Independent gamma (R)_03 Independent gamma (R)_04 Independent gamma (R)_05 Independent gamma (R)_06 Independent gamma (R)_07 ADRS 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 Content Independent gamma (G)_00 Independent gamma (G)_01 Independent gamma (G)_02 Independent gamma (G)_03 Independent gamma (G)_04 Independent gamma (G)_05 Independent gamma (G)_06 Independent gamma (G)_07 ADRS 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 Content Independent gamma (B)_00 Independent gamma (B)_01 Independent gamma (B)_02 Independent gamma (B)_03 Independent gamma (B)_04 Independent gamma (B)_05 Independent gamma (B)_06 Independent gamma (B)_07 0x48 Independent gamma (R)_08 0x88 Independent gamma (G)_08 0xC8 Independent gamma (B)_08 0x49 Independent gamma (R)_09 0x89 Independent gamma (G)_09 0xC9 Independent gamma (B)_09 0x4A Independent gamma (R)_10 0x8A Independent gamma (G)_10 0xCA Independent gamma (B)_10 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Independent gamma (R)_11 Independent gamma (R)_12 Independent gamma (R)_13 Independent gamma (R)_14 Independent gamma (R)_15 Independent gamma (R)_16 Independent gamma (R)_17 Independent gamma (R)_18 Independent gamma (R)_19 Independent gamma (R)_20 Independent gamma (R)_21 Independent gamma (R)_22 Independent gamma (R)_23 Independent gamma (R)_24 Independent gamma (R)_25 Independent gamma (R)_26 Independent gamma (R)_27 Independent gamma (R)_28 Independent gamma (R)_29 Independent gamma (R)_30 Independent gamma (R)_31 Independent gamma (R)_32 Independent gamma (R)_33 Independent gamma (R)_34 Independent gamma (R)_35 Independent gamma (R)_36 Independent gamma (R)_37 Independent gamma (R)_38 Independent gamma (R)_39 Independent gamma (R)_40 Independent gamma (R)_41 Independent gamma (R)_42 Independent gamma (R)_43 Independent gamma (R)_44 Independent gamma (R)_45 Independent gamma (R)_46 Independent gamma (R)_47 Independent gamma (R)_48 Independent gamma (R)_49 Independent gamma (R)_50 Independent gamma (R)_51 Independent gamma (R)_52 Independent gamma (R)_53 Independent gamma (R)_54 Independent gamma (R)_55 Independent gamma (R)_56 Independent gamma (R)_57 Independent gamma (R)_58 Independent gamma (R)_59 Independent gamma (R)_60 Independent gamma (R)_61 Independent gamma (R)_62 Independent gamma (R)_63 Independent gamma (G)_11 Independent gamma (G)_12 Independent gamma (G)_13 Independent gamma (G)_14 Independent gamma (G)_15 Independent gamma (G)_16 Independent gamma (G)_17 Independent gamma (G)_18 Independent gamma (G)_19 Independent gamma (G)_20 Independent gamma (G)_21 Independent gamma (G)_22 Independent gamma (G)_23 Independent gamma (G)_24 Independent gamma (G)_25 Independent gamma (G)_26 Independent gamma (G)_27 Independent gamma (G)_28 Independent gamma (G)_29 Independent gamma (G)_30 Independent gamma (G)_31 Independent gamma (G)_32 Independent gamma (G)_33 Independent gamma (G)_34 Independent gamma (G)_35 Independent gamma (G)_36 Independent gamma (G)_37 Independent gamma (G)_38 Independent gamma (G)_39 Independent gamma (G)_40 Independent gamma (G)_41 Independent gamma (G)_42 Independent gamma (G)_43 Independent gamma (G)_44 Independent gamma (G)_45 Independent gamma (G)_46 Independent gamma (G)_47 Independent gamma (G)_48 Independent gamma (G)_49 Independent gamma (G)_50 Independent gamma (G)_51 Independent gamma (G)_52 Independent gamma (G)_53 Independent gamma (G)_54 Independent gamma (G)_55 Independent gamma (G)_56 Independent gamma (G)_57 Independent gamma (G)_58 Independent gamma (G)_59 Independent gamma (G)_60 Independent gamma (G)_61 Independent gamma (G)_62 Independent gamma (G)_63 Independent gamma (B)_11 Independent gamma (B)_12 Independent gamma (B)_13 Independent gamma (B)_14 Independent gamma (B)_15 Independent gamma (B)_16 Independent gamma (B)_17 Independent gamma (B)_18 Independent gamma (B)_19 Independent gamma (B)_20 Independent gamma (B)_21 Independent gamma (B)_22 Independent gamma (B)_23 Independent gamma (B)_24 Independent gamma (B)_25 Independent gamma (B)_26 Independent gamma (B)_27 Independent gamma (B)_28 Independent gamma (B)_29 Independent gamma (B)_30 Independent gamma (B)_31 Independent gamma (B)_32 Independent gamma (B)_33 Independent gamma (B)_34 Independent gamma (B)_35 Independent gamma (B)_36 Independent gamma (B)_37 Independent gamma (B)_38 Independent gamma (B)_39 Independent gamma (B)_40 Independent gamma (B)_41 Independent gamma (B)_42 Independent gamma (B)_43 Independent gamma (B)_44 Independent gamma (B)_45 Independent gamma (B)_46 Independent gamma (B)_47 Independent gamma (B)_48 Independent gamma (B)_49 Independent gamma (B)_50 Independent gamma (B)_51 Independent gamma (B)_52 Independent gamma (B)_53 Independent gamma (B)_54 Independent gamma (B)_55 Independent gamma (B)_56 Independent gamma (B)_57 Independent gamma (B)_58 Independent gamma (B)_59 Independent gamma (B)_60 Independent gamma (B)_61 Independent gamma (B)_62 Independent gamma (B)_63 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF 00h to 3Fh (Basic register setting part) For the register (marked with ) for auto-loading in the register Map, be sure to store an initial setting data in this area. For an area not for auto-loading, even if any data is stored in EEPROM, it is not stored in the internal register. 40h to FFh (Area to store independent gamma parameter) Independent gamma LUT in ASIC is available for 129 addresses (64 x RGB) x 8 bits. To use the independent gamma function, store the values in 0x40 to 0xFF. Page 25 LCY-09033B-26 15. Control of D/A Converter (hereinafter referred to as "DAC") 15.1. Overview of DAC Control When the external DAC is connected to this ASIC, the ASIC can decide (1) the amplitude value and center voltage value of signal for the opposite electrode (COM electrode) of liquid display and (2) the gradation setting voltage values etc. of the source driver according to the ASIC's internal register settings. It is assumed that the DAC control is used for the two ways below. (1) Use in a fixed set value for mass production (2) Adjustment of opposite electrode center value in a process/source driver gradation setting voltage value 15.2. Recommended Component for DAC Fujitsu 8chDAC "MB88347" can be recommended as DAC that connection verification was executed. 15.3. Description of Register Regarding DAC Control Table 15-1 describes the register regarding DAC control Table 15-1: Description of Register Regarding DAC Control DAC control address initial value dac_0ch[7:0] 0000_0000b dac_1ch[7:0] 0000_0000b dac_2ch[7:0] 0000_0000b dac_3ch[7:0] 0000_0000b dac_4ch[7:0] 0000_0000b dac_5ch[7:0] 1111_1111b dac_6ch[7:0] 0111_1000b dac_7ch 0000_0000b DAC 5ch setting register DAC 6ch setting register 07h dac_7ch bit0 DAC 4ch setting register 06h dac_6ch bit1 DAC 3ch setting register 05h dac_5ch bit2 DAC 2ch setting register 04h dac_4ch bit3 DAC 1ch setting register 03h dac_3ch bit4 DAC 0ch setting register 02h dac_2ch bit5 01h dac_1ch bit6 00h dac_0ch bit7 DAC 7ch setting register Page 26 LCY-09033B-27 15.4. (1) Actual Usage Use in a fixed set value for mass production For the use in mass production (normal), store a voltage value to be set in EEPROM in advance. Then, ASIC stores a setting data in the ASIC's register at the initial loading after FRESET and, based on that, a control instruction to DAC is transferred. (2) Adjustment of opposite electrode center value in a process/source driver gradation setting voltage value This register is for auto-loading. To adjust in a process, follow the flow below. (How to adjust the amplitude of opposite electrode signal of address is described below. This applies also to any other set values.) 1. Set the ASIC register address 0x31[0]: als `1' and stop loading from EEPROM. 2. Change the ASIC register address DAC set value to find the most suitable value. (If the amplitude of opposite electrode signal is adjusting, a point that a flicker of liquid crystal minimizes is the most suitable value.) *) As described above, when als = `1', transfer to DAC is performed at every 1V. Even if a register is rewritten at a frequency of 1V or less, nothing is reflected in the display. Pay great attention to a change speed of register value. 3. Write the most suitable value confirmed in the step 2 into EEPROM. For how to write it, refer to "14.4. How to Write/Read to/from EEPROM". 4. Here, an initial value has been stored in EEPROM. From now on, ASIC recognizes this initial value whenever the power supply turns on. Page 27 LCY-09033B-28 16. Control of A/D Converter (hereinafter referred to as "ADC") 16.1. Overview of ADC Control When the external ADC is connected to this ASIC, the ASIC can read a value from a photo sensor or thermistor connected to the liquid crystal module and can store it in the ASIC's internal register. The ASIC can read a data from ADC by reading an applicable register. 16.2. Recommended Component for ADC National Semiconductor 2chADC "ADCVO8832" can be recommended ADC that connection verification was executed. Table 16-1: Description of Register Regarding ADC Control ADC control address bit7 bit6 bit4 bit3 adc_data1 adc_data2 34h 35h adc_data1 adc_data2 bit5 ADC 1ch Register ADC 2ch Register Page 28 bit2 bit1 bit0 initial value 0000_0000b 0000_0000b LCY-09033B-29 17. Output I/F to LCD Output timing in WVGA,WQVGA,WEGA1 and WEGA2 is shown below. 17.1. Example of Horizontal Timing 17.1.1. Horizontal Timing for Horizontal Resolution 800 Dots (WVGA) CLK 1 800 OutData STHR (STHL) stb_hl[69] (803) * For S_SEL = 1, fixed to 5. STB gck_hl[70] (702) GCK (CLS polarity is reversed) (792) REVV slp_ctrl[67] G_SLP (759) REVC (Available for S_SEL = `1') * Only once after VSY fall |FS (Available for S_SEL = `0') Figure in [ ] is a value for ROMOFF = `1'. Figure in ( ) is a standard value. Figure 17-1: Horizontal Timing Chart for Horizontal Resolution 800 Dots (WVGA) Page 29 LCY-09033B-30 17.1.2. Horizontal Timing for Horizontal Resolution 480 Dots (WEGA1/WEGA2) CLK 480 1 OutData STHR (STHL) (483) stb_hl[20] * For S_SEL = 1, fixed to 5. STB gck_hl[49] (436) GCK (CLS polarity is reversed) (472) REVV slp_ctrl[19] G_SLP (465) REVC (Available for S_SEL = `1') |FS * Only once after VSY fall (Available for S_SEL = `0') Figure in [ ] is a value for ROMOFF = `1'. [V = for 240 lines: V = for 272 lines] Figure in ( ) is a standard value. Figure 17-2: Horizontal Timing Chart for Horizontal Resolution 480 Dots (WEGA1/WEGA2) Page 30 LCY-09033B-31 17.1.3. Horizontal Timing for Horizontal Resolution 400 Dots (WQVGA) CLK 400 1 OutData STHR (STHL) (403) stb_hl[16] * For S_SEL = 1, fixed to 5. STB gck_hl[40] (363) GCK (CLS polarity is reversed) (393) REVV slp_ctrl[16] G_SLP (387) REVC (Available for S_SEL = `1') |FS * Only once after VSY fall (Available for S_SEL = `0') Figure in [ ] is a value for ROMOFF = `1'. Figure in ( ) is a standard value. Figure 17-3: Horizontal Timing Chart for Horizontal Resolution 400 Dots (WQVGA) Page 31 LCY-09033B-32 17.2. 17.2.1. Example of Vertical Timing Vertical Timing for Vertical Resolution 480 Lines (WVGA) For G_SEL = 0 DataIn H1 H2 H3 H1 Vsy Hsy REV G_SLP V_CNT |GSPOI GCK OG1 (dummy Line) OG2 (The 1st line on a display) [2] [1] Page 32 H2 H3 LCY-09033B-33 For G_SEL=1 DataIn H1 H2 H3 H1 H2 H3 Vsy Hsy REV G_SLP V_CNT SPS CLS OG1 (dummy Line) OG4 (Line No. 0) OG5 Hi (The 1st line on a display) Hi MODE1 MODE2 Hi Lo [1] [2] * In the chart above, [1] and [2] refer to the interlacing two-pulse mode and normal mode, respectively. Figure 15-4: Vertical Timing Chart for Vertical Resolution 480 Lines (WVGA) Page 33 LCY-09033B-34 17.2.2. Vertical Timing for Vertical Resolution 240 Lines (WQVGA/WEGA2) For G_SEL = 0 H1 DataIn H2 H3 H1 Vsy Hsy REV G_SLP V_CNT |GSPOI GCK OG1 (dummy Line) OG2 (The 1st line on a display) [1] [2] Page 34 H2 H3 LCY-09033B-35 For G_SEL=1 DataIn H1 H2 H3 H1 H2 H3 Vsy Hsy REV G_SLP V_CNT SPS CLS OG1 (dummy Line) OG2 (dummy Line) OG3 (The 1st line on a display) MODE1 Hi Hi Hi MODE2 Lo [1] [2] * In the chart above, [1] and [2] refer to the interlacing two-pulse mode and normal mode, respectively. Figure 17-5: Vertical Timing Chart for Vertical Resolution 240 Lines (WQVGA/WEGA2) Page 35 LCY-09033B-36 17.2.3. Vertical Timing for Vertical Resolution 272 Lines (WEGA1) For G_SEL = 0 H1 DataIn H2 H1 Vsy Hsy REV G_SLP V_CNT |GSPOI GCK OG1 GCK idle feeding 11 ck (2H period) [1] [2] OG13 OG14 (dummy1) OG15 (dummy2) OG16 (The 1st line on a display) * In the chart above, [1] and [2] refer to the interlacing two-pulse mode and normal mode, respectively. Figure 17-6: Vertical Timing Chart for Vertical Resolution 272 Lines (WEGA1) Page 36 H2 LCY-09033B-37 18. Cautions on storage 18.1. Storage environment To maintain the quality of semiconductor devices in storage, the storage environment must be controlled in terms of temperature and humidity and the presence of hazards such as corrosive gas,radioactive rays,and static electricity. <1> Maintasin the storage site's temperature (Ta) within 5 to 30 and the humidity (RH) within 20 to 70%. Also note the following points. Use a humidifier in dry regions. In this case, use demineralized water of distilled water for humidifyin. Avoid storing semiconductor devices in an overheated area, such as an area exposed to direct sunlight or near a heater, since overheated conditions may result in warping of product containers (magazines, etc). <2> Store semiconductor devices in areas where temperatures do not fluctuate widely (such as in direct sunlight areas or dark areas), since rapid changes in temperature can cause moisture condensation on the devices. <3> Store semiconductor devices in an area where the air is clean and free of excess salt, dust, or corrosive gases (such as exhaust gas, smoke, nitrous oxides, sulfur oxides, etc.). <4> Store semiconductor devices in an area that where they will not undergo mechanical stresses such as vibration or shock. <5> Store semiconductor devices in an area that where they will not be exposed to radioactive rays, static electricity, or strong magnetic fields. <6> Points to check after opening a complete dry pack. A humidity indicator card is included in dry pack packages. When moisture has been absorbed, the color of the card changes from blue to pink. If the card has changed to pink, the product may have absorbed moisture.So bake them before mounting. 18.2. Storage methods Note the following cautions on semiconductor device storage methods in order to maintain the quality of semiconductor devices. <1> Avoid stacking heavy items on top semiconductor device boxes since the devices may become damaged (cracks, bent leads, etc.). Since stacking boxes adds an undetermined amount of weight, avoid stacking heavy boxes on top of lighter boxes. <2> Do not allow any vibration or shock that is strong enough to dent the exterior boxes. <3> Leave lead ends on external pins of semiconductor devices unprocessed to avoid defects that can occur during solder mounting due to rust, etc. 18.3. Long-term storage When storing semiconductor devices for a long period (two years or longer), the following cautions should be noted in addition to the caution points mentioned for "18.1. Storage environment" and"18.2. Storage methods" above. <1> If long-term storage is expected from the start, use either dry pack or a sealed container that also contains silica gel desiccant. After opening a dry pack package, put the contents back into a dry pack to ensure a long shelf life. Page 37 LCY-09033B-38 <2> If a long period (two years or longer) has elapsed for semiconductor devices that have been stored under in a normal storage environment and using normal storage methods, we recommend checking for solderability and rust on pins before using the semiconductor devices. Page 38 LCY-09033B-39 19. Recommended soldering condition of infrared reflow Page 39 LCY-09033B-40 20. Outline drawings Page 40 LCY-09033B-41 21. Marking This marking drawing shows the marking items and layout of the contents, and does not specify the typeface size of precise position. Assembly lot number* No.1 pin index mark Lead-free mark * Construction of lot number In-house code Week assembled (2 digits) Year assembled (Last 2 digits) Page 41 LCY-09033B-42 22. Tray container Page 42 LCY-09033B-43 23.Packing outline drawing Page 43 LCY-09033B-44 24. Carton Page 44