Application Note 1919 ISL8115DEMO1Z Synchronous Buck Converter User Guide Introduction Key Features The ISL8115DEMO1Z is a compact reference design Synchronous Buck Converter (28.19mmx16.89mm) implementing Intersil's wide input range PWM controller ISL8115. Utilizing voltage mode control with input feed-forward, the ISL8115DEMO1Z maintains a constant loop gain for optimal transient response, especially for applications with a wide input voltage range. For a more detailed description of the ISL8115 functionality, refer to the ISL8115 datasheet. * Small, compact design This user guide includes the test setup, typical performance waveforms, schematic, layout and bill of materials (BOM). DESCRIPTION Input voltage range MIN TYP 16 24 MAX UNIT 36 V VOUT Output voltage 5 V IOUT Output rated current 10 A IOC Overcurrent threshold 13 A fsw Switching frequency 600 kHz 15 V Falling threshold 14.2 V Efficiency at 24V input full load (10A) 90.12 % Input UVP Rising threshold * Oscillator programmable from 150kHz to 1.5MHz - Frequency synchronization to external clock signal * Output OVP/UVP; OCP and OTP TABLE 1. DEMONSTRATION BOARD ELECTRICAL SPECIFICATIONS VIN * Integrated 5V high speed 4A MOSFET gate drivers - Internal bootstrap diode * Diode emulation mode for light load efficiency improvement Specifications SPEC * Fast transient response - Voltage-mode PWM leading-edge modulation with nonlinear control - Input voltage feed-forward * Adjustable soft-start * Prebias start-up function * Excellent output voltage regulation - 0.6V 1.0% internal reference (-40C~+125C) - 0.6V 0.7% internal reference (-40C~+105C) - Differential voltage sensing References * ISL8115 datasheet Ordering Information PART NUMBER ISL8115DEMO1Z DESCRIPTION Demonstration Board for ISL8115 Recommended Equipment * Input power source up to 36V supply voltage with 125W power supply ability * Electronic load with 100W power sinking ability * Voltmeters and ammeters * 100MHz quad-trace oscilloscope FIGURE 1. ISL8115DEMO1Z DEMONSTRATION BOARD March 11, 2015 AN1919.2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1919 FIGURE 2. ISL8115DEMO1Z TEST SETUP Quick Test Setup 1. Ensure that the demonstration board is correctly connected to the power supply and the electronic load prior to applying any power. Refer to Figure 2 for proper setup. 2. Set the input voltage to 24V, turn on the power supply and observe output voltage. The output voltage variation should be within 5%. 3. Adjust load current within 10A. The output voltage variation should be within 5%. 4. Use oscilloscope to observe output ripple voltage and phase node ringing. For accurate measurement, refer to Figure 3 for proper setup. Probe Setup Design Guide The ISL8115DEMO1Z is optimized for 16V to 36V input voltage range. However, the evaluation board can be modified to support multiple applications due to the customer's requirements. Refer to the ISL8115 datasheet for detailed information. TABLE 2. 12V APPLICATION VIN R35 12V 71.5k Quick modify to 12V input application, Table 2 can be followed. Some other modifications need to be made at the same time if best performance is expected. Output Voltage Adjustment The output voltage can be set by the resistors R4 and R1. In order to keep the existing compensation parameters unchanged, adjust R4 to set the output voltage by the following Equation 1: 0.6V R 1 R 4 = ---------------------------------V OUT - 0.6V (EQ. 1) The VMON monitors the output for UVP and OVP, the resistor divider value of R11/R8 should be the same with the R1/R4. Synchronization FIGURE 3. OSCILLOSCOPE PROBE SETUP Submit Document Feedback 2 The ISL8115DEMOZ board can be synchronized with an external clock. Applying a clock signal (10% to 90% duty cycle) in the range of 150kHz to 1.5MHz to the FSET pin makes the internal frequency synchronized with the external clock. Please remove R27 when the synchronized function is implemented. AN1919.2 March 11, 2015 Application Note 1919 Typical Performance Curves Unless otherwise specified, the input voltage is 28V. 95 95 85 90 EFFICIENCY (%) EFFICIENCY (%) 75 85 VIN = 16V 80 75 VIN = 36V VIN = 24V 65 VIN = 16V 55 VIN = 36V 45 VIN = 24V 35 25 70 65 15 1 2 3 4 5 6 7 8 9 5 10 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 4.0 3.6 OUTPUT CURRENT (A) OUTPUT CURRENT (A) FIGURE 5. EFFICIENCY vs LOAD CURRENT AT DEM MODE FIGURE 4. EFFICIENCY vs LOAD CURRENT AT CCM MODE 5.0390 5.0370 5.0365 5.0380 5.0370 5.0355 VOUT (V) VOUT (V) 5.0360 5.0350 5.0345 5.0360 5.0350 VIN = 24V VIN = 24V 5.0340 5.0340 5.0335 5.0330 0 1 2 3 4 5 6 LOAD CURRENT (A) 7 8 9 5.0330 10 FIGURE 6. VOUT LOAD REGULATION AT CCM MODE 2 3 4 5 6 LOAD CURRENT (A) 7 8 9 10 5.038 5.038 5.037 5.037 5.036 5.037 5.036 VOUT (V) VOUT (V) 1 FIGURE 7. VOUT LOAD REGULATION AT DEM MODE 5.038 5.036 5.035 0 NO LOAD 5.035 5.034 5.033 5.035 5.032 5.034 NO LOAD 5.034 5.031 5.033 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VIN (V) 5.030 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VIN (V) FIGURE 8. LINE REGULATION AT NO LOAD CCM MODE Submit Document Feedback 3 FIGURE 9. LINE REGULATION AT NO LOAD DEM MODE AN1919.2 March 11, 2015 Application Note 1919 Typical Performance Curves Unless otherwise specified, the input voltage is 28V. (Continued) 5.038 5.037 5.037 5.036 5.035 VOUT (V) VOUT (V) 5.036 5.035 5.034 FULL LOAD 10A 5.033 5.033 FULL LOAD 10A 5.032 5.031 5.032 5.031 16 5.034 5.030 18 20 22 24 26 28 VIN (V) 30 32 34 5.029 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VIN (V) 36 FIGURE 10. LINE REGULATION AT FULL LOAD CCM MODE FIGURE 11. LINE REGULATION AT FULL LOAD DEM MODE VOUT OUTPUT LOAD 20mV/DIV 5A/DIV 10s/DIV FIGURE 12. OUTPUT VOLTAGE RIPPLE AT 10A LOAD CONDITION VOUT 100mV/DIV OUTPUT LOAD 5A/DIV VOUT 100mV/DIV OUTPUT LOAD 5A/DIV 100s/DIV 100s/DIV FIGURE 13. LOAD TRANSIENT 0A TO 5A; 2A/s AT CCM FIGURE 14. LOAD TRANSIENT 5A TO 10A; 2A/s AT CCM Submit Document Feedback 4 AN1919.2 March 11, 2015 Application Note 1919 Typical Performance Curves VOUT 2V/DIV OUTPUT LOAD 5A/DIV Unless otherwise specified, the input voltage is 28V. (Continued) VOUT 2V/DIV OUTPUT LOAD 5A/DIV 2msDIV 2ms/DIV FIGURE 15. START-UP AT 0A LOAD CONDITION FIGURE 16. START-UP AT 10A LOAD CONDITION VOUT OUTPUT LOAD 2V/DIV 5A/DIV VOUT VOUT 500mV/DIV OUTPUT LOAD 5A/DIV 500s/DIV FIGURE 18. SHUTDOWN AT 10A LOAD CONDITION VOUT OUTPUT LOAD PH PH 1V/DIV 5A/DIV 50V/DIV 20V/DIV 5ms/DIV FIGURE 19. OVERCURRENT PROTECTION AT 12.6A LOAD Submit Document Feedback 5A/DIV OUTPUT LOAD 100s/DIV FIGURE 17. SHUTDOWN AT 0A LOAD CONDITION 2V/DIV 5 5ms/DIV FIGURE 20. SHORT PROTECTION AN1919.2 March 11, 2015 R4 R8 2K 2K R1 14.7k C3 R3 1. 8n R 11 14.7k R9 0 133 C17 47nF C1 20 R23 22 ISHARE PVCC U1 PLL_COMP PHASE ISL8115 CONF UG ATE BOOT L1 2.4uH TP3 2 8 Q2 C16 1 VOUT VOUT 74432524 0 2.4uH 14 A 4.8mohm C36 DNP 0.22uF 7 C24 C26 100uF 100uF C23 C25 100uF 100uF C11 1uF 5V/10A C 15 1uF TP4 VFF 1 R14 2 R27 C21 2.2uF GND Upper MOS: BSC039N06NS Lower MOS: BSC039N06NS R20 R36 46. 4K input rising shreshold: 15V input falling shreshold: 14.2V 1 4 9 40. 2K R29 10k 4.7uF 10 6 RAMP EN VIN 5 4 3 2 VCC SS PGOOD CLKOUT 1 18.2K 24 F SET 23 Q4 C 20 11 PVCC 732 R26 1 2 3 13 ISEN A 14 ISENB 15 16 LG ATE R28 9.1k C22 2. 2uF R35 113k 30K R12 2k R34 2.2 TP1 PVCC 1 VIN C30 10uF DEMO1Z Input: 16V - 36V Frequency: 600KHz C29 10uF C35 100uF 16 - 3 6V Output: 5V/10A TP2 1 GND FIGURE 21. ISL8115DEMO1Z SCHEMATIC Application Note 1919 21 ISET 4 12 5 390pF VMON 19 R39 10k 1 2 3 5.11K C19 GND RGND R21 17 470p 4.22k FB C4 25 R17 C2 33p 18 R40 10k R2 16.5k COMP 6 C14 2.2nF R22 0 2.2nF Average OCP: 12.8A Peak current limit: 13A 5 Submit Document Feedback Schematic AN1919.2 March 11, 2015 Application Note 1919 Bill of Materials ITEM QTY REFERENCE VALUE DESCRIPTION 1 2 C1, C14 2.2nF CAP CER 2200pF 25V 10% X7R 0402 Generic Generic 2 1 C2 33pF CAP CER 33pF 50V 5% NP0 0402 Generic Generic 3 1 C3 1.8nF CAP CER 1800pF 50V 10% X7R 0402 Generic Generic 4 1 C4 470pF CAP CER 470pF 50V 10% X7R 0402 Generic Generic 5 2 C11, C15 1F CAP CER 1F 10V 10% X5R 0603 Generic Generic 7 1 C16 0.22F CAP CER 0.22F 16V 10% X7R 0402 Generic Generic 8 1 C17 47nF CAP CER 0.047F 25V 10% X7R 0402 Generic Generic 9 1 C19 390pF CAP CER 390pF 50V 10% X7R 0402 Generic Generic 10 1 C20 4.7F CAP CER 4.7F 6.3V 10% X5R 0805 Generic Generic 11 1 C21 2.2F CAP CER 2.2F 50V 10% X7R 1210 TDK 12 1 C22 2.2F CAP CER 2.2F 6.3V 20% X5R 0603 Generic 13 4 C23, C24, C25, C26 100F CAP CER 100F 6.3V 20% X5R 1210 TDK C3225X5R0J107M250AC 14 2 C29, C30 10F CAP CER 10F 50V 10% X5R 1206 TDK C3216X5R1H106K160AB 15 1 C35 100F CAP ALUM 100F 50V 20% SMD 16 1 C36 DNP 17 1 L1 2.4H 18 2 Q2, Q4 BSC039N06NS 19 2 R1, R11 20 1 21 CAP 220F 6.3V INDUCTOR POWER 2.4H 31.5A SMD MANUFACTURER Nichicon Panasonic WE-Midcom PART NUMBER C3225X7R1H225K Generic PCV1H101MCL2GS 6TPF220M5L 744325240 MOSFET N-CH 60V 19A TDSON-8 Infineon BSC039N06NS 14.7k RES 14.7k 1/16W 1% 0402 SMD Generic Generic R2 16.5k RES 16.5k 1/16W 1% 0402 SMD Generic Generic 1 R3 133 RES 133 1/16W 1% 0402 SMD Generic Generic 22 3 R4, R8, R12 2k RES 2.00k 1/16W 1% 0402 SMD Generic Generic 23 2 R9, R22 0 RES 0.0 1/16W JUMP 0402 SMD Generic Generic 24 1 R14 2 RES 2.00 1/4W 1% 1206 SMD Generic Generic 25 1 R17 4.22k RES 4.22k 1/16W 1% 0402 SMD Generic Generic 26 1 R20 30k RES 30k 1/16W 1% 0402 SMD Generic Generic 27 1 R21 5.11k RES 5.11k 1/16W 1% 0402 SMD Generic Generic 28 1 R23 732 RES 732 1/16W 1% 0402 SMD Generic Generic 29 1 R26 18.2k RES 18.2k 1/16W 1% 0402 SMD Generic Generic 30 1 R27 40.2k RES 40.2k 1/16W 1% 0402 SMD Generic Generic 31 1 R28 9.1k RES 9.1k 1/16W 1% 0402 SMD Generic Generic 32 3 R29, R39, R40 10k RES 10k 1/16W 1% 0402 SMD Generic Generic 33 1 R34 2.2 RES 2.2 1/16W 1% 0402 SMD Generic Generic 34 1 R35 113k RES 113k 1/16W 1% 0402 SMD Generic Generic Submit Document Feedback 7 AN1919.2 March 11, 2015 Application Note 1919 Assembly Drawing FIGURE 22. TOP FIGURE 23. BOTTOM Submit Document Feedback 8 AN1919.2 March 11, 2015 Application Note 1919 PCB Layout FIGURE 24. TOP LAYER FIGURE 25. LAYER 2 Submit Document Feedback 9 AN1919.2 March 11, 2015 Application Note 1919 PCB Layout (Continued) FIGURE 26. LAYER 3 FIGURE 27. BOTTOM LAYER Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the document is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 10 AN1919.2 March 11, 2015 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Intersil: ISL8115DEMO1Z