128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Features DDR SDRAM Registered DIMM MT9VDDT1672 - 128MB MT9VDDT3272 - 256MB MT9VDDT6472 - 512MB For the latest data sheet, please refer to the Micron(R) Web site: www.micron.com/products/modules Features Figure 1: * 184-pin, dual in-line memory modules (DIMM) * Fast data transfer rates: PC1600, PC2100, and PC2700 * Supports ECC error detection and correction * Registered inputs with one-clock delay * Phase-lock loop (PLL) clock driver to reduce loading * Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM components * 128MB (16 Meg x 72), 256MB (32 Meg x 72), and 512MB (64 Meg x 72) * VDD= VDDQ= +2.5V * VDDSPD = +2.3V to +3.6V * 2.5V I/O (SSTL_2 compatible) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle * Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture * Differential clock inputs (CK and CK#) * Four internal device banks for concurrent operation * Selectable burst lengths: 2, 4, or 8 * Auto precharge option, auto refresh and self refresh modes * 15.6s (128MB); 7.8125s (256MB, 512MB) maximum average periodic refresh interval * Serial Presence-Detect (SPD) with EEPROM * Selectable READ CAS latency * Gold edge contacts Standard PCB 1.7in. (43.18mm) pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_1.fm - Rev. D 8/05 EN 184-Pin DIMM (MO-206) Low Profile PCB 1.2in. (30.48mm) Options Marking * Operating Temperature Range Commercial No Mark * Package 184-pin DIMM (standard) G 184-pin DIMM (lead-free)1 Y * Memory Clock, Speed, CAS Latency2 6ns (167 MHz), 333 MT/s, CL = 2.5 -3353 7.5ns (133 Mhz), 266 MT/s, CL = 2 -2621 7.5ns (133 Mhz), 266 MT/s, CL = 2 -26A1 7.5ns (133 Mhz), 266 MT/s, CL = 2.5 -2651 10ns (100 Mhz), 200 MT/s, CL = 2 -2021 * PCB Height Standard 1.7in. (43.18mm)1 See note, page 2 Low Profile 1.2in. (30.48mm)1 See note, page 2 Notes: 1. Contact Micron for product availability; not recommended for new designs. 2. CL = Device CAS (READ) Latency; registered mode adds one clock cycle to CL. 3. Available in 128MB density only. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Features Table 1: Address Table Refresh Count Row Addressing Device Bank Addressing Base Device Configuration Column Addressing Module Rank Addressing Table 2: MT9VDDT1672 MT9VDDT3272 MT9VDDT6472 4K 4K (A0-A11) 4 (BA0, BA1) 128Mb (16 Meg x 8) 1K (A0-A9) 1 (S0#) 8K 8K(A0-A12) 4 (BA0, BA1) 256Mb (32 Meg x 8) 1K(A0-A9) 1 (S0#) 8K 8K(A0-A12) 4 (BA0, BA1) 512Mb (64 Meg x 8) 2K(A0-A9, A11) 1 (S0#) Part Numbers and Timing Parameters Part Number MT9VDDT1672G-335__ MT9VDDT1672Y-335__ MT9VDDT1672G-262__ MT9VDDT1672Y-262__ MT9VDDT1672G-26A__ MT9VDDT1672Y-26A__ MT9VDDT1672G-265__ MT9VDDT1672Y-265__ MT9VDDT1672G-202__ MT9VDDT1672Y-202__ MT9VDDT3272G-262__ MT9VDDT3272Y-262__ MT9VDDT3272G-26A__ MT9VDDT3272Y-26A__ MT9VDDT3272G-265__ MT9VDDT3272Y-265__ MT9VDDT3272G-202__ MT9VDDT3272Y-202__ MT9VDDT6472G-262__ MT9VDDT6472Y-262__ MT9VDDT6472G-26A__ MT9VDDT6472Y-26A__ MT9VDDT6472G-265__ MT9VDDT6472Y-265__ MT9VDDT6472G-202__ MT9VDDT6472Y-202__ Note: pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_1.fm - Rev. D 8/05 EN Module Density Configuration Module Bandwidth Memory Clock/ Data Frequency Latency (CL - tRCD - tRP) 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 32 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 1.6 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 1.6 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 1.6 GB/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 10ns/200 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 10ns/200 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 10ns/200 MT/s 2.5-2-2 2.5-2-2 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDT3272G-265A1. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PLL and Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Serial Presence-Detect Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 DLL Enable/Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Register and PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Serial Presence-Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 SPD Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 SPD Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 SPD Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 SPD Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72TOC.fm - Rev. D 8/05 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: 184-Pin DIMM (MO-206) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pin Locations (184-Pin DIMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Mode Register Definition Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 CAS Latency Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Extended Mode Register Definition Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Derating Data Valid Window (tQH - tDQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Definition of Start and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Acknowledge Response From Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 SPD EEPROM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 184-Pin DIMM Dimensions (Standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 184-Pin DIMM Dimensions (Low-Profile) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72LOF.fm - Rev. D 8/05 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Part Numbers and Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Burst Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 CAS Latency (CL) Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Commands Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 DM Operation Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 IDD Specifications and Conditions - 128MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 IDD Specifications and Conditions - 256MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 IDD Specifications and Conditions - 512MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 DDR Device Electrical Characteristics and Recommended AC Operating Conditions. . . . . . . . . . . .22 DDR Device Electrical Characteristics and Recommended AC Operating Conditions. . . . . . . . . . . .23 Register Timing Requirements and Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 PLL Clock Driver Timing Requirements and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . .33 EEPROM Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 EEPROM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Serial Presence-Detect EEPROM DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Serial Presence-Detect EEPROM AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Serial Presence-Detect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72LOT.fm - Rev. D 8/05 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 3: Pin Assignment 184-Pin DIMM Front 184-Pin DIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC RESET# VSS DQ8 DQ9 DQS1 VDDQ DNU DNU VSS DQ10 DQ11 CKE0 VDDQ DQ16 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDD NC DQ48 DQ49 VSS DNU DNU VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 NC VDDQ NC DQ20 NC/A12 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 CK0# 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 VSS DM8 A10 CB6 VDDQ CB7 VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VDDQ S0# NC DM5 VSS DQ46 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD Notes: 1. Pin 115 is no connect (NC) for 128MB, A12 for 256MB and 512MB. Figure 2: Pin Locations (184-Pin DIMM) Standard 1.7in. (43.18mm) Front View U3 U1 U5 Low Profile 1.2in. (30.48mm) U7 U9 U10 Front View U11 U1 U11 PIN 52 U5 U13 U12 PIN 1 U3 U7 U9 U12 PIN 92 PIN 53 PIN 52 PIN 1 PIN 92 PIN 53 Back View Back View U15 U17 U19 U21 U13 U15 U17 U19 U21 U10 PIN 184 PIN 145 PIN 144 PIN 184 PIN 93 Indicates a VDD or VDDQ pin pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 6 PIN 145 PIN 144 PIN 93 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Pin Assignments and Descriptions Table 4: Pin Descriptions Pin numbers may not correlate with symbols. Refer to pin assignment tables on page 6 for more information Pin Numbers Symbol Type 63, 65, 154 WE#, CAS#, RAS# Input 137, 138 CK0, CK0# 21 CKE0 157 S0# 52, 59 BA0, BA1 27, 29, 32, 37, 41, 43, 48, 115 (A12), 118, 122, 125, 130, 141 A0-A11 (128MB) A0-A12 (256MB, 512MB) 91 SDA 92 SCL 181, 182, 183 SA0-SA2 10 RESET# 44, 45, 49, 51, 134, 135, 142, 144 97, 107, 119, 129, 140, 149, 159, 169, 177 CB0-CB7 pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN DM0-DM8 Description Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for POWERDOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. Input Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Input Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the opcode during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to Output transfer addresses and data into and out of the presence-detect portion of the module. Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Input Asynchronously forces all register outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure CKE is LOW and SDRAM DQ is High-Z. Input/ Check bits. Output Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM state does not affect READ command. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Pin Assignments and Descriptions Table 4: Pin Descriptions Pin numbers may not correlate with symbols. Refer to pin assignment tables on page 6 for more information Pin Numbers Symbol 5, 14, 25, 36, 47, 56, 67, 78, 86 DQS0-DQS8 2, 4, 6, 8, 12, 13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 1 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, 120, 148, 168 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 184 9, 71, 82, 90, 101, 102, 103, 111, 113, 115 (128MB), 158, 163, 167, 173 16, 17, 75, 76 DQ0-DQ63 pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN VREF VDDQ Type Description Input/ Data Strobe: Output with READ data, input with WRITE data. DQS Output is edge-aligned with READ data, centered in WRITE data. Used to capture data. Input/ Data I/Os: Data bus. Output Supply SSTL_2 reference voltage. Supply DQ Power Supply: +2.5V 0.2V. VDD Supply Power Supply: +2.5V 0.2V. VSS Supply Ground. VDDSPD NC DNU Supply Serial EEPROM positive power supply: +2.3V to +3.6V. -- No Connect: These pins should be left unconnected. -- Do Not Use: These pins are not connected on this module but are assigned pins on other modules in this product family. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Functional Block Diagram Functional Block Diagram All resistor values are 22 unless otherwise specified. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide. Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB); MT46V32M8TG (256MB); MT46V64M8TG (512MB). Lead-free modules use the following DDR SDRAM devices: MT46V16M8P (128MB); MT46V32M8P (256MB); MT46V64M8P (512MB). Contact Micron for availability of IT DIMMs. Figure 3: Functional Block Diagram RS0# DQS0 DQS4 DM0 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ DQ DQ U1 DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ U21 DQ DQ DQ DQ DQ DQS1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ U17 DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ U7 DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ U15 DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ U9 DQ DQ DQ DQ DQ DQS5 DM1 DM5 DQS2 DQS6 DM2 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ U3 DQ DQ DQ DQ DQ DQS3 DQS7 DM3 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ U19 DQ DQ DQ DQ DQ DQS8 DM8 U11, U13 S0# BA0, BA1 A0-A11 (128MB) A0-A12 (256MB, 512MB) RAS# CAS# CKE0 WE# CK R E G I S T E R S CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS# DQS DQ DQ DQ U5 DQ DQ DQ DQ DQ U12 120 CK0 CK0# PLL SERIAL PD SCL WP A0 U10 A1 A2 DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM REGISTER X 2 SDA SA0 SA1 SA2 RS0# RBA0, RBA1: DDR SDRAMS RA0-RA11: DDR SDRAMS RA0-RA12: DDR SDRAMS RRAS#: DDR SDRAMS RCAS#: DDR SDRAMS RCKE0: DDR SDRAMS RWE#: DDR SDRAMS VDDSPD SPD/EEPROM VDDQ DDR SDRAMS VDD DDR SDRAMS VREF DDR SDRAMS VSS DDR SDRAMS RESET# CK# pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM General Description General Description The MT9VDDT1672, MT9VDDT3272, and MT9VDDT6472 are high-speed CMOS, dynamic random-access, 128MB, 256MB, and 512MB registered memory modules organized in a x72 (ECC) configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding nbit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select device bank; A0-A11 select device row for 128MB; A0-A12 select device row for 256MB, 512MB). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. DDR SDRAM modules provide for programmable read or write burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM component data sheets. PLL and Register Operation DDR SDRAM modules operate in registered mode where the control/address input signals are latched in the register on one rising clock edge and sent to the DDR SDRAM devices on the following rising clock edge (data access is delayed by one clock). A phaselock loop (PLL) on the module is used to redrive the differential clock signals CK and CK# to the DDR SDRAM devices to minimize system clock loading. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Mode Register Definition Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of DDR SDRAM devices. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 4, Mode Register Definition Diagram, on page 12. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 (128MB) or A7-A12 (256MB, 512MB) specify the operating mode. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration. See Note 5 of Table 5, Burst Definition Table, on page 13). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Mode Register Definition The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 5, Burst Definition Table, on page 13. Figure 4: Mode Register Definition Diagram 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 0* 0* 11 10 9 8 7 6 5 4 3 2 1 0 Operating Mode CAS Latency BT Burst Length Address Bus Mode Register (Mx) * M13 and M12 (BA0 and BA1) must be "0, 0" to select the base mode register (vs. the extended mode register). 256MB and 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 Operating Mode 0* 0* 7 6 5 4 3 2 1 0 CAS Latency BT Burst Length * M14 and M13 (BA0 and BA1) must be "0, 0" to select the base mode register (vs. the extended mode register). Mode Register (Mx) Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved Burst Type M3 0 Sequential 1 Interleaved CAS Latency M6 M5 M4 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M12 M11 M10 M9 M8 M7 pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN Address Bus M6-M0 Operating Mode 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - 12 All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Mode Register Definition Table 5: Burst Definition Table Burst Length A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 2 4 A2 0 0 0 0 1 1 1 1 8 Order of Accesses Within a Burst Starting Column Address A1 0 0 1 1 A1 0 0 1 1 0 0 1 1 Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Notes: 1. For a burst length of two, A1-Ai select the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai select the four-data-element block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 (128MB, 256MB) i = 9, 11 (512MB) Table 6: CAS Latency (CL) Table Allowable Operating Clock Frequency (MHz) pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN Speed CL = 2 CL = 2.5 -335 -262 -26A -265 -202 75 f 133 75 f 133 75 f 133 75 f 100 75 f 100 75 f 167 75 f 133 75 f 133 75 f 133 N/A 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Mode Register Definition Figure 5: CAS Latency Diagram T0 T1 T2 READ NOP NOP T2n T3 T3n CK# CK COMMAND NOP CL = 2 DQS DQ CK# T0 T1 T2 READ NOP NOP T2n T3 T3n CK COMMAND NOP CL = 2.5 DQS DQ Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA DON'T CARE Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS Latency Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Figure 6, CAS Latency (CL) Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 (128MB), or A7-A12 (256MB, 512MB) each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A11 (128MB), or A7 and A9-A12 (256MB, 512MB) each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Extended Mode Register All other combinations of values for A7-A11 (128MB), or A7-A12 (256MB, 512MB) are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 6, Extended Mode Register Definition Diagram. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both low) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during powerup initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE HIGH must occur before a READ command can be issued. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Extended Mode Register Figure 6: Extended Mode Register Definition Diagram 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 11 10 9 8 7 6 5 Operating Mode 01 11 4 3 2 1 0 Address Bus Extended Mode Register (Ex) DS DLL 256MB and 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 7 6 5 Operating Mode 01 11 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22 4 3 2 1 0 Extended Mode Register (Ex) DS DLL E1, E0 Address Bus E0 DLL 0 Enable 1 Disable E1 Drive Strength 0 Normal Operating Mode 0 0 0 0 0 0 0 0 0 0 0 Valid Reserved - - - - - - - - - - - - Reserved Notes: 1. BA1 and BA0 (E13 and E12 for 128MB, E14 and E13 for 256MB and 512MB) must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register. 2. QFC# is not supported. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Commands Commands Table 7, Commands Truth Table, and Table 8, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description of commands and operations, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM component data sheet. Table 7: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; all states/sequences not shown are illegal or reserved Name (Function) DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER CS# RAS# CAS# WE# Address Notes H L L L L L L L L X H L H H H L L L X H H L L H H L L X H H H L L L H L X X Bank/Row Bank/Col Bank/Col X Code X Op-Code 1 1 2 3 3 4 5 6, 7 8 Notes: 1. DESELECT and NOP are functionally interchangeable. 2. BA0-BA1 provide device bank address and A0-A11 (128MB) or A0-A12 (256MB, 512MB) provide row address. 3. BA0-BA1 provide device bank address; A0-A9 (128MB, 256MB) or A0-A9, A11 (512MB) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 (128MB) or A0-A12 (256MB, 512MB) provide the op-code to be written to the selected mode register. Table 8: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data Name (Function) WRITE Enable WRITE Inhibit pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 17 DM DQs L H Valid X Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Absolute Maximum Ratings Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VREF and Inputs Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on I/O Pins Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDDQ +0.5V Operating Temperature TA (commercial). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0C to +70C Storage Temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +150C Short Circuit Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Electrical Specifications Table 9: DC Electrical Characteristics and Operating Conditions Notes: 1-5, 14; notes appear on pages 25-29; 0C TA +70C Parameter/Condition Symbol Supply Voltage I/O Supply Voltage I/O Reference Voltage VDD VDDQ VREF I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V VIN VDD, VREF pin 0V VIN 1.35V (All other pins not under test = 0V) VTT VIH(DC) VIL(DC) Command/ Address, RAS#, CAS#, WE#, CKE, S# CK, CK# DM DQ, DQS OUTPUT LEAKAGE CURRENT: Single-Rank DIMM (DQ are disabled; 0V VOUT VDDQ) OUTPUT LEVELS High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) Table 10: Min Max 2.3 2.7 2.3 2.7 0.51 x 0.49 x VDDQ VDDQ VREF - 0.04 VREF + 0.04 VREF + 0.15 VDD + 0.3 -0.3 VREF - 0.15 -5 Units Notes V V V 32, 36 32, 36, 39 6, 39 V V V 7, 39 25 25 A 47 5 II IOZ -10 -2 -5 10 2 5 A 47 IOH IOL -16.8 16.8 - - mA mA 33, 34 AC Input Operating Conditions Notes: 1-5, 14, 48; notes appear pages 25-29; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V Parameter/Condition Symbol Min Max Units Notes Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage VIH(AC) VIL(AC) VREF(AC) VREF + 0.310 - 0.49 x VDDQ - VREF - 0.310 0.51 x VDDQ V V V 12, 25, 35 12, 25, 35 6 pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Electrical Specifications Table 11: IDD Specifications and Conditions - 128MB DDR SDRAM components only Notes: 1-5, 8, 10, 12, 48; notes appear on pages 25-29; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V Max Parameter/Condition Symbol -335 -262 -26A/ -265/ -202 IDD0 1,125 990 945 mA 20, 42 IDD1 1,215 1,080 1,080 mA 20, 42 IDD2P 27 27 27 mA IDD2F 405 405 360 mA 21, 28, 44 45 IDD3P 225 225 180 mA IDD3N 450 450 405 mA 21, 28, 44 20, 41 IDD4R 1,260 1,170 1,125 mA 20, 42 IDD4W 1,260 1,125 1,080 mA 20 IDD5 2,385 1,980 1,980 mA 24, 44 IDD5A IDD6 IDD7 45 27 3,195 45 27 2,970 45 18 2,925 mA mA mA 24, 44 9 20, 43 OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC AUTO REFRESH CURRENT (MIN) tREFC = 15.625s SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 19 Units Notes Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Electrical Specifications Table 12: IDD Specifications and Conditions - 256MB DDR SDRAM components only Notes: 1-5, 8, 10, 12, 48; notes appear on pages 25-29; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V Max Parameter/Condition t t OPERATING CURRENT: One device bank; Active-Precharge; RC = RC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) AUTO REFRESH CURRENT tREFC = 7.8125s SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 20 Symbol -262 -26A/ -265/ -202 IDD0 1,125 1,080 mA 20, 42 IDD1 1,440 1,305 mA 20, 42 IDD2P 36 36 mA IDD2F 405 405 mA 21, 28, 44 45 IDD3P 225 225 mA IDD3N 450 450 mA 21, 28, 44 20, 41 IDD4R 1,350 1,350 mA 20, 42 IDD4W 1,350 1,350 mA 20 IDD5 IDD5A IDD6 IDD7 2,115 54 36 3,150 2,115 54 36 3,150 mA mA mA mA 24, 44 24, 44 9 20, 43 Units Notes Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Electrical Specifications Table 13: IDD Specifications and Conditions - 512MB DDR SDRAM components only Notes: 1-5, 8, 10, 12, 48; notes appear on pages 25-29; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V Max Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge; RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) AUTO REFRESH CURRENT tREFC = 7.8125s SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands Symbol -262 -26A/ -265/ -202 IDD0 1,170 1,035 mA 20, 42 IDD1 1,440 1,305 mA 20, 42 IDD2P 45 45 mA IDD2F 405 360 mA 21, 28, 44 45 IDD3P 315 270 mA IDD3N 450 405 mA 21, 28, 44 20, 41 IDD4R 1,485 1,305 mA 20, 42 IDD4W 1,575 1,215 mA 20 IDD5 IDD5A IDD6 IDD7 2,610 90 45 3,600 2,520 90 45 3,150 mA mA mA mA 24, 44 24, 44 9 20, 43 Units Notes t Table 14: Capacitance Note: 11; notes appear on pages 25-29 Parameter Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CK, CK#, CKE pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 21 Symbol Min Max Units CIO CI1 4 2.5 5 3.5 pF pF Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Electrical Specifications Table 15: DDR Device Electrical Characteristics and Recommended AC Operating Conditions Notes: 1-5, 8, 12-15, 29; notes appear on pages 25-29; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC Characteristics Parameter Access window of DQ from CK/CK# CK high-level width CK low-level width Clock cycle time CL = 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period 128MB, 256MB 512MB ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN -335 Sym t AC t CH t CL tCK (2.5) tCK (2) t DH t DS t DIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIH tIS F F tIH S tIS S tIPW tMRD tQH Min Max Min Max Units -0.7 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.60 0.35 0.35 +0.7 0.55 0.55 13 13 -0.70 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.65 0.35 0.35 +0.70 0.55 0.55 13 13 0.45 ns t CK t CK ns ns ns ns ns ns tCK tCK ns 1.25 tCK t RAP tRC tRFC t RCD t RP tRPRE tRPST tRRD t WPRE tWPRES tWPST tWR tWTR 22 +0.60 0.45 0.75 1.25 0.2 0.2 tCH,tCL +0.70 -0.70 0.75 0.75 0.80 0.80 2.2 12 tHP -tQHS tQHS tRAS -262 42 15 60 72 120 15 15 0.9 0.4 12 0.25 0 0.4 15 1 0.55 70,000 1.1 0.6 0.6 0.75 0.2 0.2 +0.60 26 26 40, 46 40, 46 23, 27 23, 27 27 22, 23 tCK tCK tCH,tCL +0.70 -0.70 0.75 0.75 0.8 0.8 2.2 15 tHPtQHS 40 15 60 75 120 15 15 0.9 0.4 15 0.25 0 0.4 15 1 Notes 0.75 120,000 1.1 0.6 0.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK ns t CK ns tCK ns tCK 30 16, 37 16, 37 12 12 12 12 22, 23 31 44 38 38 19, 19 18 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Electrical Specifications Table 15: DDR Device Electrical Characteristics and Recommended AC Operating Conditions (Continued) AC Characteristics Parameter Data valid output window (DVW) REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ 128MB, 256MB command 512MB Exit SELF REFRESH to READ command Table 16: -335 Sym na t REFC t REFI t VTD t XSNR t XSRD Min -262 Max t QH -tDQSQ 70.3 7.8 0 75 127.5 200 Min Max tQH -tDQSQ 70.3 7.8 0 75 127.5 200 Units ns s s ns ns ns t CK Notes 21 21 DDR Device Electrical Characteristics and Recommended AC Operating Conditions Notes: 1-5, 8, 12-15, 29; notes appear on pages 25-29; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC Characteristics Parameter -26A/-265 Sym Min Max Min Max tAC -0.75 0.45 0.45 7.5 7.5/10 0.5 0.5 1.75 -0.75 0.35 0.35 +0.75 0.55 0.55 13 13 -0.8 0.45 0.45 8 10 0.6 0.6 2 -0.8 0.35 0.35 +0.8 0.55 0.55 13 13 Access window of DQs from CK/CK# tCH CK high-level width tCL CK low-level width tCK (2.5) Clock cycle time CL= 2.5 tCK (2) CL= 2 tDH DQ and DM input hold time relative to DQS tDS DQ and DM input setup time relative to DQS tDIPW DQ and DM input pulse width (for each input) tDQSCK Access window of DQS from CK/CK# tDQSH DQS input high pulse width tDQSL DQS input low pulse width tDQSQ DQS-DQ skew, DQS to last DQ valid, per group, per access t DQSS Write command to first DQS latching transition tDSS DQS falling edge to CK rising - setup time tDSH DQS falling edge from CK rising - hold time tHP Half clock period tHZ Data-out high-impedance window from CK/CK# t LZ Data-out low-impedance window from CK/CK# t IHF Address and control input hold time (fast slew rate) tIS Address and control input setup time (fast slew rate) F tIH Address and control input hold time (slow slew rate) S tIS Address and control input setup time (slow slew rate) S t IPW Address and control input pulse width (for each input) t MRD LOAD MODE REGISTER command cycle time tQH DQ-DQS hold, DQS to first DQ to go non-valid, per access tQHS Data hold skew factor t RAS ACTIVE to PRECHARGE command tRAP ACTIVE to READ with auto precharge command pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN -202 23 +0.75 0.5 0.75 1.25 0.20 0.20 tCH,tCL +0.75 -0.75 0.90 0.90 1 1 2.2 15 tHP tQHS 0.75 40 120,000 20 +0.8 0.6 0.75 1.25 0.20 0.20 tCH,tCL +0.8 -0.8 1.1 1.1 1.1 1.1 2.2 16 tHP tQHS 1 40 120,000 20 Units Notes ns tCK tCK ns ns ns ns ns ns tCK tCK ns t 26 26 40, 46 40, 46 23, 27 23, 27 27 22, 23 CK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns 30 16, 37 16, 37 12 12 12 12 22, 23 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Electrical Specifications Table 16: DDR Device Electrical Characteristics and Recommended AC Operating Conditions (Continued) AC Characteristics -26A/-265 Parameter Sym Min ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command 128MB interval 256MB, 512MB Average periodic refresh interval 128MB 256MB, 512MB Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command t 65 75 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH -tDQSQ 140.6 70.3 15.6 7.8 0 75 200 pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN RC t RFC t RCD tRP tRPRE t RPST t RRD t WPRE tWPRES tWPST tWR tWTR na tREFC tREFI tVTD tXSNR tXSRD 24 Max -202 Min Max 70 80 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 140.6 70.3 15.6 7.8 0 80 200 Units ns ns ns ns tCK t CK ns t CK ns tCK ns tCK ns s s s s ns ns tCK Notes 44 38 38 19, 19 18 22 21 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Notes Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: VTT Output (VOUT) 50 Reference Point 30pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent upon output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -262, -26A, and -202, CL = 2.5 for -335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, TA = 25C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 12. For slew rates < 1V/ns and 0.5 V/ns. If slew rate is < 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while tIH is unaffected. If slew rate exceeds 4.5 V/ns, functionality is uncertain. 13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. 15. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Notes 16. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The intent of the Don't Care state after completion of the postamble is the DQS-driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above VIHDC (MIN) then it must not transition low (below VIHDC) prior to tDQSH (MIN)). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period 64ms. This equates to an average refresh rate of 15.625s (128MB) or 7.8125s (256MB, 512MB). However, an AUTO REFRESH command must be asserted at least once every 140.6s (128MB) or 70.3s (256MB, 512MB); burst refreshing or posting by the DDR SDRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: tHP (tCK/2), t DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportionally with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 7, Derating Data Valid Window (tQH - tDQSQ), shows derating curves duty cycles ranging between 50/50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). 26. CK and CK# input slew rate must be 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 28. VDD must not vary more than 4 percent if CKE is not active while any bank is active. 29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Notes Derating Data Valid Window (tQH - tDQSQ) Figure 7: 3.8 3.750 3.700 3.6 3.400 3.350 3.4 3.650 3.600 3.550 3.500 3.300 3.450 3.400 3.250 3.200 3.150 3.2 3.100 ns 3.300 3.250 3.050 3.000 -262/-26A/-265 @ tCK = 10ns -202 @ tCK = 10ns -262/-26A/-265 @ tCK = 7.5ns 3.0 3.350 2.950 2.900 2.8 2.6 2.500 2.463 2.425 2.388 2.4 2.350 2.313 2.275 2.238 2.200 2.163 2.2 2.125 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Duty Cycle 32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/ 3 of the clock cycle and not exceed either -300mV or 2.2V, whichever is more positive. However, the DC average cannot be below 2.3V minimum. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pulldown current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. 34. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Notes Figure 8: Pull-Down Characteristics 160 um 140 Maxim 120 Nominal IOUT (mA) 100 high 80 Nominal low 60 Minimum 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 VOUT (V) Figure 9: Pull-Up Characteristics 0 -20 Maximum -40 Nominal high IOUT (mA) -60 -80 -100 Nom -120 inal -140 Min low imu -160 m -180 -200 0.0 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V) 35. VIH overshoot: VIH (MAX) = VDDQ+1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 36. VDD and VDDQ must track each other. 37. tHZ(MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE ( MAX) condition. 38. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 39. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0 volts, provided a minimum of 42 of series resistance is used between the VTT supply and the input pin. 40. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 41. For -335, -262, -265, and -26A speed grades, IDD3N is specified to be 35mA per DDR SDRAM device at 100 MHz. 42. Random addressing changing and 50 percent of data changing at every transfer. 43. Random addressing changing and 100 percent of data changing at every transfer. 44. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Notes 45. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 46. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 48. When an input signal is HIGH or LOW, it is defined as a steady state logic high or logic low. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Initialization Initialization To ensure device operation the DRAM must be initialized as described below: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN Simultaneously apply power to VDD and VDDQ. Apply VREF and then VTT power. Assert and hold CKE at a LVCMOS logic LOW. Provide stable CLOCK signals. Wait at least 200s. Bring CKE high and provide at least one NOP or DESELECT command. At this point the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a SSTL_2 input unless a power cycle occurs. Perform a PRECHARGE ALL command. Wait at least tRP time, during this time NOPs or DESELECT commands must be given. Using the LMR command program the extended mode register (E0 = 0 to enable the DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set to 0; where n = most significant bit). Wait at least tMRD time, only NOPs or DESELECT commands are allowed. Using the LMR command program the Mode Register to set operating parameters and to reset the DLL. Note at least 200 clock cycles are required between a DLL reset and any READ command. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. Issue a PRECHARGE ALL command. Wait at least tRP time, only NOPs or DESELECT commands are allowed. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). Wait at least tRFC time, only NOPs or DESELECT commands are allowed. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). Wait at least tRFC time, only NOPs or DESELECT commands are allowed. Although not required by the Micron device, JEDEC requires a LMR command to clear the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters should be utilized as in step 11. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. At this point the DRAM is ready for any valid command. Note 200 clock cycles are required between step 11 (DLL Reset) and any READ command. 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Initialization Figure 10: Initialization Flow Diagram Step pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 1 VDD and VDDQ Ramp 2 Apply VREF and VTT 3 CKE must be LVCMOS Low 4 Apply stable CLOCKs 5 Wait at least 200s 6 Bring CKE High with a NOP command 7 PRECHARGE ALL 8 Assert NOP or DESELECT for tRP time 9 Configure Extended Mode Register 10 Assert NOP or DESELECT for tMRD time 11 Configure Load Mode Register and reset DLL 12 Assert NOP or DESELECT for tMRD time 13 PRECHARGE ALL 14 Assert NOP or DESELECT for tRP time 15 Issue AUTO REFRESH command 16 Assert NOP or DESELECT commands for tRFC 17 Issue AUTO REFRESH command 18 Assert NOP or DESELECT for tRFC time 19 Optional LMR command to clear DLL bit 20 Assert NOP or DESELECT for tMRD time 21 DRAM is ready for any valid command 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Register and PLL Specifications Register and PLL Specifications Table 17: Register Timing Requirements and Switching Characteristics Note: 1 0C TA +70C VDD = 2.5V 0.2V Register SSTL (bit pattern by JESD82-3 or JESD82-4) Symbol Paramerter Condition Min Max Units fclock tpd tPHL tw Clock Frequency Clock to Output Time Reset to Output Time Pulse Duration 30pF to GND and 50 to VTT 1.1 2.5 200 2.8 5 - MHz ns ns ns - 22 22 ns ns 2 3 0.75 0.90 0.75 0.90 - ns ns ns ns 4, 6 5, 6 4, 6 5, 6 tact tinact tsu th CK, CK# HIGH or LOW Differential Inputs Active Time Differential Inputs Inactive Time Setup Time, Fast Slew Rate Data Before CK HIGH, CK# LOW Setup Time, Slow Slew Rate Hold Time, Fast Slew Rate Data After CK HIGH, CK# LOW Hold Time, Slow Slew Rate Notes Notes: 1. The timing and switching specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. 2. Data inputs must be low a minimum time of tact (MAX), after RESET# is taken HIGH. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact (MAX), after RESET# is taken LOW. 4. For data signal input slew rate 1 V/ns. 5. For data signal input slew rate 0.5 V/ns and < 1 V/ns. 6. CK, CK# signals input slew rate 1 V/ns. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Register and PLL Specifications Table 18: PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 0C TA +70C VDD = 2.5V 0.2V Parameter Symbol Operating Clock Frequency Input Duty Cycle Stabilization Time Cycle to Cycle Jitter Static Phase Offset Output Clock Skew Period Jitter Half-Period Jitter Input Clock Slew Rate Output Clock Slew Rate f CK tDC t STAB t JITCC t t SKO tJIT PER t JITHPER tLS I tLS O Min Nominal Max Units notes 60 40 -75 -50 -75 -100 1.0 1.0 0 - 170 60 100 75 50 100 75 100 4 2 MHz % ms ps ps ps ps ps V/ns V/ns 2, 3 4 5 6 6 7 Notes: 1. The timing and switching specifications for the PLL listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this PLL is available in JEDEC Standard JESD82. 2. The PLL must be able to handle spread spectrum induced skew. 3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. 5. Static Phase Offset does not include Jitter. 6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. 7. The Output Slew Rate is determined from the IBIS model: VDD CDCV857 VCK R=60 R=60 VDD/2 VCK GND pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Serial Presence-Detect Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure 12, Definition of Start and Stop). SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SPD Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 13, Acknowledge Response From Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. Figure 11: Data Validity SCL SDA DATA STABLE pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN DATA CHANGE 34 DATA STABLE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Serial Presence-Detect Figure 12: Definition of Start and Stop SCL SDA START BIT Figure 13: STOP BIT Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Serial Presence-Detect Table 19: EEPROM Device Select Code Most significant bit (b7) is sent first Device Type Identifier Select Code RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Memory Area Select Code (two arrays) Protection Register Select Code Table 20: Chip Enable EEPROM Operating Modes Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write Figure 14: RW Bit WC Bytes 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 1 1 16 Initial Sequence START, Device Select, RW = `1' START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1' Similar to Current or Random Address Read START, Device Select, RW = `0' START, Device Select, RW = `0' SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Serial Presence-Detect Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V Parameter/Condition Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICC 2.3 VDD x 0.7 -1 - - - - - 3.6 VDD + 0.5 VDD + 0.3 0.4 10 10 30 2 V V V V A A A mA SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz Table 22: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V Parameter/condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Symbol Min Max Units Notes tAA 0.2 1.3 200 0.9 s s ns ns s s s ns s s KHz ns s s ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT tSU:STA tSU:STO tWRC 100 0.6 0.6 10 2 2 3 4 Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Serial Presence-Detect Table 23: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 40 Byte 0 1 2 3 4 5 6 7 8 9 Description Number of SPD Bytes Used by Micron Total Number of Bytes In SPD Device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of Physical Ranks on DIMM Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, tCK (CAS Latency = 2.5) (See note 1) Entry (Version) MT9VDDT1672 MT9VDDT3272 MT9VDDT6472 128 256 SDRAM DDR 12 or 13 10 or 11 80 08 07 0C 0A 80 08 07 0D 0A 80 08 07 0D 0B 1 72 0 SSTL 2.5V 6ns(-335) 7ns (-262/-26A) 7.5ns (-265) 8ns (-202) 01 48 00 04 60 70 75 80 70 75 80 02 80 08 01 48 00 04 60 70 75 80 70 75 80 02 82 08 01 48 00 04 60 70 75 80 70 75 80 02 82 08 08 01 08 01 08 01 N/A 0E 04 0C 01 02 26 C0 75 A0 70 75 80 00 0E 04 0C 01 02 26 C0 75 A0 70 75 80 00 0E 04 0C 01 02 26 C0 75 A0 70 75 80 00 N/A 00 00 00 18ns (-335) 15ns (-262) 20ns (-202/-265/-26A) 48 3C 50 30 3C 48 3C 50 30 3C 48 3C 50 30 3C 10 SDRAM Access from Clock, tAC (CAS Latency = 2.5) 11 12 13 ECC Module Configuration Type 15.6 or 7.81s/SELF Refresh Rate/Type 8 SDRAM Device Width (Primary DDR SDRAM) 8 Error-checking DDR SDRAM Data Width 1 clock Minimum Clock Delay, Back-to-Back Random Column Access 2, 4, 8 Burst Lengths Supported 4 Number of Banks on DDR SDRAM Device 2, 2.5 CAS Latencies Supported 0 CS Latency 1 WE Latency Registered, PLL/Diff. Clock SDRAM Module Attributes Fast/Concurrent AP SDRAM Device Attributes: General SDRAM Cycle Time, tCK (CAS Latency = 2) 7.5ns (-335/-262/-26A) 10ns (-265/-202) 0.70ns (-335) SDRAM Access from CK, tAC (CAS Latency 0.75ns (-262/-26A/-265) = 2) 0.8ns (-202) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SDRAM Cycle Time, tCK (CAS Latency = 1.5) SDRAM Access from CK, tAC (CAS Latency = 1.5) Minimum Row Precharge Time, tRP Minimum Row Active to Row Active, tRRD pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 0.7(-335) 0.75ns (-262/-26A/-265) 0.8ns (-202) 12ns (-335) 15ns (-262/-26A/-265/-202) 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Serial Presence-Detect Table 23: Serial Presence-Detect Matrix (Continued) "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 40 Byte 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46 47 48-61 62 63 64 65-71 72 73-90 91 92 Description t Entry (Version) MT9VDDT1672 MT9VDDT3272 MT9VDDT6472 18ns (-335) 15ns (-262) 20ns (-202/-265/-26A) 48 3C 50 2A 2D 28 20 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 2D 32 3C 55 75 A0 00 10/01 00 10 4E/3F E1/D2 0E/FF 3E/2F D9/CA 2C FF 01-0C Variable Data 01-09 00 48 3C 50 t 42ns (-335) 2A Minimum RAS# Pulse Width, RAS (See 45ns (-262/-26A/-265) 2D note 2) 40ns (-202) 28 128MB, 256MB, 512MB 20 Module Rank Density 0.80ns (-335) 80 Address And Command Setup Time, tISs 1ns (-262/-26A/-265) A0 (See note 3) 1.1ns (-202) B0 0.80ns (-335) 80 Address And Command Hold Time, tIHs 1ns (-262/-26A/-265) A0 (See note 3) 1.1ns (-202) B0 0.45ns (-335) 45 Data/ Data Mask Input Setup Time, tDS 0.50ns (-262/-26A/-265) 50 0.60ns (-202) 60 0.45ns (-335) 45 Data/ Data Mask Input Hold Time, tDH 0.50ns (-262/-26A/-265) 50 0.60ns (-202) 60 00 Reserved 60ns (-335/-262) 3C Min Active Auto Refresh Time tRC 65ns (-26A/-265) 41 70ns (-202) 46 72ns (-335) 48 Minimum Auto Refresh to Active/ Auto 75ns (-262/-26A/-265) 4B Refresh Command Period, tRFC 80ns (-202) 50 12ns (-335) 30 SDRAM Device Max Cycle Time, tCKMAX 13ns (-262/-26A/-265/-202) 34 0.4ns (-335) 2D SDRAM Device Max DQS-DQ Skew Time, tDQSQ 0.5ns (-262/-26A/-265) 32 0.6ns (-202) 3C 0.5ns (-335) 55 SDRAM Device Max Read Data Hold Skew 0.75ns (-262/-26A/-265) 75 Facto,r tQHS 1.0ns (-202) A0 00 Reserved Standard/Low-Profile 10/01 DIMM Height 00 Reserved Release 1.0 10 SPD Revision -335 2B/1C Checksum for Bytes 0-62 -262 BE/AF (Standard/Low-profile) -26A EB/DC -265 1B/0C -202 B6/A7 MICRON 2C Manufacturer's JEDEC ID Code (Continued) FF Manufacturer's JEDEC ID Code 01-12 01-0C Manufacturing Location Variable Data Module Part Number (ASCII) 1-9 01-09 PCB Identification Code 0 00 Identification Code (Continued) Minimum RAS# to CAS# Delay, RCD pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 39 48 3C 50 2A 2D 28 20 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 2D 32 3C 55 75 A0 00 10/01 00 10 8F/80 22/13 4F/40 7F/70 1A/0B 2C FF 01-0C Variable Data 01-09 00 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Serial Presence-Detect Table 23: Serial Presence-Detect Matrix (Continued) "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 40 Byte 93 94 95-98 99-127 Description Entry (Version) MT9VDDT1672 MT9VDDT3272 MT9VDDT6472 Variable Data Variable Data Variable Data -- Year of Manufacture in BCD Week of Manufacture in BCD Module Serial Number Manufacturer-Specific Data (RSVD) Variable Data Variable Data Variable Data -- Variable Data Variable Data Variable Data -- Notes: 1. Value for -262/-26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns. 2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual device spec. value is 40ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worstcase (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Module Dimensions Module Dimensions All dimensions are in inches (millimeters); MAX or typical where noted. MIN Figure 15: 184-Pin DIMM Dimensions (Standard) FRONT VIEW 0.125 (3.175) MAX 5.256 (133.50) 5.244 (133.20) U10 U1 U3 U5 U9 U7 1.705 (43.31) 1.695 (43.05) 0.079 (2.00) R (4X) U11 U13 U12 0.700 (17.78) TYP. 0.098 (2.50) D (2X) 0.091 (2.30) TYP. 0.035 (0.90) R PIN 1 0.050 (1.27) 0.040 (1.02) TYP. TYP. 2.55 (64.77) 0.091 (2.30) TYP. 0.054 (1.37) 0.046 (1.17) 0.394 (10.00) TYP. 0.250 (6.35) TYP. 1.95 (49.53) PIN 92 4.750 (120.65) BACK VIEW U15 U17 U19 U21 PIN 184 Figure 16: PIN 93 184-Pin DIMM Dimensions (Low-Profile) 0.125 (3.175) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (4X) U11 U1 U5 U3 U7 U9 1.205 (30.61) 1.195 (30.35) U12 0.700 (17.78) TYP. 0.098 (2.50) D (2X) 0.091 (2.30) TYP. 0.035 (0.90) R PIN 1 0.050 (1.27) 0.040 (1.02) TYP. TYP. 2.55 (64.77) 0.091 (2.30) TYP. 0.394 (10.00) TYP. 0.250 (6.35) TYP. 1.95 (49.53) 0.054 (1.37) 0.046 (1.17) PIN 92 4.750 (120.65) BACK VIEW U13 U15 U17 U19 U21 U10 PIN 93 PIN 184 pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM Data Sheet Designation Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. pdf: 09005aef80e119b2, source: 09005aef80a2e15c DD9C16_32_64x72_2.fm - Rev. D 8/05 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.