MT9VDDT1672G-202XX - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Features

pdf: 09005aef80e119b2, source: 09005aef80a2e15c Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDR SDRAM Registered DIMM

MT9VDDT1672 – 128MB

MT9VDDT3272 – 256MB

MT9VDDT6472 – 512MB

For the latest data sheet, please refer to the Micron® Web site: www.micron.com/products/modules

Features

• 184-pin, dual in-line memory modules (DIMM)

• Fast data transfer rates: PC1600, PC2100, and

PC2700

• Supports ECC error detection and correction

• Registered inputs with one-clock delay

• Phase-lock loop (PLL) clock driver to reduce loading

• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR

SDRAM components

• 128MB (16 Meg x 72), 256MB (32 Meg x 72), and

512MB (64 Meg x 72)

•V

DD= VDDQ= +2.5V

•V

DDSPD = +2.3V to +3.6V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture

• Differential clock inputs (CK and CK#)

• Four internal device banks for concurrent operation

• Selectable burst lengths: 2, 4, or 8

• Auto precharge option, auto refresh and self refresh

modes

• 15.6µs (128MB); 7.8125µs (256MB, 512MB)

maximum average periodic refresh interval

• Serial Presence-Detect (SPD) with EEPROM

• Selectable READ CAS latency

• Gold edge contacts

Figure 1: 184-Pin DIMM (MO-206)

Notes: 1. Contact Micron for product availability; not

recommended for new designs.

2. CL = Device CAS (READ) Latency; registered

mode adds one clock cycle to CL.

3. Available in 128MB density only.

Options Marking

• Operating Temperature Range

Commercial No Mark

•Package

184-pin DIMM (standard) G

184-pin DIMM (lead-free)1Y

• Memory Clock, Speed, CAS Latency2

6ns (167 MHz), 333 MT/s, CL = 2.5 -3353

7.5ns (133 Mhz), 266 MT/s, CL = 2 -2621

7.5ns (133 Mhz), 266 MT/s, CL = 2 -26A1

7.5ns (133 Mhz), 266 MT/s, CL = 2.5 -2651

10ns (100 Mhz), 200 MT/s, CL = 2 -2021

•PCB Height

Standard 1.7in. (43.18mm)1

See note, page 2

Low Profile 1.2in. (30.48mm)1

See note, page 2

Standard PCB 1.7in. (43.18mm)

Low Profile PCB 1.2in. (30.48mm)

pdf: 09005aef80e119b2, source: 09005aef80a2e15c Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Features

Note: All part numbers end with a two-place code (not shown), designating component and PCB

revisions. Consult factory for current revision codes. Example: MT9VDDT3272G-265A1.

Table 1: Address Table

MT9VDDT1672 MT9VDDT3272 MT9VDDT6472

Refresh Count 4K 8K 8K

Row Addressing 4K (A0–A11) 8K(A0–A12) 8K(A0–A12)

Device Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Base Device Configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8)

Column Addressing 1K (A0–A9) 1K(A0–A9) 2K(A0–A9, A11)

Module Rank Addressing 1 (S0#) 1 (S0#) 1 (S0#)

Table 2: Part Numbers and Timing Parameters

Part Number

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Frequency

Latency

(CL - tRCD - tRP)

MT9VDDT1672G-335__ 128MB 16 Meg x 72 2.7 GB/s 6ns/333 MT/s 2.5-2-2

MT9VDDT1672Y-335__ 128MB 16 Meg x 72 2.7 GB/s 6ns/333 MT/s 2.5-2-2

MT9VDDT1672G-262__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT9VDDT1672Y-262__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT9VDDT1672G-26A__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT9VDDT1672Y-26A__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT9VDDT1672G-265__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT9VDDT1672Y-265__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT9VDDT1672G-202__ 128MB 16 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT9VDDT1672Y-202__ 128MB 16 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT9VDDT3272G-262__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT9VDDT3272Y-262__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT9VDDT3272G-26A__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT9VDDT3272Y-26A__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT9VDDT3272G-265__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT9VDDT3272Y-265__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT9VDDT3272G-202__ 256MB 32 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT9VDDT3272Y-202__ 256MB 32 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT9VDDT6472G-262__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT9VDDT6472Y-262__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2

MT9VDDT6472G-26A__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT9VDDT6472Y-26A__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT9VDDT6472G-265__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT9VDDT6472Y-265__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT9VDDT6472G-202__ 512MB 64 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT9VDDT6472Y-202__ 512MB 64 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

pdf: 09005aef80e119b2, source: 09005aef80a2e15c Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

PLL and Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Serial Presence-Detect Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

DLL Enable/Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Register and PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Serial Presence-Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

SPD Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

SPD Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

SPD Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

SPD Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Module Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

pdf: 09005aef80e119b2, source: 09005aef80a2e15c Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

List of Figures

Figure 1: 184-Pin DIMM (MO-206) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: Pin Locations (184-Pin DIMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 3: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 4: Mode Register Definition Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 5: CAS Latency Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 6: Extended Mode Register Definition Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 7: Derating Data Valid Window (tQH - tDQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 8: Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 9: Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 10: Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 11: Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 12: Definition of Start and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 13: Acknowledge Response From Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 14: SPD EEPROM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 15: 184-Pin DIMM Dimensions (Standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 16: 184-Pin DIMM Dimensions (Low-Profile) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

pdf: 09005aef80e119b2, source: 09005aef80a2e15c Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

List of Tables

Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 2: Part Numbers and Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3: Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 4: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 5: Burst Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 6: CAS Latency (CL) Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 7: Commands Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 8: DM Operation Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 9: DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 10: AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 11: IDD Specifications and Conditions – 128MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 12: IDD Specifications and Conditions – 256MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 13: IDD Specifications and Conditions – 512MB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 14: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 15: DDR Device Electrical Characteristics and Recommended AC Operating Conditions. . . . . . . . . . . .22

Table 16: DDR Device Electrical Characteristics and Recommended AC Operating Conditions. . . . . . . . . . . .23

Table 17: Register Timing Requirements and Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 18: PLL Clock Driver Timing Requirements and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . .33

Table 19: EEPROM Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 20: EEPROM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 21: Serial Presence-Detect EEPROM DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 22: Serial Presence-Detect EEPROM AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 23: Serial Presence-Detect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

pdf: 09005aef80e119b2, source: 09005aef80a2e15c Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Pin Assignments and Descriptions

Notes: 1. Pin 115 is no connect (NC) for 128MB, A12 for 256MB and 512MB.

Figure 2: Pin Locations (184-Pin DIMM)

Table 3: Pin Assignment

184-Pin DIMM Front 184-Pin DIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1VREF 24 DQ17 47 DQS8 70 VDD 93 VSS 116 VSS 139 VSS 162 DQ47

2DQ025 DQS2 48 A0 71 NC 94 DQ4 117 DQ21 140 DM8 163 NC

SS 26 VSS 49 CB2 72 DQ48 95 DQ5 118 A11 141 A10 164 VDDQ

4DQ127 A9 50 VSS 73 DQ49 96 VDDQ119 DM2 142 CB6 165 DQ52

5DQS028 DQ18 51 CB3 74 VSS 97 DM0 120 VDD 143 VDDQ166 DQ53

6DQ229 A7 52 BA1 75 DNU 98 DQ6 121 DQ22 144 CB7 167 NC

DD 30 VDDQ53 DQ32 76 DNU 99 DQ7 122 A8 145 VSS 168 VDD

8 DQ3 31 DQ19 54 VDDQ77VDDQ 100 VSS 123 DQ23 146 DQ36 169 DM6

9NC32 A5 55 DQ33 78 DQS6 101 NC 124 VSS 147DQ37170DQ54

10 RESET# 33 DQ24 56 DQS4 79 DQ50 102 NC 125 A6 148 VDD 171 DQ55

11 VSS 34 VSS 57 DQ34 80 DQ51 103 NC 126 DQ28 149 DM4 172 VDDQ

12 DQ8 35 DQ25 58 VSS 81 VSS 104 VDDQ127DQ29150DQ38173 NC

13 DQ9 36 DQS3 59 BA0 82 NC 105 DQ12 128 VDDQ151DQ39174DQ60

14 DQS1 37 A4 60 DQ35 83 DQ56 106 DQ13 129 DM3 152 VSS 175 DQ61

15 VDDQ38 VDD 61 DQ40 84 DQ57 107 DM1 130 A3 153 DQ44 176 VSS

16 DNU 39 DQ26 62 VDDQ85 VDD 108 VDD 131 DQ30 154RAS#177DM7

17 DNU 40 DQ27 63 WE# 86 DQS7 109 DQ14 132 VSS 155DQ45178DQ62

18 VSS 41 A2 64 DQ41 87 DQ58 110 DQ15 133 DQ31 156 VDDQ179 DQ63

19 DQ10 42 VSS 65 CAS# 88 DQ59 111 NC 134 CB4 157 S0# 180 VDDQ

20 DQ11 43 A1 66 VSS 89 VSS 112 VDDQ 135 CB5 158 NC 181 SA0

21 CKE0 44 CB0 67 DQS5 90 NC 113 NC 136 VDDQ 159 DM5 182 SA1

22 VDDQ45 CB1 68 DQ42 91 SDA 114 DQ20 137 CK0 160 VSS 183 SA2

23 DQ16 46 VDD 69 DQ43 92 SCL 115 NC/A12 138 CK0# 161 DQ46 184 VDDSPD

PIN 1

U1 U5 U7 U9

U15 U17 U19 U21

PIN 52 PIN 53 PIN 92

Back View

Front View

U10

U11 U12 U13

Standard 1.7in. (43.18mm)

PIN 93

PIN 144

PIN 145

PIN 184

PIN 1 PIN 52 PIN 53 PIN 92

U1 U3

U11

U12

U5 U7 U9

U10

U15 U17

U13

U19 U21

Indicates a V

or V

Q pin Indicates a V

Front View

Low Profile 1.2in. (30.48mm)

Back View

PIN 93

PIN 144

PIN 145

PIN 184

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Pin Assignments and Descriptions

Table 4: Pin Descriptions

Pin numbers may not correlate with symbols. Refer to pin assignment tables on page 6 for more information

Pin Numbers Symbol Type Description

63, 65, 154 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define

the command being entered.

137, 138 CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive

edge of CK and negative edge of CK#. Output data (DQs and

DQS) is referenced to the crossings of CK and CK#.

21 CKE0 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the

internal clock, input buffers, and output drivers. Taking CKE LOW

provides PRECHARGE POWER-DOWN and SELF REFRESH

operations (all device banks idle), or ACTIVE POWER-DOWN (row

ACTIVE in any device bank). CKE is synchronous for POWER-

DOWN entry and exit, and for SELF REFRESH entry. CKE is

asynchronous for SELF REFRESH exit and for disabling the outputs.

CKE must be maintained HIGH throughout read and write

accesses. Input buffers (excluding CK, CK# and CKE) are disabled

during POWER-DOWN. Input buffers (excluding CKE) are disabled

during SELF REFRESH. CKE is an SSTL_2 input but will detect an

LVCMOS LOW level after VDD is applied and until CKE is first

brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2

input only.

157 S0# Input Chip Select: S# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when S#

is registered HIGH. S# is considered part of the command code.

52, 59 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

27, 29, 32, 37, 41, 43,

48, 115 (A12), 118, 122,

125, 130, 141

A0–A11

(128MB)

A0–A12

(256MB, 512MB)

Input Address Inputs: Provide the row address for ACTIVE commands,

and the column address and auto precharge bit (A10) for READ/

WRITE commands, to select one location out of the memory array

in the respective device bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one

device bank (A10 LOW, device bank selected by BA0, BA1) or all

device banks (A10 HIGH). The address inputs also provide the op-

code during a MODE REGISTER SET command. BA0 and BA1

define which mode register (mode register or extended mode

91 SDA Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to

transfer addresses and data into and out of the presence-detect

portion of the module.

92 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the

presence-detect data transfer to and from the module.

181, 182, 183 SA0–SA2 Input Presence-Detect Address Inputs: These pins are used to configure

the presence-detect device.

10 RESET# Input Asynchronously forces all register outputs LOW when RESET# is

LOW. This signal can be used during power-up to ensure CKE is

LOW and SDRAM DQ is High-Z.

44, 45, 49, 51, 134, 135,

142, 144

CB0–CB7 Input/

Output

Check bits.

97, 107, 119, 129, 140, 149,

159, 169, 177

DM0–DM8 Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH

blocks WRITE operation. DM state does not affect READ

command.

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Pin Assignments and Descriptions

5, 14, 25, 36, 47, 56, 67, 78,

DQS0–DQS8 Input/

Output

Data Strobe: Output with READ data, input with WRITE data. DQS

is edge-aligned with READ data, centered in WRITE data. Used to

capture data.

2, 4, 6, 8, 12, 13, 19, 20, 23,

24, 28, 31, 33, 35, 39, 40,

53, 55, 57, 60, 61, 64, 68,

69, 72, 73, 79, 80, 83, 84,

87, 88, 94, 95, 98, 99, 105,

106, 109, 110, 114, 117,

121, 123, 126, 127, 131,

133, 146, 147, 150, 151,

153, 155, 161, 162, 165,

166, 170, 171, 174, 175,

178, 179

DQ0–DQ63 Input/

Output

Data I/Os: Data bus.

REF Supply SSTL_2 reference voltage.

15, 22, 30, 54, 62, 77, 96,

104, 112, 128, 136, 143,

156, 164, 172, 180

VDDQ Supply DQ Power Supply: +2.5V ±0.2V.

7, 38, 46, 70, 85, 108, 120,

148, 168

VDD Supply Power Supply: +2.5V ±0.2V.

3, 11, 18, 26, 34, 42, 50, 58,

66, 74, 81, 89, 93, 100, 116,

124, 132, 139, 145, 152,

160, 176

VSS Supply Ground.

184 VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V.

9, 71, 82, 90, 101, 102, 103,

111, 113, 115 (128MB),

158, 163, 167, 173

NC — No Connect: These pins should be left unconnected.

16, 17, 75, 76 DNU — Do Not Use: These pins are not connected on this module but are

assigned pins on other modules in this product family.

Table 4: Pin Descriptions

Pin numbers may not correlate with symbols. Refer to pin assignment tables on page 6 for more information

Pin Numbers Symbol Type Description

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Functional Block Diagram

All resistor values are 22Ω unless otherwise specified. Per industry standard, Micron

modules utilize various component speed grades, as referenced in the module part

number guide at www.micron.com/numberguide.

Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB);

MT46V32M8TG (256MB); MT46V64M8TG (512MB). Lead-free modules use the follow-

ing DDR SDRAM devices: MT46V16M8P (128MB); MT46V32M8P (256MB);

MT46V64M8P (512MB). Contact Micron for availability of IT DIMMs.

Figure 3: Functional Block Diagram

SA0

SERIAL PD

SDA

SA1

SA2

S0#

BA0, BA1

A0-A11 (128MB)

A0-A12 (256MB, 512MB)

RAS#

RS0#

RBA0, RBA1: DDR SDRAMS

RA0-RA11: DDR SDRAMS

RA0-RA12: DDR SDRAMS

RRAS#: DDR SDRAMS

RCAS#: DDR SDRAMS

RCKE0: DDR SDRAMS

RWE#: DDR SDRAMS

RESET#

CAS#

CKE0

WE#

CK#

VREF

VSS

DDR SDRAMS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U17

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U19

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U21

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

RS0#

PLL

DDR SDRAM

SCL

DM CS# DQS

DQS0

DM4

DQS4

DM1

DQS1

DM5

DQS5

DM2

DQS2

DM6

DQS6

DM CS# DQS

U15

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DM3

DQS3

DM7

DQS7

DM8

DQS8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

VDDQ

VDD DDR SDRAMS

DDR SDRAMS

CK0

CK0#

120 U12

U10

U11, U13

SPD/EEPROM

VDDSPD

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

General Description

The MT9VDDT1672, MT9VDDT3272, and MT9VDDT6472

are high-speed CMOS, dynamic

random-access, 128MB, 256MB, and 512MB registered memory modules organized in a

x72 (ECC) configuration. DDR SDRAM modules use internally configured quad-bank

DDR SDRAM devices.

DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-

tion. The double data rate architecture is essentially a 2n-prefetch architecture with an

interface designed to transfer two data words per clock cycle at the I/O pins. A single

read or write access for the DDR SDRAM module effectively consists of a single 2n-bit

wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-

bit wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in

data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR

SDRAM during READs and by the memory controller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with data for WRITEs.

DDR SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK

going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-

mands (address and control signals) are registered at every positive edge of CK. Input

data is registered on both edges of DQS, and output data is referenced to both edges of

DQS, as well as to both edges of CK.

Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a

selected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVE command are used to select the device bank and row to be accessed (BA0,

BA1 select device bank; A0–A11 select device row for 128MB; A0–A12 select device row

for 256MB, 512MB). The address bits registered coincident with the READ or WRITE

command are used to select the device bank and the starting device column location for

the burst access.

DDR SDRAM modules provide for programmable read or write burst lengths of 2, 4, or 8

locations. An auto precharge function may be enabled to provide a self-timed row pre-

charge that is initiated at the end of the burst access.

The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent

operation, thereby providing high effective bandwidth by hiding row precharge and acti-

vation time.

An auto refresh mode is provided, along with a power-saving power-down mode. All

inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class

II compatible. For more information regarding DDR SDRAM operation, refer to the

128Mb, 256Mb, or 512Mb DDR SDRAM component data sheets.

PLL and Register Operation

DDR SDRAM modules operate in registered mode where the control/address input sig-

nals are latched in the register on one rising clock edge and sent to the DDR SDRAM

devices on the following rising clock edge (data access is delayed by one clock). A phase-

lock loop (PLL) on the module is used to redrive the differential clock signals CK and CK#

to the DDR SDRAM devices to minimize system clock loading.

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Mode Register Definition

Serial Presence-Detect Operation

DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is

implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256

bytes. The first 128 bytes can be programmed by Micron to identify the module type and

various SDRAM organizations and timing parameters. The remaining 128 bytes of stor-

age are available for use by the customer. System READ/WRITE operations between the

master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C

bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which

provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on

the module, permanently disabling hardware write protect.

Mode Register Definition

The mode register is used to define the specific mode of operation of DDR SDRAM

devices. This definition includes the selection of a burst length, a burst type, a CAS

latency and an operating mode, as shown in Figure 4, Mode Register Definition Dia-

gram, on page 12. The mode register is programmed via the MODE REGISTER SET com-

mand (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is

programmed again or the device loses power (except for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the contents of the memory, provided it

is performed correctly. The mode register must be loaded (reloaded) when all device

banks are idle and no bursts are in progress, and the controller must wait the specified

time before initiating the subsequent operation. Violating either of these requirements

will result in unspecified operation.

Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequen-

tial or interleaved), A4–A6 specify the CAS latency, and A7–A11 (128MB) or A7–A12

(256MB, 512MB) specify the operating mode.

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length

being programmable, as shown in Figure 4, Mode Register Definition Diagram. The

burst length determines the maximum number of column locations that can be

accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are

available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with

future versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst

length is effectively selected. All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a boundary is reached. The block is

uniquely selected by A1–Ai when the burst length is set to two, by A2–Ai when the burst

length is set to four and by A3–Ai when the burst length is set to eight (where Ai is the

most significant column address bit for a given configuration. See Note 5 of Table 5,

Burst Definition Table, on page 13). The remaining (least significant) address bit(s) is

(are) used to select the starting location within the block. The programmed burst length

applies to both read and write bursts.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved;

this is referred to as the burst type and is selected via bit M3.

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Mode Register Definition

The ordering of accesses within a burst is determined by the burst length, the burst type

and the starting column address, as shown in Figure 5, Burst Definition Table, on

page 13.

Figure 4: Mode Register Definition Diagram

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA0 and BA1)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M9M10M12 M11

Burst LengthCAS Latency BT0*0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

Operating Mode

A10

A11

BA0

BA1

* M13 and M12 (BA0 and BA1)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

256MB and 512MB Modules

128MB Module

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Mode Register Definition

Notes: 1. For a burst length of two, A1-Ai select the two-data-element block; A0 selects the first

access within the block.

2. For a burst length of four, A2-Ai select the four-data-element block; A0-A1 select the first

access within the block.

3. For a burst length of eight, A3-Ai select the eight-data-element block; A0-A2 select the

first access within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the follow-

ing access wraps within the block.

5. i = 9 (128MB, 256MB)

i = 9, 11 (512MB)

Table 5: Burst Definition Table

Burst Length

Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential Type = Interleaved

00-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Table 6: CAS Latency (CL) Table

Allowable Operating Clock Frequency (MHz)

Speed CL = 2 CL = 2.5

-335 75 ≤ f ≤ 133 75 ≤ f ≤ 167

-262 75 ≤ f ≤ 133 75 ≤ f ≤ 133

-26A 75 ≤ f ≤ 133 75 ≤ f ≤ 133

-265 75 ≤ f ≤ 100 75 ≤ f ≤ 133

-202 75 ≤ f ≤ 100 N/A

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Mode Register Definition

Figure 5: CAS Latency Diagram

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ com-

mand and the availability of the first bit of output data. The latency can be set to 2 or 2.5

clocks, as shown in Figure 5, CAS Latency Diagram.

If a READ command is registered at clock edge n, and the latency is m clocks, the data

will be available nominally coincident with clock edge n + m. Figure 6, CAS Latency (CL)

Table, indicates the operating frequencies at which each CAS latency setting can be

used.

Reserved states should not be used as unknown operation or incompatibility with future

versions may result.

Operating Mode

The normal operating mode is selected by issuing a MODE REGISTER SET command

with bits A7–A11 (128MB), or A7–A12 (256MB, 512MB) each set to zero, and bits A0-A6

set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET com-

mand with bits A7 and A9–A11 (128MB), or A7 and A9–A12 (256MB, 512MB) each set to

zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required by

the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER

command is issued to reset the DLL, it should always be followed by a LOAD MODE

CK#

COMMAND

DQS

CL = 2

READ NOP NOP NOP

Burst Length = 4 in the cases shown

Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T0 T1 T2 T2n T3 T3n

DON’T CARETRANSITIONING DATA

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Extended Mode Register

All other combinations of values for A7–A11 (128MB), or A7–A12 (256MB, 512MB) are

reserved for future use and/or test modes. Test modes and reserved states should not be

used because unknown operation or incompatibility with future versions may result.

Extended Mode Register

The extended mode register controls functions beyond those controlled by the mode

These functions are controlled via the bits shown in Figure 6, Extended Mode Register

Definition Diagram. The extended mode register is programmed via the LOAD MODE

stored information until it is programmed again or the device loses power. The enabling

of the DLL should always be followed by a LOAD MODE REGISTER command to the

mode register (BA0/BA1 both low) to reset the DLL.

The extended mode register must be loaded when all device banks are idle and no bursts

are in progress, and the controller must wait the specified time before initiating any sub-

sequent operation. Violating either of these requirements could result in unspecified

operation.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power-

up initialization and upon returning to normal operation after having disabled the DLL

for the purpose of debug or evaluation. (When the device exits self refresh mode, the

DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE

HIGH must occur before a READ command can be issued.

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Extended Mode Register

Figure 6: Extended Mode Register Definition Diagram

Notes: 1. BA1 and BA0 (E13 and E12 for 128MB, E14 and E13 for 256MB and 512MB) must be “0, 1”

to select the Extended Mode Register (vs. the base Mode Register.

2. QFC# is not supported.

Operating Mode

Reserved

–

Valid

–

DLL

Enable

Disable

DLL11

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Drive Strength

Normal

E1,

Operating Mode

A10

A11A12

BA1 BA0

1314

E3E4

–

E6 E5

E7E8E9

–

E10E11

–

E12

DLL11

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Operating Mode

A10

A11

BA1 BA0

128MB Module

256MB and 512MB Modules

–

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Commands

Table 7, Commands Truth Table, and Table 8, DM Operation Truth Table, provide a gen-

eral reference of available commands. For a more detailed description of commands and

operations, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM component data sheet.

Notes: 1. DESELECT and NOP are functionally interchangeable.

2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB)

provide row address.

3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB)

provide column address; A10 HIGH enables the auto precharge feature (nonpersistent),

and A10 LOW disables the auto precharge feature.

4. Applies only to read bursts with auto precharge disabled; this command is undefined (and

should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.

5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device

banks are precharged and BA0–BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”

except for CKE.

8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0

select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combina-

tions of BA0–BA1 are reserved). A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide the

op-code to be written to the selected mode register.

Table 7: Commands Truth Table

CKE is HIGH for all commands shown except SELF REFRESH; all states/sequences not shown are illegal or reserved

Name (Function) CS# RAS# CAS# WE# Address Notes

DESELECT (NOP) HXXX X 1

NO OPERATION (NOP) LHHH X 1

ACTIVE (Select bank and activate row) L L H H Bank/Row 2

READ (Select bank and column, and start READ burst) L H L H Bank/Col 3

WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 3

BURST TERMINATE LHHL X 4

PRECHARGE (Deactivate row in bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LLLH X 6, 7

LOAD MODE REGISTER L L L L Op-Code 8

Table 8: DM Operation Truth Table

Used to mask write data; provided coincident with the corresponding data

Name (Function) DM DQs

WRITE Enable LValid

WRITE Inhibit HX

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Absolute Maximum Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on VREF and Inputs Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on I/O Pins Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDDQ +0.5V

Operating Temperature

TA (commercial). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C

Storage Temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +150°C

Short Circuit Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA

Electrical Specifications

Table 9: DC Electrical Characteristics and Operating Conditions

Notes: 1–5, 14; notes appear on pages 25–29; 0°C ≤ TA ≤ +70°C

Parameter/Condition Symbol Min Max Units Notes

Supply Voltage VDD 2.3 2.7 V 32, 36

I/O Supply Voltage VDDQ 2.3 2.7 V 32, 36, 39

I/O Reference Voltage VREF 0.49 ×

VDDQ

0.51 ×

VDDQ

V6, 39

I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 39

Input High (Logic 1) Voltage VIH(DC)VREF + 0.15 VDD + 0.3 V 25

Input Low (Logic 0) Voltage VIL(DC)-0.3VREF - 0.15 V 25

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤

1.35V (All other pins not under test = 0V)

Command/

Address

, RAS#,

CAS#, WE#, CKE,

-5 5

µA 47

CK, CK# -10 10

DM -2 2

OUTPUT LEAKAGE CURRENT: Single-Rank

DIMM

(DQ are disabled; 0V ≤ VOUT ≤ VDDQ)

DQ, DQS IOZ -5 5 µA 47

OUTPUT LEVELS

High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT)

Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)

IOH -16.8 – mA

33, 34

IOL 16.8 – mA

Table 10: AC Input Operating Conditions

Notes: 1–5, 14, 48; notes appear pages 25–29; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

Parameter/Condition Symbol Min Max Units Notes

Input High (Logic 1) Voltage VIH(AC)VREF + 0.310 – V 12, 25, 35

Input Low (Logic 0) Voltage VIL(AC)–VREF - 0.310 V 12, 25, 35

I/O Reference Voltage VREF(AC)0.49 × VDDQ0.51 × VDDQV 6

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Electrical Specifications

Table 11: IDD Specifications and Conditions – 128MB

DDR SDRAM components only

Notes: 1–5, 8, 10, 12, 48; notes appear on pages 25–29; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

Max

Parameter/Condition Symbol -335 -262

-26A/

-265/

-202 Units Notes

OPERATING CURRENT: One device bank; Active-Precharge;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs

changing once every two clock cycles

IDD0 1,125 990 945 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read

Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT =

0mA; Address and control inputs changing once per clock

cycle

IDD1 1,215 1,080 1,080 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks idle; Power-down mode;

CK =

CK (MIN); CKE = (LOW)

IDD2P 27 27 27 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

tCK = tCK MIN; CKE = HIGH; Address and other control

inputs changing once per clock cycle. VIN = VREF for DQ, DQS,

and DM

IDD2F 405 405 360 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank

active; Power-down mode;

CK =

CK (MIN);

CKE = LOW

IDD3P 225 225 180 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One

device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK

(MIN); DQ, DM and DQS inputs changing twice per clock

cycle; Address and other control inputs changing once per

clock cycle

IDD3N 450 450 405 mA 20, 41

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;

One bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4R 1,260 1,170 1,125 mA 20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;

One device bank active; Address and control inputs

changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and

DQS inputs changing twice per clock cycle

IDD4W 1,260 1,125 1,080 mA 20

AUTO REFRESH CURRENT tREFC = tRFC

(MIN)

IDD5 2,385 1,980 1,980 mA 24, 44

tREFC = 15.625µs IDD5A 45 45 45 mA 24, 44

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6 27 27 18 mA 9

OPERATING CURRENT: Four device bank interleaving READs

(BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK

(MIN); Address and control inputs change only during Active

READ, or WRITE commands

IDD7 3,195 2,970 2,925 mA 20, 43

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Electrical Specifications

Table 12: IDD Specifications and Conditions – 256MB

DDR SDRAM components only

Notes: 1–5, 8, 10, 12, 48; notes appear on pages 25–29; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

Max

Parameter/Condition Symbol -262

-26A/

-265/

-202 Units Notes

OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC

(MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per

clock cyle; Address and control inputs changing once every two clock

cycles

IDD0 1,125 1,080 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read Precharge; Burst =

4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control

inputs changing once per clock cycle

IDD1 1,440 1,305 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks idle;

Power-down mode;

CK =

CK (MIN); CKE = (LOW)

IDD2P 36 36 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK

MIN; CKE = HIGH; Address and other control inputs changing once per

clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2F 405 405 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank active;

Power-down mode;

CK =

CK (MIN);

CKE = LOW

IDD3P 225 225 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank;

Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS

inputs changing twice per clock cycle; Address and other control inputs

changing once per clock cycle

IDD3N 450 450 mA 20, 41

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank

active; Address and control inputs changing once per clock cycle; tCK =

tCK (MIN); IOUT = 0mA

IDD4R 1,350 1,350 mA 20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device

bank active; Address and control inputs changing once per clock cycle;

tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle

IDD4W 1,350 1,350 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5 2,115 2,115 mA 24, 44

tREFC = 7.8125µs IDD5A 54 54 mA 24, 44

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6 36 36 mA 9

OPERATING CURRENT: Four device bank interleaving READs (BL = 4)

with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and

control inputs change only during Active READ, or WRITE commands

IDD7 3,150 3,150 mA 20, 43

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Electrical Specifications

Table 13: IDD Specifications and Conditions – 512MB

DDR SDRAM components only

Notes: 1–5, 8, 10, 12, 48; notes appear on pages 25–29; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

Max

Parameter/Condition Symbol -262

-26A/

-265/

-202 Units Notes

OPERATING CURRENT: One device bank; Active-Precharge;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs changing

once every two clock cycles

IDD0 1,170 1,035 mA 20, 42

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address

and control inputs changing once per clock cycle

IDD1 1,440 1,305 mA 20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)

IDD2P 45 45 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ, DQS, and DM

IDD2F 405 360 mA 45

ACTIVE POWER-DOWN STANDBY CURRENT: One device

bank

active; Power-down mode;

CK =

CK (MIN); CKE = LOW

IDD3P 315 270 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,

DM andDQS inputs changing twice per clock cycle; Address and

other control inputs changing once per clock cycle

IDD3N 450 405 mA 20, 41

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One

bank active; Address and control inputs changing once per clock

cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4R 1,485 1,305 mA 20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One

device bank active; Address and control inputs changing once per

clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

IDD4W 1,575 1,215 mA 20

AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5 2,610 2,520 mA 24, 44

tREFC = 7.8125µs IDD5A 90 90 mA 24, 44

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6 45 45 mA 9

OPERATING CURRENT: Four device bank interleaving READs (BL =

4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address

and control inputs change only during Active READ, or WRITE

commands

IDD7 3,600 3,150 mA 20, 43

Table 14: Capacitance

Note: 11; notes appear on pages 25–29

Parameter Symbol Min Max Units

Input/Output Capacitance: DQ, DQS, DM CIO 45 pF

Input Capacitance: Command and Address, S#, CK, CK#, CKE CI1 2.5 3.5 pF

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Electrical Specifications

Table 15: DDR Device Electrical Characteristics and Recommended AC Operating Conditions

Notes: 1–5, 8, 12–15, 29; notes appear on pages 25–29; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC Characteristics -335 -262

UnitsParameter Sym Min Max Min Max

Notes

Access window of DQ from CK/CK# tAC -0.7 +0.7 -0.70 +0.70 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 26

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 26

Clock cycle time CL = 2.5 tCK (2.5) 6 13 6 13 ns 40, 46

CL = 2 tCK (2) 7.5 13 7.5 13 ns 40, 46

DQ and DM input hold time relative to DQS tDH 0.45 0.45 ns 23, 27

DQ and DM input setup time relative to DQS tDS 0.45 0.45 ns 23, 27

DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 ns 27

Access window of DQS from CK/CK#

DQSCK

-0.60 +0.60 -0.65 +0.60 ns

DQS input high pulse width tDQSH 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per

access

tDQSQ 0.45 0.45 ns 22, 23

Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.2 0.2 tCK

DQS falling edge from CK rising - hold time tDSH 0.2 0.2 tCK

Half clock period tHP tCH,tCL tCH,tCL ns 30

Data-out high-impedance window from CK/CK# tHZ +0.70 +0.70 ns 16, 37

Data-out low-impedance window from CK/CK# tLZ -0.70 -0.70 ns 16, 37

Address and control input hold time (fast slew rate) tIHF0.75 0.75 ns 12

Address and control input setup time (fast slew rate) tISF0.75 0.75 ns 12

Address and control input hold time (slow slew rate) tIHS0.80 0.8 ns 12

Address and control input setup time (slow slew rate) tISS0.80 0.8 ns 12

Address and control input pulse width (for each input) tIPW 2.2 2.2 ns

LOAD MODE REGISTER command cycle time tMRD 12 15 ns

DQ-DQS hold, DQS to first DQ to go non-valid, per

access

tQH tHP -tQHS tHP-

tQHS

ns 22, 23

Data hold skew factor tQHS 0.55 0.75 ns

ACTIVE to PRECHARGE command tRAS 42 70,000 40

120,000

ns 31

ACTIVE to READ with auto precharge command tRAP 15 15 ns

ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 60 ns

AUTO REFRESH command period 128MB, 256MB tRFC 72 75 ns 44

512MB 120 120 ns

ACTIVE to READ or WRITE delay tRCD 15 15 ns

PRECHARGE command period tRP 15 15 ns 38

DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 38

DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK

ACTIVE bank a to ACTIVE bank b command tRRD 12 15 ns

DQS write preamble tWPRE 0.25 0.25 tCK 19, 19

DQS write preamble setup time

WPRES

00ns18

DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK

Write recovery time tWR 15 15 ns

Internal WRITE to READ command delay tWTR 1 1 tCK 22

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Electrical Specifications

Data valid output window (DVW) na tQH -tDQSQ tQH -tDQSQ ns 21

REFRESH to REFRESH command interval tREFC 70.3 70.3 µs

Average periodic refresh interval tREFI 7.8 7.8 µs 21

Terminating voltage delay to VDD tVTD 0 0 ns

Exit SELF REFRESH to non-READ

command

128MB, 256MB tXSNR 75 75 ns

512MB 127.5 127.5 ns

Exit SELF REFRESH to READ command tXSRD 200 200 tCK

Table 16: DDR Device Electrical Characteristics and Recommended AC Operating Conditions

Notes: 1–5, 8, 12–15, 29; notes appear on pages 25–29; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC Characteristics -26A/-265 -202

Parameter

Sym

Min Max

Min

Max

Units Notes

Access window of DQs from CK/CK# tAC -0.75 +0.75 -0.8 +0.8 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 26

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 26

Clock cycle time CL= 2.5 tCK (2.5) 7.5 13 8 13 ns 40, 46

CL= 2 tCK (2) 7.5/10 13 10 13 ns 40, 46

DQ and DM input hold time relative to DQS tDH 0.5 0.6 ns 23, 27

DQ and DM input setup time relative to DQS tDS 0.5 0.6 ns 23, 27

DQ and DM input pulse width (for each input) tDIPW 1.75 2 ns 27

Access window of DQS from CK/CK# tDQSCK -0.75 +0.75 -0.8 +0.8 ns

DQS input high pulse width tDQSH 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per

access

tDQSQ 0.5 0.6 ns 22, 23

Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.20 0.20 tCK

DQS falling edge from CK rising - hold time tDSH 0.20 0.20 tCK

Half clock period tHP tCH,tCL tCH,tCL ns 30

Data-out high-impedance window from CK/CK# tHZ +0.75 +0.8 ns 16, 37

Data-out low-impedance window from CK/CK# tLZ -0.75 -0.8 ns 16, 37

Address and control input hold time (fast slew rate) tIHF0.90 1.1 ns 12

Address and control input setup time (fast slew rate) tISF0.90 1.1 ns 12

Address and control input hold time (slow slew rate) tIHS11.1ns12

Address and control input setup time (slow slew rate) tISS11.1ns12

Address and control input pulse width (for each input) tIPW 2.2 2.2 ns

LOAD MODE REGISTER command cycle time tMRD 15 16 ns

DQ-DQS hold, DQS to first DQ to go non-valid, per

access

tQH tHP -

tQHS

tHP -

tQHS

ns 22, 23

Data hold skew factor tQHS 0.75 1 ns

ACTIVE to PRECHARGE command tRAS 40

120,000

ns 31

ACTIVE to READ with auto precharge command tRAP 20 20 ns

Table 15: DDR Device Electrical Characteristics and Recommended AC Operating Conditions

(Continued)

AC Characteristics -335 -262

UnitsParameter Sym Min Max Min Max

Notes

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Electrical Specifications

ACTIVE to ACTIVE/AUTO REFRESH command period tRC 65 70 ns

AUTO REFRESH command period tRFC 75 80 ns 44

ACTIVE to READ or WRITE delay tRCD 20 20 ns

PRECHARGE command period tRP 20 20 ns

DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 38

DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK 38

ACTIVE bank a to ACTIVE bank b command tRRD 15 15 ns

DQS write preamble tWPRE 0.25 0.25 tCK

DQS write preamble setup time tWPRES 0 0 ns 19, 19

DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 18

Write recovery time tWR 15 15 ns

Internal WRITE to READ command delay tWTR 1 1 tCK

Data valid output window na tQH -tDQSQ

QH -

DQSQ

ns 22

REFRESH to REFRESH command

interval

128MB tREFC 140.6 140.6 µs 21

256MB, 512MB 70.3 70.3 µs

Average periodic refresh interval 128MB tREFI 15.6 15.6 µs 21

256MB, 512MB 7.8 7.8 µs

Terminating voltage delay to VDD tVTD 0 0 ns

Exit SELF REFRESH to non-READ command tXSNR 75 80 ns

Exit SELF REFRESH to READ command tXSRD 200 200 tCK

Table 16: DDR Device Electrical Characteristics and Recommended AC Operating Conditions

(Continued)

AC Characteristics -26A/-265 -202

Parameter

Sym

Min Max

Min

Max

Units Notes

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Notes

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted

at nominal reference/supply voltage levels, but the related specifications and device

operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environ-

ment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#),

and parameter specifications are guaranteed for the specified AC input levels under

normal use conditions. The minimum slew rate for the input signals used to test the

device is 1V/ns in the range between VIL(AC) and VIH(AC).

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e.,

the receiver will effectively switch as a result of the signal crossing the AC input level,

and will remain in that state as long as the signal does not ring back above [below] the

DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in

the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not

exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC

error and an additional ±25mV for AC noise. This measurement is to be taken at the

nearest VREF by-pass capacitor.

7. VTT is not applied directly to the device. VTT is a system supply for signal termination

resistors, is expected to be set equal to VREF and must track variations in the DC level

of VREF.

8. IDD is dependent upon output loading and cycle rates. Specified values are obtained

with minimum cycle time at CL = 2 for -262, -26A, and -202, CL = 2.5 for -335 and -265

with the outputs open.

9. Enables on-chip refresh and address counters.

10. IDD specifications are tested after the device is properly initialized, and is averaged at

the defined cycle rate.

11. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100

MHz, TA=25°C, V

OUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped

with I/O pins, reflecting the fact that they are matched in loading.

12.

For slew rates < 1V/ns and

≥

0.5 V/ns. If slew rate is < 0.5 V/ns, timing must be derated:

has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while

IH is unaffected. If slew rate exceeds 4.5 V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at

which CK and CK# cross; the input reference level for signals other than CK/CK# is

VREF.

14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period

before VREF stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.

15. The output timing reference level, as measured at the timing reference point indi-

cated in Note 3, is VTT.

Output

(VOUT)

Reference

Point

50Ω

VTT

30pF

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Notes

16. tHZ and tLZ transitions occur in the same access time windows as valid data transi-

tions. These parameters are not referenced to a specific voltage level, but specify

when the device output is no longer driving (HZ) or begins driving (LZ).

17. The intent of the Don’t Care state after completion of the postamble is the DQS-driven

signal should either be high, low, or high-Z and that any signal transition within the

input switching region must follow valid input requirements. That is, if DQS transi-

tions high (above VIHDC (MIN) then it must not transition low (below VIHDC) prior to

tDQSH (MIN)).

18. This is not a device limit. The device will operate with a negative value, but system

performance could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-

mand. The case shown (DQS going from High-Z to logic LOW) applies when no

WRITEs were previously in progress on the bus. If a previous WRITE was in progress,

DQS could be HIGH during this time, depending on tDQSS.

20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the

minimum absolute value for the respective parameter. tRAS (MAX) for IDD measure-

ments is the largest multiple of tCK that meets the maximum absolute value for tRAS.

21. The refresh period 64ms. This equates to an average refresh rate of 15.625µs (128MB)

or 7.8125µs (256MB, 512MB). However, an AUTO REFRESH command must be

asserted at least once every 140.6µs (128MB) or 70.3µs (256MB, 512MB); burst

refreshing or posting by the DDR SDRAM controller greater than eight refresh cycles is

not allowed.

22. The valid data window is derived by achieving other specifications: tHP (tCK/2),

tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porpor-

tionally with the clock duty cycle and a practical data valid window can be derived.

The clock is allowed a maximum duty cycle variation of 45/55, beyond which func-

tionality is uncertain. Figure 7, Derating Data Valid Window (tQH - tDQSQ), shows

derating curves duty cycles ranging between 50/50 and 45/55.

23. Each byte lane has a corresponding DQS.

24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH

during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during

standby).

25. To maintain a valid level, the transitioning edge of the input must:

a. Sustain a constant slew rate from the current AC level through to the target AC

level, VIL (AC) or VIH (AC).

b. Reach at least the target AC level.

c. After the AC target level is reached, continue to maintain at least the target DC

level, VIL (DC) or VIH (DC).

26. CK and CK# input slew rate must be ≥ 1V/ns (2V/ns differentially).

27.

DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If

the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be

added to

DS and

DH for each 100mV/ns reduction in slew rate. If slew rate exceeds

4V/ns, functionality is uncertain.

28. VDD must not vary more than 4 percent if CKE is not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by

the same amount.

30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the

device CK and CK# inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN)

can be satisfied prior to the internal precharge command being issued.

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Notes

Figure 7: Derating Data Valid Window (tQH - tDQSQ)

32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not

more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/

3 of the clock cycle and not exceed either -300mV or 2.2V, whichever is more positive.

However, the DC average cannot be below 2.3V minimum.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current from minimum to maximum pro-

cess, temperature and voltage will lie within the outer bounding lines of the V-I

curve of Figure 8, Pull-Down Characteristics.

b. The variation in driver pull-down current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding

lines of the V-I curve of Figure 8, Pull-Down Characteristics.

c. The full variation in driver pull-up current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve

of Figure 9, Pull-Up Characteristics.

d. The variation in driver pull-up current within nominal limits of voltage and tem-

perature is expected, but not guaranteed, to lie within the inner bounding lines of

the V-I curve of Figure 9, Pull-Up Characteristics.

e. The full variation in the ratio of the maximum to minimum pull-up and pull-

down current should be between 0.71 and 1.4, for device drain-to-source voltages

from 0.1V to 1.0V, and at the same voltage and temperature.

f. The full variation in the ratio of the nominal pull-up to pull-down current should

be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.

34. The voltage levels used are derived from a minimum VDD level and the referenced test

load. In practice, the voltage levels obtained from a properly terminated bus will pro-

vide significantly different voltage values.

3.750 3.700 3.650 3.600 3.550

3.500 3.450

3.400 3.350 3.300 3.250

3.400 3.350 3.300

3.250

3.200 3.150 3.100 3.050

3.000 2.950 2.900

2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55

Clock Duty Cycle

-262/-26A/-265 @ tCK = 10ns

-202 @ tCK = 10ns

-262/-26A/-265 @ tCK = 7.5ns

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Notes

Figure 8: Pull-Down Characteristics

Figure 9: Pull-Up Characteristics

35. VIH overshoot: VIH (MAX) = VDDQ+1.5V for a pulse width ≤ 3ns and the pulse width

can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a

pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.

36. VDD and VDDQ must track each other.

37. tHZ(MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will

prevail over tDQSCK (MIN) + tRPRE ( MAX) condition.

38. tRPST end point and tRPRE begin point are not referenced to a specific voltage level

but specify when the device output is no longer driving (tRPST), or begins driving

(tRPRE).

39. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V.

Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0

volts, provided a minimum of 42Ω of series resistance is used between the VTT supply

and the input pin.

40. The current Micron part operates below the slowest JEDEC operating frequency of 83

MHz. As such, future die may not reflect this option.

41. For -335, -262, -265, and -26A speed grades, IDD3N is specified to be 35mA per DDR

SDRAM device at 100 MHz.

42. Random addressing changing and 50 percent of data changing at every transfer.

43. Random addressing changing and 100 percent of data changing at every transfer.

44. CKE must be active (high) during the entire time a refresh command is executed.

That is, from the time the AUTO REFRESH command is registered, CKE must be

active at each rising clock edge, until tREF later.

160

140

IOUT (mA)

VOUT (V)

Nominal low

Minimum

Nominal high

Maximum

120

100

0.0 0.5 1.0 1.5 2.0 2.5

VOUT (V)

-20

IOUT (mA)

Nominal low

Minimum

Nominal high

Maximum

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0 0.5 1.0 1.5 2.0 2.5

VDDQ - VOUT (V)

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Notes

45. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.

IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to

remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”

46. Whenever the operating frequency is altered, not including jitter, the DLL is required

to be reset. This is followed by 200 clock cycles.

47. Leakage number reflects the worst case leakage possible through the module pin, not

what each memory device contributes.

48. When an input signal is HIGH or LOW, it is defined as a steady state logic high or logic

low.

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Initialization

To ensure device operation the DRAM must be initialized as described below:

1. Simultaneously apply power to VDD and VDDQ.

2. Apply VREF and then VTT power.

3. Assert and hold CKE at a LVCMOS logic LOW.

4. Provide stable CLOCK signals.

5. Wait at least 200µs.

6. Bring CKE high and provide at least one NOP or DESELECT command. At this point

the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a

SSTL_2 input unless a power cycle occurs.

7. Perform a PRECHARGE ALL command.

8. Wait at least tRP time, during this time NOPs or DESELECT commands must be given.

9. Using the LMR command program the extended mode register (E0 = 0 to enable the

DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set

to 0; where n = most significant bit).

10. Wait at least tMRD time, only NOPs or DESELECT commands are allowed.

11. Using the LMR command program the Mode Register to set operating parameters

and to reset the DLL. Note at least 200 clock cycles are required between a DLL reset

and any READ command.

12. Wait at least tMRD time, only NOPs or DESELECT commands are allowed.

13. Issue a PRECHARGE ALL command.

14. Wait at least tRP time, only NOPs or DESELECT commands are allowed.

15. Issue an AUTO REFRESH command (Note this may be moved prior to step 13).

16. Wait at least tRFC time, only NOPs or DESELECT commands are allowed.

17. Issue an AUTO REFRESH command (Note this may be moved prior to step 13).

18. Wait at least tRFC time, only NOPs or DESELECT commands are allowed.

19. Although not required by the Micron device, JEDEC requires a LMR command to clear

the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters

should be utilized as in step 11.

20. Wait at least tMRD time, only NOPs or DESELECT commands are allowed.

21. At this point the DRAM is ready for any valid command. Note 200 clock cycles are

required between step 11 (DLL Reset) and any READ command.

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Initialization

Figure 10: Initialization Flow Diagram

and V

Q Ramp

Apply V

REF

and V

CKE must be LVCMOS Low

Apply stable CLOCKs

Bring CKE High with a NOP command

Wait at least 200µs

PRECHARGE ALL

Assert NOP or DESELECT for tRP time

Configure Extended Mode Register

Configure Load Mode Register and reset DLL

Assert NOP or DESELECT for tMRD time

PRECHARGE ALL

Issue AUTO REFRESH command

Assert NOP or DESELECT for tRFC time

Optional LMR command to clear DLL bit

Assert NOP or DESELECT for tMRD time

DRAM is ready for any valid command

Step

Assert NOP or DESELECT commands for tRFC

Issue AUTO REFRESH command

Assert NOP or DESELECT for tRP time

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Notes: 1. The timing and switching specifications for the register listed above are critical for proper

operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the

parameters for the specific device used on the module. Detailed information for this regis-

ter is available in JEDEC Standard JESD82.

2. Data inputs must be low a minimum time of tact (MAX), after RESET# is taken HIGH.

3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact

(MAX), after RESET# is taken LOW.

4. For data signal input slew rate ≥ 1 V/ns.

5. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns.

6. CK, CK# signals input slew rate ≥ 1 V/ns.

Table 17: Register Timing Requirements and Switching Characteristics

Note: 1

0°C ≤ TA ≤ +70°C

VDD = 2.5V ± 0.2V

Units NotesMin Max

SSTL

(bit pattern

by JESD82-3

or JESD82-4)

fclock Clock Frequency - 200 MHz

tpd Clock to Output Time 30pF to GND and

50Ω to VTT

1.1 2.8 ns

tPHL Reset to Output Time - 5 ns

twPulse Duration CK, CK# HIGH or

LOW

2.5 - ns

tact Differential Inputs Active Time - 22 ns 2

tinact Differential Inputs Inactive

Time

-22ns 3

tsu Setup Time, Fast Slew Rate Data Before CK

HIGH, CK# LOW

0.75 - ns 4, 6

Setup Time, Slow Slew Rate 0.90 - ns 5, 6

thHold Time, Fast Slew Rate Data After CK HIGH,

CK# LOW

0.75 - ns 4, 6

Hold Time, Slow Slew Rate 0.90 - ns 5, 6

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Notes: 1. The timing and switching specifications for the PLL listed above are critical for proper

operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the

parameters for the specific device used on the module. Detailed information for this PLL is

available in JEDEC Standard JESD82.

2. The PLL must be able to handle spread spectrum induced skew.

3. Operating clock frequency indicates a range over which the PLL must be able to lock, but

in which it is not required to meet the other timing parameters. (Used for low speed sys-

tem debug.)

4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of

its feedback signal to its reference signal after power up.

5. Static Phase Offset does not include Jitter.

6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be

met independently of each other.

7. The Output Slew Rate is determined from the IBIS model:

Table 18: PLL Clock Driver Timing Requirements and Switching Characteristics

Note: 1

Parameter Symbol

0°C ≤ TA ≤ +70°C

VDD = 2.5V ± 0.2V

Units notesMin Nominal Max

Operating Clock Frequency fCK 60 - 170 MHz 2, 3

Input Duty Cycle tDC 40 - 60 %

Stabilization Time tSTAB - - 100 ms 4

Cycle to Cycle Jitter tJITCC -75 - 75 ps

Static Phase Offset t∅-50 0 50 ps 5

Output Clock Skew tSKO-- 100ps

Period Jitter tJITPER -75 - 75 ps 6

Half-Period Jitter tJITHPER -100 - 100 ps 6

Input Clock Slew Rate tLSI1.0 - 4 V/ns

Output Clock Slew Rate tLSO1.0 - 2 V/ns 7

GND

CDCV857

R=60

ΩΩ

R=60

ΩΩ

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Serial Presence-Detect

SPD Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA state changes during

SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11,

Data Validity, and Figure 12, Definition of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition, which is a HIGH-to-LOW transition

of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL

lines for the start condition and will not respond to any command until this condition

has been met.

SPD Stop Condition

All communications are terminated by a stop condition, which is a LOW-to-HIGH tran-

sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device

into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indicate successful data transfers. The

transmitting device, either master or slave, will release the bus after transmitting eight

bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (as shown in Figure 13, Acknowledge Response

From Receiver).

The SPD device will always respond with an acknowledge after recognition of a start

condition and its slave address. If both the device and a WRITE operation have been

selected, the SPD device will respond with an acknowledge after the receipt of each sub-

sequent eight-bit word. In the read mode the SPD device will transmit eight bits of data,

release the SDA line and monitor the line for an acknowledge. If an acknowledge is

detected and no stop condition is generated by the master, the slave will continue to

transmit data. If an acknowledge is not detected, the slave will terminate further data

transmissions and await the stop condition to return to standby power mode.

Figure 11: Data Validity

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Serial Presence-Detect

Figure 12: Definition of Start and Stop

Figure 13: Acknowledge Response From Receiver

SCL

SDA

START

BIT

STOP

BIT

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Serial Presence-Detect

Figure 14: SPD EEPROM Timing Diagram

Table 19: EEPROM Device Select Code

Most significant bit (b7) is sent first

Select Code Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory Area Select Code (two arrays) 1 0 1 0 SA2 SA1 SA0 RW

Protection Register Select Code 0 1 1 0 SA2 SA1 SA0 RW

Table 20: EEPROM Operating Modes

Mode RW Bit WC Bytes Initial Sequence

Current Address Read 1V

IH or VIL 1START, Device Select, RW = ‘1’

Random Address Read 0VIH or VIL 1START, Device Select, RW = ‘0’, Address

IH or VIL 1reSTART, Device Select, RW = ‘1’

Sequential Read 1VIH or VIL ≥ 1 Similar to Current or Random Address Read

Byte Write 0V

IL 1START, Device Select, RW = ‘0’

Page Write 0VIL ≤ 16 START, Device Select, RW = ‘0’

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Serial Presence-Detect

Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1

and the falling or rising edge of SDA.

2. This parameter is sampled.

3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a

write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE

cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-

tor, and the EEPROM does not respond to its slave address.

Table 21: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

Parameter/Condition Symbol Min Max Units

SUPPLY VOLTAGE VDDSPD 2.3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD × 0.7 VDD + 0.5 V

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD + 0.3 V

OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4V

INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –10µA

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10µA

STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD ISB –30µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz ICC –2mA

Table 22: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

Parameter/condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 µs

Data-out hold time tDH 200 ns

SDA and SCL fall time tF 300 ns 2

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 0.6 µs

Clock HIGH period tHIGH 0.6 µs

Noise suppression time constant at SCL, SDA inputs tI50ns

Clock LOW period tLOW 1.3 µs

SDA and SCL rise time tR0.3µs2

SCL clock frequency fSCL 400 KHz

Data-in setup time tSU:DAT 100 ns

Start condition setup time tSU:STA 0.6 µs 3

Stop condition setup time tSU:STO 0.6 µs

WRITE cycle time tWRC 10 ms 4

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Serial Presence-Detect

Table 23: Serial Presence-Detect Matrix

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 40

Byte Description Entry (Version)

MT9VDDT1672 MT9VDDT3272 MT9VDDT6472

0Number of SPD Bytes Used by Micron 128 808080

1Total Number of Bytes In SPD Device 256 080808

2Fundamental Memory Type SDRAM DDR070707

3Number of Row Addresses on Assembly 12 or 13 0C 0D 0D

4Number of Column Addresses on

Assembly

10 or 11 0A 0A 0B

5Number of Physical Ranks on DIMM 1 010101

6Module Data Width 72 48 48 48

7Module Data Width (Continued) 0 000000

Module Voltage Interface Levels

SSTL 2.5V 04 04 04

9SDRAM Cycle Time, tCK (CAS Latency =

2.5) (See note 1)

6ns(-335)

7ns (-262/-26A)

7.5ns (-265)

8ns (-202)

10 SDRAM Access from Clock, tAC (CAS

Latency = 2.5)

0.7(-335)

0.75ns (-262/-26A/-265)

0.8ns (-202)

11 Module Configuration Type ECC 020202

12 Refresh Rate/Type 15.6 or 7.81µs/SELF 80 82 82

13 SDRAM Device Width (Primary DDR

SDRAM)

8 080808

14 Error-checking DDR SDRAM Data Width 8 080808

15 Minimum Clock Delay, Back-to-Back

Random Column Access

1 clock 010101

16 Burst Lengths Supported 2, 4, 8 0E 0E 0E

17 Number of Banks on DDR SDRAM Device 4 040404

18 CAS Latencies Supported 2, 2.5 0C0C0C

19 CS Latency 0 010101

20 WE Latency 1 020202

21 SDRAM Module Attributes

Registered, PLL/Diff. Clock

26 26 26

22 SDRAM Device Attributes: General Fast/Concurrent AP C0 C0 C0

23 SDRAM Cycle Time, tCK (CAS Latency = 2) 7.5ns (-335/-262/-26A)

10ns (-265/-202)

24 SDRAM Access from CK, tAC (CAS Latency

= 2)

0.70ns (-335)

0.75ns (-262/-26A/-265)

0.8ns (-202)

25 SDRAM Cycle Time, tCK (CAS Latency =

1.5)

N/A 000000

26 SDRAM Access from CK, tAC (CAS Latency

= 1.5)

N/A 000000

27 Minimum Row Precharge Time, tRP 18ns (-335)

15ns (-262)

20ns (-202/-265/-26A)

28 Minimum Row Active to Row Active,

tRRD

12ns (

-335

)

15ns (-262/-26A/-265/-202)

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128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Serial Presence-Detect

29 Minimum RAS# to CAS# Delay, tRCD 18ns (-335)

15ns (-262)

20ns (-202/-265/-26A)

30 Minimum RAS# Pulse Width, tRAS (See

note 2)

42ns (-335)

45ns (-262/-26A/-265)

40ns (-202)

31 Module Rank Density 128MB, 256MB, 512MB 20 20 20

32 Address And Command Setup Time, tISs

(See note 3)

0.80ns (-335)

1ns (-262/-26A/-265)

1.1ns (-202)

33 Address And Command Hold Time, tIHs

(See note 3)

0.80ns (-335)

1ns (-262/-26A/-265)

1.1ns (-202)

34 Data/ Data Mask Input Setup Time, tDS 0.45ns (-335)

0.50ns (-262/-26A/-265)

0.60ns (-202)

35 Data/ Data Mask Input Hold Time, tDH 0.45ns (-335)

0.50ns (-262/-26A/-265)

0.60ns (-202)

36-40 Reserved 00 00 00

41 Min Active Auto Refresh Time tRC 60ns (-335/-262)

65ns (-26A/-265)

70ns (-202)

42 Minimum Auto Refresh to Active/ Auto

Refresh Command Period, tRFC

72ns (-335)

75ns (-262/-26A/-265)

80ns (-202)

43 SDRAM Device Max Cycle Time, tCKMAX

12ns (

-335)

13ns (-262/-26A/-265/-202)

44 SDRAM Device Max DQS-DQ Skew Time,

tDQSQ

0.4ns (-335)

0.5ns (-262/-26A/-265)

0.6ns (-202)

45 SDRAM Device Max Read Data Hold Skew

Facto,r tQHS

0.5ns (-335)

0.75ns (-262/-26A/-265)

1.0ns (-202)

46 Reserved 00 00 00

47 DIMM Height Standard/Low-Profile 10/01 10/01 10/01

48–61 Reserved 00 00 00

62 SPD Revision Release 1.0 10 10 10

63 Checksum for Bytes 0-62

(Standard/Low-profile)

-335

-262

-26A

-265

-202

2B/1C

BE/AF

EB/DC

1B/0C

B6/A7

4E/3F

E1/D2

0E/FF

3E/2F

D9/CA

8F/80

22/13

4F/40

7F/70

1A/0B

64 Manufacturer’s JEDEC ID Code MICRON 2C 2C 2C

65-71 Manufacturer’s JEDEC ID Code (Continued) FF FF FF

72 Manufacturing Location 01–12 01–0C 01–0C 01–0C

73-90 Module Part Number (ASCII) Variable Data Variable Data Variable Data

91 PCB Identification Code 1-9 01–09 01–09 01–09

92 Identification Code (Continued) 0 000000

Table 23: Serial Presence-Detect Matrix (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 40

Byte Description Entry (Version)

MT9VDDT1672 MT9VDDT3272 MT9VDDT6472

pdf: 09005aef80e119b2, source: 09005aef80a2e15c Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Serial Presence-Detect

Notes: 1. Value for -262/-26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device

spec. value is 7.5ns.

2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual

device spec. value is 40ns.

3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-

case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup

and hold values are supported, provided the faster minimum slew rate is met.

93 Year of Manufacture in BCD Variable Data Variable Data Variable Data

94 Week of Manufacture in BCD Variable Data Variable Data Variable Data

95-98 Module Serial Number Variable Data Variable Data Variable Data

99-127

Manufacturer-Specific Data (RSVD) ———

Table 23: Serial Presence-Detect Matrix (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 40

Byte Description Entry (Version)

MT9VDDT1672 MT9VDDT3272 MT9VDDT6472

pdf: 09005aef80e119b2, source: 09005aef80a2e15c Micron Technology, Inc., reserves the right to change products or specifications without notice.

128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Module Dimensions

All dimensions are in inches (millimeters); or typical where noted.

Figure 15: 184-Pin DIMM Dimensions (Standard)

Figure 16: 184-Pin DIMM Dimensions (Low-Profile)

MAX

MIN

1.705 (43.31)

1.695 (43.05)

PIN 1

0.700 (17.78)

TYP.

0.098 (2.50) D

(2X)

0.091 (2.30) TYP.

0.250 (6.35) TYP.

4.750 (120.65)

0.050 (1.27)

TYP.

0.091 (2.30)

TYP.

0.040 (1.02)

TYP.

0.079 (2.00) R

(4X)

0.035 (0.90) R

PIN 92

FRONT VIEW

0.054 (1.37)

0.046 (1.17)

5.256 (133.50)

5.244 (133.20)

2.55 (64.77) 1.95 (49.53)

0.394 (10.00)

TYP.

0.125 (3.175)

MAX

BACK VIEW

PIN 184 PIN 93

U1 U3 U5

U11 U12

U13

U10

U15 U17 U19 U21

U1 U3

U11

U12

U5 U7 U9

U15 U17

U13

U10

U19 U21

0.054 (1.37)

0.046 (1.17)

0.125 (3.175)

MAX

1.205 (30.61)

1.195 (30.35)

PIN 1

0.700 (17.78)

TYP.

0.098 (2.50) D

(2X)

0.091 (2.30) TYP.

0.250 (6.35) TYP.

4.750 (120.65)

0.050 (1.27)

TYP.

0.091 (2.30)

TYP.

0.040 (1.02)

TYP.

0.079 (2.00) R

(4X)

0.035 (0.90) R

PIN 92

FRONT VIEW

5.256 (133.50)

5.244 (133.20)

2.55 (64.77) 1.95 (49.53)

0.394 (10.00)

TYP.

BACK VIEW

PIN 184 PIN 93

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range

for production devices. Although considered final, these specifications are subject to change, as further product

development and data characterization sometimes occur.

128MB, 256MB, 512MB: (x72, ECC, PLL, SR) 184-Pin DDR RDIMM

Data Sheet Designation

pdf: 09005aef80e119b2, source: 09005aef80a2e15c Micron Technology, Inc., reserves the right to change products or specifications without notice.

Data Sheet Designation

Released (No Mark): This data sheet contains minimum and maximum limits specified

over the complete power supply and temperature range for production devices.

Although considered final, these specifications are subject to change, as further product

development and data characterization sometimes occur.