 
  
   
SCLS374L − M AY 1997 − REVISED FEBRUARY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DInputs Are TTL-Voltage Compatible
D8-Bit Serial-In, Parallel-Out Shift
DShift Register Has Direct Clear
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The ’AHCT595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
the shift and storage registers. The shift register
has a direct overriding clear (SRCLR) input, serial
(SER) input, and serial outputs for cascading.
When the output-enable (OE) input is high, the
outputs are in the high-impedance state.
Both the shift register clock (SRCLK) and storage
register clock (RCLK) are positive-edge triggered.
If both clocks are connected together, the shift
register always is one clock pulse ahead of the
storage register.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube SN74AHCT595N SN74AHCT595N
SOIC − D
Tube SN74AHCT595D
AHCT595
SOIC − D Tape and reel SN74AHCT595DR AHCT595
−40°C to 85°CSOP − NS Tape and reel SN74AHCT595NSR AHCT595
−40 C to 85 C
SSOP − DB Tape and reel SN74AHCT595DBR HB595
TSSOP − PW
Tube SN74AHCT595PW
HB595
TSSOP − PW Tape and reel SN74AHCT595PWR HB595
CDIP − J Tube SNJ54AHCT595J SNJ54AHCT595J
−55°C to 125°CCFP − W Tube SNJ54AHCT595W SNJ54AHCT595W
−55 C to 125 C
LCCC − FK Tube SNJ54AHCT595FK SNJ54AHCT595FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2004, Texas Instruments Incorporated
    !"#$%& "!&'& 
 &(!)$'!& "#))%& ' !( *#+,"'!& '%- )!#" "!&(!)$ !
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)!#"!& *)!"%&1 !% &! &%"%'),0 &",#% %&1 !( ',,
*')'$%%)-
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54AHCT595 ...J OR W PACKAGE
SN74AHCT595 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AHCT595 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QB
QC
QD
QE
QF
QG
QH
GND
VCC
QA
SER
OE
RCLK
SRCLK
SRCLR
QH′
4
5
6
7
8
18
17
16
15
14
SER
OE
NC
RCLK
SRCLK
QD
QE
NC
QF
QG
Q
NC
SRCLR
H
GND
NC
C
QB
VCC
QA
Q
H
Q′
910111213
3 2 1 20 19
 
  
   
SCLS374L − M AY 1997 − REVISED FEBRUARY 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK OE
FUNCTION
X X X X H Outputs QA−QH are disabled.
XX X X L Outputs QA−QH are enabled.
XX L X X Shift register is cleared.
L↑H X X First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H↑H X X First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X X X ↑XShift-register data is stored in the storage register.
 
  
   
SCLS374L − M AY 1997 − REVISED FEBRUARY 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
3D
C3
1D
C1
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
13
12
10
11
14 15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QH′
OE
SRCLR
RCLK
SRCLK
SER
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
Q
Q
Q
Q
Q
Q
Q
QQ
Q
Q
Q
Q
Q
Q
Q
 
  
   
SCLS374L − M AY 1997 − REVISED FEBRUARY 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
ÎÎÎÎÎ
ÎÎÎÎÎ
QA
ÎÎÎÎÎ
ÎÎÎÎÎ
QB
ÎÎÎÎÎ
ÎÎÎÎÎ
QC
ÎÎÎÎÎ
ÎÎÎÎÎ
QD
ÎÎÎÎÎ
ÎÎÎÎÎ
QE
ÎÎÎÎÎ
ÎÎÎÎÎ
QF
ÎÎÎÎÎ
ÎÎÎÎÎ
QG
ÎÎÎÎÎ
ÎÎÎÎÎ
QH
QH’
ÎÎÎÎ
implies that the output is in 3-State mode.NOTE:
 
  
   
SCLS374L − M AY 1997 − REVISED FEBRUARY 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AHCT595 SN74AHCT595
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
IOH High-level output current −8 −8 mA
IOL Low-level output current 8 8 mA
∆t/∆vInput transition rise or fall rate 20 20 ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
 2 &(!)$'!& "!&"%)& *)!#" & % (!)$'3% !)
%1& *'% !( %3%,!*$%&- ')'"%)" '' '& !%)
*%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)3% % )1 !
"'&1% !) "!&&#% %% *)!#" /!# &!"%-
 
  
   
SCLS374L − M AY 1997 − REVISED FEBRUARY 2004
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C SN54AHCT595 SN74AHCT595
UNIT
PARAMETER
TEST CONDITIONS
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
VOH
IOH = −50 mA
4.4 4.5 4.4 4.4
V
VOH IOH = −8 mA 4.5 V 3.94 3.8 3.8 V
VOL
IOL = 50 mA
0.1 0.1 0.1
V
VOL IOL = 8 mA 4.5 V 0.36 0.44 0.44 V
IIVI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1mA
IOZ VO = VCC or GND, QA−QH5.5 V ±0.25 ±2.5 ±2.5 mA
ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40 mA
∆ICC†One input at 3.4V,
Other inputs at VCC or GND 5.5 V 2 2.2 2.2 mA
CiVI = VCC or GND 5 V 3 10 10 pF
CoVO = VCC or GND 5 V 5.5 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AHCT595 SN74AHCT595
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
SRCLK high or low 5 5.5 5.5
t
w
Pulse duration RCLK high or low 5 5.5 5.5 ns
tw
Pulse duration
SRCLR low 5 5 5
ns
SER before SRCLK↑3 3 3
tsu
Setup time
SRCLK↑ before RCLK↑‡5 5 5
ns
tsu
Setup time
SRCLR low before RCLK↑5 5 5 ns
SRCLR high (inactive) before SRCLK↑3.4 3.8 3.8
thHold time SER after SRCLK↑2 2 2 ns
‡This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
 2 &(!)$'!& "!&"%)& *)!#" & % (!)$'3% !)
%1& *'% !( %3%,!*$%&- ')'"%)" '' '& !%)
*%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)3% % )1 !
"'&1% !) "!&&#% %% *)!#" /!# &!"%-
 
  
   
SCLS374L − M AY 1997 − REVISED FEBRUARY 2004
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C SN54AHCT595 SN74AHCT595
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax
CL = 15 pF 135* 170* 115* 115
MHz
fmax CL = 50 pF 95 140 85 85 MHz
tPLH
RCLK
QA−QH
CL = 15 pF
4.3* 7.4* 1* 8.5* 1 8.5
ns
tPHL RCLK QA−QHCL = 15 pF 4.3* 7.4* 1* 8.5* 1 8.5 ns
tPLH
SRCLK
QH
CL = 15 pF
4.5* 8.2* 1* 9.4* 1 9.4
ns
tPHL SRCLK QH′CL = 15 pF 4.5* 8.2* 1* 9.4* 1 9.4 ns
tPHL SRCLR QH′CL = 15 pF 4.5* 8* 1* 9.1* 1 9.1 ns
tPZH
OE
QA−QH
CL = 15 pF
4.3* 8.6* 1* 10* 1 10
ns
tPZL OE QA−QHCL = 15 pF 5.4* 8.6* 1* 10* 1 10 ns
tPLH
RCLK
QA−QH
CL = 50 pF
5.6 9.4 1 10.5 1 10.5
ns
tPHL RCLK QA−QHCL = 50 pF 5.6 9.4 1 10.5 1 10.5 ns
tPLH
SRCLK
QH
CL = 50 pF
6.4 10.2 1 11.4 1 11.4
ns
tPHL SRCLK QH′CL = 50 pF 6.4 10.2 1 11.4 1 11.4 ns
tPHL SRCLR QH′CL = 50 pF 6.4 10 1 11.1 1 11.1 ns
tPZH
OE
QA−QH
CL = 50 pF
5.7 10.6 1 12 1 12
ns
tPZL OE QA−QHCL = 50 pF 6.8 10.6 1 12 1 12 ns
tPHZ
OE
QA−QH
CL = 50 pF
3.5 10.3 1 11 111
ns
tPLZ
OE
Q
A
−Q
H
C
L
= 50 pF
3.4 10.3 1 11 111
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4)
PARAMETER
SN74AHCT595
UNIT
PARAMETER
MIN TYP MAX
UNIT
VOL(P) Quiet output, maximum dynamic VOL 1 V
VOL(V) Quiet output, minimum dynamic VOL −0.6 V
VOH(V) Quiet output, minimum dynamic VOH 3.8 V
VIH(D) High-level dynamic input voltage 2 V
VIL(D) Low-level dynamic input voltage 0.8 V
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 112 pF
 2 &(!)$'!& "!&"%)& *)!#" & % (!)$'3% !)
%1& *'% !( %3%,!*$%&- ')'"%)" '' '& !%)
*%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)3% % )1 !
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 
  
   
SCLS374L − M AY 1997 − REVISED FEBRUARY 2004
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
V
CC
RL = 1 kΩ
GND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH − 0.3 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V1.5 V 1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74AHCT595D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595DBR ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595DE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595DRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74AHCT595NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74AHCT595NSR ACTIVE SO NS 16 TBD Call TI Call TI
SN74AHCT595NSRE4 ACTIVE SO NS 16 TBD Call TI Call TI
SN74AHCT595NSRG4 ACTIVE SO NS 16 TBD Call TI Call TI
SN74AHCT595PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT595PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74AHCT595PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AHCT595DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74AHCT595DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74AHCT595PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHCT595DBR SSOP DB 16 2000 367.0 367.0 38.0
SN74AHCT595DR SOIC D 16 2500 333.2 345.9 28.6
SN74AHCT595PWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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