19-2542; Rev 0; 7/02 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs The MAX9310A is a fast, low-skew 1:5 differential driver with selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 340ps with 48mA of supply current. The MAX9310A operates from a 3V to 3.6V power supply for use in 3.3V systems. A 2:1 input multiplexer is used to select one of two differential inputs. The input selection is controlled through the CLKSEL pin. This device features a synchronous enable function. The MAX9310A LVPECL inputs can be driven by either a differential or single-ended signal. A VBB reference voltage output is provided for use with single-ended inputs. The device can also accept differential HSTL signals. The MAX9310A is offered in a space-saving 20-pin TSSOP package and operates over the extended temperature range from -40C to +85C. Features Guaranteed 1.0GHz Operating Frequency 8.0ps Output-to-Output Skew 340ps Propagation Delay Accepts LVPECL and Differential HSTL Inputs Synchronous Output Enable/Disable Two Selectable Differential Inputs 3V to 3.6V Supply Voltage On-Chip Reference for Single-Ended Operation ESD Protection: 2kV (Human Body Model) Input Bias Resistors Drive Output Low for Open Inputs Applications Ordering Information Data and Clock Drivers and Buffers Central-Office Backplane Clock Distribution DSLAM PART TEMP RANGE PIN-PACKAGE MAX9310AEUP -40C to +85C 20 TSSOP Base Stations ATE Pin Configuration Functional Diagram appears at end of data sheet. TOP VIEW Typical Application Circuit RECEIVER MAX9310A ZO = 50 Q_ ZO = 50 Q_ 100 Q0 1 20 VCC QO 2 19 EN Q1 3 18 VCC Q1 4 17 CLK1 Q2 5 MAX9310A 16 CLK1 Q2 6 15 VBB Q3 7 14 CLK0 Q3 8 13 CLK0 Q4 9 12 CLKSEL Q4 10 11 GND TSSOP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX9310A General Description MAX9310A 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.1V EN, CLKSEL, CLK_, CLK_, to GND............-0.3V to (VCC + 0.3V) CLK_ to CLK_.........................................................................3V Continuous Output Current .................................................24mA Surge Output Current..........................................................50mA VBB Sink/Source Current ...............................................0.65mA Continuous Power Dissipation (TA = +70C) Single-Layer PC Board 20-Pin TSSOP (derate 7.69mW/C above +70C) ......615mW Multilayer PC Board 20-Pin TSSOP (derate 11mW/C above +70C) .........879mW Junction-to-Ambient Thermal Resistance in Still Air Single-Layer PC Board 20-Pin TSSOP .........................................................+130C/W Multilayer PC Board 20-Pin TSSOP ...........................................................+91C/W Junction-to-Ambient Thermal Resistance with 500LFPM Airflow Single-Layer PC board 20-Pin TSSOP ...........................................................+96C/W Junction-to-Case Thermal Resistance 20-Pin TSSOP ...........................................................+20C/W Operating Temperature Range .......................... -40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (inputs and outputs) .......................2kV Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - GND = 3V to 3.6V, outputs terminated with 100 1%, unless otherwise noted. Typical values are at VCC - GND = 3.3V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS -40C MIN TYP +25C MAX MIN TYP +85C MAX MIN TYP MAX UNITS SINGLE-ENDED INPUTS (CLKSEL, EN) Input High Voltage VIH VCC 1.165 VCC 0.88 VCC 1.165 VCC 0.88 VCC 1.165 VCC 0.88 V Input Low Voltage VIL VCC 1.81 VCC 1.475 VCC 1.81 VCC 1.475 VCC 1.81 VCC 1.475 V Input Current IIN -10 +70 -10 +70 -10 +70 A VIH(MAX), VIL(MAX) DIFFERENTIAL INPUTS (CLK_, CLK_) Single-Ended Input High Voltage VIH Figure 1 VCC 1.125 VCC 0.88 VCC 1.165 VCC 0.88 VCC 1.165 VCC 0.88 V Single-Ended Input Low Voltage VIL Figure 1 VCC 1.81 VCC 1.475 VCC 1.81 VCC 1.475 VCC 1.81 VCC 1.495 V Differential Input High Voltage VIHD Figure 2 1.2 VCC 1.2 VCC 1.2 VCC V Differential Input Low Voltage VILD Figure 2 GND VCC 0.095 GND VCC 0.095 GND VCC 0.095 V Differential Input Voltage VID VIHD - VILD 0.095 3.0 0.095 3.0 0.095 3.0 V CLK_, or CLK_ = VIHD or VILD -100 +100 -100 +100 -100 +100 A Input Current 2 IIH, IIL _______________________________________________________________________________________ 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs (VCC - GND = 3V to 3.6V, outputs terminated with 100 1%, unless otherwise noted. Typical values are at VCC - GND = 3.3V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3) PARAMETER SYMBOL CONDITIONS -40C MIN TYP +25C MAX MIN TYP +85C MAX MIN TYP MAX UNITS OUTPUTS (Q_, Q_) Output High Voltage VOH Figure 2 Output Low Voltage VOL Figure 2 0.9 Differential Output Voltage VOD VOH - VOL, Figure 2 250 Change in VOD Between Complementary Output States VOD Output Offset Voltage Change in VOS Between Complementary Output States Output ShortCircuit Current 1.6 0.9 350 450 250 1.125 1.25 VOCM 1.375 1.6 0.9 350 50 VOS IOSC 1.6 450 250 V 350 50 1.125 1.25 1.375 1.125 V 1.25 450 mV 50 mV 1.375 mV mV 25 25 25 Q_ shorted to Q_ 12 12 12 Q_ or Q_ shorted to GND 29 29 29 mA REFERENCE Reference Voltage Output VBB IBB = 0.65mA (Note 4) ICC (Note 5) VCC 1.38 VCC 1.22 VCC 1.38 VCC 1.26 VCC 1.40 VCC 1.26 V 75 mA POWER SUPPLY Power-Supply Current 45 75 48 75 51 _______________________________________________________________________________________ 3 MAX9310A DC ELECTRICAL CHARACTERISTICS (continued) MAX9310A 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs AC ELECTRICAL CHARACTERISTICS (V CC - GND = 3V to 3.6V, outputs terminated with 100 1%, f IN 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted. Typical values are at VCC - GND = 3.3V, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 6) PARAMETER SYMBOL CONDITIONS Propagation Delay CLK_, CLK_ to Q_, Q_ tPHL, tPLH Figure 2 Output-toOutput Skew tSKOO (Note 7) Part-to-Part Skew tSKPP (Note 8) -40C +25C +85C UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX 250 340 600 250 340 600 250 340 600 ps 10 30 8 25 20 45 ps 145 ps 145 145 Added Random Jitter tRJ fIN = 1.0GHz, clock pattern (Note 9) 0.3 1.0 0.3 1.0 0.3 1.0 ps (RMS) Added Deterministic Jitter tDJ fIN = 1.0Gsps, 223 - 1 PRBS pattern (Note 9) 50 60 50 60 50 60 ps (P-P) Operating Frequency fMAX VOD 250mV 1.0 Differential Output Rise/Fall Time tR/tF 20% to 80%, Figure 2 140 1.0 205 300 140 1.0 205 300 140 GHz 205 Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25C. DC limits are guaranteed by design and characterized over the full operating temperature range. Note 4: Use VBB only for inputs that are on the same device as the VBB reference. Note 5: All pins are open except VCC and GND, all outputs are loaded with 100 differentially. Note 6: Guaranteed by design and characterization. Limits are set to 6 sigma. Note 7: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 8: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 9: Device jitter added to the input signal. 4 _______________________________________________________________________________________ 300 ps 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. FREQUENCY 48 47 46 45 44 43 MAX9310A toc02 400 300 250 200 150 10 35 60 tF 210 tR 100 200 0.25 0 85 0.50 0.75 1.00 1.25 1.50 1.75 -40 -15 FREQUENCY (GHz) TEMPERATURE (C) PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT (VIHD) 390 350 330 310 35 60 85 PROPAGATION DELAY vs. TEMPERATURE 400 PROPAGATION DELAY (ps) 370 10 TEMPERATURE (C) MAX9310A toc05 -15 215 205 MAX9310A toc04 -40 fIN = 500MHz 350 50 42 OUTPUT RISE/FALL vs. TEMPERATURE 220 RISE/FALL TIME (ps) 49 PROPAGATION DELAY (ps) SUPPLY CURRENT (mA) 50 DIFFERENTIAL OUTPUT VOLTAGE (mV) ALL PINS ARE OPEN EXCEPT VCC AND GND OUTPUTS LOADED WITH 100 DIFFERENTIAL 51 450 MAX9310A toc01 52 MAX9310A toc03 SUPPLY CURRENT vs. TEMPERATURE 380 360 340 320 290 300 1.2 1.5 1.8 2.1 2.4 VIHD (V) 2.7 3.0 3.3 -40 -15 10 35 60 85 TEMPERATURE (C) _______________________________________________________________________________________ 5 MAX9310A Typical Operating Characteristics (VCC - GND = 3.3V, outputs terminated with 100 1%, fIN = 1.0GHz, input transition time = 125ps (20% to 80%),VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs MAX9310A Pin Description PIN NAME 1 Q0 2 Q0 Inverting Differential Output 0. Typically terminated with 100 to Q0. 3 Q1 Noninverting Differential Output 1. Typically terminated with 100 to Q1. 4 Q1 Inverting Differential Output 1. Typically terminated with 100 to Q1. 5 Q2 Noninverting Differential Output 2. Typically terminated with 100 to Q2. 6 Q2 Inverting Differential Output 2. Typically terminated with 100 to Q2. 7 Q3 Noninverting Differential Output 3. Typically terminated with 100 to Q3. 8 Q3 Inverting Differential Output 3. Typically terminated with 100 to Q3. 9 Q4 Noninverting Differential Output 4. Typically terminated with 100 to Q4. 10 Q4 Inverting Differential Output 4. Typically terminated with 100 to Q4. 11 GND 12 CLKSEL 13 CLK0 Noninverting Differential Clock Input 0. Internal 75k pulldown to GND. 14 CLK0 Inverting Differential Clock Input 0. Internal 75k pullup to VCC and 75k pulldown to GND. 15 VBB 16 CLK1 Noninverting Differential Input 1. Internal 75k pulldown to GND. 17 CLK1 Inverting Differential Input 1. Internal 75k pullup to VCC and 75k pulldown to GND. 18, 20 VCC Positive Supply Voltage. Bypass VCC to GND with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. EN Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected clock input when EN is low. Outputs are synchronously driven to a differential low state on the falling edge of the selected clock input when EN is high. Internal 60k pulldown to GND (Figure 3). 19 6 FUNCTION Noninverting Differential Output 0. Typically terminated with 100 to Q0. Ground Clock Select Input. Drive low to select the CLK0, CLK0 input. Drive high to select the CLK1, CLK1 input. The CLKSEL threshold is equal to VBB. Internal 60k pulldown to GND. Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass with a 0.01F ceramic capacitor to VCC; otherwise, leave open. _______________________________________________________________________________________ 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs MAX9310A CLK OR CLK VIH CLK OR CLK VBB (CLK IS CONNECTED TO VBB) VIL VOH Q_ VOH - VOL VOL Q_ Figure 1. MAX9310A Switching Characteristics with Single-Ended Input CLK VIHD VIHD - VILD CLK VILD tPLHD tPHLD Q_ VOH VOH - VOL Q_ VOL 80% 80% 0V (DIFFERENTIAL) 0V (DIFFERENTIAL) 20% 20% Q_ - Q_ tR tF Figure 2. MAX9310A Timing Diagram _______________________________________________________________________________________ 7 MAX9310A 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs EN tS CLK tH tS tH CLK tPLHD Q_ Q_ OUTPUTS ARE LOW OUTPUTS STAY LOW tS = SETUP TIME tH = HOLD TIME Figure 3. MAX9310A Timing EN Diagram Detailed Description The MAX9310A is a low-skew 1:5 differential driver with two selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. The selected clock accepts a differential input signal and reproduces it on five separate differential LVDS outputs. The inputs are biased with internal resistors such that the output is differential low when inputs are open. An onchip VBB reference output is available for single-ended input operation. The device is guaranteed to operate at frequencies up to 1.0GHz with LVDS output levels conforming to the EIA/TIA-644 standard. The MAX9310A is designed for 3V to 3.6V operation in systems with a nominal 3.3V supply. Differential LVPECL Input The MAX9310A has two input differential pairs that accept differential LVPECL/HSTL inputs, and can be configured to accept single-ended LVPECL inputs through the use of the VBB voltage-reference output. Each differential input pair has to be independently terminated. A select pin (CLKSEL) is used to activate the desired input. The maximum magnitude of the differential signal applied to the input is 3V. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously. Single-Ended Inputs and VBB The differential inputs can be configured to accept a single-ended input through the use of the VBB reference voltage. A noninverting, single-ended input is produced by connecting V BB to the CLK_ input and applying a single-ended signal to the CLK_ input. Similarly, an inverting input is produced by connecting VBB to the CLK_ input and applying the signal to the CLK_ input. With a differential input configured as single ended (using VBB), the single-ended input can be driven to V CC and GND, or with a single-ended LVPECL signal. Note the single-ended input must be at least VBB 95mV or a differential input of at least 95mV 8 to switch the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table (Figure 1). When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If the VBB reference is not used, leave unconnected. The VBB reference can source or sink 500A. Use VBB only for inputs that are on the same device as the VBB reference. Synchronous Enable The MAX9310A is synchronously enabled and disabled with outputs in a differential low state to eliminate shortened clock pulses. EN is connected to the input of an edge-triggered D flip-flop. After power-up, drive EN low and toggle the selected clock input to enable the outputs. The outputs are enabled on the falling edge of the selected clock input after EN goes low. The outputs are set to a differential low state on the falling edge of the selected clock input after EN goes high (Figure 3). Input Bias Resistors Internal biasing resistors ensure a (differential) output low condition in the event that the inputs are not connected. The inverting input (CLK_) is biased with a 75k pulldown to GND and a 75k pullup to VCC. The noninverting input (CLK_) is biased with a 75k pulldown to GND. Differential LVDS Output The LVDS outputs must be terminated with 100 across Q and Q, as shown in the Typical Application Circuit. The outputs are short-circuit protected. _______________________________________________________________________________________ 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs Supply Bypassing Bypass each VCC to GND with high-frequency surfacemount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If the VBB reference is not used, it can be left open. Controlled-Impedance Traces Input and output trace characteristics affect the performance of the MAX9310A. Connect high-frequency input and output signals to 50 characteristic impedance traces. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through cables and connectors. Reduce skew within a differential pair by matching the electrical length of the traces. Output Termination Terminate the outputs with 100 across Q_ and Q_, as shown in the Typical Application Circuit. Chip Information TRANSISTOR COUNT: 716 PROCESS: Bipolar _______________________________________________________________________________________ 9 MAX9310A Applications Information 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs MAX9310A Functional Diagram VCC Q0 75k Q0 CLK0 Q1 CLK0 Q1 75k GND 75k Q2 GND 0 VCC Q2 Q3 1 75k CLK1 Q3 CLK1 Q4 75k 75k Q4 GND GND CLKSEL Q EN D VBB 60k 60k GND GND MAX9310A 10 ______________________________________________________________________________________ 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs TSSOP,NO PADS.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9310A Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)