74AC161PC - Fairchild Semiconductor

November 1988

Revised September 2003

74AC161 • 74ACT161 Synchronous Presettable Binary Counter

74AC161 • 74ACT161

Synchronous Presettable Binary Counter

General Description

The AC/ACT161 are high-speed synchronous modulo-16

binary counters. They are synchronously presettable for

application in programmable dividers and have two types

of Count Enable inputs plus a Terminal Count output for

versatility in forming synchronous multistage counte rs. The

AC/ACT1 61 has an asynch ronous Mas ter Reset input th at

overrides all other inputs and forces the outputs LOW.

Features

■ICC reduced by 50%

■Synchronous counting and loading

■High-spe ed synch ro nou s expan sion

■Typical count rate of 125 MHz

■Outputs source/sink 24 mA

■ACT161 has TTL-compatible inputs

Ordering Code:

Device a ls o av ailable in Tape and Reel. Specify b y a ppending s uffix let te r “X” to the or dering code.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Number Package Description

74AC161SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74AC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74AC161PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74ACT161SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74ACT161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACT161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ACT161PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pin Names Description

CEP Count Enable Parallel Input

CET Count Enable T rickle Input

CP Clock Pulse Input

MR Asynchronous Master Reset Input

P0–P3Parallel Data Inputs

PE Parallel Enable Inputs

Q0–Q3Flip-Flop Outputs

TC Terminal Count Output

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74AC161 • 74ACT161

Functional Description

The AC/ACT161 count in modulo-16 binary sequence.

From state 15 (HHHH) they increment to state 0 (LLLL).

The clock inputs of all flip-flops are driven in parallel

through a clock buffer. Thus all changes of the Q outputs

(except due to Master Reset of the AC/ACT161) occur as a

result of, and synchronous with, the LOW-to-HIGH transi-

tion of the CP input signal. The circuits have four funda-

mental modes of operation, in order of precedence:

async hronous reset , paral lel load, c ount-up a nd hold. F ive

control inputs—Master Reset, Pa rallel Enable (PE), Count

Enable Parallel (CEP) and Count Enable Trickle (CET)—

determine the mode of operation, as shown in the Mode

Select Table. A LOW signal on MR overrides all other

inpu ts and asyn chr ono usly fo rces al l outp uts LOW. A LOW

signal on PE overrides counting and allows information on

the Parallel Data (Pn) inputs t o be l oaded into the f lip-fl ops

on the next rising edge of CP. With PE and MR HIGH, CEP

and CE T p er mi t c o un ti n g wh en b ot h are H IGH . Co nv e rse l y,

a LOW signal on either CEP or CET inhibits counting.

The AC/ACT161 use D-type edge-triggered flip-flops and

chan ging the PE, CEP, and CET inputs when the CP is in

either state does not cause errors, provided that the recom-

mended setup and hold times, with respect to the rising

edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is

HIGH and counter is in state 15. To implement synchro-

nous multistage counters, the TC outputs can be used with

the CEP and CET inpu ts in two differen t way s.

Figure 1 shows the connections for simple ripple carry, in

which the clock period must be longer than the CP to TC

delay of the first stage, plus the cumulative CET to TC

delays of the intermediate stages, plus the CET to CP

setup time of the last stage. This total delay plus setup time

sets the upper limit on clock frequency. For faster clock

rates, the carry lookahea d connections shown in Figu re 2

are r ecom m end ed. In this sche me th e rip pl e de lay thr oug h

the intermediate stages commences with the same clock

that cau ses the first stage to tick over from max to min in

the Up mode, or min to max in the Down mode, to start its

final cy cle. Since this final cycle r equ ires 16 clo cks to com -

plete, there is plenty of time for the ripple to progress

through the intermediate stages. The critical timing that lim-

its the clo ck period is the CP to TC delay of the fir st stage

plus the CEP to CP setup time of the last stage. The TC

output is subject to decoding spikes due to internal race

conditio ns and is therefor e not reco mmended for use a s a

clock or asynchronous reset for flip-flops, registers or

counters.

Logic Equations: Count Enable = CEP • CET • PE

TC = Q0 • Q1 • Q2 • Q3 • CET

Mode Select Table

H = HIGH Voltage Lev el

L = LOW Voltage Level

X = Immaterial

State Diagram

FIGURE 1. Multistage Counter with Ripple Carry

FIGURE 2. Multistage Counter with Lookahead Carry

PE CET CEP Action on the Rising

Clock Edge (



)

X X X Reset (Clear)

L X X Load (Pn→Qn)

H H H Count (Increment)

H L X No Change (Hold)

H X L No Change (Hold)

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74AC161 • 74ACT161

Block Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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74AC161 • 74ACT161

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with-

out exception, to ensure that the system design is reliable over its power

supply, temperatu re, and output /input lo ading variable s. Fairch ild do es not

recomm end operation of FACT circ uit s out s ide databook specificat ions.

DC Electrical Characteristics for AC

Note 2: All outputs loaded; th resholds on input associate d w it h output under tes t.

Note 3: Maximum test du ration 2.0 m s, one out put loaded a t a tim e.

Note 4: IIN and ICC @ 3.0V are guara nt eed to be les s th an or equa l to th e respect iv e limit @ 5. 5V VCC.

Supply Voltage (VCC)−0.5V to +7.0V

DC Input Diode Current (IIK)

VI = −0.5V −20 mA

VI = VCC + 0.5V +20 mA

DC Input Voltage (VI)−0.5V to VCC + 0.5V

DC Output Diode Current (IOK)

VO = −0.5V −20 mA

VO = VCC + 0.5V +20 mA

DC Output Voltage (VO)−0.5V to VCC + 0.5V

DC Output Source

or Sink Current (IO) ±50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)±50 mA

Storage Temperature (TSTG)−65°C to +150°C

Junction Temperature (TJ)

PDIP 140°C

Supply Voltage (VCC)

AC 2.0V to 6.0V

ACT 4.5V to 5.5V

Input Voltage (VI) 0V to VCC

Output Voltage (VO) 0V to VCC

Operati ng Temperature (TA)−40°C to +85°C

Minimum Input Edge Rate (∆V/∆t)

AC Devices

IN from 30% to 70% of VCC

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (∆V/∆t)

ACT Devices

VIN from 0.8V to 2.0V

VCC @ 4.5V, 5.5V 125 mV/ns

Symbol Parameter VCC TA = +25°C TA = −40°C to +85°CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT = 0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V

5.5 2.75 3.85 3.85

VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT = 0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V

5.5 2.75 1.65 1.65

VOH Minimum HIGH Level 3.0 2.99 2.9 2.9

Output Voltage 4.5 4.49 4.4 4.4 V IOUT = −50 µA

5.5 5.49 5.4 5.4 VIN = VIL or VIH

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 IOH = −24 mA (Note 2)

VOL Maximum LOW Level 3.0 0.002 0.1 0.1

Output Voltage 4.5 0.001 0.1 0.1 V IOUT = 50 µA

5.5 0.001 0.1 0.1 VIN = VIL or VIH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

IIN Maximum Input 5.5 ±0.1 ±1.0 µAV

I = VCC, GND

(Note 4) Leakage Current

IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max

IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min

ICC Maximum Quiescent 5.5 4.0 40.0 µAVIN = VCC

(Note 4) Supply Current or GND

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74AC161 • 74ACT161

DC Electrical Characteristics for ACT

Note 5: All outputs lo aded; thre sholds on input as s oc iated with outpu t un der test.

Note 6: Maximum test duration 2.0 ms, one output loaded at a time.

AC Electrical Characteristics for AC

Note 7: Vo lt age Ran ge 3.3 is 3.3V ± 0.3V

Voltage Range 5. 0 is 5. 0V ± 0.5V

Symbol Parameter VCC TA = +25°C TA = −40°C to +85°CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 VVOUT = 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

VIL Maximum LOW Level 4.5 1.5 0.8 0.8 V VOUT = 0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC − 0.1V

VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VIOUT = −50 µA

Output Voltage 5.5 5.49 5.4 5.4 VIN = VIL or V IH

4.5 3.86 3.76 V IOH = −24 mA

5.54.864.76I

OH = −24 mA (Note 5)

VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VIOUT = 50 µA

Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH

4.5 0.36 0.44 V IOL = 24 mA

5.50.360.44I

OL = 24 mA (Note 5)

IIN Maximum Input 5.5 ±0.1 ±1.0 µAV

I = VCC, GND

Leakage Current

ICCT Maximum 5.5 0.6 1.5 mA VI = VCC − 2.1V

ICC/Input

IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max

IOHD Output Current (Note 6) 5.5 −75 mA VOHD = 3.85V Min

ICC Maximum Quiescent 5.5 4.0 40.0 µAVIN = VCC

Supply Current or GND

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 7) Min Typ Max Min Max

fMAX Maximum Count 3.3 70 111 60 MHz

Frequency 5.0 110 167 95

tPLH Propagation Delay CP to Qn3.3 2.0 7.0 12 1.5 13.5 ns

(PE Input HIGH or LOW) 5.0 1.5 5.0 9.0 1.0 9.5

tPHL Propagation Delay CP to Qn3.3 1.5 7.0 12 1.5 13 ns

(PE Input HIGH or LOW) 5.0 1.5 5.0 9.5 1.5 10

tPLH Propagation Delay 3.3 3.0 9 15 2.5 16.5 ns

CP to TC 5.0 2.0 6 10.5 1.5 11.5

tPHL Propagation Delay 3.3 3.5 8.5 14 2.5 15.5 ns

CP to TC 5.0 2.0 6.5 11 2.0 11 .5

tPLH Propagation Delay 3.3 2.0 5.5 9.5 1.5 11 ns

CET to TC 5.0 1.5 3.5 6.5 1.0 7.5

tPHL Propagation Delay 3.3 2.5 6.5 11 2.0 12.5 ns

CET to TC 5.0 2.0 5 8.5 1.5 9.5

tPHL Propagation Delay 3.3 2.0 6.5 12 1.5 13.5 ns

MR to Qn5.0 1.5 5.5 9.5 1.5 10

tPHL Propagation Delay 3.3 3.5 10 15 3.0 17.5 ns

MR to TC 5.0 2.5 8.5 13 2.5 13.5

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74AC161 • 74ACT161

AC Operating Requirements for AC

Note 8: Voltage Range 3.3 is 3.3V ± 0.3V

Voltage Range 5. 0 is 5. 0V ± 0.5V

AC Electrical Characteristics for ACT

Note 9: Voltage Range 5.0 is 5.0V ± 0.5V

CC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 8) Typ Guaranteed Minimum

tSSetup Time, HIGH or LOW 3.3 6.0 13.5 16 ns

Pn to CP 5.0 3.5 8.5 10.5

tHHold Time, HIGH or LOW 3.3 −7.0 −1−0.5 ns

Pn to CP 5.0 −4.0 0 0

tSSetup Time, HIGH or LOW 3.3 6.5 11.5 14 ns

PE to CP 5.0 4.0 7.5 8.5

tHHold Time, HIGH or LOW 3.3 −6.0 0 0 ns

PE to CP 5.0 −3.5 0.5 1

tSSetup Time, HIGH or LOW 3.3 3.0 6.0 7 ns

CEP or CET to CP 5.0 2.0 4.5 5

tHHold Time, HIGH or LOW 3.3 −3.5 0 0 ns

CEP or CET to CP 5.0 −20 0.5

tWClock Pulse Width 3.3 2.0 3.5 4 ns

(Load) HIGH or LOW 5.0 2.0 2.5 3

tWClock Pulse Width 3.3 2.0 4.0 4.5 ns

(Count) HIGH or LOW 5.0 2.0 3.0 3.5

tWMR Pulse Width, 3.3 3.0 5.5 7.5 ns

LOW 5.0 2.5 4.5 6.0

tREC Recovery Time −2 −0.5 0 ns

MR to CP −10 0.5

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 9) M in Typ Max Min Max

fMAX Maximum Count 5.0 115 125 100 MHz

Frequency

tPLH Propagation Delay CP to Qn5.0 1.5 5.5 9.5 1.5 10.5 ns

(PE Input HIGH or LOW)

tPHL Propagation Delay CP to Qn5.0 1.5 6.0 10.5 1.5 11.5 ns

(PE Input HIGH or LOW)

tPLH Propagation Delay 5.0 2.0 7.0 11.0 1.5 12.5 ns

CP to TC

tPHL Propagation Delay 5.0 1.5 8.0 12.5 1.5 13.5 ns

CP to TC

tPLH Propagation Delay 5.0 1.5 5.5 8.5 1.5 10.0 ns

CET to TC

tPHL Propagation Delay 5.0 1.5 6.5 9.5 1.5 10.5 ns

CET to TC

tPHL Propagation Delay 5.0 1.5 6.0 10.0 1.5 11.0 ns

MR to Qn

tPHL Propagation Delay 5.0 2.5 8.0 13.5 2.0 14.5 ns

MR to TC

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74AC161 • 74ACT161

AC Operating Requirements for ACT

Note 10: Voltage Range 5.0 is 5.0V ± 0.5V

Capacitance

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 10) Typ Guaranteed Minimum

tSSetup Time, HIGH or LOW 5.0 4.0 9.5 11.5 ns

Pn to CP

tHHold Time, HIGH or LOW 5.0 −5.0 0 0 ns

Pn to CP

tSSetup Time, HIGH or LOW 5.0 4.0 8.5 9.5 ns

PE to CP

tHHold Time, HIGH or LOW 5.0 −5.5 −0.5 −0.5 ns

PE to CP

tSSetup Time, HIGH or LOW 5.0 2.5 5.5 6.5 ns

CEP or CET to CP

tHHold Time, HIGH or LOW 5.0 −3.0 0 0 ns

CEP or CET to CP

tWClock Pulse Width, 5.0 2.0 3.0 3.5 ns

(Load) HIGH or LOW

tWClock Pulse Width, 5.0 2.0 3.0 3.5 ns

(Count) HIGH or LOW

tWMR Pulse Width, LOW 5.0 3.0 3.0 7.5 ns

tREC Recovery Time 5.0 0 0 0.5 ns

MR to CP

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC = OPEN

CPD Power Dissipation Capacitance 45.0 pF VCC = 5.0V

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74AC161 • 74ACT161

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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74AC161 • 74ACT161

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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74AC161 • 74ACT161

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

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74AC161 • 74ACT161 Synchronous Presettable Binary Counter

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assume an y responsibility for u se of any circuitry descr ibed, no circuit pat ent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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