DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is low the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is high, the data from the J and K inputs are disabled. On the negative transition of the clock, the data from the master is transferred to the slave. The logic states of the J and K inputs must not be allowed to change while the clock is high. Data is transferred to the outputs on the falling edge of the clock pulse. A low logic level on the clear input will reset the outputs regardless of the logic states of the other inputs. Connection Diagram Dual-In-Line Package TL/F/6630 - 1 Order Number DM54L73J or DM54L73W See NS Package Number J14A or W14B Function Table Inputs Outputs CLR CLK J K L H H H H X E E E E X L H L H X L L H H Q Q L H QO QO H L L H Toggle H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level E e Positive pulse data. The J and K inputs must be held constant while the clock is high. Data is transferred to the outputs on the falling edge of the clock pulse. QO e The output logic level before the indicated input conditions were established. Toggle e Each output changes to the complement of its previous level on each complete high level clock pulse. C1995 National Semiconductor Corporation TL/F/6630 RRD-B30M105/Printed in U. S. A. DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1989 Absolute Maximum Ratings (Note) Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device can not be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Storage Temperature Range 8V 5.5V b 65 C to a 150 C Operating Free Air Temperature Range b 55 C to a 125 C DM54L Recommended Operating Conditions Symbol DM54L73 Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage Units Min Nom Max 4.5 5 5.5 2 V V Clock 0.6 Others 0.7 V IOH High Level Output Current b 0.2 IOL Low Level Output Current 2 mA fCLK Clock Frequency (Note 2) 6 MHz tW Pulse Width (Note 2) 0 Clock High 100 Clock Low 100 Clear Low 100 Input Setup Time (Notes 1 & 2) tH Input Hold Time (Notes 1 & 2) 0v TA Free Air Operating Temperature b 55 Note 1: The symbols ( ns 0u tSU u, v) indicate the edge of the clock pulse used for reference: u for rising edge, v for falling edge. Note 2: TA e 25 C and VCC e 5V. 2 mA ns ns 125 C Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) 2.4 3.3 VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Voltage Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min II Input Current @ Max Input Voltage VCC e Max VI e 5.5V IIH IIL High Level Input Current Low Level Input Current Max V 0.15 0.3 J, K VCC e Max VI e 2.4V VCC e Max VI e 0.3V IOS Short Circuit Output Current VCC e Max ICC Supply Current VCC e Max (Note 2) Units V 100 Clear 200 Clock 200 J, K 10 Clear 20 Clock b 200 J, K b 0.18 Clear b 0.36 Clock b 0.36 b3 1.5 mA mA mA b 15 mA 2.88 mA Note 1: All typicals are at VCC e 5V, TA e 25 C. Note 2: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock is grounded. Switching Characteristics VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter From (Input) To (Output) RL e 4 kX, CL e 50 pF Min Units Max fMAX Maximum Clock Frequency tPHL Propagation Delay Time High to Low Level Output 6 Clear to Q 150 ns tPLH Propagation Delay Time Low to High Level Output Clear to Q 75 ns tPLH Propagation Delay Time Low to High Level Output Clock to Q or Q 10 75 ns tPHL Propagation Delay Time High to Low Level Output Clock to Q or Q 10 150 ns 3 MHz DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs Physical Dimensions inches (millimeters) 14-Lead Ceramic Dual-In-Line Package (J) Order Number DM54L73J NS Package Number J14A 14-Lead Ceramic Flat Package (W) Order Number DM54L73W NS Package Number W14B LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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