DM54L73J/883 - National Semiconductor

TL/F/6630

DM54L73 Dual Master-Slave J-K Flip-Flops

with Clear and Complementary Outputs

August 1989

DM54L73 Dual Master-Slave J-K Flip-Flops

with Clear and Complementary Outputs

General Description

This device contains two independent positive pulse trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flops after a complete clock

pulse. While the clock is low the slave is isolated from the

master. On the positive transition of the clock, the data from

the J and K inputs is transferred to the master. While the

clock is high, the data from the J and K inputs are

disabled. On the negative transition of the clock, the data

from the master is transferred to the slave. The logic states

of the J and K inputs must not be allowed to change while

the clock is high. Data is transferred to the outputs on the

falling edge of the clock pulse. A low logic level on the clear

input will reset the outputs regardless of the logic states of

the other inputs.

Connection Diagram

Dual-In-Line Package

TL/F/6630–1

Order Number DM54L73J or DM54L73W

See NS Package Number J14A or W14B

Function Table

Inputs Outputs

CLR CLK J K Q Q

LXXXLH

HÉLLQ

HÉHL H L

HÉLH L H

HÉH H Toggle

HeHigh Logic Level

XeEither Low or High Logic Level

LeLow Logic Level

ÉePositive pulse data. The J and K inputs must be held constant while

the clock is high. Data is transferred to the outputs on the falling edge of the

clock pulse.

QOeThe output logic level before the indicated input conditions were

established.

Toggle eEach output changes to the complement of its previous level on

each complete high level clock pulse.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 8V

Input Voltage 5.5V

Storage Temperature Range b65§Ctoa

150§C

Operating Free Air Temperature Range

DM54L b55§Ctoa

125§C

Note:

The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device can not be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation.

Recommended Operating Conditions

Symbol Parameter DM54L73 Units

Min Nom Max

VCC Supply Voltage 4.5 5 5.5 V

VIH High Level Input Voltage 2 V

VIL Low Level Input Voltage Clock 0.6 V

Others 0.7

IOH High Level Output Current b0.2 mA

IOL Low Level Output Current 2 mA

fCLK Clock Frequency (Note 2) 0 6 MHz

tWPulse Width (Note 2) Clock High 100

Clock Low 100 ns

Clear Low 100

tSU Input Setup Time (Notes1&2) 0

tHInput Hold Time (Notes1&2) 0

TAFree Air Operating Temperature b55 125 §C

Note 1: The symbols (

) indicate the edge of the clock pulse used for reference:

for rising edge,

for falling edge.

Note 2: TAe25§C and VCC e5V.

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

VOH High Level Output VCC eMin, IOH eMax 2.4 3.3 V

Voltage VIL eMax, VIH eMin

VOL Low Level Voltage VCC eMin, IOL eMax 0.15 0.3 V

Voltage VIL eMax, VIH eMin

IIInput Current @Max VCC eMax J, K 100

Input Voltage VIe5.5V Clear 200 mA

Clock 200

IIH High Level Input VCC eMax J, K 10

Current VIe2.4V Clear 20 mA

Clock b200

IIL Low Level Input VCC eMax J, K b0.18

Current VIe0.3V Clear b0.36 mA

Clock b0.36

IOS Short Circuit VCC eMax b3b15 mA

Output Current

ICC Supply Current VCC eMax (Note 2) 1.5 2.88 mA

Note 1: All typicals are at VCC e5V, TAe25§C.

Note 2: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock is grounded.

Switching Characteristics VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load)

Symbol Parameter From (Input) RLe4kX,C

Le50 pF Units

To (Output) Min Max

fMAX Maximum Clock Frequency 6 MHz

tPHL Propagation Delay Time Clear to Q 150 ns

High to Low Level Output

tPLH Propagation Delay Time Clear to Q 75 ns

Low to High Level Output

tPLH Propagation Delay Time Clock to Q or Q 10 75 ns

Low to High Level Output

tPHL Propagation Delay Time Clock to Q or Q 10 150 ns

High to Low Level Output

DM54L73 Dual Master-Slave J-K Flip-Flops

with Clear and Complementary Outputs

Physical Dimensions inches (millimeters)

14-Lead Ceramic Dual-In-Line Package (J)

Order Number DM54L73J

NS Package Number J14A

14-Lead Ceramic Flat Package (W)

Order Number DM54L73W

NS Package Number W14B

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failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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