intel. 8255A/8255A-5 PROGRAMMABLE PERIPHERAL INTERFACE m@ MCS-85T Compatible 8255A-5 gw Direct Bit Set/Reset Capability Easing m 24 Programmable I/O Pins Control Application Interface = Completely TTL Compatibie m Reduces System Package Count m Fully Compatible with Intel m= Improved DC Driving Capability Microprocessor Families @ Available in EXPRESS w Improved Timing Characteristics Standard Temperature Range Extended Temperature Range @ 40 Pin DIP Package (See Intel Packaging: Order Number: 240800-001, Package Type P) The intel 8255A is a general purpose programmable I/O device designed for use with Intel microprocessors. It has 24 {/O pins which may de individually programmed in 2 groups of 12 and used in 3 major modes of operation. In the first mode (MODE 0), each group of 12 I/O pins may be programmed in sets of 4 to be input or output. In MODE 1, the second mode, each group may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for handshaking and interrupt control signals. The third mode of operation (MODE 2) is a bidirectional bus mode which uses 8 lines for a bidirectional bus, and 5 lines, borrowing one from the other group, for handshaking. - 1 PowER _ +0 amour emus oo Grove Ce Pont C_> Par Php ms NS of | cowmnoe Ke i oF Bn mai q 3 Pry r) Pas l eao q 4 Pd D ma? | mw]: a [7] anor es(]s 38 a RESET Kes Kee TG pe BLOIREC TIONAL DATA SUS pata _ a0 q 9 ao or CY 7?.= Ko er] gaecy Pn eer ves CPt a0 a Da INTERNAL Grove OaTa BUS a 1 rcs a a | > ms Kee "h. iay eco} v D> f Cl q 6 as a} Voc _ ah pe wm e ware GrouP Grour reo oO 1. 2 Tr res =} <P poe gs pa sr LW 231308-2 Figure 2. Pin ; Configuration a 231308-1 Figure 1. 8255A Block Diagram August 1991 3-100 Order Number; 231303-003 www.chipdocs.com Be sure to visit ChipDocs web site for more information.www.chipdocs.com intel. 8255A/8255A-5 8255A FUNCTIONAL DESCRIPTION General The 8255A is a programmable peripheral interface (PPI} device designed for use in Intel microcomputer systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. The functional configu- ration of the 8255A is programmed by the system software so that normally no external logic is neces- sary to interface peripheral devices or structures. Data Bus Buffer This 3-state bidirectional 8-bit buffer is used to inter- face the 8255A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. (CS) Chip Select. A low on this input pin enables the communication between the 8255A and the CPU. (RD) Read. A low on this input pin enables the 8255A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to read from the 8255A. (WR) Write. A tow on this input pin enables the CPU to write data or controt words into the 8255A. (Ag and A;) Port Select 0 and Port Select 1. These input sig- nals, in conjunction with the RD and WR inputs, con- trol the selection of one of the three ports or the control word registers. They are normally connected to the least significant bits of the address bus (Ag and Aj). POWER SUPPLIES ono GROW A CONTAOL L Ki eke PA; Pag Gt DIRECTIONAL DATA BUS. Data 0,0 as oS BUFFER GROUP A ve PORT C UPPER PCr Pa 1a) | BBIT INTERNAL GROUP 6 DATA BUS Ky ror c LOWER 14) > te PCy PL Lit READY WRITE CONTROL Logie Gaour CONTROL | on oe a fT Cert KO En 8 PB, PBg RESET +| ee {8} s_____ 231308-3 Figure 3. 8255A Block Diagram Showing Data Bus Buffer and Read/Write Controt Logic Functions 3-101 Be sure to visit ChipDocs web site for more information.www.chipdocs.com intel. 8255A/8255A-5 8255A BASIC OPERATION A; | Ao| RD | WR | CS | Input Operation (READ) 1 PortA Data Bus 0) 0 1 0 1 0 | PorttB Data Bus 0 0 | PortC Data Bus Output Operation (WRITE) Data Bus PortA Data Bus PortB Data Bus Port +~/aiolo -[ofialo a~low/ofa olololo clolojfo Data Bus Control Disable Function Data Bus 3-State Iliegal Condition Data Bus 3-State (RESET) Reset. A high on this input clears the control reg- ister and all ports (A, B, C) are set to the input mode. Group A and Group B Controls The functional configuration of each port is pro- grammed by the systems software. in essence, the CPU outputs a contro! word to the 8255A. The control word contains information such as mode, bit set, bit reset, etc., that initializes the func- tional configuration of the 8255A. Each of the Control blocks (Group A and Group B) accepts commands from the Read/Write Control Logic, receives control words from the internal data bus and issues the proper commands to its as- sociated ports. Control Group APort A and Port C upper (C7--C4) Control Group BPort 8 and Port C lower (C3-C0) The Contro! Word Register can Only be written into. No Read operation of the Control Word Register is allowed. Ports A, B, and C The 8255A contains three 8-bit ports {A, B, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 8255A. Port A. One 8-bit data output latch/buffer and one 8-bit data input latch. Port B. One 8-bit data input/output /atch/buffer and one 8-bit data input buffer. Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no iatch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B. 3-102 Be sure to visit ChipDocs web site for more information.8255A/8255A-5 POWER SUPPLIES _t GND B-CWREC TIONAL DATA BUS , DATA aus BUFFER i ______+a __-q we WAITE CONTROL LOG a | RESET .__| tov Group a 7) te A Co CONTROL a GROUP A vo PORT C PCy-PC4 UPPER cy 8-BIT INTERNAL GROUP DATA BUS pont om vo LOWER Pea-PCo ta GROUP Grove cot [J r e 8 PB?-PBg (8) - | 231308-4 Figure 4. 8225A Block Diagram Showing Group A and Group B Control Functions Pin Configuration pas NH aot) paa ear (2 3017) Pas par (3 ae [7] Pas wao[ ja 3717 par RDC] s 38 [7] we as 35 [7] RESET cao {]7 Clo, ar(le x3[] 0, aos 32(7) o, ec? (]10 ufo, pee (]1t S256A = wa, pcs [12 2317] b, pce [113 zl} o, pcol | 14 7h bp, poi l15 2611 Yee oc2 0) 16 2s|) eB? pca Cj? 2e[] vos roo (}18 237] Pes Per; jis 227) pase Pez ] 20 21]7] 83 Pin Names D7-Do Data Bus (Bi-Directional) RESET Reset Input cs Chip Select RD Read Input WA Write Input AO, Ai Port Address PA7-PAGQ Port A (BIT) PB7-PBO Port B (BIT) PC7-PCO Port C (BIT) Voc + 5 Volts GND 0 Volts 231308-5 www.chipdocs.com 8255A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software: 3-103 Be sure to visit ChipDocs web site for more information.www.chipdocs.com intel. 8255A/8255A-5 Mode 0Basic Input/Output Mode 1Strobed Input/Output Mode 2Bi-Directional Bus When the reset input goes high all ports will be set to the input mode (i.e., all 24 fines will be in the high impedance state). After the reset is removed the 8255A can remain in the input mode with no addi- tional initialization required. During the execution of the system program any of the other modes may be selected using a single output instruction. This al- lows a single 8255A to service a variety of peripheral devices with a simple software maintenance routine. The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be tailored to almost any I/O structure. For instance; Group B can be programmed in Mode 0 to monitor simple switch closings or display computa- tional results, Group A could be programmed in Mode 7 to monitor a keyboard or tape reader on an interrupt-driven basis. { ADDAESS BUS | { CONTROL BUS Li LI C DATA BUS dete TITY UT PB, PB vo U-1 pap _ CONTROL 7PAa > BIDIRECTIONAL 231308-6 CONTROL WORD b, | O,| 0, | By | 0, | D, | Oo, | Oo, GROUP & PORT C (LOWER) 1 = INPUT 0 = OUTPUT PORT B t= INPUT 0 = OUTPUT MOOE SELECTION 0 = MODE 0 1=MOOE 1 GROUP A PORT C (UPPER) T= INPUT O= OUTPUT PORT A 1 = INPUT O= OUTPUT MODE SELECTION OO = MODE 0 O01 = MODE 1 1X = MODE 2 MODE SET FLAG 1 = ACTIVE Figure 5. Basic Mode Definitions and Bus Interface 231308-7 Figure 6. Mode Definition Format The mode definitions and possible mode combina- tions may seem confusing at first but after a cursory review of the complete device operation a simple, logical |/O approach will surface. The design of the 8255A has taken into account things such as effi- cient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. Single Bit Set/Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUT put instruction. This feature re- duces software requirements in Control-based appli- cations. 3-104 Be sure to visit ChipDocs web site for more information.www.chipdocs.com - 8255A/8255A-5 a intel. CONTROL WORD D7 | Dg | Ds | Oy | Os | O2 | By | Dy BIT SET/RESET x x x 1=SET O= RESET DON'T CARE BIT SELECT [0] 1] 2]3] 4] 5] 6] 7 0} 1) 0} 1/0) 1/0) 1| Bol lololaiilololits la, a|G/O}O}t/ 111/19 BIT SET/RESET FLAG O= ACTIVE 231308-8 Figure 7. Bit Set/Reset Format When Port C is being used as status/control for Port Aor 6B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were data output ports. Interrupt Control Functions When the 8255A is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The in- terrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C. MODE 0 (BASIC INPUT) This function allows the Programmer to disallow or allow a specific I/O device to interrupt the CPU with- out affecting any other device in the interrupt struc- ture. INTE flip-flop definition: (BIT-SET)INTE is setinterrupt enable (BIT-RESET)INTE is RESETInterrupt disable NOTE: Alt Mask flip-flops are automatically reset during mode selection and device Reset. Operating Modes MODE 0 (Basic Input/Output). This functional con- figuration provides simple input and output opera- tions for each of the three ports. No handshaking is required, data is simply written to or read from a specified port. Mode 0 Basic Functional Definitions: * Two &-bit ports and two 4-bit ports. e Any port can be input or output. * Outputs are latched. Inputs are not latched. 16 different Input/Output configurations are pos- sible in this Mode. INPUT CS, A1, AO D,-D, 231308-9 3-105 Be sure to visit ChipDocs web site for more information.intel. 8255A/8255A-5 MODE 0 (BASIC OUTPUT) D,-D, C$, a1, Ao OUTPUT 231308-10 MODE 0 PORT DEFINITION A B GroupA Group B D4 D3 D, Do Port A Wppen # Port B Lower) 0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT 0 0 0 1 OUTPUT OUTPUT 1 OUTPUT INPUT 0 0 1 0 OUTPUT QUTPUT 2 INPUT OUTPUT 0 0 1 1 OUTPUT OUTPUT 3 INPUT INPUT 0 1 0 0 OUTPUT INPUT 4 OUTPUT OUTPUT 0 1 0 1 OUTPUT INPUT 5 OUTPUT INPUT ] 1 1 0 OUTPUT INPUT 6 INPUT OUTPUT 0 1 1 1 OUTPUT INPUT 7 INPUT INPUT 1 0 0 0 INPUT OUTPUT 8 OUTPUT OUTPUT 1 0 0 1 INPUT OUTPUT 9 OUTPUT INPUT 1 0 1 0 INPUT OUTPUT 10 INPUT OUTPUT 1 0 1 1 INPUT OUTPUT 11 INPUT INPUT 1 1 0 0 INPUT INPUT 12 OUTPUT OUTPUT 1 1 0 1 INPUT INPUT 13 OUTPUT INPUT 1 1 1 0 INPUT INPUT 14 INPUT OUTPUT 1 1 1 1 INPUT INPUT 15 INPUT INPUT 3-106 www.chipdocs.com Be sure to visit ChipDocs web site for more information.a intel. B255A/8255A-5 MODE CONFIGURATIONS CONTROL WORD #0 CONTROL WORD #2 D, Dg Dy; D% 0, D, D, Dy D, Ds Os; Dy 0, DB, 9, Dy 1/o};]o];ojafaflo]o 1], oO; oO; oO); oF} OF 1] O 18 a A y PA; PA, A PA;-PAg 8255A B255A 4 4 PC, PC, } A PC, PC, D,-D, ___+ c 0,D, _+} a 4 # PC, PC, } A PC, PC, 8 5 # PB, -PB, B 7 PB, PB, 231308-11 231308-12 CONTROL WORD #1 CONTROL WORD #3 D, Dg Ds DB DB, BD, O, D, DP, Dg Dy Dy 0, D, Dy Dy t1}ofo]e}ol]oa]o{. 1}/ofojojoj]o]af4 A 48 a 7 PA -PAy al-4+ PA, PA, 8255A B255A 4 4 PC,-PC, p_y~4 PC, PC, D,-Dg _\___+] c D; Oy _______-} 4 4 4 PC,-PC, j+-_"_ pc, #0, B 48 1 8 7 PB, PB, 8} _/7-___ P,P, 231308-13 231308-14 CONTROL WORD #4 CONTROL WORD #8 D, 0g DBD; DO, Dy DB, DB, Dy D, Dg D, 0, Dy, DB, DB, Dy rio!}oaotoitirtfoloalo 1J/oloj;1a]olololoa A 44 PA,-PA, a +48 papery S255A 82554 4 4 4 PC, PC, +A -> PC, PC, Dy-Dy <> D, Dy << 4 4 f PC, PC, }-A- PC, PC, a 8 B 7 PB,-PB, 8 | --+-> P8, Pa, 231308-15 231308-16 3-107 www.chipdocs.com Be sure to visit ChipDocs web site for more information.e intel. 8255A/8255A-5 CONTROL WORD #5 CONTROL WORD #9 Oy O, By Dy 0, Dp 1, 2% D, De Ds OO 0D, Dz D, Dy 1/o}/ofo]}1rjo]o]f4 1}of/ofa]ofof]oj]4 8 aA -42> Pa, Pa, a |+~* papa, 8255A 8255A 4 4 ef ..- PC,.PC, }-f- PC,-PC, D,-D, _s D,-By ___+] 4 4 +f - Pe, PCy }+#--_ PC PCy 8 : 8 8|--7-_ PB,-PB, PB, -PBy 231308-17 231908-18 CONTROL WORD #6 CONTROL WORD =10 D, De Ds Dy, 03 0, D0, Dg D, Og OF O Dy DO, DOD, OD 1}o;/ofof;afo;r4]a r1lo!lol+ioliotiaio J vs PA,-P 8 A 7 PAg Ale" Pay PA, 6255A 8255A j~_,-- Pc, Pc, pA PC,-PC, Dy Dy <__ D0, <________+ 4 4 [7+ PC, PCy ~ --4+> Pc, PC, 8 8 B i= ---- PB, PB, p |=_/_ pa, CONTROL WORD #7 CONTROL WORD #11 D, De 0, O Ds D, By, Dy D, Dg DO, Dy 2; Dz OB, Dy 1loflol}o;}rjofaf. 1)/o0fol1]o]o);1441 8 a A |-_4-_ Pa, PA, A --_4+__ Pa PA, B255A 8255A 4 4 J fm~ PC, PC, +7 PCP, D,-D, + 0,0, -_ 4 4 -_{-___ PC4-PCy A PC, -PC, 8 8 & |~+___- P,P, B+ P,P, 231308-21 231308-22 www.chipdocs.com 3-108 Be sure to visit ChipDocs web site for more information.www.chipdocs.com intel. 8255A/8255A-5 CONTROL WORD #12 BD, Ds Dg Dy Dy Dy D, Dy 1 o 0 1 1 0 Q 9 D7-Dy 231308-23 CONTROL WORD #14 D; Og 05; OD, Dy 0, D, Dg 1 0 0 1 1 9 1 0 255A 0,-Dy + _______| 231308-24 CONTROL WORD #13 D, Dg, DB, Dy Dy OB, DO, Dy t}oloj;1]/1]fo]o]4 & A |~_/-_-_ Pa-PA, 8255A 0,-Dy _ HY 4 ? PC, -PC, { ~__~4 PC, PC, 8 & ;}/+-> PB, PB, 231308-25 Operating Modes MODE 1 (Strobed Input/Output). This functional configuration provides a means for transferring 1/O data to or from a specified port in conjunction with strobes or handshaking signals. In mode 1, port A and port B use the lines on port C to generate or accept these handshaking signals. Mode 1 Basic Functional Definitions: Two Groups (Group A and Group B) * Each group contains one 68-bit data port and one 4-bit control/data port. The 8-bit data port can be either input or output. Both inputs and outputs are latched. e The 4-bit pert is used for control and status of the 8-bit data port. CONTROL WORD #15 D, Dg OF DB, Oy D, D, Dy 1 0 0 1 1 0 1 1 a }+/* pa, pa, 231308-26 Input Control Signal Definition STB (Strobe Input). A low on this input loads data into the input latch. IBF (Input Buffer Full F/F) A high on this output indicates that the data has been loaded into the input latch; in essence, an ac- knowledgement. IBF is set by STB input being low and is reset by the rising edge of the RD input. INTR (interrupt Request) A high on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the STB is a one, IBF is a one and INTE is a one. It is reset by the falling edge of RD. This procedure allows an input device to re- quest service from the CPU by simply strobing its data into the port. 3-109 Be sure to visit ChipDocs web site for more information.www.chipdocs.com intel. 8255A/8255A-5 INTE A Controlled by bit set/reset of PC,. INTE B Controlled by bit set/reset of PCo. MODE 1 (PORT A) MOD E 1 (PORT B) INPUT FROM PERIPHERAL _ << tps PA, P. FI PB, PB, Ca] CONTROL WORD Ar? CONTROL WORD D, Dg Dg Dy Dy DZ D, Oy ara db, D, D, D, D; D, 0, Dy raat INTE pc, }- STB RA 7 PC) ---- ST, Ptpopey ope | u*Ag Lt * Lt DXEXD I + 1 DX Ute , PCy 7 | PC, + 18F, PC,}-> IBF, 1 = INPUT a= OUTPUT PC, INTR, PCy p-> INTR, Ao ie RG _+a 2 PC, of vo 231308 -27 231308-26 Figure 6. MODE 1 Input -~ 1 a8 y jo Ugg 1OF \ sity | , > "ra *| INTR / \ [ tant AD \ { [e Ugg a 231308-29 Figure 9. MODE 3 1 (Strobed Input) -110 Be sure to visit ChipDocs web site for more information.intel. 8255A/8255A-5 tout ntrol Si initi device has accepted data transmitted by the CPU. Output Control S gnal Definition INTR is set when ACK is a one, OBF is a one, OBF (Output Buffer Full F/F). The OBF output will and INTE is a one. It is reset by the falling edge of go low to indicate that the CPU has written data WR. out to the specified port. The OBF F/F will be set by the rising edge of the WR input and reset by ACK INTE A input being low. ACK (Acknowledge Input). A low on this input Controlled by bit set/reset of PCg. informs the 8255A that the data from port A or port B has been accepted. In essence, a response from INTE B the peripheral device indicating that it has received ; the data output by the CPU. | Controlled by bit set/reset of PCo. INTR (Interrupt Request). A high on this output can de used to interrupt the CPU when an output MODE 1 (PORT A) MODE 1 (PORT B) Payee Le > CONTROL WORD CONTROL WORD D; Dg Dg Dy Dy Dz Dy Dy sat ane REE a + 66 PPLE DES frst BODO Peas Inte PCS Ie ACK, 1 = INPUT ~-4 @= OUTPUT PC, + INTR, Wh ro We _~o 2 PCs atta 231308-30 231308-31 Figure 10, MODE 1 Output ont \ Po + wn _ \\ 4 aK } tart OUTPUT : wo Figure 11. MODE 1 (Strobed Output) 231308-32 3-111 www.chipdocs.com Be sure to visit ChipDocs web site for more information.www.chipdocs.com 8255A/8255A-5 PA,PAy Ca AD eg PC, L+_ STB, Pcs + ler, CONTROL WORD D, Og DO, Dy Dy 0, D, Dy PC, > INTR, PPE Pop [eX we. [e Ze vo PCQ 7 sa | ttl WR eo ce OBF, PC) | ACK, PCy f--> INTR, 231308-33 PORT A(STROBED INPUT) PORT B--{STROBED OUTPUT) PA,-PAg{ 8 > wR +q PC, [+ OBF, PC, |-+- ACK, CONTROL WORD D, 0, Ds 0, D, 0, DB, Dy PC, |}- INTR, Pt fet fo fot |X ? PCa gf 0 Plas 1* INPUT 0 = OUTPUT PB, PBy RD9 PC, +. STB, PC\;/> IBF, PCy b> INTR, 231308-34 PORT A(STROBEDO OUTPUT) PORT B(STROBED INPUT) Figure 12. Combinations of MODE 1 Combinations of MODE 1 Port A and Port B can be individually defined as in- put or output in MODE 1 to support a wide variety of strobed |/O applications. Operating Modes MODE 2 (Strobed Bidirectional Bus 1/0). This functional configuration provides a means for com- municating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus !/O). Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1. Interrupt generation and enable/disable functions are also available. MODE 2 Basic Functional Definitions: * Used in Group A only. * One 8-bit, bi-directional bus Port (Port A) and a 5- bit control Port (Port C). Both inputs and outputs are latched. e The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A). Bidirectional Bus I/O Control Signal Definition INTR (Interrupt Request). A high on this output can be used to interrupt the CPU for both input or output operations. Output Operations OBF (Output Buffer Full). The OBF output will go low to indicate that the CPU has written data out to port A. ACK (Acknowledge). A low on this input enables the tri-state output buffer of port A to send out the data. Otherwise, the output buffer will be in the high impedance state. INTE 1 (The INTE Flip-Flop Associated with OBF). Controlled by bit set/reset of PCg. Input Operations STB (Strobe Input). A low on this input loads data into the input latch. 3-112 Be sure to visit ChipDocs web site for more information.intel. 8255A/8255A-5 IBF (input Buffer Full F/F). A high on this output INTE 2 (The INTE Flip-Flop Associated with IBF). indicates that data has been loaded into the input Controlled by bit set/reset of PC4. latch. CONTROL WORD Dr Og Ds DB, DO, DB, D, Dy INTR, 1 1 1/0 | 1/0 | 1/0 8 OOF, Plog aK 1 = INPUT ack, O= OUTPUT < PORT 5 T= INPUT STB, O = OUTPUT IBF, Wa nnn nen GROUP B MODE O= MODE 0 1= MODE 1 3 231906-35 RD vo Figure 13. MODE Contro! Word 231308-96 Figure 14. MODE 2 DATA FROM i wh > me / 1 - "wos iNTR ACK IGF PERIPHERAL Bus OATA FROM 82554 TO 9080 231308-37 NOTE: Any sequence where WR occurs before ACK and STB occurs before AD is permissible. (INT = IBF MASK STB * RD + OBF MASK ACK WR) Figure 15. MODE 2 (Bidirectional) 3-113 www.chipdocs.com Be sure to visit ChipDocs web site for more information.www.chipdocs.com intel. 8255A/8255A-5 MODE 2 AND MODE 0 (INPUT) MODE 2 AND MODE 0 (OUTPUT) PC, iNTR, PC, -> INTRy PA, -PAy PA,-PA, PC, + oar, PC, - oBF, CONTROL WORD Pc, |< ACK, CONTROL WORD Pc, |~ Ack, D, Dg D5 D, Ds Dy D, Dy Dy Og Dy Dy 03 Dy D, Dy AT CD PB TeL be i CED 00 | __=, Pc J, Pc pc, | 1F Pag = PC, 18F, vir as 0= OUTPUT ; 3 PC, |* 4 v0 Peg f+ vO AD __++a RD -__q re rem 5 > CONTROL WORD 0, Dg Ds Dy Dy Dy D, Dy Pd ke fab PC; PA,-PA, PB, PR, PCy PC2 PCy 231308-38 MODE 2 AND MODE 1 (OUTPUT) }___ INTA, --__ 8T8, } IBF, => |__.. af, ++ ACK, - INTRA, 231308-40 MODE 2 AND MODE 1 (INPUT) 231308-39 CONTROL WORD Dy Dg Dg Dy Dy D2 O Dy AL PD [TX] RD .-___d WR -q mC, P8, Py PC, PCy +_-> INTR, $n OOF, ___ ACK, fap nte STB, |} IBF, }+_- S78, p> 1 BF, -> INTR, 231308-41 Figure 16. MODE 1 Combinations Be sure to visit ChipDocs web site for more information.intel. 8255A/8255A-5 Mode Definition Summary MODE 0 MODE 1 MODE 2 IN OUT IN OUT GROUP A ONLY PAg IN OUT IN OUT _ PA, IN OUT iN OUT _ PAs IN OUT IN OUT <_ PA3 IN OUT IN OUT _ PA, IN OUT IN OUT PAs IN OUT IN OUT _ PAg IN OUT IN OUT _ PA; IN OUT iN OUT PBo IN OUT IN OUT __ PB, IN- OUT IN OUT PBo iN OUT IN ~ QUT PB3 iN OUT iN OUT _ MODE 0 PB, IN OUT IN OUT __ OR MODE 1 PBs iN OUT IN OUT __ ONLY PBs iN OUT IN OUT PB; iN OUT IN OUT PCo IN OUT INTRg INTRB 1/0 PC, IN OUT IBFg OBFs /O PCo IN OUT STBg ACKg 1/0 PC3 (IN OUT INTRA INTRA INTRa PCy IN OUT STB, 1/0 STBa PCs IN OUT IBFa 1/0 IBFa PGs5 iN OUT 1/0 ACKa ACKa PC; IN OUT 1/0 OBFa OBFa www.chipdocs.com Special Mode Combination Considerations There are several combinations of modes when not ail of the bits in Port C are used for control or status. The remaining bits can be used as foltows: lf Programmed as Inputs All input lines can be accessed during a normal Port C read. lf Programmed as Outputs Bits in C upper (PC7-PC,) must be individually ac- cessed using the bit set/reset function. Bits in C lower (PC3-PCog) can be accessed using the bit set/reset function or accessed as a three- some by writing into Port C. Source Current Capability on Port B and Port C Any set of eight output buffers, selected randomly from Ports B and C can source 1 mA at 1.5 voits. This feature allows the 8255 to directly drive Darling- ton type drivers and high-voltage displays that re- quire such source current. Reading Port C Status in Mode 0, Port C transfers data to or from the pe- ripheral device. When the 8255 is programmed to function in Modes 1 or 2, Port C generates or ac- cepts hand-shaking signals with the peripheral de- vice. Reading the contents of Port C allows the pro- grammer to test or verify the status of each pe- ripheral device and change the program flow ac- cordingly. There is no special instruction to read the status in- formation from Port C. A normai read operation of Port C is executed to perform this function. 3-115 Be sure to visit ChipDocs web site for more information.8255A/8255A-5 INPUT CONFIGURATION BD, Dg Ds Dg dD, Oo, OD, 0% Figure 18. MODE 2 Status Word Format APPLICATIONS OF THE 8255A INTERRUPT REQUEST | INTERRUPT | REQUEST me, = vO | VO [ IBF, | INTE, [INTR,| INTE, | IBF, |INTR, 3 | Pag PA, \ moe T PA, GROUP A GRouP 8 PA, PRINTER PA, OUTPUT CONFIGURATION PA, MODE 1 D 6DPg)hCOUWg:hCU CO CDCg tourpuT} | PAs PA, | HAMMER GBF, |INTE,; 170 | VO JINTR,| INTE,! OBF, HNTR, RELAYS Pc, DATA READY T . T , PC, ACK GROUP A GROUP B PC, PAPER FEED 231308-59 [PCa FORWAAD/REV e285a Figure 17. MODE 1 Status Word Format me 1 . 3, Pe; DATA READY Pa, ACK D & = =68%66Um 6h UF MODE1 | Pa, PAPER FEED fourPur) 8, FORWARD/REV ar, | NTE, | 18F, | INTE, |INTR, oe roma u aS ee CARRIAGE SEN. GROUP A GROUP B PC, DATA READY Pc, ACK (DEFINED BY MODE 0 OR MODE 1 SELECTION) ~ 23130842 Peo CONTROL LOGIC AND DRIVERS 23130843 Figure 19. Printer interface The 8255A is a very powerful tool for interfacing pe- INTERRUPT ripheral equipment to the microcomputer system. !t REQUEST represents the optimum use of avaiiable pins and is Fs flexible enough to interface almost any t/O device ee ro without the need for additional external logic. meet om, a, puuty PA. R DECODED Each peripheral device in a microcomputer system PA, n, EvBOARD usually has a service routine associated with it. PAS Ry The routine manages the software interface be- hNeuT) | PAs SHIFT tween the device and the CPU. The functional defini- PA, CONTROL tion of the 8255A is programmed by the |/O service bc STROBE routine and becomes an extension of the system rc, ACK software. By examining the I/O devices interface characteristics for both data transfer and timing, and matching this information to the examples and ta- _ bies in the detailed operational description, a control PB By word can easily be developed to initialize the 8255A PB, Bt BURROUGHS to exactly fit the application. Figures 19 through PB, By 'SELF-SCAN : sas PB, By OISPLAY 25 represent a few examples of typical applications eB, e, of the 8255A. PB oururr 7] 8, DACKSPACE PB, CLEAR PC, DATA READY PC, ACK PC, BLANKING PC, |_PC, CANCEL WORD REQUEST 231308-44 Figure 20. Keyboard and Display Interface 3-116 www.chipdocs.com Be sure to visit ChipDocs web site for more information.intel. 8255A/8255A-5 INTERRUPT REQUEST PCs TPA, Ry PA, a, PA, R, FULLY monet | PAs a _pecopep ONPUT) | Pa, R, KEYBOARD Pas Rs PA, SHIFT a255A PA, CONTROL PC, strope PC, ACKNOWLEDGE PC, Busy LT PC, TEST LT a 7 sg, PBy Le TERMINAL B, ADORESS PB, oe move o | PB; _? (INPUT) | PR, oc ra, oc PB, oc Pa, cu as 231308-45 (INTERRUPT REQUEST MODE 2 ] PAg MODE fouTeuT) | PBs 2, a, o, Dy FLOPPY DISK b CONTROLLER N's AND DRIVE Os dF b, DATA STB ACK (IN} DATA READY ACK (OUT) TRACK 0 SENSOA SYNC READY INDEX EN HEAD FORWARD/REV. READ ENABLE WRITE ENABLE Ons SELECT ENABLE CRC TEST BUSY LT 231308-47 Figure 21. Keyboard and Terminal Address Interface Figure 23. Basic Floppy Disk Interface MODE 0 _} PAs (ouTeuT) | pa, BIT SET/AESET MODE GO | PA; (INPUT) Pay Pa. Pe, tse 12-81T BA CONVERTER (DAC) STB DATA OUTPUT EN fP+ ANALOG OUTPUT PCy [ ep, PB, Pa, Pe, 8, SAMPLE EN STB LSB 8-8IT aD CONVERTER (ADC} MS j= ANALOG INPUT 231308 -46 INTERRUPT REQUEST PC3 Ppa, MODE 1 | PAy (OUTPUT! | Pa. 7 a3 # 3 : PSFIZZ R, CRT CONTROLLER A, CHARACTER GEN. R, REFRESH BUFFER Ry CURSOR CONTROL As SHIET CONTROL DATA READY ACK BLANKED BLACK/WHITE ROW STB COLUMN STS CURSOR H/V STB CURSOR/ROW/COLUMN ADORESS Hav 231308-48 Figure 22. Digital to Analog, Analog to Digital www.chipdocs.com 3-117 Figure 24. Basic CRT Controller Interface Be sure to visit ChipDocs web site for more information.a intel. 8255A/8255A-5 INTERRUPT REQUEST ~ | mae 3 PA, Ry PA, ay ba, }+_____. _Ia 8 LEVEL 2 2 PAPER PAS 9 TAPE PA, rR, READER P A, MODE t _| My Rn uneuT) | PAs 6 PA, Ry Pe, s6 PC, ACK PC, STOP/GO G255A MACHINE TOOL MODE o PCy START/STOP wneuts 7] PC LIMIT SENSOR (H/V} Pep OUT OF FLUID a PB, CHANGE TOOL PB, LEFT/AIGHT Pa, UP/DOWN MODE O _| P8, HOR. STEP STROBE toureuTl | PB, VERT. STEP STROBE PB, SLEW/STEP PB, FLUID ENABLE PB, - | EMERGENCY STOP 5 231308-49 Figure 25. Machine Tool Controller Interface ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias ...... 0C to 70C Storage Temperature Voltage on Any Pin with Respect to Ground.......... 0.5V to +7V Power Dissipation NOTICE: This is a production data sheet. The speciti- cations are subject to change without notice. * WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- fended exposure beyond the Operating Conditions may affect device reliability. D.C. CHARACTERISTICS T, = 0C to 70C, Voc = +5V +10%, GND = OV" Symbol Parameter Min Max | Unit Test Conditions VIL Input Low Voltage 0.5 0.8 Vv Vin Input High Voltage 2.0 Vec Vv Vo (DB) Output Low Voltage (Data Bus) 0.45* Vv lo. = 2.5mA Vor (PER) | Output Low Voltage (Peripheral Port) 0.45* Vv lop = 1.7 mA Vou (DB) Output High Voltage (Data Bus) 2.4 Vv lon = 400 pA Vou (PER) | Output High Voltage (Peripheral Port) 2.4 V lon = 200 pA Ipag) Dartington Drive Current -1.0 | -4.0 | mA | Reyz = 7509; Vext = 1.5V loc Power Supply Current 120 mA hie input Load Current +0 | pA | Vin = Voc to OV lOFL Output Float Leakage +40 | pA | Vout = Voc to 0.45V NOTE: 1. Available on any 8 pins from Port B and C. 3-118 www.chipdocs.com Be sure to visit ChipDocs web site for more information.intel. 8255A/8255A-5 CAPACITANCE Ta = 25C, Vcc = GND = OV Symbol Parameter Min Typ Max Unit Test Conditions Cin Input Capacitance 10 pF fe = 1 MHz(4) Cio 1/O Capacitance 20 pF Unmeasured pins returned to GND(@4) A.C. CHARACTERISTICS T, = 0C to 70C, Veg = +5V +10%, GND = OV* Bus Parameters READ Symbol Parameter 8255A 8255A-5 Unit Min Max Min Max tar Address Stable before READ 0 0 ns tra Address Stable after READ 0 0 ns tRR READ Pulse Width 300 300 ns trp Data Valid from READ) 250 200 ns tor Data Float after READ 16 150 10 100 ns try Time between READs and/or WRITEs 850 850 ns WRITE Symbol Parameter B255A S255A-5 Unit Min Max Min Max taw Address Stable before WRITE 0 0 ns twa Address Stabie after WRITE 20 20 ns tww WRITE Pulse Width 400 300 ns tow Data Valid to WRITE (T.E.) 100 100 ns twp Data Valid after WRITE 30 30 ns OTHER TIMINGS Symbol Parameter B255A 8255A-5 Unit Min Max Min Max twp WR = 1 to Output(1) 350 350 ns tin Peripheral Data before RD 0 0 ns tur Peripheral Data after RD 0 0 ns tak ACK Pulse Width 300 300 ns tst STB Pulse Width 500 500 ns tps Per. Data before T.E. of STB 0 0) ns teH Per. Data after T.E. of STB 180 180 ns tap ACK = 0 to Output(1) 300 300 ns tkp ACK = 1 to Output Float 20 250 20 250 ns 3-119 www.chipdocs.com Be sure to visit ChipDocs web site for more information.intel. 8255A/8255A-5 A.C. CHARACTERISTICS (Continued) OTHER TIMINGS (Continued) Symbol Parameter B255A 8255A5 Unit Min Max Min Max twos WR = 1 to OBF = 001) 650 650 ns taos ACK = 0to OBF = 1(1) 350 350 ns tsip STB = Oto IBF = 1(1) 300 300 ns trip RD = 1to IBF = ot!) 300 300 ns tit RD = Oto INTR = ott) 400 400 ns tsit | STB = 1toINTR = 1(1) 300 300 ns tait ACK = 1to INTR = 1(1) 350 350 ns twit WR = Oto INTR = 0(1,3) 850 850 ns NOTES: 1. Test Conditions: CL = 150 pF. 2. Period of Reset pulse must be at least 50 :s during or after power on. Subsequent Reset pulse can be 500 ns min. 3. INTR T may occur as early as WR I. 4. Sampled, not 100% tested. "For Extended Temperature EXPRESS, use M8255A electrical parameters. A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT Input/Output 2A me 20 DEVICE - s UNDER pO Vext* > TEST POINTS < Cy = 180 pF TEST Cc = 156 pF 08 os 0.45 231308-50 - A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V 231308-51 for a Logic 0. Timing measurements are made at 2.0V for a Vex is set at various voltages during testing to guarantee the Lagic 1 and 0.6V for a Logic 0. specification. C, includes jig capacitance. 3-120 www.chipdocs.com Be sure to visit ChipDocs web site for more information.intel. 8255A/8255A-5 WAVEFORMS MODE 0 (BASIC INPUT) INPUT C5, At, Ad D,-Dy ee eee 231308-52 MODE 0 (BASIC OUTPUT) D,-Dy 5, Al, AO OUTPUT 231308-53 3-121 www.chipdocs.com Be sure to visit ChipDocs web site for more information.intel. 8255A/8255A-5 WAVEFORMS (Continued) MODE 1 (STROBED INPUT) \8F INTR AD INPUT FROM PERIPHERAL }-_ te tsip > , a s ce ee ee ee ee ee ee ie a 2313038-54 MODE 1 (STROBED OUTPUT) - 0D0UDUCSN INTR wt yp Th La tan t Vat OUTPUT 231308-55 www.chipdocs.com 3-122 Be sure to visit ChipDocs web site for more information.intel. 8255A/8255A-5 WAVEFORMS (Continued) MODE 2 (BIDIRECTIONAL) DATA FROM 8080 FO 8255 \ I Tax [L AgK ON 7] PERIPHERAL BUS AB DATA FROM DATA FROM PERIPHERAL TO 8255 8255 TO PERIPHERAL J I DATA FROM 8255 TO 8080 NOTE: _ 231308 -56 Any sequence where WR occurs before ACK and STB occurs before AD is permissible. (INTR = IBF MASK STS RD + OBF MASK ACK Wh) WRITE TIMING READ TIMING Ag-+. C8 &o.4. CS tan -_ _{ DATA BUS RD Wh DATA BUS HIGH IMPEDANCE VALID [HIGH IMPEDANCE 231308-57 231308 -58 3-123 www.chipdocs.com Be sure to visit ChipDocs web site for more information.