© 2008 Microchip Technology Inc. DS39626E
PIC18F2525/2620/4525/4620
Data Sheet
28/40/44-Pin
Enhanced Flash Microcontrollers
with 10-Bit A/D and nanoWatt Technology
DS39626E-page ii © 2008 Microchip Technology Inc.
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ECONOMONITOR, FanSense, In-Circuit Serial
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Printed on recycled paper.
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• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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© 2008 Microchip Technology Inc. DS39626E-page 1
PIC18F2525/2620/4525/4620
Power Management Features:
• Run: CPU on, Peripherals on
• Idle: CPU off, Peripherals on
• Sleep: CPU off, Peripherals off
• Ultra Low 50nA Input Leakage
• Run mode Currents Down to 11 μA Typical
• Idle mo de Curren ts Down to 2.5 μA Typical
• Sleep mode Current Down to 100 nA Typical
• Timer1 Oscillator: 900 nA, 32 kHz, 2V
• Watchdog Timer: 1.4 μA, 2V T y pi ca l
• Two-Speed Oscillator Start-up
Flexible Oscil lator Struc ture:
• Four Crystal modes, up to 40 MHz
• 4x Phase Lock Loop (PLL) – Available for Crystal
and Internal Oscillators
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 40 MHz
• Intern al Os ci ll ator Block:
- Fast wake from Sleep and Idle, 1 μs typical
- 8 use-selectable frequencies, from 31 kHz to
8MHz
- Provides a complete range of clock speeds
from 31 kHz to 32 MHz when used with PLL
- User-tunable to compensate for frequency drift
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock stops
Peripheral Highlights:
• High-Current Sink/Source 25 mA/25 mA
• Three Programmable External Interrupts
• Four Input Change Interrupts
• Up to 2 Capture/Compare/PWM (C CP) modules,
one with Auto-Shutdown (28-pin devices)
• Enhanced Capture/Compare/PWM (ECCP)
module (40/44-pin devices only):
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
Peripheral Highl ight s (Continued):
• Master Synchronous Serial Port (MSSP) module
Supporting 3-Wire SPI (all 4 modes) and I2C™
Master and Slav e mod es
• Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN/J2602
- RS-232 operation using internal oscillator
block (no external crystal required)
- Auto-wake-up on Start bit
- Auto-Baud Detect
• 10-Bit, up to 13-Channel Analog-to-Digital (A/D)
Converter module:
- Auto-acquisition capability
- Conversion available during Sleep
• Dual Analog Comparators with Input Multiplexing
• Programmable 16-Level High/Low-Voltage
Detection (HLVD) module:
- Supports interrupt on High/Low-Voltage Detection
S pecial Microcontroller Features:
• C Compil er Optimized Architecture:
- Optional extended instruct ion set designed to
optimize re-entrant code
• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory Typical
• 1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
• Flash/Data EEPROM Retention: 100 Years Typical
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single -Supply 5V In -Circuit Serial
Programming™ (ICSP™) via Two Pins
• In-Circuit De bug (ICD) vi a Two Pins
• Wide Operating Voltage Range: 2.0V to 5.5V
• Programmable Brown-out Reset (BOR) with
Software Enable Option
-
Device Program Memory Data Memory I/O 10-Bit
A/D (ch)
CCP/
ECCP
(PWM)
MSSP
EUSART
Comp. Timers
8/16-Bit
Flash
(bytes) # Single-Word
Instructions SRAM
(bytes) EEPROM
(bytes) SPI Master
I2C™
PIC18F2525 48K 24576 3968 1024 25 10 2/0 Y Y 1 2 1/3
PIC18F2620 64K 32768 3968 1024 25 10 2/0 Y Y 1 2 1/3
PIC18F4525 48K 24576 3968 1024 36 13 1/1 Y Y 1 2 1/3
PIC18F4620 64K 32768 3968 1024 36 13 1/1 Y Y 1 2 1/3
28/40/44-Pin Enhanced Flash Microcontrollers with
10-Bit A/D and nanoWatt Technology
PIC18F2525/2620/4525/4620
DS39626E-page 2 © 2008 Microchip Technology Inc.
Pin Diag r ams
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2(1)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4620 PIC18F2620
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2(1)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
40-Pin PDIP
28-Pin SPDIP, SOIC
PIC18F4525 PIC18F2525
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
© 2008 Microchip Technology Inc. DS39626E-page 3
PIC18F2525/2620/4525/4620
Pin Diagrams (Cont.’d)
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4525
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
RB3/AN9/CCP2(1)
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
44-Pin QFN(2)
PIC18F4620
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4525
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
NC
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
NC RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)
NC
NC
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2(1)
44-Pin TQFP
PIC18F4620
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: For the QFN package, it is recommended that the bottom pad be connected to VSS.
PIC18F2525/2620/4525/4620
DS39626E-page 4 © 2008 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power-Managed Modes .............. .. ....... .... .... .. .... ....... .... .. .... .. ....... .... .... .. .... .. ......... .. .... .. .... ......................................................... 33
4.0 Reset.......................................................................................................................................................................................... 41
5.0 Memory O rganization................................................................................................................................................................. 53
6.0 Data EEP R OM Memo ry.... ........................... ..................... ........................... ..................... ......................................................... 73
7.0 Flash Pro g ram Memory........................ ........................... ..................... ........................... ........................................................... 79
8.0 8 x 8 Hardware Multip lier..... ............... .............. ............... ..................... ............... ....................................................................... 89
9.0 I/O Ports . .............. ............................ ........................... ........................... .................................................................................... 91
10.0 Interrupts.................................................................................................................................................................................. 109
11.0 Timer0 Module ......................................................................................................................................................................... 123
12.0 Timer1 Module ......................................................................................................................................................................... 127
13.0 Timer2 Module ......................................................................................................................................................................... 133
14.0 Timer3 Module ......................................................................................................................................................................... 135
15.0 Capture/Compare/PWM (CCP) Modules ................................................. ................. ...... ................. ........................................ 139
16.0 Enhanc ed Capture/Com pare/PW M (ECCP) Module................................................................................................................ 147
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 161
18.0 Enhanc ed Universal Sync hronous Receiv er Transmitter (EUS ART)....................................................................................... 201
19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 223
20.0 Comparator Module............. .... .... ......... .. .... .... .... ......... .. .... .... ......... .. .... .... .... ......... .. .... .... ......................................................... 233
21.0 Comparator Voltage Reference Module......................................... .... .... .. .... ....... .... .... .. .... ......... .. . ........................................... 239
22.0 High/Low-Voltage Detect (HLVD)...................................... .... ............. .... ...... ........... ...... .... ....... ................................................ 243
23.0 Specia l Features of the CPU.............. ..................... ..................... ..................... ....................................................................... 249
24.0 Instruction Set Summary.......................................................................................................................................................... 267
25.0 Developm ent Suppor t............................................................................................................................................................... 317
26.0 Electrical Characteristics.......................................................................................................................................................... 321
27.0 DC and AC Characteristics Graphs and Tables.......................................................... .... ......... .... .... ........................................ 361
28.0 Packagin g In formation............. ..................... ..................... ..................... ..................... ............................................................. 383
Appendix A: Revision History............................................................................................................................................................. 393
Appendix B: Device Differences......................................................................................................................................................... 394
Appendix C: Conversion Considerations ................. .... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .... ....... . ................................................. 395
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 395
Appendix E: Migration from Mid-Range TO Enhanced Devices ....... ............. .... ............. .... ...... ........... ...... .... ... ................................. 396
Appendix F: Migration from High-End to Enhanced Devices............................. .... ......... .. .... .... ......... .... .. .... . ..................................... 396
Index .................................................................................................................................................................................................. 397
The Micro chip Web Site..... ..................... ............................ ........................... .................................................................................... 407
Customer Change Notification Service ............................................................ ................... ........ ....................................................... 407
Customer Support............ ................. ................. ...... ................. ........ ................. ................................................................................ 407
Reader Response.............................................................................................................................................................................. 408
PIC18F2525/2620/4525/4620 Product Identification System ............................................................................................................ 409
© 2008 Microchip Technology Inc. DS39626E-page 5
PIC18F2525/2620/4525/4620
TO OUR VALUED CUSTOMERS
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PIC18F2525/2620/4525/4620
DS39626E-page 6 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS39626E-page 7
PIC18F2525/2620/4525/4620
1.0 DEVICE OVERVIEW
This docu ment contains device -sp ec ifi c info rm atio n for
the following devices:
This family offers the advantages of all PIC18
microcontrollers – namely, high computational perfor-
mance at an economical price – with the addition of
high-endurance, Enhanced Flash program memory.
On top of these features, the PIC18F2525/2620/4525/
4620 family introduces design enhancements that
make these microcontrollers a logical choice for many
high-performance, power sensitive applications.
1.1 New Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F2525/2620/4525/4620
family incorporate a range of features that can signifi-
cantly reduce power consumption during operation.
Key items include:
•Alternate Run Modes: By clo cking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
•Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active . In these st ates, powe r consumptio n can be
reduced even further, to as little as 4%, of normal
operation requirements.
•On-the-Fly Mode Switching: The power-
manage d mode s a re invo ked b y user code d urin g
operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
•Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are min imiz ed. See
Section 26.0 “Electrical Characteristics” for
values.
1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F2525/2620/4525/4620
family offer ten different oscillator options, allowing
users a wide range o f choices i n developin g applica tion
hardware. These include:
• Four Crystal modes, using crystals or ceramic
resonators
• Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)
• Two External RC Oscillator modes with the same
pin options as the External Clock modes
• An internal oscillator block which provides
an 8 MHz clock and an INTRC source
(approximately 31 kHz), as well as a range of
6 user-select a ble clock frequen ci es , betw een
125 kHz to 4 MHz, for a total of 8 clock frequencies.
This o pt io n frees th e two oscillator pi ns fo r use as
additional general purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the High-Speed Crystal and Inter-
nal Oscillator m odes, which allows clock speeds of
up to 40 MHz. Used with the internal oscillator, the
PLL gives users a compl ete selec tion of clock
speeds, from 31 kHz to 32 MHz – all without using
an external crysta l or clock circuit.
Besides its availability as a clock source, the internal
oscill ato r blo ck pro vid es a s t ab le reference so urc e th at
gives the family additional features for robust
operation:
•Fail-Safe Clock Monitor: This option consta ntly
monitors the main c lock source against a reference
signal provided by the internal os cillator. If a clock
failure occurs, the controller is sw itche d to the
internal oscillator b lock, all owing for continued
low-speed operation or a safe appl ication
shutdown.
•Two-Speed S tart-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset , or wake-up from Sleep
mode, until the primary clock source is available.
• PIC18F2525 • PIC18LF2525
• PIC18F2620 • PIC18LF2620
• PIC18F4525 • PIC18LF4525
• PIC18F4620 • PIC18LF4620
PIC18F2525/2620/4525/4620
DS39626E-page 8 © 2008 Microchip Technology Inc.
1.2 Oth er Special Features
•Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 year s.
•Self-Programmability: These devices can write
to their own program memory spaces und er inter-
nal sof tware control. By using a bo otloader routine
located in the protected Boot Block at the top of
program memory, it becomes possible to create
an application that can update itself in the field.
•Extended Instruction Set: The PIC18F2525/
2620/4525/4620 family introduces an opt ional
extens ion to the PIC18 instruc tion set, which ad ds
8 new instructions and an Indexed Addressing
mode. This extension, enabled as a device con-
figuration option, has been specifically designed
to optimize re-entrant application code originally
developed in high-level languages, such as C.
•Enhanced CCP Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other featu res inc lu de auto - sh ut d ow n, for
disabl ing PWM output s on interrup t or other selec t
conditions and auto-restart, to reactivate outputs
once the condition has cleared.
•Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation an d provides support for th e LIN
bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Genera tor for improved res olution. Whe n the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
•10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated withou t waiting for a sa mpling perio d and
thus, reducing code overhead.
•Extended Watchdog Timer (WDT): This
enhanc ed vers ion in corpora tes a 1 6-bit pre scale r,
allow ing a n exte nded time-o ut rang e that is s ta ble
across operating voltage and temperature. See
Section 26.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Individual Family
Members
Devices in the PIC18F 2525/2620/45 25/4620 famil y are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in five
ways:
1. Flash program memory (48 Kbytes for
PIC18FX525 devices, 64 Kbytes for
PIC18FX6 20 dev ices).
2. A/D channels (10 for 28-pin devices, 13 for
40/44-pin devices).
3. I/O ports (3 bidirectio nal ports on 28 -pin devices,
5 bidirectional ports on 40/44-pin devices).
4. CCP and Enhanced CCP implementation
(28-pin devices have 2 standard CCP
m od ules, 40/44-pin devices have one standard
CCP module and one ECCP module).
5. Parallel Slave Port (present only on 40/44-pin
devices).
All other feature s for devi ces in th is fami ly are ide ntical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F2525/2620/4525/4620 family are available as
both standard and low-voltage devices. Standard
device s with En hanced Fl ash memory, designate d with
an “F” in the part number (such as PIC18F2620),
accom modate an operati ng VDD ra nge of 4.2V to 5. 5V.
Low-voltage parts, designated by “LF” (such as
PIC18LF2620), function over an extended VDD range
of 2.0V to 5.5V.
© 2008 Microchip Technology Inc. DS39626E-page 9
PIC18F2525/2620/4525/4620
TABLE 1-1: DEVICE FEATURES
Features PIC18F2525 PIC18F2620 PIC18F4525 PIC18F4620
Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memo ry (Bytes ) 49152 65536 49152 65536
Program Memo ry (Instructions) 24576 32768 24576 32768
Data Memory (Bytes) 3968 3968 3968 3968
Data EEPROM Memory (Bytes) 1024 1024 1024 1024
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM Modules 2 2 1 1
Enhanced Capture/Compare/
PWM Modules 0011
Serial Communications MSSP,
Enhanced USART MSSP,
Enhanced USART MSSP,
Enhanced USART MSSP,
Enhanced USART
Parallel Communications (PSP) No No Ye s Yes
10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Resets (and Delays) POR, BOR,
RESET Instruction,
Stack Full,
St ac k Unde rflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instru ct ion ,
Stack Full,
Stack Un derf low
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWR T, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Ins truction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Programmable Low -Voltage
Detect Yes Yes Yes Yes
Programmab le Brown-o ut Rese t Yes Yes Yes Yes
Inst ruction Set 75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Inst ruction Set
Enabled
75 Instructi ons;
83 with Extend ed
Instructi on Set
Enabled
75 Instructions;
83 with Extended
Ins truction Set
Enabled
Packages 28-Pin SPDIP
28-Pin SOIC 28-Pin SPDIP
28-Pin SOIC 40-Pin PDIP
44-Pin QFN
44-Pin TQFP
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
PIC18F2525/2620/4525/4620
DS39626E-page 10 © 2008 Microchip Technology Inc.
FIGURE 1-1: PIC18F 2525/ 2620 (28- PIN) BL OCK DIAGR AM
Instruction
Decode &
Control
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10
Data Latch
Data Memory
(3.9 Kbytes)
Addr ess Lat ch
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31 Level Stack
Progra m Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP 8
8
ALU<8>
Address Latch
Prog ram Memo ry
(48/64Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
RB2/INT2/AN8
RB3/AN9/CCP2(1)
PCLATU
PCU
OSC2/CLKO(3)/RA6
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.
2: RE3 is only availa ble w hen MCLR functionality is disabled.
3: OSC1/CLKI and OS C2/CL KO are only availa ble in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
EUSARTComparator MSSP 10-Bit
ADC
Timer2Timer1 Timer3Timer0
CCP2
LVD
CCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State Machine
Control Signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(3)
OSC2(3)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
VSS
MCLR(2)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSO
OSC1/CLKI(3)/RA7
T1OSI
PORTE
MCLR/VPP/RE3(2)
© 2008 Microchip Technology Inc. DS39626E-page 11
PIC18F2525/2620/4525/4620
FIGURE 1-2: PIC18F4525/4620 (40/44-PIN) BLOCK DIAGRAM
Instruction
Decode &
Control
Data Latch
Data Memory
(3.9 Kbytes)
Addr ess Lat ch
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31 Level Stack
Progra m Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP 8
8
ALU<8>
Address Latch
Prog ram Memo ry
(48/64Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PORTD
RD0/PSP0
PCLATU
PCU
PORTE
MCLR/VPP/RE3(2)
RE2/CS/AN7
RE0/RD/AN5
RE1/WR/AN6
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
:RD4/PSP4
EUSARTComparator MSSP 10-Bit
ADC
Timer2Timer1 Timer3Timer0
CCP2
LVD
ECCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State Machine
Control Signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(3)
OSC2(3)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
VSS
MCLR(2)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2(1)
OSC2/CLKO(3)/RA6
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
OSC1/CLKI(3)/RA7
PIC18F2525/2620/4525/4620
DS39626E-page 12 © 2008 Microchip Technology Inc.
TABLE 1-2: PIC18F2525/2620 PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Number Pin
Type Buffer
Type Description
SPDIP,
SOIC
MCLR/VPP/RE3
MCLR
VPP
RE3
1I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
9I
I
I/O
ST
CMOS
TTL
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
External clock source input. Alw ays as soci ated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10 O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assi gnment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2008 Microchip Technology Inc. DS39626E-page 13
PIC18F2525/2620/4525/4620
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2I/O
ITTL
Analog Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3I/O
ITTL
Analog Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
4I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6I/O
I
O
ST
ST
—
Digital I/O.
Timer0 external clock input.
Compara tor 1 output.
RA5/AN4/SS/HLVDIN/
C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
7
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Compara tor 2 output.
RA6 See the OSC2/CLKO /R A6 pin .
RA7 See the OSC1/CLKI/RA7 pin.
TABLE 1-2: PIC18F2525/2620 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type Buffer
Type Description
SPDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
PIC18F2525/2620/4525/4620
DS39626E-page 14 © 2008 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
21 I/O
I
I
I
TTL
ST
ST
Analog
Digit al I/O .
External interrupt 0.
PWM Fault input for CCP1.
Anal og inp ut 12.
RB1/INT1/AN10
RB1
INT1
AN10
22 I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 1.
Analog input 10.
RB2/INT2/AN8
RB2
INT2
AN8
23 I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 2.
Analog input 8.
RB3/AN9/CCP2
RB3
AN9
CCP2(1)
24 I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM2 output.
RB4/KBI0/AN11
RB4
KBI0
AN11
25 I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
Analog input 11.
RB5/KBI1/PGM
RB5
KBI1
PGM
26 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
27 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
28 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-2: PIC18F2525/2620 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type Buffer
Type Description
SPDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assi gnment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
© 2008 Microchip Technology Inc. DS39626E-page 15
PIC18F2525/2620/4525/4620
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
11 I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscilla tor outp ut.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
12 I/O
I
I/O
ST
Analog
ST
Digital I/O.
Timer1 oscil la tor inpu t.
Capture 2 input/Compare 2 output/PWM2 output.
RC2/CCP1
RC2
CCP1
13 I/O
I/O ST
ST Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
14 I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA
RC4
SDI
SDA
15 I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
16 I/O
OST
—Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
17 I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
18 I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
RE3 — — — See MCLR/VPP/RE3 pin.
VSS 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 P — Positive supply for logic and I/O pins.
TABLE 1-2: PIC18F2525/2620 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type Buffer
Type Description
SPDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
PIC18F2525/2620/4525/4620
DS39626E-page 16 © 2008 Microchip Technology Inc.
TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
MCLR/VPP/RE3
MCLR
VPP
RE3
11818I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Cl ear (Reset) input. This pin is an activ e-low
Reset to the device.
Prog ramming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
13 32 30 I
I
I/O
ST
CMOS
TTL
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode;
analog otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 33 31 O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assi gnment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
3: For the QFN package, it is recommended that the bottom pad be connected to VSS.
© 2008 Microchip Technology Inc. DS39626E-page 17
PIC18F2525/2620/4525/4620
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
21919
I/O
ITTL
Analog Digi tal I/O.
Analog input 0.
RA1/AN1
RA1
AN1
32020
I/O
ITTL
Analog Digi tal I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREF-
CVREF
42121
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
RA3/AN3/VREF+
RA3
AN3
VREF+
52222
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
62323
I/O
I
O
ST
ST
—
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
RA5/AN4/SS/HLVDIN/
C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
72424
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 See the OSC2/CLKO/RA 6 pin.
RA7 See the OSC1/CLKI/RA7 pin.
TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
3: For the QFN package, it is recommended that the bottom pad be connected to VSS.
PIC18F2525/2620/4525/4620
DS39626E-page 18 © 2008 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
33 9 8 I/O
I
I
I
TTL
ST
ST
Analog
Digital I/O.
External int errup t 0.
PWM Fault input for Enhanced CCP1.
Analog input 12.
RB1/INT1/AN10
RB1
INT1
AN10
34 10 9 I/O
I
I
TTL
ST
Analog
Digital I/O.
External int errup t 1.
Analog input 10.
RB2/INT2/AN8
RB2
INT2
AN8
35 11 10 I/O
I
I
TTL
ST
Analog
Digital I/O.
External int errup t 2.
Analog input 8.
RB3/AN9/CCP2
RB3
AN9
CCP2(1)
36 12 11 I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Co mpare 2 output/PWM2 outp ut.
RB4/KBI0/AN11
RB4
KBI0
AN11
37 14 14 I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-o n-c han ge pin .
Analog input 11.
RB5/KBI1/PGM
RB5
KBI1
PGM
38 15 15 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-o n-c han ge pin .
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
39 16 16 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-o n-c han ge pin .
In-Circuit Debugger and ICSP programming
clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
40 17 17 I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-o n-c han ge pin .
In-Circuit Debugger and ICSP programming
data pin.
TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assi gnment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
3: For the QFN package, it is recommended that the bottom pad be connected to VSS.
© 2008 Microchip Technology Inc. DS39626E-page 19
PIC18F2525/2620/4525/4620
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
15 34 32 I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
16 35 35 I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Co mpare 2 output/PWM2 outp ut.
RC2/CCP1/P1A
RC2
CCP1
P1A
17 36 36 I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Co mpare 1 output/PWM1 outp ut.
Enhanced CCP1 output.
RC3/SCK/SCL
RC3
SCK
SCL
18 37 37 I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for I2C™
mode.
RC4/SDI/SDA
RC4
SDI
SDA
23 42 42 I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
24 43 43 I/O
OST
—Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
25 44 44 I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
26 1 1 I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
3: For the QFN package, it is recommended that the bottom pad be connected to VSS.
PIC18F2525/2620/4525/4620
DS39626E-page 20 © 2008 Microchip Technology Inc.
PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when the PSP
module is enabled.
RD0/PSP0
RD0
PSP0
19 38 38 I/O
I/O ST
TTL Digital I/O.
Parallel Slave Port data.
RD1/PSP1
RD1
PSP1
20 39 39 I/O
I/O ST
TTL Digital I/O.
Parallel Slave Port data.
RD2/PSP2
RD2
PSP2
21 40 40 I/O
I/O ST
TTL Digital I/O.
Parallel Slave Port data.
RD3/PSP3
RD3
PSP3
22 41 41 I/O
I/O ST
TTL Digital I/O.
Parallel Slave Port data.
RD4/PSP4
RD4
PSP4
27 2 2 I/O
I/O ST
TTL Digital I/O.
Parallel Slave Port data.
RD5/PSP5/P1B
RD5
PSP5
P1B
28 3 3 I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
RD6/PSP6/P1C
RD6
PSP6
P1C
29 4 4 I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
RD7/PSP7/P1D
RD7
PSP7
P1D
30 5 5 I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assi gnment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
3: For the QFN package, it is recommended that the bottom pad be connected to VSS.
© 2008 Microchip Technology Inc. DS39626E-page 21
PIC18F2525/2620/4525/4620
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
RD
AN5
82525
I/O
I
I
ST
TTL
Analog
Digital I/O.
Read control for Parallel Slave P ort
(see also WR and CS pins).
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
92626
I/O
I
I
ST
TTL
Analog
Digital I/O.
Write control for Parallel Slave Port
(see CS and RD pins).
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10 27 27 I/O
I
I
ST
TTL
Analog
Digital I/O.
Chip select control for Parallel Slave Port
(see related RD and WR).
Analog input 7.
RE3 — — — — — See MCLR/VPP/RE3 pin.
VSS 12, 31 6, 30,
31 6, 29 P — Ground reference for logic and I/O pins.
VDD 11, 32 7, 8,
28, 29 7, 28 P — Positive supply for logic and I/O pins.
NC — 13 12, 13,
33, 34 — — No conne ct.
TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
3: For the QFN package, it is recommended that the bottom pad be connected to VSS.